main.c 92 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/rtnetlink.h>
  40. #include <linux/if_vlan.h>
  41. #include <linux/sched/mm.h>
  42. #include <linux/sched/task.h>
  43. #include <net/ipv6.h>
  44. #include <net/addrconf.h>
  45. #include <net/devlink.h>
  46. #include <rdma/ib_smi.h>
  47. #include <rdma/ib_user_verbs.h>
  48. #include <rdma/ib_addr.h>
  49. #include <rdma/ib_cache.h>
  50. #include <net/bonding.h>
  51. #include <linux/mlx4/driver.h>
  52. #include <linux/mlx4/cmd.h>
  53. #include <linux/mlx4/qp.h>
  54. #include "mlx4_ib.h"
  55. #include <rdma/mlx4-abi.h>
  56. #define DRV_NAME MLX4_IB_DRV_NAME
  57. #define DRV_VERSION "4.0-0"
  58. #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
  59. #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
  60. #define MLX4_IB_CARD_REV_A0 0xA0
  61. MODULE_AUTHOR("Roland Dreier");
  62. MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
  63. MODULE_LICENSE("Dual BSD/GPL");
  64. int mlx4_ib_sm_guid_assign = 0;
  65. module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
  66. MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
  67. static const char mlx4_ib_version[] =
  68. DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
  69. DRV_VERSION "\n";
  70. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
  71. static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
  72. u8 port_num);
  73. static struct workqueue_struct *wq;
  74. static void init_query_mad(struct ib_smp *mad)
  75. {
  76. mad->base_version = 1;
  77. mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
  78. mad->class_version = 1;
  79. mad->method = IB_MGMT_METHOD_GET;
  80. }
  81. static int check_flow_steering_support(struct mlx4_dev *dev)
  82. {
  83. int eth_num_ports = 0;
  84. int ib_num_ports = 0;
  85. int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
  86. if (dmfs) {
  87. int i;
  88. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
  89. eth_num_ports++;
  90. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  91. ib_num_ports++;
  92. dmfs &= (!ib_num_ports ||
  93. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
  94. (!eth_num_ports ||
  95. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
  96. if (ib_num_ports && mlx4_is_mfunc(dev)) {
  97. pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
  98. dmfs = 0;
  99. }
  100. }
  101. return dmfs;
  102. }
  103. static int num_ib_ports(struct mlx4_dev *dev)
  104. {
  105. int ib_ports = 0;
  106. int i;
  107. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  108. ib_ports++;
  109. return ib_ports;
  110. }
  111. static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
  112. {
  113. struct mlx4_ib_dev *ibdev = to_mdev(device);
  114. struct net_device *dev;
  115. rcu_read_lock();
  116. dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
  117. if (dev) {
  118. if (mlx4_is_bonded(ibdev->dev)) {
  119. struct net_device *upper = NULL;
  120. upper = netdev_master_upper_dev_get_rcu(dev);
  121. if (upper) {
  122. struct net_device *active;
  123. active = bond_option_active_slave_get_rcu(netdev_priv(upper));
  124. if (active)
  125. dev = active;
  126. }
  127. }
  128. }
  129. if (dev)
  130. dev_hold(dev);
  131. rcu_read_unlock();
  132. return dev;
  133. }
  134. static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
  135. struct mlx4_ib_dev *ibdev,
  136. u8 port_num)
  137. {
  138. struct mlx4_cmd_mailbox *mailbox;
  139. int err;
  140. struct mlx4_dev *dev = ibdev->dev;
  141. int i;
  142. union ib_gid *gid_tbl;
  143. mailbox = mlx4_alloc_cmd_mailbox(dev);
  144. if (IS_ERR(mailbox))
  145. return -ENOMEM;
  146. gid_tbl = mailbox->buf;
  147. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  148. memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
  149. err = mlx4_cmd(dev, mailbox->dma,
  150. MLX4_SET_PORT_GID_TABLE << 8 | port_num,
  151. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  152. MLX4_CMD_WRAPPED);
  153. if (mlx4_is_bonded(dev))
  154. err += mlx4_cmd(dev, mailbox->dma,
  155. MLX4_SET_PORT_GID_TABLE << 8 | 2,
  156. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  157. MLX4_CMD_WRAPPED);
  158. mlx4_free_cmd_mailbox(dev, mailbox);
  159. return err;
  160. }
  161. static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
  162. struct mlx4_ib_dev *ibdev,
  163. u8 port_num)
  164. {
  165. struct mlx4_cmd_mailbox *mailbox;
  166. int err;
  167. struct mlx4_dev *dev = ibdev->dev;
  168. int i;
  169. struct {
  170. union ib_gid gid;
  171. __be32 rsrvd1[2];
  172. __be16 rsrvd2;
  173. u8 type;
  174. u8 version;
  175. __be32 rsrvd3;
  176. } *gid_tbl;
  177. mailbox = mlx4_alloc_cmd_mailbox(dev);
  178. if (IS_ERR(mailbox))
  179. return -ENOMEM;
  180. gid_tbl = mailbox->buf;
  181. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  182. memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
  183. if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
  184. gid_tbl[i].version = 2;
  185. if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
  186. gid_tbl[i].type = 1;
  187. else
  188. memset(&gid_tbl[i].gid, 0, 12);
  189. }
  190. }
  191. err = mlx4_cmd(dev, mailbox->dma,
  192. MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
  193. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  194. MLX4_CMD_WRAPPED);
  195. if (mlx4_is_bonded(dev))
  196. err += mlx4_cmd(dev, mailbox->dma,
  197. MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
  198. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  199. MLX4_CMD_WRAPPED);
  200. mlx4_free_cmd_mailbox(dev, mailbox);
  201. return err;
  202. }
  203. static int mlx4_ib_update_gids(struct gid_entry *gids,
  204. struct mlx4_ib_dev *ibdev,
  205. u8 port_num)
  206. {
  207. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  208. return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
  209. return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
  210. }
  211. static int mlx4_ib_add_gid(struct ib_device *device,
  212. u8 port_num,
  213. unsigned int index,
  214. const union ib_gid *gid,
  215. const struct ib_gid_attr *attr,
  216. void **context)
  217. {
  218. struct mlx4_ib_dev *ibdev = to_mdev(device);
  219. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  220. struct mlx4_port_gid_table *port_gid_table;
  221. int free = -1, found = -1;
  222. int ret = 0;
  223. int hw_update = 0;
  224. int i;
  225. struct gid_entry *gids = NULL;
  226. if (!rdma_cap_roce_gid_table(device, port_num))
  227. return -EINVAL;
  228. if (port_num > MLX4_MAX_PORTS)
  229. return -EINVAL;
  230. if (!context)
  231. return -EINVAL;
  232. port_gid_table = &iboe->gids[port_num - 1];
  233. spin_lock_bh(&iboe->lock);
  234. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  235. if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
  236. (port_gid_table->gids[i].gid_type == attr->gid_type)) {
  237. found = i;
  238. break;
  239. }
  240. if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
  241. free = i; /* HW has space */
  242. }
  243. if (found < 0) {
  244. if (free < 0) {
  245. ret = -ENOSPC;
  246. } else {
  247. port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
  248. if (!port_gid_table->gids[free].ctx) {
  249. ret = -ENOMEM;
  250. } else {
  251. *context = port_gid_table->gids[free].ctx;
  252. memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
  253. port_gid_table->gids[free].gid_type = attr->gid_type;
  254. port_gid_table->gids[free].ctx->real_index = free;
  255. port_gid_table->gids[free].ctx->refcount = 1;
  256. hw_update = 1;
  257. }
  258. }
  259. } else {
  260. struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
  261. *context = ctx;
  262. ctx->refcount++;
  263. }
  264. if (!ret && hw_update) {
  265. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  266. if (!gids) {
  267. ret = -ENOMEM;
  268. } else {
  269. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
  270. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  271. gids[i].gid_type = port_gid_table->gids[i].gid_type;
  272. }
  273. }
  274. }
  275. spin_unlock_bh(&iboe->lock);
  276. if (!ret && hw_update) {
  277. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  278. kfree(gids);
  279. }
  280. return ret;
  281. }
  282. static int mlx4_ib_del_gid(struct ib_device *device,
  283. u8 port_num,
  284. unsigned int index,
  285. void **context)
  286. {
  287. struct gid_cache_context *ctx = *context;
  288. struct mlx4_ib_dev *ibdev = to_mdev(device);
  289. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  290. struct mlx4_port_gid_table *port_gid_table;
  291. int ret = 0;
  292. int hw_update = 0;
  293. struct gid_entry *gids = NULL;
  294. if (!rdma_cap_roce_gid_table(device, port_num))
  295. return -EINVAL;
  296. if (port_num > MLX4_MAX_PORTS)
  297. return -EINVAL;
  298. port_gid_table = &iboe->gids[port_num - 1];
  299. spin_lock_bh(&iboe->lock);
  300. if (ctx) {
  301. ctx->refcount--;
  302. if (!ctx->refcount) {
  303. unsigned int real_index = ctx->real_index;
  304. memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
  305. kfree(port_gid_table->gids[real_index].ctx);
  306. port_gid_table->gids[real_index].ctx = NULL;
  307. hw_update = 1;
  308. }
  309. }
  310. if (!ret && hw_update) {
  311. int i;
  312. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  313. if (!gids) {
  314. ret = -ENOMEM;
  315. } else {
  316. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
  317. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  318. }
  319. }
  320. spin_unlock_bh(&iboe->lock);
  321. if (!ret && hw_update) {
  322. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  323. kfree(gids);
  324. }
  325. return ret;
  326. }
  327. int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
  328. u8 port_num, int index)
  329. {
  330. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  331. struct gid_cache_context *ctx = NULL;
  332. union ib_gid gid;
  333. struct mlx4_port_gid_table *port_gid_table;
  334. int real_index = -EINVAL;
  335. int i;
  336. int ret;
  337. unsigned long flags;
  338. struct ib_gid_attr attr;
  339. if (port_num > MLX4_MAX_PORTS)
  340. return -EINVAL;
  341. if (mlx4_is_bonded(ibdev->dev))
  342. port_num = 1;
  343. if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
  344. return index;
  345. ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
  346. if (ret)
  347. return ret;
  348. if (attr.ndev)
  349. dev_put(attr.ndev);
  350. if (!memcmp(&gid, &zgid, sizeof(gid)))
  351. return -EINVAL;
  352. spin_lock_irqsave(&iboe->lock, flags);
  353. port_gid_table = &iboe->gids[port_num - 1];
  354. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  355. if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
  356. attr.gid_type == port_gid_table->gids[i].gid_type) {
  357. ctx = port_gid_table->gids[i].ctx;
  358. break;
  359. }
  360. if (ctx)
  361. real_index = ctx->real_index;
  362. spin_unlock_irqrestore(&iboe->lock, flags);
  363. return real_index;
  364. }
  365. static int mlx4_ib_query_device(struct ib_device *ibdev,
  366. struct ib_device_attr *props,
  367. struct ib_udata *uhw)
  368. {
  369. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  370. struct ib_smp *in_mad = NULL;
  371. struct ib_smp *out_mad = NULL;
  372. int err;
  373. int have_ib_ports;
  374. struct mlx4_uverbs_ex_query_device cmd;
  375. struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
  376. struct mlx4_clock_params clock_params;
  377. if (uhw->inlen) {
  378. if (uhw->inlen < sizeof(cmd))
  379. return -EINVAL;
  380. err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
  381. if (err)
  382. return err;
  383. if (cmd.comp_mask)
  384. return -EINVAL;
  385. if (cmd.reserved)
  386. return -EINVAL;
  387. }
  388. resp.response_length = offsetof(typeof(resp), response_length) +
  389. sizeof(resp.response_length);
  390. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  391. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  392. err = -ENOMEM;
  393. if (!in_mad || !out_mad)
  394. goto out;
  395. init_query_mad(in_mad);
  396. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  397. err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
  398. 1, NULL, NULL, in_mad, out_mad);
  399. if (err)
  400. goto out;
  401. memset(props, 0, sizeof *props);
  402. have_ib_ports = num_ib_ports(dev->dev);
  403. props->fw_ver = dev->dev->caps.fw_ver;
  404. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  405. IB_DEVICE_PORT_ACTIVE_EVENT |
  406. IB_DEVICE_SYS_IMAGE_GUID |
  407. IB_DEVICE_RC_RNR_NAK_GEN |
  408. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  409. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  410. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  411. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  412. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  413. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
  414. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  415. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
  416. props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  417. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  418. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  419. if (dev->dev->caps.max_gso_sz &&
  420. (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
  421. (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
  422. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  423. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
  424. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  425. if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
  426. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
  427. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
  428. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  429. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
  430. props->device_cap_flags |= IB_DEVICE_XRC;
  431. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
  432. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
  433. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  434. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
  435. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
  436. else
  437. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
  438. }
  439. if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  440. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  441. props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
  442. props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
  443. 0xffffff;
  444. props->vendor_part_id = dev->dev->persist->pdev->device;
  445. props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
  446. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  447. props->max_mr_size = ~0ull;
  448. props->page_size_cap = dev->dev->caps.page_size_cap;
  449. props->max_qp = dev->dev->quotas.qp;
  450. props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
  451. props->max_sge = min(dev->dev->caps.max_sq_sg,
  452. dev->dev->caps.max_rq_sg);
  453. props->max_sge_rd = MLX4_MAX_SGE_RD;
  454. props->max_cq = dev->dev->quotas.cq;
  455. props->max_cqe = dev->dev->caps.max_cqes;
  456. props->max_mr = dev->dev->quotas.mpt;
  457. props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
  458. props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
  459. props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
  460. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  461. props->max_srq = dev->dev->quotas.srq;
  462. props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
  463. props->max_srq_sge = dev->dev->caps.max_srq_sge;
  464. props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
  465. props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
  466. props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
  467. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  468. props->masked_atomic_cap = props->atomic_cap;
  469. props->max_pkeys = dev->dev->caps.pkey_table_len[1];
  470. props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
  471. props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
  472. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  473. props->max_mcast_grp;
  474. props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
  475. props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
  476. props->timestamp_mask = 0xFFFFFFFFFFFFULL;
  477. props->max_ah = INT_MAX;
  478. if ((dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
  479. (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
  480. mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET)) {
  481. props->rss_caps.max_rwq_indirection_tables = props->max_qp;
  482. props->rss_caps.max_rwq_indirection_table_size =
  483. dev->dev->caps.max_rss_tbl_sz;
  484. props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
  485. props->max_wq_type_rq = props->max_qp;
  486. }
  487. if (!mlx4_is_slave(dev->dev))
  488. err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
  489. if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
  490. resp.response_length += sizeof(resp.hca_core_clock_offset);
  491. if (!err && !mlx4_is_slave(dev->dev)) {
  492. resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
  493. resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
  494. }
  495. }
  496. if (uhw->outlen >= resp.response_length +
  497. sizeof(resp.max_inl_recv_sz)) {
  498. resp.response_length += sizeof(resp.max_inl_recv_sz);
  499. resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
  500. sizeof(struct mlx4_wqe_data_seg);
  501. }
  502. if (uhw->outlen) {
  503. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  504. if (err)
  505. goto out;
  506. }
  507. out:
  508. kfree(in_mad);
  509. kfree(out_mad);
  510. return err;
  511. }
  512. static enum rdma_link_layer
  513. mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
  514. {
  515. struct mlx4_dev *dev = to_mdev(device)->dev;
  516. return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
  517. IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
  518. }
  519. static int ib_link_query_port(struct ib_device *ibdev, u8 port,
  520. struct ib_port_attr *props, int netw_view)
  521. {
  522. struct ib_smp *in_mad = NULL;
  523. struct ib_smp *out_mad = NULL;
  524. int ext_active_speed;
  525. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  526. int err = -ENOMEM;
  527. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  528. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  529. if (!in_mad || !out_mad)
  530. goto out;
  531. init_query_mad(in_mad);
  532. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  533. in_mad->attr_mod = cpu_to_be32(port);
  534. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  535. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  536. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  537. in_mad, out_mad);
  538. if (err)
  539. goto out;
  540. props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
  541. props->lmc = out_mad->data[34] & 0x7;
  542. props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
  543. props->sm_sl = out_mad->data[36] & 0xf;
  544. props->state = out_mad->data[32] & 0xf;
  545. props->phys_state = out_mad->data[33] >> 4;
  546. props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
  547. if (netw_view)
  548. props->gid_tbl_len = out_mad->data[50];
  549. else
  550. props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
  551. props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
  552. props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
  553. props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
  554. props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
  555. props->active_width = out_mad->data[31] & 0xf;
  556. props->active_speed = out_mad->data[35] >> 4;
  557. props->max_mtu = out_mad->data[41] & 0xf;
  558. props->active_mtu = out_mad->data[36] >> 4;
  559. props->subnet_timeout = out_mad->data[51] & 0x1f;
  560. props->max_vl_num = out_mad->data[37] >> 4;
  561. props->init_type_reply = out_mad->data[41] >> 4;
  562. /* Check if extended speeds (EDR/FDR/...) are supported */
  563. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  564. ext_active_speed = out_mad->data[62] >> 4;
  565. switch (ext_active_speed) {
  566. case 1:
  567. props->active_speed = IB_SPEED_FDR;
  568. break;
  569. case 2:
  570. props->active_speed = IB_SPEED_EDR;
  571. break;
  572. }
  573. }
  574. /* If reported active speed is QDR, check if is FDR-10 */
  575. if (props->active_speed == IB_SPEED_QDR) {
  576. init_query_mad(in_mad);
  577. in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
  578. in_mad->attr_mod = cpu_to_be32(port);
  579. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
  580. NULL, NULL, in_mad, out_mad);
  581. if (err)
  582. goto out;
  583. /* Checking LinkSpeedActive for FDR-10 */
  584. if (out_mad->data[15] & 0x1)
  585. props->active_speed = IB_SPEED_FDR10;
  586. }
  587. /* Avoid wrong speed value returned by FW if the IB link is down. */
  588. if (props->state == IB_PORT_DOWN)
  589. props->active_speed = IB_SPEED_SDR;
  590. out:
  591. kfree(in_mad);
  592. kfree(out_mad);
  593. return err;
  594. }
  595. static u8 state_to_phys_state(enum ib_port_state state)
  596. {
  597. return state == IB_PORT_ACTIVE ? 5 : 3;
  598. }
  599. static int eth_link_query_port(struct ib_device *ibdev, u8 port,
  600. struct ib_port_attr *props)
  601. {
  602. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  603. struct mlx4_ib_iboe *iboe = &mdev->iboe;
  604. struct net_device *ndev;
  605. enum ib_mtu tmp;
  606. struct mlx4_cmd_mailbox *mailbox;
  607. int err = 0;
  608. int is_bonded = mlx4_is_bonded(mdev->dev);
  609. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  610. if (IS_ERR(mailbox))
  611. return PTR_ERR(mailbox);
  612. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  613. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  614. MLX4_CMD_WRAPPED);
  615. if (err)
  616. goto out;
  617. props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
  618. (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  619. IB_WIDTH_4X : IB_WIDTH_1X;
  620. props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  621. IB_SPEED_FDR : IB_SPEED_QDR;
  622. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
  623. props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
  624. props->max_msg_sz = mdev->dev->caps.max_msg_sz;
  625. props->pkey_tbl_len = 1;
  626. props->max_mtu = IB_MTU_4096;
  627. props->max_vl_num = 2;
  628. props->state = IB_PORT_DOWN;
  629. props->phys_state = state_to_phys_state(props->state);
  630. props->active_mtu = IB_MTU_256;
  631. spin_lock_bh(&iboe->lock);
  632. ndev = iboe->netdevs[port - 1];
  633. if (ndev && is_bonded) {
  634. rcu_read_lock(); /* required to get upper dev */
  635. ndev = netdev_master_upper_dev_get_rcu(ndev);
  636. rcu_read_unlock();
  637. }
  638. if (!ndev)
  639. goto out_unlock;
  640. tmp = iboe_get_mtu(ndev->mtu);
  641. props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
  642. props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
  643. IB_PORT_ACTIVE : IB_PORT_DOWN;
  644. props->phys_state = state_to_phys_state(props->state);
  645. out_unlock:
  646. spin_unlock_bh(&iboe->lock);
  647. out:
  648. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  649. return err;
  650. }
  651. int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  652. struct ib_port_attr *props, int netw_view)
  653. {
  654. int err;
  655. /* props being zeroed by the caller, avoid zeroing it here */
  656. err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
  657. ib_link_query_port(ibdev, port, props, netw_view) :
  658. eth_link_query_port(ibdev, port, props);
  659. return err;
  660. }
  661. static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  662. struct ib_port_attr *props)
  663. {
  664. /* returns host view */
  665. return __mlx4_ib_query_port(ibdev, port, props, 0);
  666. }
  667. int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  668. union ib_gid *gid, int netw_view)
  669. {
  670. struct ib_smp *in_mad = NULL;
  671. struct ib_smp *out_mad = NULL;
  672. int err = -ENOMEM;
  673. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  674. int clear = 0;
  675. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  676. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  677. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  678. if (!in_mad || !out_mad)
  679. goto out;
  680. init_query_mad(in_mad);
  681. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  682. in_mad->attr_mod = cpu_to_be32(port);
  683. if (mlx4_is_mfunc(dev->dev) && netw_view)
  684. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  685. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
  686. if (err)
  687. goto out;
  688. memcpy(gid->raw, out_mad->data + 8, 8);
  689. if (mlx4_is_mfunc(dev->dev) && !netw_view) {
  690. if (index) {
  691. /* For any index > 0, return the null guid */
  692. err = 0;
  693. clear = 1;
  694. goto out;
  695. }
  696. }
  697. init_query_mad(in_mad);
  698. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  699. in_mad->attr_mod = cpu_to_be32(index / 8);
  700. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
  701. NULL, NULL, in_mad, out_mad);
  702. if (err)
  703. goto out;
  704. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  705. out:
  706. if (clear)
  707. memset(gid->raw + 8, 0, 8);
  708. kfree(in_mad);
  709. kfree(out_mad);
  710. return err;
  711. }
  712. static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  713. union ib_gid *gid)
  714. {
  715. int ret;
  716. if (rdma_protocol_ib(ibdev, port))
  717. return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
  718. if (!rdma_protocol_roce(ibdev, port))
  719. return -ENODEV;
  720. if (!rdma_cap_roce_gid_table(ibdev, port))
  721. return -ENODEV;
  722. ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
  723. if (ret == -EAGAIN) {
  724. memcpy(gid, &zgid, sizeof(*gid));
  725. return 0;
  726. }
  727. return ret;
  728. }
  729. static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
  730. {
  731. union sl2vl_tbl_to_u64 sl2vl64;
  732. struct ib_smp *in_mad = NULL;
  733. struct ib_smp *out_mad = NULL;
  734. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  735. int err = -ENOMEM;
  736. int jj;
  737. if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
  738. *sl2vl_tbl = 0;
  739. return 0;
  740. }
  741. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  742. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  743. if (!in_mad || !out_mad)
  744. goto out;
  745. init_query_mad(in_mad);
  746. in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
  747. in_mad->attr_mod = 0;
  748. if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
  749. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  750. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  751. in_mad, out_mad);
  752. if (err)
  753. goto out;
  754. for (jj = 0; jj < 8; jj++)
  755. sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
  756. *sl2vl_tbl = sl2vl64.sl64;
  757. out:
  758. kfree(in_mad);
  759. kfree(out_mad);
  760. return err;
  761. }
  762. static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
  763. {
  764. u64 sl2vl;
  765. int i;
  766. int err;
  767. for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
  768. if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
  769. continue;
  770. err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
  771. if (err) {
  772. pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
  773. i, err);
  774. sl2vl = 0;
  775. }
  776. atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
  777. }
  778. }
  779. int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  780. u16 *pkey, int netw_view)
  781. {
  782. struct ib_smp *in_mad = NULL;
  783. struct ib_smp *out_mad = NULL;
  784. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  785. int err = -ENOMEM;
  786. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  787. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  788. if (!in_mad || !out_mad)
  789. goto out;
  790. init_query_mad(in_mad);
  791. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  792. in_mad->attr_mod = cpu_to_be32(index / 32);
  793. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  794. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  795. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  796. in_mad, out_mad);
  797. if (err)
  798. goto out;
  799. *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
  800. out:
  801. kfree(in_mad);
  802. kfree(out_mad);
  803. return err;
  804. }
  805. static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  806. {
  807. return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
  808. }
  809. static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
  810. struct ib_device_modify *props)
  811. {
  812. struct mlx4_cmd_mailbox *mailbox;
  813. unsigned long flags;
  814. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  815. return -EOPNOTSUPP;
  816. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  817. return 0;
  818. if (mlx4_is_slave(to_mdev(ibdev)->dev))
  819. return -EOPNOTSUPP;
  820. spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
  821. memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  822. spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
  823. /*
  824. * If possible, pass node desc to FW, so it can generate
  825. * a 144 trap. If cmd fails, just ignore.
  826. */
  827. mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
  828. if (IS_ERR(mailbox))
  829. return 0;
  830. memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  831. mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
  832. MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  833. mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
  834. return 0;
  835. }
  836. static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
  837. u32 cap_mask)
  838. {
  839. struct mlx4_cmd_mailbox *mailbox;
  840. int err;
  841. mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
  842. if (IS_ERR(mailbox))
  843. return PTR_ERR(mailbox);
  844. if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  845. *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
  846. ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
  847. } else {
  848. ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
  849. ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
  850. }
  851. err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
  852. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  853. MLX4_CMD_WRAPPED);
  854. mlx4_free_cmd_mailbox(dev->dev, mailbox);
  855. return err;
  856. }
  857. static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  858. struct ib_port_modify *props)
  859. {
  860. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  861. u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
  862. struct ib_port_attr attr;
  863. u32 cap_mask;
  864. int err;
  865. /* return OK if this is RoCE. CM calls ib_modify_port() regardless
  866. * of whether port link layer is ETH or IB. For ETH ports, qkey
  867. * violations and port capabilities are not meaningful.
  868. */
  869. if (is_eth)
  870. return 0;
  871. mutex_lock(&mdev->cap_mask_mutex);
  872. err = ib_query_port(ibdev, port, &attr);
  873. if (err)
  874. goto out;
  875. cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
  876. ~props->clr_port_cap_mask;
  877. err = mlx4_ib_SET_PORT(mdev, port,
  878. !!(mask & IB_PORT_RESET_QKEY_CNTR),
  879. cap_mask);
  880. out:
  881. mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
  882. return err;
  883. }
  884. static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
  885. struct ib_udata *udata)
  886. {
  887. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  888. struct mlx4_ib_ucontext *context;
  889. struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
  890. struct mlx4_ib_alloc_ucontext_resp resp;
  891. int err;
  892. if (!dev->ib_active)
  893. return ERR_PTR(-EAGAIN);
  894. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
  895. resp_v3.qp_tab_size = dev->dev->caps.num_qps;
  896. resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
  897. resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  898. } else {
  899. resp.dev_caps = dev->dev->caps.userspace_caps;
  900. resp.qp_tab_size = dev->dev->caps.num_qps;
  901. resp.bf_reg_size = dev->dev->caps.bf_reg_size;
  902. resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  903. resp.cqe_size = dev->dev->caps.cqe_size;
  904. }
  905. context = kzalloc(sizeof(*context), GFP_KERNEL);
  906. if (!context)
  907. return ERR_PTR(-ENOMEM);
  908. err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
  909. if (err) {
  910. kfree(context);
  911. return ERR_PTR(err);
  912. }
  913. INIT_LIST_HEAD(&context->db_page_list);
  914. mutex_init(&context->db_page_mutex);
  915. INIT_LIST_HEAD(&context->wqn_ranges_list);
  916. mutex_init(&context->wqn_ranges_mutex);
  917. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
  918. err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
  919. else
  920. err = ib_copy_to_udata(udata, &resp, sizeof(resp));
  921. if (err) {
  922. mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
  923. kfree(context);
  924. return ERR_PTR(-EFAULT);
  925. }
  926. return &context->ibucontext;
  927. }
  928. static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  929. {
  930. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  931. mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
  932. kfree(context);
  933. return 0;
  934. }
  935. static void mlx4_ib_vma_open(struct vm_area_struct *area)
  936. {
  937. /* vma_open is called when a new VMA is created on top of our VMA.
  938. * This is done through either mremap flow or split_vma (usually due
  939. * to mlock, madvise, munmap, etc.). We do not support a clone of the
  940. * vma, as this VMA is strongly hardware related. Therefore we set the
  941. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  942. * calling us again and trying to do incorrect actions. We assume that
  943. * the original vma size is exactly a single page that there will be no
  944. * "splitting" operations on.
  945. */
  946. area->vm_ops = NULL;
  947. }
  948. static void mlx4_ib_vma_close(struct vm_area_struct *area)
  949. {
  950. struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
  951. /* It's guaranteed that all VMAs opened on a FD are closed before the
  952. * file itself is closed, therefore no sync is needed with the regular
  953. * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
  954. * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
  955. * The close operation is usually called under mm->mmap_sem except when
  956. * process is exiting. The exiting case is handled explicitly as part
  957. * of mlx4_ib_disassociate_ucontext.
  958. */
  959. mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
  960. area->vm_private_data;
  961. /* set the vma context pointer to null in the mlx4_ib driver's private
  962. * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
  963. */
  964. mlx4_ib_vma_priv_data->vma = NULL;
  965. }
  966. static const struct vm_operations_struct mlx4_ib_vm_ops = {
  967. .open = mlx4_ib_vma_open,
  968. .close = mlx4_ib_vma_close
  969. };
  970. static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  971. {
  972. int i;
  973. int ret = 0;
  974. struct vm_area_struct *vma;
  975. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  976. struct task_struct *owning_process = NULL;
  977. struct mm_struct *owning_mm = NULL;
  978. owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
  979. if (!owning_process)
  980. return;
  981. owning_mm = get_task_mm(owning_process);
  982. if (!owning_mm) {
  983. pr_info("no mm, disassociate ucontext is pending task termination\n");
  984. while (1) {
  985. /* make sure that task is dead before returning, it may
  986. * prevent a rare case of module down in parallel to a
  987. * call to mlx4_ib_vma_close.
  988. */
  989. put_task_struct(owning_process);
  990. usleep_range(1000, 2000);
  991. owning_process = get_pid_task(ibcontext->tgid,
  992. PIDTYPE_PID);
  993. if (!owning_process ||
  994. owning_process->state == TASK_DEAD) {
  995. pr_info("disassociate ucontext done, task was terminated\n");
  996. /* in case task was dead need to release the task struct */
  997. if (owning_process)
  998. put_task_struct(owning_process);
  999. return;
  1000. }
  1001. }
  1002. }
  1003. /* need to protect from a race on closing the vma as part of
  1004. * mlx4_ib_vma_close().
  1005. */
  1006. down_write(&owning_mm->mmap_sem);
  1007. for (i = 0; i < HW_BAR_COUNT; i++) {
  1008. vma = context->hw_bar_info[i].vma;
  1009. if (!vma)
  1010. continue;
  1011. ret = zap_vma_ptes(context->hw_bar_info[i].vma,
  1012. context->hw_bar_info[i].vma->vm_start,
  1013. PAGE_SIZE);
  1014. if (ret) {
  1015. pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
  1016. BUG_ON(1);
  1017. }
  1018. context->hw_bar_info[i].vma->vm_flags &=
  1019. ~(VM_SHARED | VM_MAYSHARE);
  1020. /* context going to be destroyed, should not access ops any more */
  1021. context->hw_bar_info[i].vma->vm_ops = NULL;
  1022. }
  1023. up_write(&owning_mm->mmap_sem);
  1024. mmput(owning_mm);
  1025. put_task_struct(owning_process);
  1026. }
  1027. static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
  1028. struct mlx4_ib_vma_private_data *vma_private_data)
  1029. {
  1030. vma_private_data->vma = vma;
  1031. vma->vm_private_data = vma_private_data;
  1032. vma->vm_ops = &mlx4_ib_vm_ops;
  1033. }
  1034. static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  1035. {
  1036. struct mlx4_ib_dev *dev = to_mdev(context->device);
  1037. struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
  1038. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  1039. return -EINVAL;
  1040. if (vma->vm_pgoff == 0) {
  1041. /* We prevent double mmaping on same context */
  1042. if (mucontext->hw_bar_info[HW_BAR_DB].vma)
  1043. return -EINVAL;
  1044. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1045. if (io_remap_pfn_range(vma, vma->vm_start,
  1046. to_mucontext(context)->uar.pfn,
  1047. PAGE_SIZE, vma->vm_page_prot))
  1048. return -EAGAIN;
  1049. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
  1050. } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
  1051. /* We prevent double mmaping on same context */
  1052. if (mucontext->hw_bar_info[HW_BAR_BF].vma)
  1053. return -EINVAL;
  1054. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  1055. if (io_remap_pfn_range(vma, vma->vm_start,
  1056. to_mucontext(context)->uar.pfn +
  1057. dev->dev->caps.num_uars,
  1058. PAGE_SIZE, vma->vm_page_prot))
  1059. return -EAGAIN;
  1060. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
  1061. } else if (vma->vm_pgoff == 3) {
  1062. struct mlx4_clock_params params;
  1063. int ret;
  1064. /* We prevent double mmaping on same context */
  1065. if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
  1066. return -EINVAL;
  1067. ret = mlx4_get_internal_clock_params(dev->dev, &params);
  1068. if (ret)
  1069. return ret;
  1070. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1071. if (io_remap_pfn_range(vma, vma->vm_start,
  1072. (pci_resource_start(dev->dev->persist->pdev,
  1073. params.bar) +
  1074. params.offset)
  1075. >> PAGE_SHIFT,
  1076. PAGE_SIZE, vma->vm_page_prot))
  1077. return -EAGAIN;
  1078. mlx4_ib_set_vma_data(vma,
  1079. &mucontext->hw_bar_info[HW_BAR_CLOCK]);
  1080. } else {
  1081. return -EINVAL;
  1082. }
  1083. return 0;
  1084. }
  1085. static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
  1086. struct ib_ucontext *context,
  1087. struct ib_udata *udata)
  1088. {
  1089. struct mlx4_ib_pd *pd;
  1090. int err;
  1091. pd = kmalloc(sizeof *pd, GFP_KERNEL);
  1092. if (!pd)
  1093. return ERR_PTR(-ENOMEM);
  1094. err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
  1095. if (err) {
  1096. kfree(pd);
  1097. return ERR_PTR(err);
  1098. }
  1099. if (context)
  1100. if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
  1101. mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
  1102. kfree(pd);
  1103. return ERR_PTR(-EFAULT);
  1104. }
  1105. return &pd->ibpd;
  1106. }
  1107. static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
  1108. {
  1109. mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
  1110. kfree(pd);
  1111. return 0;
  1112. }
  1113. static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
  1114. struct ib_ucontext *context,
  1115. struct ib_udata *udata)
  1116. {
  1117. struct mlx4_ib_xrcd *xrcd;
  1118. struct ib_cq_init_attr cq_attr = {};
  1119. int err;
  1120. if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
  1121. return ERR_PTR(-ENOSYS);
  1122. xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
  1123. if (!xrcd)
  1124. return ERR_PTR(-ENOMEM);
  1125. err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
  1126. if (err)
  1127. goto err1;
  1128. xrcd->pd = ib_alloc_pd(ibdev, 0);
  1129. if (IS_ERR(xrcd->pd)) {
  1130. err = PTR_ERR(xrcd->pd);
  1131. goto err2;
  1132. }
  1133. cq_attr.cqe = 1;
  1134. xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
  1135. if (IS_ERR(xrcd->cq)) {
  1136. err = PTR_ERR(xrcd->cq);
  1137. goto err3;
  1138. }
  1139. return &xrcd->ibxrcd;
  1140. err3:
  1141. ib_dealloc_pd(xrcd->pd);
  1142. err2:
  1143. mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
  1144. err1:
  1145. kfree(xrcd);
  1146. return ERR_PTR(err);
  1147. }
  1148. static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
  1149. {
  1150. ib_destroy_cq(to_mxrcd(xrcd)->cq);
  1151. ib_dealloc_pd(to_mxrcd(xrcd)->pd);
  1152. mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
  1153. kfree(xrcd);
  1154. return 0;
  1155. }
  1156. static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
  1157. {
  1158. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1159. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1160. struct mlx4_ib_gid_entry *ge;
  1161. ge = kzalloc(sizeof *ge, GFP_KERNEL);
  1162. if (!ge)
  1163. return -ENOMEM;
  1164. ge->gid = *gid;
  1165. if (mlx4_ib_add_mc(mdev, mqp, gid)) {
  1166. ge->port = mqp->port;
  1167. ge->added = 1;
  1168. }
  1169. mutex_lock(&mqp->mutex);
  1170. list_add_tail(&ge->list, &mqp->gid_list);
  1171. mutex_unlock(&mqp->mutex);
  1172. return 0;
  1173. }
  1174. static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
  1175. struct mlx4_ib_counters *ctr_table)
  1176. {
  1177. struct counter_index *counter, *tmp_count;
  1178. mutex_lock(&ctr_table->mutex);
  1179. list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
  1180. list) {
  1181. if (counter->allocated)
  1182. mlx4_counter_free(ibdev->dev, counter->index);
  1183. list_del(&counter->list);
  1184. kfree(counter);
  1185. }
  1186. mutex_unlock(&ctr_table->mutex);
  1187. }
  1188. int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  1189. union ib_gid *gid)
  1190. {
  1191. struct net_device *ndev;
  1192. int ret = 0;
  1193. if (!mqp->port)
  1194. return 0;
  1195. spin_lock_bh(&mdev->iboe.lock);
  1196. ndev = mdev->iboe.netdevs[mqp->port - 1];
  1197. if (ndev)
  1198. dev_hold(ndev);
  1199. spin_unlock_bh(&mdev->iboe.lock);
  1200. if (ndev) {
  1201. ret = 1;
  1202. dev_put(ndev);
  1203. }
  1204. return ret;
  1205. }
  1206. struct mlx4_ib_steering {
  1207. struct list_head list;
  1208. struct mlx4_flow_reg_id reg_id;
  1209. union ib_gid gid;
  1210. };
  1211. #define LAST_ETH_FIELD vlan_tag
  1212. #define LAST_IB_FIELD sl
  1213. #define LAST_IPV4_FIELD dst_ip
  1214. #define LAST_TCP_UDP_FIELD src_port
  1215. /* Field is the last supported field */
  1216. #define FIELDS_NOT_SUPPORTED(filter, field)\
  1217. memchr_inv((void *)&filter.field +\
  1218. sizeof(filter.field), 0,\
  1219. sizeof(filter) -\
  1220. offsetof(typeof(filter), field) -\
  1221. sizeof(filter.field))
  1222. static int parse_flow_attr(struct mlx4_dev *dev,
  1223. u32 qp_num,
  1224. union ib_flow_spec *ib_spec,
  1225. struct _rule_hw *mlx4_spec)
  1226. {
  1227. enum mlx4_net_trans_rule_id type;
  1228. switch (ib_spec->type) {
  1229. case IB_FLOW_SPEC_ETH:
  1230. if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
  1231. return -ENOTSUPP;
  1232. type = MLX4_NET_TRANS_RULE_ID_ETH;
  1233. memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
  1234. ETH_ALEN);
  1235. memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
  1236. ETH_ALEN);
  1237. mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
  1238. mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
  1239. break;
  1240. case IB_FLOW_SPEC_IB:
  1241. if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
  1242. return -ENOTSUPP;
  1243. type = MLX4_NET_TRANS_RULE_ID_IB;
  1244. mlx4_spec->ib.l3_qpn =
  1245. cpu_to_be32(qp_num);
  1246. mlx4_spec->ib.qpn_mask =
  1247. cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
  1248. break;
  1249. case IB_FLOW_SPEC_IPV4:
  1250. if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
  1251. return -ENOTSUPP;
  1252. type = MLX4_NET_TRANS_RULE_ID_IPV4;
  1253. mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
  1254. mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
  1255. mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
  1256. mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
  1257. break;
  1258. case IB_FLOW_SPEC_TCP:
  1259. case IB_FLOW_SPEC_UDP:
  1260. if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
  1261. return -ENOTSUPP;
  1262. type = ib_spec->type == IB_FLOW_SPEC_TCP ?
  1263. MLX4_NET_TRANS_RULE_ID_TCP :
  1264. MLX4_NET_TRANS_RULE_ID_UDP;
  1265. mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
  1266. mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
  1267. mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
  1268. mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
  1269. break;
  1270. default:
  1271. return -EINVAL;
  1272. }
  1273. if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
  1274. mlx4_hw_rule_sz(dev, type) < 0)
  1275. return -EINVAL;
  1276. mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
  1277. mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
  1278. return mlx4_hw_rule_sz(dev, type);
  1279. }
  1280. struct default_rules {
  1281. __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1282. __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1283. __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1284. __u8 link_layer;
  1285. };
  1286. static const struct default_rules default_table[] = {
  1287. {
  1288. .mandatory_fields = {IB_FLOW_SPEC_IPV4},
  1289. .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
  1290. .rules_create_list = {IB_FLOW_SPEC_IB},
  1291. .link_layer = IB_LINK_LAYER_INFINIBAND
  1292. }
  1293. };
  1294. static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
  1295. struct ib_flow_attr *flow_attr)
  1296. {
  1297. int i, j, k;
  1298. void *ib_flow;
  1299. const struct default_rules *pdefault_rules = default_table;
  1300. u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
  1301. for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
  1302. __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1303. memset(&field_types, 0, sizeof(field_types));
  1304. if (link_layer != pdefault_rules->link_layer)
  1305. continue;
  1306. ib_flow = flow_attr + 1;
  1307. /* we assume the specs are sorted */
  1308. for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
  1309. j < flow_attr->num_of_specs; k++) {
  1310. union ib_flow_spec *current_flow =
  1311. (union ib_flow_spec *)ib_flow;
  1312. /* same layer but different type */
  1313. if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
  1314. (pdefault_rules->mandatory_fields[k] &
  1315. IB_FLOW_SPEC_LAYER_MASK)) &&
  1316. (current_flow->type !=
  1317. pdefault_rules->mandatory_fields[k]))
  1318. goto out;
  1319. /* same layer, try match next one */
  1320. if (current_flow->type ==
  1321. pdefault_rules->mandatory_fields[k]) {
  1322. j++;
  1323. ib_flow +=
  1324. ((union ib_flow_spec *)ib_flow)->size;
  1325. }
  1326. }
  1327. ib_flow = flow_attr + 1;
  1328. for (j = 0; j < flow_attr->num_of_specs;
  1329. j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
  1330. for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
  1331. /* same layer and same type */
  1332. if (((union ib_flow_spec *)ib_flow)->type ==
  1333. pdefault_rules->mandatory_not_fields[k])
  1334. goto out;
  1335. return i;
  1336. }
  1337. out:
  1338. return -1;
  1339. }
  1340. static int __mlx4_ib_create_default_rules(
  1341. struct mlx4_ib_dev *mdev,
  1342. struct ib_qp *qp,
  1343. const struct default_rules *pdefault_rules,
  1344. struct _rule_hw *mlx4_spec) {
  1345. int size = 0;
  1346. int i;
  1347. for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
  1348. int ret;
  1349. union ib_flow_spec ib_spec;
  1350. switch (pdefault_rules->rules_create_list[i]) {
  1351. case 0:
  1352. /* no rule */
  1353. continue;
  1354. case IB_FLOW_SPEC_IB:
  1355. ib_spec.type = IB_FLOW_SPEC_IB;
  1356. ib_spec.size = sizeof(struct ib_flow_spec_ib);
  1357. break;
  1358. default:
  1359. /* invalid rule */
  1360. return -EINVAL;
  1361. }
  1362. /* We must put empty rule, qpn is being ignored */
  1363. ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
  1364. mlx4_spec);
  1365. if (ret < 0) {
  1366. pr_info("invalid parsing\n");
  1367. return -EINVAL;
  1368. }
  1369. mlx4_spec = (void *)mlx4_spec + ret;
  1370. size += ret;
  1371. }
  1372. return size;
  1373. }
  1374. static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1375. int domain,
  1376. enum mlx4_net_trans_promisc_mode flow_type,
  1377. u64 *reg_id)
  1378. {
  1379. int ret, i;
  1380. int size = 0;
  1381. void *ib_flow;
  1382. struct mlx4_ib_dev *mdev = to_mdev(qp->device);
  1383. struct mlx4_cmd_mailbox *mailbox;
  1384. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  1385. int default_flow;
  1386. static const u16 __mlx4_domain[] = {
  1387. [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
  1388. [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
  1389. [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
  1390. [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
  1391. };
  1392. if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
  1393. pr_err("Invalid priority value %d\n", flow_attr->priority);
  1394. return -EINVAL;
  1395. }
  1396. if (domain >= IB_FLOW_DOMAIN_NUM) {
  1397. pr_err("Invalid domain value %d\n", domain);
  1398. return -EINVAL;
  1399. }
  1400. if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
  1401. return -EINVAL;
  1402. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  1403. if (IS_ERR(mailbox))
  1404. return PTR_ERR(mailbox);
  1405. ctrl = mailbox->buf;
  1406. ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
  1407. flow_attr->priority);
  1408. ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
  1409. ctrl->port = flow_attr->port;
  1410. ctrl->qpn = cpu_to_be32(qp->qp_num);
  1411. ib_flow = flow_attr + 1;
  1412. size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  1413. /* Add default flows */
  1414. default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
  1415. if (default_flow >= 0) {
  1416. ret = __mlx4_ib_create_default_rules(
  1417. mdev, qp, default_table + default_flow,
  1418. mailbox->buf + size);
  1419. if (ret < 0) {
  1420. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1421. return -EINVAL;
  1422. }
  1423. size += ret;
  1424. }
  1425. for (i = 0; i < flow_attr->num_of_specs; i++) {
  1426. ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
  1427. mailbox->buf + size);
  1428. if (ret < 0) {
  1429. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1430. return -EINVAL;
  1431. }
  1432. ib_flow += ((union ib_flow_spec *) ib_flow)->size;
  1433. size += ret;
  1434. }
  1435. if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
  1436. flow_attr->num_of_specs == 1) {
  1437. struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
  1438. enum ib_flow_spec_type header_spec =
  1439. ((union ib_flow_spec *)(flow_attr + 1))->type;
  1440. if (header_spec == IB_FLOW_SPEC_ETH)
  1441. mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
  1442. }
  1443. ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
  1444. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  1445. MLX4_CMD_NATIVE);
  1446. if (ret == -ENOMEM)
  1447. pr_err("mcg table is full. Fail to register network rule.\n");
  1448. else if (ret == -ENXIO)
  1449. pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
  1450. else if (ret)
  1451. pr_err("Invalid argument. Fail to register network rule.\n");
  1452. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1453. return ret;
  1454. }
  1455. static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
  1456. {
  1457. int err;
  1458. err = mlx4_cmd(dev, reg_id, 0, 0,
  1459. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  1460. MLX4_CMD_NATIVE);
  1461. if (err)
  1462. pr_err("Fail to detach network rule. registration id = 0x%llx\n",
  1463. reg_id);
  1464. return err;
  1465. }
  1466. static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1467. u64 *reg_id)
  1468. {
  1469. void *ib_flow;
  1470. union ib_flow_spec *ib_spec;
  1471. struct mlx4_dev *dev = to_mdev(qp->device)->dev;
  1472. int err = 0;
  1473. if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
  1474. dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
  1475. return 0; /* do nothing */
  1476. ib_flow = flow_attr + 1;
  1477. ib_spec = (union ib_flow_spec *)ib_flow;
  1478. if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
  1479. return 0; /* do nothing */
  1480. err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
  1481. flow_attr->port, qp->qp_num,
  1482. MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
  1483. reg_id);
  1484. return err;
  1485. }
  1486. static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
  1487. struct ib_flow_attr *flow_attr,
  1488. enum mlx4_net_trans_promisc_mode *type)
  1489. {
  1490. int err = 0;
  1491. if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
  1492. (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
  1493. (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
  1494. return -EOPNOTSUPP;
  1495. }
  1496. if (flow_attr->num_of_specs == 0) {
  1497. type[0] = MLX4_FS_MC_SNIFFER;
  1498. type[1] = MLX4_FS_UC_SNIFFER;
  1499. } else {
  1500. union ib_flow_spec *ib_spec;
  1501. ib_spec = (union ib_flow_spec *)(flow_attr + 1);
  1502. if (ib_spec->type != IB_FLOW_SPEC_ETH)
  1503. return -EINVAL;
  1504. /* if all is zero than MC and UC */
  1505. if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
  1506. type[0] = MLX4_FS_MC_SNIFFER;
  1507. type[1] = MLX4_FS_UC_SNIFFER;
  1508. } else {
  1509. u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
  1510. ib_spec->eth.mask.dst_mac[1],
  1511. ib_spec->eth.mask.dst_mac[2],
  1512. ib_spec->eth.mask.dst_mac[3],
  1513. ib_spec->eth.mask.dst_mac[4],
  1514. ib_spec->eth.mask.dst_mac[5]};
  1515. /* Above xor was only on MC bit, non empty mask is valid
  1516. * only if this bit is set and rest are zero.
  1517. */
  1518. if (!is_zero_ether_addr(&mac[0]))
  1519. return -EINVAL;
  1520. if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
  1521. type[0] = MLX4_FS_MC_SNIFFER;
  1522. else
  1523. type[0] = MLX4_FS_UC_SNIFFER;
  1524. }
  1525. }
  1526. return err;
  1527. }
  1528. static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
  1529. struct ib_flow_attr *flow_attr,
  1530. int domain)
  1531. {
  1532. int err = 0, i = 0, j = 0;
  1533. struct mlx4_ib_flow *mflow;
  1534. enum mlx4_net_trans_promisc_mode type[2];
  1535. struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
  1536. int is_bonded = mlx4_is_bonded(dev);
  1537. if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
  1538. return ERR_PTR(-EINVAL);
  1539. if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
  1540. (flow_attr->type != IB_FLOW_ATTR_NORMAL))
  1541. return ERR_PTR(-EOPNOTSUPP);
  1542. memset(type, 0, sizeof(type));
  1543. mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
  1544. if (!mflow) {
  1545. err = -ENOMEM;
  1546. goto err_free;
  1547. }
  1548. switch (flow_attr->type) {
  1549. case IB_FLOW_ATTR_NORMAL:
  1550. /* If dont trap flag (continue match) is set, under specific
  1551. * condition traffic be replicated to given qp,
  1552. * without stealing it
  1553. */
  1554. if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
  1555. err = mlx4_ib_add_dont_trap_rule(dev,
  1556. flow_attr,
  1557. type);
  1558. if (err)
  1559. goto err_free;
  1560. } else {
  1561. type[0] = MLX4_FS_REGULAR;
  1562. }
  1563. break;
  1564. case IB_FLOW_ATTR_ALL_DEFAULT:
  1565. type[0] = MLX4_FS_ALL_DEFAULT;
  1566. break;
  1567. case IB_FLOW_ATTR_MC_DEFAULT:
  1568. type[0] = MLX4_FS_MC_DEFAULT;
  1569. break;
  1570. case IB_FLOW_ATTR_SNIFFER:
  1571. type[0] = MLX4_FS_MIRROR_RX_PORT;
  1572. type[1] = MLX4_FS_MIRROR_SX_PORT;
  1573. break;
  1574. default:
  1575. err = -EINVAL;
  1576. goto err_free;
  1577. }
  1578. while (i < ARRAY_SIZE(type) && type[i]) {
  1579. err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
  1580. &mflow->reg_id[i].id);
  1581. if (err)
  1582. goto err_create_flow;
  1583. if (is_bonded) {
  1584. /* Application always sees one port so the mirror rule
  1585. * must be on port #2
  1586. */
  1587. flow_attr->port = 2;
  1588. err = __mlx4_ib_create_flow(qp, flow_attr,
  1589. domain, type[j],
  1590. &mflow->reg_id[j].mirror);
  1591. flow_attr->port = 1;
  1592. if (err)
  1593. goto err_create_flow;
  1594. j++;
  1595. }
  1596. i++;
  1597. }
  1598. if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  1599. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1600. &mflow->reg_id[i].id);
  1601. if (err)
  1602. goto err_create_flow;
  1603. if (is_bonded) {
  1604. flow_attr->port = 2;
  1605. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1606. &mflow->reg_id[j].mirror);
  1607. flow_attr->port = 1;
  1608. if (err)
  1609. goto err_create_flow;
  1610. j++;
  1611. }
  1612. /* function to create mirror rule */
  1613. i++;
  1614. }
  1615. return &mflow->ibflow;
  1616. err_create_flow:
  1617. while (i) {
  1618. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1619. mflow->reg_id[i].id);
  1620. i--;
  1621. }
  1622. while (j) {
  1623. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1624. mflow->reg_id[j].mirror);
  1625. j--;
  1626. }
  1627. err_free:
  1628. kfree(mflow);
  1629. return ERR_PTR(err);
  1630. }
  1631. static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
  1632. {
  1633. int err, ret = 0;
  1634. int i = 0;
  1635. struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
  1636. struct mlx4_ib_flow *mflow = to_mflow(flow_id);
  1637. while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
  1638. err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
  1639. if (err)
  1640. ret = err;
  1641. if (mflow->reg_id[i].mirror) {
  1642. err = __mlx4_ib_destroy_flow(mdev->dev,
  1643. mflow->reg_id[i].mirror);
  1644. if (err)
  1645. ret = err;
  1646. }
  1647. i++;
  1648. }
  1649. kfree(mflow);
  1650. return ret;
  1651. }
  1652. static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1653. {
  1654. int err;
  1655. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1656. struct mlx4_dev *dev = mdev->dev;
  1657. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1658. struct mlx4_ib_steering *ib_steering = NULL;
  1659. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1660. struct mlx4_flow_reg_id reg_id;
  1661. if (mdev->dev->caps.steering_mode ==
  1662. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1663. ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
  1664. if (!ib_steering)
  1665. return -ENOMEM;
  1666. }
  1667. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
  1668. !!(mqp->flags &
  1669. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1670. prot, &reg_id.id);
  1671. if (err) {
  1672. pr_err("multicast attach op failed, err %d\n", err);
  1673. goto err_malloc;
  1674. }
  1675. reg_id.mirror = 0;
  1676. if (mlx4_is_bonded(dev)) {
  1677. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
  1678. (mqp->port == 1) ? 2 : 1,
  1679. !!(mqp->flags &
  1680. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1681. prot, &reg_id.mirror);
  1682. if (err)
  1683. goto err_add;
  1684. }
  1685. err = add_gid_entry(ibqp, gid);
  1686. if (err)
  1687. goto err_add;
  1688. if (ib_steering) {
  1689. memcpy(ib_steering->gid.raw, gid->raw, 16);
  1690. ib_steering->reg_id = reg_id;
  1691. mutex_lock(&mqp->mutex);
  1692. list_add(&ib_steering->list, &mqp->steering_rules);
  1693. mutex_unlock(&mqp->mutex);
  1694. }
  1695. return 0;
  1696. err_add:
  1697. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1698. prot, reg_id.id);
  1699. if (reg_id.mirror)
  1700. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1701. prot, reg_id.mirror);
  1702. err_malloc:
  1703. kfree(ib_steering);
  1704. return err;
  1705. }
  1706. static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
  1707. {
  1708. struct mlx4_ib_gid_entry *ge;
  1709. struct mlx4_ib_gid_entry *tmp;
  1710. struct mlx4_ib_gid_entry *ret = NULL;
  1711. list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
  1712. if (!memcmp(raw, ge->gid.raw, 16)) {
  1713. ret = ge;
  1714. break;
  1715. }
  1716. }
  1717. return ret;
  1718. }
  1719. static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1720. {
  1721. int err;
  1722. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1723. struct mlx4_dev *dev = mdev->dev;
  1724. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1725. struct net_device *ndev;
  1726. struct mlx4_ib_gid_entry *ge;
  1727. struct mlx4_flow_reg_id reg_id = {0, 0};
  1728. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1729. if (mdev->dev->caps.steering_mode ==
  1730. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1731. struct mlx4_ib_steering *ib_steering;
  1732. mutex_lock(&mqp->mutex);
  1733. list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
  1734. if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
  1735. list_del(&ib_steering->list);
  1736. break;
  1737. }
  1738. }
  1739. mutex_unlock(&mqp->mutex);
  1740. if (&ib_steering->list == &mqp->steering_rules) {
  1741. pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
  1742. return -EINVAL;
  1743. }
  1744. reg_id = ib_steering->reg_id;
  1745. kfree(ib_steering);
  1746. }
  1747. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1748. prot, reg_id.id);
  1749. if (err)
  1750. return err;
  1751. if (mlx4_is_bonded(dev)) {
  1752. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1753. prot, reg_id.mirror);
  1754. if (err)
  1755. return err;
  1756. }
  1757. mutex_lock(&mqp->mutex);
  1758. ge = find_gid_entry(mqp, gid->raw);
  1759. if (ge) {
  1760. spin_lock_bh(&mdev->iboe.lock);
  1761. ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
  1762. if (ndev)
  1763. dev_hold(ndev);
  1764. spin_unlock_bh(&mdev->iboe.lock);
  1765. if (ndev)
  1766. dev_put(ndev);
  1767. list_del(&ge->list);
  1768. kfree(ge);
  1769. } else
  1770. pr_warn("could not find mgid entry\n");
  1771. mutex_unlock(&mqp->mutex);
  1772. return 0;
  1773. }
  1774. static int init_node_data(struct mlx4_ib_dev *dev)
  1775. {
  1776. struct ib_smp *in_mad = NULL;
  1777. struct ib_smp *out_mad = NULL;
  1778. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  1779. int err = -ENOMEM;
  1780. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  1781. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  1782. if (!in_mad || !out_mad)
  1783. goto out;
  1784. init_query_mad(in_mad);
  1785. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  1786. if (mlx4_is_master(dev->dev))
  1787. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  1788. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1789. if (err)
  1790. goto out;
  1791. memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
  1792. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  1793. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1794. if (err)
  1795. goto out;
  1796. dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
  1797. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  1798. out:
  1799. kfree(in_mad);
  1800. kfree(out_mad);
  1801. return err;
  1802. }
  1803. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  1804. char *buf)
  1805. {
  1806. struct mlx4_ib_dev *dev =
  1807. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1808. return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
  1809. }
  1810. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  1811. char *buf)
  1812. {
  1813. struct mlx4_ib_dev *dev =
  1814. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1815. return sprintf(buf, "%x\n", dev->dev->rev_id);
  1816. }
  1817. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  1818. char *buf)
  1819. {
  1820. struct mlx4_ib_dev *dev =
  1821. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1822. return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
  1823. dev->dev->board_id);
  1824. }
  1825. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1826. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1827. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  1828. static struct device_attribute *mlx4_class_attributes[] = {
  1829. &dev_attr_hw_rev,
  1830. &dev_attr_hca_type,
  1831. &dev_attr_board_id
  1832. };
  1833. struct diag_counter {
  1834. const char *name;
  1835. u32 offset;
  1836. };
  1837. #define DIAG_COUNTER(_name, _offset) \
  1838. { .name = #_name, .offset = _offset }
  1839. static const struct diag_counter diag_basic[] = {
  1840. DIAG_COUNTER(rq_num_lle, 0x00),
  1841. DIAG_COUNTER(sq_num_lle, 0x04),
  1842. DIAG_COUNTER(rq_num_lqpoe, 0x08),
  1843. DIAG_COUNTER(sq_num_lqpoe, 0x0C),
  1844. DIAG_COUNTER(rq_num_lpe, 0x18),
  1845. DIAG_COUNTER(sq_num_lpe, 0x1C),
  1846. DIAG_COUNTER(rq_num_wrfe, 0x20),
  1847. DIAG_COUNTER(sq_num_wrfe, 0x24),
  1848. DIAG_COUNTER(sq_num_mwbe, 0x2C),
  1849. DIAG_COUNTER(sq_num_bre, 0x34),
  1850. DIAG_COUNTER(sq_num_rire, 0x44),
  1851. DIAG_COUNTER(rq_num_rire, 0x48),
  1852. DIAG_COUNTER(sq_num_rae, 0x4C),
  1853. DIAG_COUNTER(rq_num_rae, 0x50),
  1854. DIAG_COUNTER(sq_num_roe, 0x54),
  1855. DIAG_COUNTER(sq_num_tree, 0x5C),
  1856. DIAG_COUNTER(sq_num_rree, 0x64),
  1857. DIAG_COUNTER(rq_num_rnr, 0x68),
  1858. DIAG_COUNTER(sq_num_rnr, 0x6C),
  1859. DIAG_COUNTER(rq_num_oos, 0x100),
  1860. DIAG_COUNTER(sq_num_oos, 0x104),
  1861. };
  1862. static const struct diag_counter diag_ext[] = {
  1863. DIAG_COUNTER(rq_num_dup, 0x130),
  1864. DIAG_COUNTER(sq_num_to, 0x134),
  1865. };
  1866. static const struct diag_counter diag_device_only[] = {
  1867. DIAG_COUNTER(num_cqovf, 0x1A0),
  1868. DIAG_COUNTER(rq_num_udsdprd, 0x118),
  1869. };
  1870. static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
  1871. u8 port_num)
  1872. {
  1873. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1874. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1875. if (!diag[!!port_num].name)
  1876. return NULL;
  1877. return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
  1878. diag[!!port_num].num_counters,
  1879. RDMA_HW_STATS_DEFAULT_LIFESPAN);
  1880. }
  1881. static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
  1882. struct rdma_hw_stats *stats,
  1883. u8 port, int index)
  1884. {
  1885. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1886. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1887. u32 hw_value[ARRAY_SIZE(diag_device_only) +
  1888. ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
  1889. int ret;
  1890. int i;
  1891. ret = mlx4_query_diag_counters(dev->dev,
  1892. MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
  1893. diag[!!port].offset, hw_value,
  1894. diag[!!port].num_counters, port);
  1895. if (ret)
  1896. return ret;
  1897. for (i = 0; i < diag[!!port].num_counters; i++)
  1898. stats->value[i] = hw_value[i];
  1899. return diag[!!port].num_counters;
  1900. }
  1901. static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
  1902. const char ***name,
  1903. u32 **offset,
  1904. u32 *num,
  1905. bool port)
  1906. {
  1907. u32 num_counters;
  1908. num_counters = ARRAY_SIZE(diag_basic);
  1909. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
  1910. num_counters += ARRAY_SIZE(diag_ext);
  1911. if (!port)
  1912. num_counters += ARRAY_SIZE(diag_device_only);
  1913. *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
  1914. if (!*name)
  1915. return -ENOMEM;
  1916. *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
  1917. if (!*offset)
  1918. goto err_name;
  1919. *num = num_counters;
  1920. return 0;
  1921. err_name:
  1922. kfree(*name);
  1923. return -ENOMEM;
  1924. }
  1925. static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
  1926. const char **name,
  1927. u32 *offset,
  1928. bool port)
  1929. {
  1930. int i;
  1931. int j;
  1932. for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
  1933. name[i] = diag_basic[i].name;
  1934. offset[i] = diag_basic[i].offset;
  1935. }
  1936. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
  1937. for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
  1938. name[j] = diag_ext[i].name;
  1939. offset[j] = diag_ext[i].offset;
  1940. }
  1941. }
  1942. if (!port) {
  1943. for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
  1944. name[j] = diag_device_only[i].name;
  1945. offset[j] = diag_device_only[i].offset;
  1946. }
  1947. }
  1948. }
  1949. static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
  1950. {
  1951. struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
  1952. int i;
  1953. int ret;
  1954. bool per_port = !!(ibdev->dev->caps.flags2 &
  1955. MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
  1956. if (mlx4_is_slave(ibdev->dev))
  1957. return 0;
  1958. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1959. /* i == 1 means we are building port counters */
  1960. if (i && !per_port)
  1961. continue;
  1962. ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
  1963. &diag[i].offset,
  1964. &diag[i].num_counters, i);
  1965. if (ret)
  1966. goto err_alloc;
  1967. mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
  1968. diag[i].offset, i);
  1969. }
  1970. ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
  1971. ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
  1972. return 0;
  1973. err_alloc:
  1974. if (i) {
  1975. kfree(diag[i - 1].name);
  1976. kfree(diag[i - 1].offset);
  1977. }
  1978. return ret;
  1979. }
  1980. static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
  1981. {
  1982. int i;
  1983. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1984. kfree(ibdev->diag_counters[i].offset);
  1985. kfree(ibdev->diag_counters[i].name);
  1986. }
  1987. }
  1988. #define MLX4_IB_INVALID_MAC ((u64)-1)
  1989. static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
  1990. struct net_device *dev,
  1991. int port)
  1992. {
  1993. u64 new_smac = 0;
  1994. u64 release_mac = MLX4_IB_INVALID_MAC;
  1995. struct mlx4_ib_qp *qp;
  1996. read_lock(&dev_base_lock);
  1997. new_smac = mlx4_mac_to_u64(dev->dev_addr);
  1998. read_unlock(&dev_base_lock);
  1999. atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
  2000. /* no need for update QP1 and mac registration in non-SRIOV */
  2001. if (!mlx4_is_mfunc(ibdev->dev))
  2002. return;
  2003. mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
  2004. qp = ibdev->qp1_proxy[port - 1];
  2005. if (qp) {
  2006. int new_smac_index;
  2007. u64 old_smac;
  2008. struct mlx4_update_qp_params update_params;
  2009. mutex_lock(&qp->mutex);
  2010. old_smac = qp->pri.smac;
  2011. if (new_smac == old_smac)
  2012. goto unlock;
  2013. new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
  2014. if (new_smac_index < 0)
  2015. goto unlock;
  2016. update_params.smac_index = new_smac_index;
  2017. if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
  2018. &update_params)) {
  2019. release_mac = new_smac;
  2020. goto unlock;
  2021. }
  2022. /* if old port was zero, no mac was yet registered for this QP */
  2023. if (qp->pri.smac_port)
  2024. release_mac = old_smac;
  2025. qp->pri.smac = new_smac;
  2026. qp->pri.smac_port = port;
  2027. qp->pri.smac_index = new_smac_index;
  2028. }
  2029. unlock:
  2030. if (release_mac != MLX4_IB_INVALID_MAC)
  2031. mlx4_unregister_mac(ibdev->dev, port, release_mac);
  2032. if (qp)
  2033. mutex_unlock(&qp->mutex);
  2034. mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
  2035. }
  2036. static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
  2037. struct net_device *dev,
  2038. unsigned long event)
  2039. {
  2040. struct mlx4_ib_iboe *iboe;
  2041. int update_qps_port = -1;
  2042. int port;
  2043. ASSERT_RTNL();
  2044. iboe = &ibdev->iboe;
  2045. spin_lock_bh(&iboe->lock);
  2046. mlx4_foreach_ib_transport_port(port, ibdev->dev) {
  2047. iboe->netdevs[port - 1] =
  2048. mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
  2049. if (dev == iboe->netdevs[port - 1] &&
  2050. (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
  2051. event == NETDEV_UP || event == NETDEV_CHANGE))
  2052. update_qps_port = port;
  2053. }
  2054. spin_unlock_bh(&iboe->lock);
  2055. if (update_qps_port > 0)
  2056. mlx4_ib_update_qps(ibdev, dev, update_qps_port);
  2057. }
  2058. static int mlx4_ib_netdev_event(struct notifier_block *this,
  2059. unsigned long event, void *ptr)
  2060. {
  2061. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  2062. struct mlx4_ib_dev *ibdev;
  2063. if (!net_eq(dev_net(dev), &init_net))
  2064. return NOTIFY_DONE;
  2065. ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
  2066. mlx4_ib_scan_netdevs(ibdev, dev, event);
  2067. return NOTIFY_DONE;
  2068. }
  2069. static void init_pkeys(struct mlx4_ib_dev *ibdev)
  2070. {
  2071. int port;
  2072. int slave;
  2073. int i;
  2074. if (mlx4_is_master(ibdev->dev)) {
  2075. for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
  2076. ++slave) {
  2077. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  2078. for (i = 0;
  2079. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  2080. ++i) {
  2081. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
  2082. /* master has the identity virt2phys pkey mapping */
  2083. (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
  2084. ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
  2085. mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
  2086. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
  2087. }
  2088. }
  2089. }
  2090. /* initialize pkey cache */
  2091. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  2092. for (i = 0;
  2093. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  2094. ++i)
  2095. ibdev->pkeys.phys_pkey_cache[port-1][i] =
  2096. (i) ? 0 : 0xFFFF;
  2097. }
  2098. }
  2099. }
  2100. static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2101. {
  2102. int i, j, eq = 0, total_eqs = 0;
  2103. ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
  2104. sizeof(ibdev->eq_table[0]), GFP_KERNEL);
  2105. if (!ibdev->eq_table)
  2106. return;
  2107. for (i = 1; i <= dev->caps.num_ports; i++) {
  2108. for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
  2109. j++, total_eqs++) {
  2110. if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
  2111. continue;
  2112. ibdev->eq_table[eq] = total_eqs;
  2113. if (!mlx4_assign_eq(dev, i,
  2114. &ibdev->eq_table[eq]))
  2115. eq++;
  2116. else
  2117. ibdev->eq_table[eq] = -1;
  2118. }
  2119. }
  2120. for (i = eq; i < dev->caps.num_comp_vectors;
  2121. ibdev->eq_table[i++] = -1)
  2122. ;
  2123. /* Advertise the new number of EQs to clients */
  2124. ibdev->ib_dev.num_comp_vectors = eq;
  2125. }
  2126. static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2127. {
  2128. int i;
  2129. int total_eqs = ibdev->ib_dev.num_comp_vectors;
  2130. /* no eqs were allocated */
  2131. if (!ibdev->eq_table)
  2132. return;
  2133. /* Reset the advertised EQ number */
  2134. ibdev->ib_dev.num_comp_vectors = 0;
  2135. for (i = 0; i < total_eqs; i++)
  2136. mlx4_release_eq(dev, ibdev->eq_table[i]);
  2137. kfree(ibdev->eq_table);
  2138. ibdev->eq_table = NULL;
  2139. }
  2140. static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
  2141. struct ib_port_immutable *immutable)
  2142. {
  2143. struct ib_port_attr attr;
  2144. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  2145. int err;
  2146. if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
  2147. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  2148. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2149. } else {
  2150. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
  2151. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  2152. if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  2153. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
  2154. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  2155. immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
  2156. if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
  2157. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
  2158. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2159. }
  2160. err = ib_query_port(ibdev, port_num, &attr);
  2161. if (err)
  2162. return err;
  2163. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2164. immutable->gid_tbl_len = attr.gid_tbl_len;
  2165. return 0;
  2166. }
  2167. static void get_fw_ver_str(struct ib_device *device, char *str)
  2168. {
  2169. struct mlx4_ib_dev *dev =
  2170. container_of(device, struct mlx4_ib_dev, ib_dev);
  2171. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
  2172. (int) (dev->dev->caps.fw_ver >> 32),
  2173. (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
  2174. (int) dev->dev->caps.fw_ver & 0xffff);
  2175. }
  2176. static void *mlx4_ib_add(struct mlx4_dev *dev)
  2177. {
  2178. struct mlx4_ib_dev *ibdev;
  2179. int num_ports = 0;
  2180. int i, j;
  2181. int err;
  2182. struct mlx4_ib_iboe *iboe;
  2183. int ib_num_ports = 0;
  2184. int num_req_counters;
  2185. int allocated;
  2186. u32 counter_index;
  2187. struct counter_index *new_counter_index = NULL;
  2188. pr_info_once("%s", mlx4_ib_version);
  2189. num_ports = 0;
  2190. mlx4_foreach_ib_transport_port(i, dev)
  2191. num_ports++;
  2192. /* No point in registering a device with no ports... */
  2193. if (num_ports == 0)
  2194. return NULL;
  2195. ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
  2196. if (!ibdev) {
  2197. dev_err(&dev->persist->pdev->dev,
  2198. "Device struct alloc failed\n");
  2199. return NULL;
  2200. }
  2201. iboe = &ibdev->iboe;
  2202. if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
  2203. goto err_dealloc;
  2204. if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
  2205. goto err_pd;
  2206. ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
  2207. PAGE_SIZE);
  2208. if (!ibdev->uar_map)
  2209. goto err_uar;
  2210. MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
  2211. ibdev->dev = dev;
  2212. ibdev->bond_next_port = 0;
  2213. strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
  2214. ibdev->ib_dev.owner = THIS_MODULE;
  2215. ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
  2216. ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
  2217. ibdev->num_ports = num_ports;
  2218. ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
  2219. 1 : ibdev->num_ports;
  2220. ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
  2221. ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
  2222. ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
  2223. ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
  2224. ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
  2225. if (dev->caps.userspace_caps)
  2226. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
  2227. else
  2228. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
  2229. ibdev->ib_dev.uverbs_cmd_mask =
  2230. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2231. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2232. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2233. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2234. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2235. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2236. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  2237. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2238. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2239. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2240. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  2241. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2242. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2243. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2244. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2245. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2246. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  2247. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  2248. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  2249. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  2250. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  2251. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  2252. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  2253. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  2254. ibdev->ib_dev.query_device = mlx4_ib_query_device;
  2255. ibdev->ib_dev.query_port = mlx4_ib_query_port;
  2256. ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
  2257. ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
  2258. ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
  2259. ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
  2260. ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
  2261. ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
  2262. ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
  2263. ibdev->ib_dev.mmap = mlx4_ib_mmap;
  2264. ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
  2265. ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
  2266. ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
  2267. ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
  2268. ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
  2269. ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
  2270. ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
  2271. ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
  2272. ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
  2273. ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
  2274. ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
  2275. ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
  2276. ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
  2277. ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
  2278. ibdev->ib_dev.post_send = mlx4_ib_post_send;
  2279. ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
  2280. ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
  2281. ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
  2282. ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
  2283. ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
  2284. ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
  2285. ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
  2286. ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
  2287. ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
  2288. ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
  2289. ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
  2290. ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
  2291. ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
  2292. ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
  2293. ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
  2294. ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
  2295. ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
  2296. ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
  2297. ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
  2298. if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
  2299. ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
  2300. IB_LINK_LAYER_ETHERNET) ||
  2301. (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
  2302. IB_LINK_LAYER_ETHERNET))) {
  2303. ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
  2304. ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
  2305. ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
  2306. ibdev->ib_dev.create_rwq_ind_table =
  2307. mlx4_ib_create_rwq_ind_table;
  2308. ibdev->ib_dev.destroy_rwq_ind_table =
  2309. mlx4_ib_destroy_rwq_ind_table;
  2310. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2311. (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
  2312. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
  2313. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
  2314. (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
  2315. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
  2316. }
  2317. if (!mlx4_is_slave(ibdev->dev)) {
  2318. ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
  2319. ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
  2320. ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
  2321. ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
  2322. }
  2323. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
  2324. dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  2325. ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
  2326. ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
  2327. ibdev->ib_dev.uverbs_cmd_mask |=
  2328. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  2329. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  2330. }
  2331. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
  2332. ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
  2333. ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
  2334. ibdev->ib_dev.uverbs_cmd_mask |=
  2335. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  2336. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  2337. }
  2338. if (check_flow_steering_support(dev)) {
  2339. ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
  2340. ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
  2341. ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
  2342. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2343. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  2344. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  2345. }
  2346. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2347. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  2348. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
  2349. (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
  2350. mlx4_ib_alloc_eqs(dev, ibdev);
  2351. spin_lock_init(&iboe->lock);
  2352. if (init_node_data(ibdev))
  2353. goto err_map;
  2354. mlx4_init_sl2vl_tbl(ibdev);
  2355. for (i = 0; i < ibdev->num_ports; ++i) {
  2356. mutex_init(&ibdev->counters_table[i].mutex);
  2357. INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
  2358. }
  2359. num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
  2360. for (i = 0; i < num_req_counters; ++i) {
  2361. mutex_init(&ibdev->qp1_proxy_lock[i]);
  2362. allocated = 0;
  2363. if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
  2364. IB_LINK_LAYER_ETHERNET) {
  2365. err = mlx4_counter_alloc(ibdev->dev, &counter_index,
  2366. MLX4_RES_USAGE_DRIVER);
  2367. /* if failed to allocate a new counter, use default */
  2368. if (err)
  2369. counter_index =
  2370. mlx4_get_default_counter_index(dev,
  2371. i + 1);
  2372. else
  2373. allocated = 1;
  2374. } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
  2375. counter_index = mlx4_get_default_counter_index(dev,
  2376. i + 1);
  2377. }
  2378. new_counter_index = kmalloc(sizeof(*new_counter_index),
  2379. GFP_KERNEL);
  2380. if (!new_counter_index) {
  2381. if (allocated)
  2382. mlx4_counter_free(ibdev->dev, counter_index);
  2383. goto err_counter;
  2384. }
  2385. new_counter_index->index = counter_index;
  2386. new_counter_index->allocated = allocated;
  2387. list_add_tail(&new_counter_index->list,
  2388. &ibdev->counters_table[i].counters_list);
  2389. ibdev->counters_table[i].default_counter = counter_index;
  2390. pr_info("counter index %d for port %d allocated %d\n",
  2391. counter_index, i + 1, allocated);
  2392. }
  2393. if (mlx4_is_bonded(dev))
  2394. for (i = 1; i < ibdev->num_ports ; ++i) {
  2395. new_counter_index =
  2396. kmalloc(sizeof(struct counter_index),
  2397. GFP_KERNEL);
  2398. if (!new_counter_index)
  2399. goto err_counter;
  2400. new_counter_index->index = counter_index;
  2401. new_counter_index->allocated = 0;
  2402. list_add_tail(&new_counter_index->list,
  2403. &ibdev->counters_table[i].counters_list);
  2404. ibdev->counters_table[i].default_counter =
  2405. counter_index;
  2406. }
  2407. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2408. ib_num_ports++;
  2409. spin_lock_init(&ibdev->sm_lock);
  2410. mutex_init(&ibdev->cap_mask_mutex);
  2411. INIT_LIST_HEAD(&ibdev->qp_list);
  2412. spin_lock_init(&ibdev->reset_flow_resource_lock);
  2413. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
  2414. ib_num_ports) {
  2415. ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
  2416. err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
  2417. MLX4_IB_UC_STEER_QPN_ALIGN,
  2418. &ibdev->steer_qpn_base, 0,
  2419. MLX4_RES_USAGE_DRIVER);
  2420. if (err)
  2421. goto err_counter;
  2422. ibdev->ib_uc_qpns_bitmap =
  2423. kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
  2424. sizeof(long),
  2425. GFP_KERNEL);
  2426. if (!ibdev->ib_uc_qpns_bitmap)
  2427. goto err_steer_qp_release;
  2428. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
  2429. bitmap_zero(ibdev->ib_uc_qpns_bitmap,
  2430. ibdev->steer_qpn_count);
  2431. err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
  2432. dev, ibdev->steer_qpn_base,
  2433. ibdev->steer_qpn_base +
  2434. ibdev->steer_qpn_count - 1);
  2435. if (err)
  2436. goto err_steer_free_bitmap;
  2437. } else {
  2438. bitmap_fill(ibdev->ib_uc_qpns_bitmap,
  2439. ibdev->steer_qpn_count);
  2440. }
  2441. }
  2442. for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
  2443. atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
  2444. if (mlx4_ib_alloc_diag_counters(ibdev))
  2445. goto err_steer_free_bitmap;
  2446. if (ib_register_device(&ibdev->ib_dev, NULL))
  2447. goto err_diag_counters;
  2448. if (mlx4_ib_mad_init(ibdev))
  2449. goto err_reg;
  2450. if (mlx4_ib_init_sriov(ibdev))
  2451. goto err_mad;
  2452. if (!iboe->nb.notifier_call) {
  2453. iboe->nb.notifier_call = mlx4_ib_netdev_event;
  2454. err = register_netdevice_notifier(&iboe->nb);
  2455. if (err) {
  2456. iboe->nb.notifier_call = NULL;
  2457. goto err_notif;
  2458. }
  2459. }
  2460. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
  2461. err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
  2462. if (err)
  2463. goto err_notif;
  2464. }
  2465. for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
  2466. if (device_create_file(&ibdev->ib_dev.dev,
  2467. mlx4_class_attributes[j]))
  2468. goto err_notif;
  2469. }
  2470. ibdev->ib_active = true;
  2471. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2472. devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
  2473. &ibdev->ib_dev);
  2474. if (mlx4_is_mfunc(ibdev->dev))
  2475. init_pkeys(ibdev);
  2476. /* create paravirt contexts for any VFs which are active */
  2477. if (mlx4_is_master(ibdev->dev)) {
  2478. for (j = 0; j < MLX4_MFUNC_MAX; j++) {
  2479. if (j == mlx4_master_func_num(ibdev->dev))
  2480. continue;
  2481. if (mlx4_is_slave_active(ibdev->dev, j))
  2482. do_slave_init(ibdev, j, 1);
  2483. }
  2484. }
  2485. return ibdev;
  2486. err_notif:
  2487. if (ibdev->iboe.nb.notifier_call) {
  2488. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2489. pr_warn("failure unregistering notifier\n");
  2490. ibdev->iboe.nb.notifier_call = NULL;
  2491. }
  2492. flush_workqueue(wq);
  2493. mlx4_ib_close_sriov(ibdev);
  2494. err_mad:
  2495. mlx4_ib_mad_cleanup(ibdev);
  2496. err_reg:
  2497. ib_unregister_device(&ibdev->ib_dev);
  2498. err_diag_counters:
  2499. mlx4_ib_diag_cleanup(ibdev);
  2500. err_steer_free_bitmap:
  2501. kfree(ibdev->ib_uc_qpns_bitmap);
  2502. err_steer_qp_release:
  2503. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  2504. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2505. ibdev->steer_qpn_count);
  2506. err_counter:
  2507. for (i = 0; i < ibdev->num_ports; ++i)
  2508. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
  2509. err_map:
  2510. mlx4_ib_free_eqs(dev, ibdev);
  2511. iounmap(ibdev->uar_map);
  2512. err_uar:
  2513. mlx4_uar_free(dev, &ibdev->priv_uar);
  2514. err_pd:
  2515. mlx4_pd_free(dev, ibdev->priv_pdn);
  2516. err_dealloc:
  2517. ib_dealloc_device(&ibdev->ib_dev);
  2518. return NULL;
  2519. }
  2520. int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
  2521. {
  2522. int offset;
  2523. WARN_ON(!dev->ib_uc_qpns_bitmap);
  2524. offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
  2525. dev->steer_qpn_count,
  2526. get_count_order(count));
  2527. if (offset < 0)
  2528. return offset;
  2529. *qpn = dev->steer_qpn_base + offset;
  2530. return 0;
  2531. }
  2532. void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
  2533. {
  2534. if (!qpn ||
  2535. dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
  2536. return;
  2537. BUG_ON(qpn < dev->steer_qpn_base);
  2538. bitmap_release_region(dev->ib_uc_qpns_bitmap,
  2539. qpn - dev->steer_qpn_base,
  2540. get_count_order(count));
  2541. }
  2542. int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  2543. int is_attach)
  2544. {
  2545. int err;
  2546. size_t flow_size;
  2547. struct ib_flow_attr *flow = NULL;
  2548. struct ib_flow_spec_ib *ib_spec;
  2549. if (is_attach) {
  2550. flow_size = sizeof(struct ib_flow_attr) +
  2551. sizeof(struct ib_flow_spec_ib);
  2552. flow = kzalloc(flow_size, GFP_KERNEL);
  2553. if (!flow)
  2554. return -ENOMEM;
  2555. flow->port = mqp->port;
  2556. flow->num_of_specs = 1;
  2557. flow->size = flow_size;
  2558. ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
  2559. ib_spec->type = IB_FLOW_SPEC_IB;
  2560. ib_spec->size = sizeof(struct ib_flow_spec_ib);
  2561. /* Add an empty rule for IB L2 */
  2562. memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
  2563. err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
  2564. IB_FLOW_DOMAIN_NIC,
  2565. MLX4_FS_REGULAR,
  2566. &mqp->reg_id);
  2567. } else {
  2568. err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
  2569. }
  2570. kfree(flow);
  2571. return err;
  2572. }
  2573. static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
  2574. {
  2575. struct mlx4_ib_dev *ibdev = ibdev_ptr;
  2576. int p;
  2577. int i;
  2578. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2579. devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
  2580. ibdev->ib_active = false;
  2581. flush_workqueue(wq);
  2582. mlx4_ib_close_sriov(ibdev);
  2583. mlx4_ib_mad_cleanup(ibdev);
  2584. ib_unregister_device(&ibdev->ib_dev);
  2585. mlx4_ib_diag_cleanup(ibdev);
  2586. if (ibdev->iboe.nb.notifier_call) {
  2587. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2588. pr_warn("failure unregistering notifier\n");
  2589. ibdev->iboe.nb.notifier_call = NULL;
  2590. }
  2591. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
  2592. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2593. ibdev->steer_qpn_count);
  2594. kfree(ibdev->ib_uc_qpns_bitmap);
  2595. }
  2596. iounmap(ibdev->uar_map);
  2597. for (p = 0; p < ibdev->num_ports; ++p)
  2598. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
  2599. mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
  2600. mlx4_CLOSE_PORT(dev, p);
  2601. mlx4_ib_free_eqs(dev, ibdev);
  2602. mlx4_uar_free(dev, &ibdev->priv_uar);
  2603. mlx4_pd_free(dev, ibdev->priv_pdn);
  2604. ib_dealloc_device(&ibdev->ib_dev);
  2605. }
  2606. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
  2607. {
  2608. struct mlx4_ib_demux_work **dm = NULL;
  2609. struct mlx4_dev *dev = ibdev->dev;
  2610. int i;
  2611. unsigned long flags;
  2612. struct mlx4_active_ports actv_ports;
  2613. unsigned int ports;
  2614. unsigned int first_port;
  2615. if (!mlx4_is_master(dev))
  2616. return;
  2617. actv_ports = mlx4_get_active_ports(dev, slave);
  2618. ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
  2619. first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
  2620. dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
  2621. if (!dm)
  2622. return;
  2623. for (i = 0; i < ports; i++) {
  2624. dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
  2625. if (!dm[i]) {
  2626. while (--i >= 0)
  2627. kfree(dm[i]);
  2628. goto out;
  2629. }
  2630. INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
  2631. dm[i]->port = first_port + i + 1;
  2632. dm[i]->slave = slave;
  2633. dm[i]->do_init = do_init;
  2634. dm[i]->dev = ibdev;
  2635. }
  2636. /* initialize or tear down tunnel QPs for the slave */
  2637. spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
  2638. if (!ibdev->sriov.is_going_down) {
  2639. for (i = 0; i < ports; i++)
  2640. queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
  2641. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2642. } else {
  2643. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2644. for (i = 0; i < ports; i++)
  2645. kfree(dm[i]);
  2646. }
  2647. out:
  2648. kfree(dm);
  2649. return;
  2650. }
  2651. static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
  2652. {
  2653. struct mlx4_ib_qp *mqp;
  2654. unsigned long flags_qp;
  2655. unsigned long flags_cq;
  2656. struct mlx4_ib_cq *send_mcq, *recv_mcq;
  2657. struct list_head cq_notify_list;
  2658. struct mlx4_cq *mcq;
  2659. unsigned long flags;
  2660. pr_warn("mlx4_ib_handle_catas_error was started\n");
  2661. INIT_LIST_HEAD(&cq_notify_list);
  2662. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  2663. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  2664. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  2665. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  2666. if (mqp->sq.tail != mqp->sq.head) {
  2667. send_mcq = to_mcq(mqp->ibqp.send_cq);
  2668. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  2669. if (send_mcq->mcq.comp &&
  2670. mqp->ibqp.send_cq->comp_handler) {
  2671. if (!send_mcq->mcq.reset_notify_added) {
  2672. send_mcq->mcq.reset_notify_added = 1;
  2673. list_add_tail(&send_mcq->mcq.reset_notify,
  2674. &cq_notify_list);
  2675. }
  2676. }
  2677. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  2678. }
  2679. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  2680. /* Now, handle the QP's receive queue */
  2681. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  2682. /* no handling is needed for SRQ */
  2683. if (!mqp->ibqp.srq) {
  2684. if (mqp->rq.tail != mqp->rq.head) {
  2685. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  2686. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  2687. if (recv_mcq->mcq.comp &&
  2688. mqp->ibqp.recv_cq->comp_handler) {
  2689. if (!recv_mcq->mcq.reset_notify_added) {
  2690. recv_mcq->mcq.reset_notify_added = 1;
  2691. list_add_tail(&recv_mcq->mcq.reset_notify,
  2692. &cq_notify_list);
  2693. }
  2694. }
  2695. spin_unlock_irqrestore(&recv_mcq->lock,
  2696. flags_cq);
  2697. }
  2698. }
  2699. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  2700. }
  2701. list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
  2702. mcq->comp(mcq);
  2703. }
  2704. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  2705. pr_warn("mlx4_ib_handle_catas_error ended\n");
  2706. }
  2707. static void handle_bonded_port_state_event(struct work_struct *work)
  2708. {
  2709. struct ib_event_work *ew =
  2710. container_of(work, struct ib_event_work, work);
  2711. struct mlx4_ib_dev *ibdev = ew->ib_dev;
  2712. enum ib_port_state bonded_port_state = IB_PORT_NOP;
  2713. int i;
  2714. struct ib_event ibev;
  2715. kfree(ew);
  2716. spin_lock_bh(&ibdev->iboe.lock);
  2717. for (i = 0; i < MLX4_MAX_PORTS; ++i) {
  2718. struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
  2719. enum ib_port_state curr_port_state;
  2720. if (!curr_netdev)
  2721. continue;
  2722. curr_port_state =
  2723. (netif_running(curr_netdev) &&
  2724. netif_carrier_ok(curr_netdev)) ?
  2725. IB_PORT_ACTIVE : IB_PORT_DOWN;
  2726. bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
  2727. curr_port_state : IB_PORT_ACTIVE;
  2728. }
  2729. spin_unlock_bh(&ibdev->iboe.lock);
  2730. ibev.device = &ibdev->ib_dev;
  2731. ibev.element.port_num = 1;
  2732. ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
  2733. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2734. ib_dispatch_event(&ibev);
  2735. }
  2736. void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
  2737. {
  2738. u64 sl2vl;
  2739. int err;
  2740. err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
  2741. if (err) {
  2742. pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
  2743. port, err);
  2744. sl2vl = 0;
  2745. }
  2746. atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
  2747. }
  2748. static void ib_sl2vl_update_work(struct work_struct *work)
  2749. {
  2750. struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
  2751. struct mlx4_ib_dev *mdev = ew->ib_dev;
  2752. int port = ew->port;
  2753. mlx4_ib_sl2vl_update(mdev, port);
  2754. kfree(ew);
  2755. }
  2756. void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
  2757. int port)
  2758. {
  2759. struct ib_event_work *ew;
  2760. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2761. if (ew) {
  2762. INIT_WORK(&ew->work, ib_sl2vl_update_work);
  2763. ew->port = port;
  2764. ew->ib_dev = ibdev;
  2765. queue_work(wq, &ew->work);
  2766. }
  2767. }
  2768. static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
  2769. enum mlx4_dev_event event, unsigned long param)
  2770. {
  2771. struct ib_event ibev;
  2772. struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
  2773. struct mlx4_eqe *eqe = NULL;
  2774. struct ib_event_work *ew;
  2775. int p = 0;
  2776. if (mlx4_is_bonded(dev) &&
  2777. ((event == MLX4_DEV_EVENT_PORT_UP) ||
  2778. (event == MLX4_DEV_EVENT_PORT_DOWN))) {
  2779. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2780. if (!ew)
  2781. return;
  2782. INIT_WORK(&ew->work, handle_bonded_port_state_event);
  2783. ew->ib_dev = ibdev;
  2784. queue_work(wq, &ew->work);
  2785. return;
  2786. }
  2787. if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
  2788. eqe = (struct mlx4_eqe *)param;
  2789. else
  2790. p = (int) param;
  2791. switch (event) {
  2792. case MLX4_DEV_EVENT_PORT_UP:
  2793. if (p > ibdev->num_ports)
  2794. return;
  2795. if (!mlx4_is_slave(dev) &&
  2796. rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
  2797. IB_LINK_LAYER_INFINIBAND) {
  2798. if (mlx4_is_master(dev))
  2799. mlx4_ib_invalidate_all_guid_record(ibdev, p);
  2800. if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
  2801. !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
  2802. mlx4_sched_ib_sl2vl_update_work(ibdev, p);
  2803. }
  2804. ibev.event = IB_EVENT_PORT_ACTIVE;
  2805. break;
  2806. case MLX4_DEV_EVENT_PORT_DOWN:
  2807. if (p > ibdev->num_ports)
  2808. return;
  2809. ibev.event = IB_EVENT_PORT_ERR;
  2810. break;
  2811. case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
  2812. ibdev->ib_active = false;
  2813. ibev.event = IB_EVENT_DEVICE_FATAL;
  2814. mlx4_ib_handle_catas_error(ibdev);
  2815. break;
  2816. case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
  2817. ew = kmalloc(sizeof *ew, GFP_ATOMIC);
  2818. if (!ew)
  2819. break;
  2820. INIT_WORK(&ew->work, handle_port_mgmt_change_event);
  2821. memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
  2822. ew->ib_dev = ibdev;
  2823. /* need to queue only for port owner, which uses GEN_EQE */
  2824. if (mlx4_is_master(dev))
  2825. queue_work(wq, &ew->work);
  2826. else
  2827. handle_port_mgmt_change_event(&ew->work);
  2828. return;
  2829. case MLX4_DEV_EVENT_SLAVE_INIT:
  2830. /* here, p is the slave id */
  2831. do_slave_init(ibdev, p, 1);
  2832. if (mlx4_is_master(dev)) {
  2833. int i;
  2834. for (i = 1; i <= ibdev->num_ports; i++) {
  2835. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2836. == IB_LINK_LAYER_INFINIBAND)
  2837. mlx4_ib_slave_alias_guid_event(ibdev,
  2838. p, i,
  2839. 1);
  2840. }
  2841. }
  2842. return;
  2843. case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
  2844. if (mlx4_is_master(dev)) {
  2845. int i;
  2846. for (i = 1; i <= ibdev->num_ports; i++) {
  2847. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2848. == IB_LINK_LAYER_INFINIBAND)
  2849. mlx4_ib_slave_alias_guid_event(ibdev,
  2850. p, i,
  2851. 0);
  2852. }
  2853. }
  2854. /* here, p is the slave id */
  2855. do_slave_init(ibdev, p, 0);
  2856. return;
  2857. default:
  2858. return;
  2859. }
  2860. ibev.device = ibdev_ptr;
  2861. ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
  2862. ib_dispatch_event(&ibev);
  2863. }
  2864. static struct mlx4_interface mlx4_ib_interface = {
  2865. .add = mlx4_ib_add,
  2866. .remove = mlx4_ib_remove,
  2867. .event = mlx4_ib_event,
  2868. .protocol = MLX4_PROT_IB_IPV6,
  2869. .flags = MLX4_INTFF_BONDING
  2870. };
  2871. static int __init mlx4_ib_init(void)
  2872. {
  2873. int err;
  2874. wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
  2875. if (!wq)
  2876. return -ENOMEM;
  2877. err = mlx4_ib_mcg_init();
  2878. if (err)
  2879. goto clean_wq;
  2880. err = mlx4_register_interface(&mlx4_ib_interface);
  2881. if (err)
  2882. goto clean_mcg;
  2883. return 0;
  2884. clean_mcg:
  2885. mlx4_ib_mcg_destroy();
  2886. clean_wq:
  2887. destroy_workqueue(wq);
  2888. return err;
  2889. }
  2890. static void __exit mlx4_ib_cleanup(void)
  2891. {
  2892. mlx4_unregister_interface(&mlx4_ib_interface);
  2893. mlx4_ib_mcg_destroy();
  2894. destroy_workqueue(wq);
  2895. }
  2896. module_init(mlx4_ib_init);
  2897. module_exit(mlx4_ib_cleanup);