coresight-tmc-etf.c 15 KB

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  1. /*
  2. * Copyright(C) 2016 Linaro Limited. All rights reserved.
  3. * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include <linux/circ_buf.h>
  18. #include <linux/coresight.h>
  19. #include <linux/perf_event.h>
  20. #include <linux/slab.h>
  21. #include "coresight-priv.h"
  22. #include "coresight-tmc.h"
  23. static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
  24. {
  25. CS_UNLOCK(drvdata->base);
  26. /* Wait for TMCSReady bit to be set */
  27. tmc_wait_for_tmcready(drvdata);
  28. writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
  29. writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
  30. TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
  31. TMC_FFCR_TRIGON_TRIGIN,
  32. drvdata->base + TMC_FFCR);
  33. writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
  34. tmc_enable_hw(drvdata);
  35. CS_LOCK(drvdata->base);
  36. }
  37. static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
  38. {
  39. bool lost = false;
  40. char *bufp;
  41. const u32 *barrier;
  42. u32 read_data, status;
  43. int i;
  44. /*
  45. * Get a hold of the status register and see if a wrap around
  46. * has occurred.
  47. */
  48. status = readl_relaxed(drvdata->base + TMC_STS);
  49. if (status & TMC_STS_FULL)
  50. lost = true;
  51. bufp = drvdata->buf;
  52. drvdata->len = 0;
  53. barrier = barrier_pkt;
  54. while (1) {
  55. for (i = 0; i < drvdata->memwidth; i++) {
  56. read_data = readl_relaxed(drvdata->base + TMC_RRD);
  57. if (read_data == 0xFFFFFFFF)
  58. return;
  59. if (lost && *barrier) {
  60. read_data = *barrier;
  61. barrier++;
  62. }
  63. memcpy(bufp, &read_data, 4);
  64. bufp += 4;
  65. drvdata->len += 4;
  66. }
  67. }
  68. }
  69. static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
  70. {
  71. CS_UNLOCK(drvdata->base);
  72. tmc_flush_and_stop(drvdata);
  73. /*
  74. * When operating in sysFS mode the content of the buffer needs to be
  75. * read before the TMC is disabled.
  76. */
  77. if (drvdata->mode == CS_MODE_SYSFS)
  78. tmc_etb_dump_hw(drvdata);
  79. tmc_disable_hw(drvdata);
  80. CS_LOCK(drvdata->base);
  81. }
  82. static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
  83. {
  84. CS_UNLOCK(drvdata->base);
  85. /* Wait for TMCSReady bit to be set */
  86. tmc_wait_for_tmcready(drvdata);
  87. writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
  88. writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
  89. drvdata->base + TMC_FFCR);
  90. writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
  91. tmc_enable_hw(drvdata);
  92. CS_LOCK(drvdata->base);
  93. }
  94. static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
  95. {
  96. CS_UNLOCK(drvdata->base);
  97. tmc_flush_and_stop(drvdata);
  98. tmc_disable_hw(drvdata);
  99. CS_LOCK(drvdata->base);
  100. }
  101. static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev)
  102. {
  103. int ret = 0;
  104. bool used = false;
  105. char *buf = NULL;
  106. unsigned long flags;
  107. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  108. /*
  109. * If we don't have a buffer release the lock and allocate memory.
  110. * Otherwise keep the lock and move along.
  111. */
  112. spin_lock_irqsave(&drvdata->spinlock, flags);
  113. if (!drvdata->buf) {
  114. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  115. /* Allocating the memory here while outside of the spinlock */
  116. buf = kzalloc(drvdata->size, GFP_KERNEL);
  117. if (!buf)
  118. return -ENOMEM;
  119. /* Let's try again */
  120. spin_lock_irqsave(&drvdata->spinlock, flags);
  121. }
  122. if (drvdata->reading) {
  123. ret = -EBUSY;
  124. goto out;
  125. }
  126. /*
  127. * In sysFS mode we can have multiple writers per sink. Since this
  128. * sink is already enabled no memory is needed and the HW need not be
  129. * touched.
  130. */
  131. if (drvdata->mode == CS_MODE_SYSFS)
  132. goto out;
  133. /*
  134. * If drvdata::buf isn't NULL, memory was allocated for a previous
  135. * trace run but wasn't read. If so simply zero-out the memory.
  136. * Otherwise use the memory allocated above.
  137. *
  138. * The memory is freed when users read the buffer using the
  139. * /dev/xyz.{etf|etb} interface. See tmc_read_unprepare_etf() for
  140. * details.
  141. */
  142. if (drvdata->buf) {
  143. memset(drvdata->buf, 0, drvdata->size);
  144. } else {
  145. used = true;
  146. drvdata->buf = buf;
  147. }
  148. drvdata->mode = CS_MODE_SYSFS;
  149. tmc_etb_enable_hw(drvdata);
  150. out:
  151. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  152. /* Free memory outside the spinlock if need be */
  153. if (!used)
  154. kfree(buf);
  155. return ret;
  156. }
  157. static int tmc_enable_etf_sink_perf(struct coresight_device *csdev)
  158. {
  159. int ret = 0;
  160. unsigned long flags;
  161. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  162. spin_lock_irqsave(&drvdata->spinlock, flags);
  163. if (drvdata->reading) {
  164. ret = -EINVAL;
  165. goto out;
  166. }
  167. /*
  168. * In Perf mode there can be only one writer per sink. There
  169. * is also no need to continue if the ETB/ETR is already operated
  170. * from sysFS.
  171. */
  172. if (drvdata->mode != CS_MODE_DISABLED) {
  173. ret = -EINVAL;
  174. goto out;
  175. }
  176. drvdata->mode = CS_MODE_PERF;
  177. tmc_etb_enable_hw(drvdata);
  178. out:
  179. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  180. return ret;
  181. }
  182. static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode)
  183. {
  184. int ret;
  185. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  186. switch (mode) {
  187. case CS_MODE_SYSFS:
  188. ret = tmc_enable_etf_sink_sysfs(csdev);
  189. break;
  190. case CS_MODE_PERF:
  191. ret = tmc_enable_etf_sink_perf(csdev);
  192. break;
  193. /* We shouldn't be here */
  194. default:
  195. ret = -EINVAL;
  196. break;
  197. }
  198. if (ret)
  199. return ret;
  200. dev_info(drvdata->dev, "TMC-ETB/ETF enabled\n");
  201. return 0;
  202. }
  203. static void tmc_disable_etf_sink(struct coresight_device *csdev)
  204. {
  205. unsigned long flags;
  206. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  207. spin_lock_irqsave(&drvdata->spinlock, flags);
  208. if (drvdata->reading) {
  209. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  210. return;
  211. }
  212. /* Disable the TMC only if it needs to */
  213. if (drvdata->mode != CS_MODE_DISABLED) {
  214. tmc_etb_disable_hw(drvdata);
  215. drvdata->mode = CS_MODE_DISABLED;
  216. }
  217. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  218. dev_info(drvdata->dev, "TMC-ETB/ETF disabled\n");
  219. }
  220. static int tmc_enable_etf_link(struct coresight_device *csdev,
  221. int inport, int outport)
  222. {
  223. unsigned long flags;
  224. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  225. spin_lock_irqsave(&drvdata->spinlock, flags);
  226. if (drvdata->reading) {
  227. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  228. return -EBUSY;
  229. }
  230. tmc_etf_enable_hw(drvdata);
  231. drvdata->mode = CS_MODE_SYSFS;
  232. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  233. dev_info(drvdata->dev, "TMC-ETF enabled\n");
  234. return 0;
  235. }
  236. static void tmc_disable_etf_link(struct coresight_device *csdev,
  237. int inport, int outport)
  238. {
  239. unsigned long flags;
  240. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  241. spin_lock_irqsave(&drvdata->spinlock, flags);
  242. if (drvdata->reading) {
  243. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  244. return;
  245. }
  246. tmc_etf_disable_hw(drvdata);
  247. drvdata->mode = CS_MODE_DISABLED;
  248. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  249. dev_info(drvdata->dev, "TMC-ETF disabled\n");
  250. }
  251. static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu,
  252. void **pages, int nr_pages, bool overwrite)
  253. {
  254. int node;
  255. struct cs_buffers *buf;
  256. if (cpu == -1)
  257. cpu = smp_processor_id();
  258. node = cpu_to_node(cpu);
  259. /* Allocate memory structure for interaction with Perf */
  260. buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
  261. if (!buf)
  262. return NULL;
  263. buf->snapshot = overwrite;
  264. buf->nr_pages = nr_pages;
  265. buf->data_pages = pages;
  266. return buf;
  267. }
  268. static void tmc_free_etf_buffer(void *config)
  269. {
  270. struct cs_buffers *buf = config;
  271. kfree(buf);
  272. }
  273. static int tmc_set_etf_buffer(struct coresight_device *csdev,
  274. struct perf_output_handle *handle,
  275. void *sink_config)
  276. {
  277. int ret = 0;
  278. unsigned long head;
  279. struct cs_buffers *buf = sink_config;
  280. /* wrap head around to the amount of space we have */
  281. head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
  282. /* find the page to write to */
  283. buf->cur = head / PAGE_SIZE;
  284. /* and offset within that page */
  285. buf->offset = head % PAGE_SIZE;
  286. local_set(&buf->data_size, 0);
  287. return ret;
  288. }
  289. static unsigned long tmc_reset_etf_buffer(struct coresight_device *csdev,
  290. struct perf_output_handle *handle,
  291. void *sink_config)
  292. {
  293. long size = 0;
  294. struct cs_buffers *buf = sink_config;
  295. if (buf) {
  296. /*
  297. * In snapshot mode ->data_size holds the new address of the
  298. * ring buffer's head. The size itself is the whole address
  299. * range since we want the latest information.
  300. */
  301. if (buf->snapshot)
  302. handle->head = local_xchg(&buf->data_size,
  303. buf->nr_pages << PAGE_SHIFT);
  304. /*
  305. * Tell the tracer PMU how much we got in this run and if
  306. * something went wrong along the way. Nobody else can use
  307. * this cs_buffers instance until we are done. As such
  308. * resetting parameters here and squaring off with the ring
  309. * buffer API in the tracer PMU is fine.
  310. */
  311. size = local_xchg(&buf->data_size, 0);
  312. }
  313. return size;
  314. }
  315. static void tmc_update_etf_buffer(struct coresight_device *csdev,
  316. struct perf_output_handle *handle,
  317. void *sink_config)
  318. {
  319. bool lost = false;
  320. int i, cur;
  321. const u32 *barrier;
  322. u32 *buf_ptr;
  323. u64 read_ptr, write_ptr;
  324. u32 status, to_read;
  325. unsigned long offset;
  326. struct cs_buffers *buf = sink_config;
  327. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  328. if (!buf)
  329. return;
  330. /* This shouldn't happen */
  331. if (WARN_ON_ONCE(drvdata->mode != CS_MODE_PERF))
  332. return;
  333. CS_UNLOCK(drvdata->base);
  334. tmc_flush_and_stop(drvdata);
  335. read_ptr = tmc_read_rrp(drvdata);
  336. write_ptr = tmc_read_rwp(drvdata);
  337. /*
  338. * Get a hold of the status register and see if a wrap around
  339. * has occurred. If so adjust things accordingly.
  340. */
  341. status = readl_relaxed(drvdata->base + TMC_STS);
  342. if (status & TMC_STS_FULL) {
  343. lost = true;
  344. to_read = drvdata->size;
  345. } else {
  346. to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->size);
  347. }
  348. /*
  349. * The TMC RAM buffer may be bigger than the space available in the
  350. * perf ring buffer (handle->size). If so advance the RRP so that we
  351. * get the latest trace data.
  352. */
  353. if (to_read > handle->size) {
  354. u32 mask = 0;
  355. /*
  356. * The value written to RRP must be byte-address aligned to
  357. * the width of the trace memory databus _and_ to a frame
  358. * boundary (16 byte), whichever is the biggest. For example,
  359. * for 32-bit, 64-bit and 128-bit wide trace memory, the four
  360. * LSBs must be 0s. For 256-bit wide trace memory, the five
  361. * LSBs must be 0s.
  362. */
  363. switch (drvdata->memwidth) {
  364. case TMC_MEM_INTF_WIDTH_32BITS:
  365. case TMC_MEM_INTF_WIDTH_64BITS:
  366. case TMC_MEM_INTF_WIDTH_128BITS:
  367. mask = GENMASK(31, 5);
  368. break;
  369. case TMC_MEM_INTF_WIDTH_256BITS:
  370. mask = GENMASK(31, 6);
  371. break;
  372. }
  373. /*
  374. * Make sure the new size is aligned in accordance with the
  375. * requirement explained above.
  376. */
  377. to_read = handle->size & mask;
  378. /* Move the RAM read pointer up */
  379. read_ptr = (write_ptr + drvdata->size) - to_read;
  380. /* Make sure we are still within our limits */
  381. if (read_ptr > (drvdata->size - 1))
  382. read_ptr -= drvdata->size;
  383. /* Tell the HW */
  384. tmc_write_rrp(drvdata, read_ptr);
  385. lost = true;
  386. }
  387. if (lost)
  388. perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
  389. cur = buf->cur;
  390. offset = buf->offset;
  391. barrier = barrier_pkt;
  392. /* for every byte to read */
  393. for (i = 0; i < to_read; i += 4) {
  394. buf_ptr = buf->data_pages[cur] + offset;
  395. *buf_ptr = readl_relaxed(drvdata->base + TMC_RRD);
  396. if (lost && *barrier) {
  397. *buf_ptr = *barrier;
  398. barrier++;
  399. }
  400. offset += 4;
  401. if (offset >= PAGE_SIZE) {
  402. offset = 0;
  403. cur++;
  404. /* wrap around at the end of the buffer */
  405. cur &= buf->nr_pages - 1;
  406. }
  407. }
  408. /*
  409. * In snapshot mode all we have to do is communicate to
  410. * perf_aux_output_end() the address of the current head. In full
  411. * trace mode the same function expects a size to move rb->aux_head
  412. * forward.
  413. */
  414. if (buf->snapshot)
  415. local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
  416. else
  417. local_add(to_read, &buf->data_size);
  418. CS_LOCK(drvdata->base);
  419. }
  420. static const struct coresight_ops_sink tmc_etf_sink_ops = {
  421. .enable = tmc_enable_etf_sink,
  422. .disable = tmc_disable_etf_sink,
  423. .alloc_buffer = tmc_alloc_etf_buffer,
  424. .free_buffer = tmc_free_etf_buffer,
  425. .set_buffer = tmc_set_etf_buffer,
  426. .reset_buffer = tmc_reset_etf_buffer,
  427. .update_buffer = tmc_update_etf_buffer,
  428. };
  429. static const struct coresight_ops_link tmc_etf_link_ops = {
  430. .enable = tmc_enable_etf_link,
  431. .disable = tmc_disable_etf_link,
  432. };
  433. const struct coresight_ops tmc_etb_cs_ops = {
  434. .sink_ops = &tmc_etf_sink_ops,
  435. };
  436. const struct coresight_ops tmc_etf_cs_ops = {
  437. .sink_ops = &tmc_etf_sink_ops,
  438. .link_ops = &tmc_etf_link_ops,
  439. };
  440. int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
  441. {
  442. enum tmc_mode mode;
  443. int ret = 0;
  444. unsigned long flags;
  445. /* config types are set a boot time and never change */
  446. if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB &&
  447. drvdata->config_type != TMC_CONFIG_TYPE_ETF))
  448. return -EINVAL;
  449. spin_lock_irqsave(&drvdata->spinlock, flags);
  450. if (drvdata->reading) {
  451. ret = -EBUSY;
  452. goto out;
  453. }
  454. /* There is no point in reading a TMC in HW FIFO mode */
  455. mode = readl_relaxed(drvdata->base + TMC_MODE);
  456. if (mode != TMC_MODE_CIRCULAR_BUFFER) {
  457. ret = -EINVAL;
  458. goto out;
  459. }
  460. /* Don't interfere if operated from Perf */
  461. if (drvdata->mode == CS_MODE_PERF) {
  462. ret = -EINVAL;
  463. goto out;
  464. }
  465. /* If drvdata::buf is NULL the trace data has been read already */
  466. if (drvdata->buf == NULL) {
  467. ret = -EINVAL;
  468. goto out;
  469. }
  470. /* Disable the TMC if need be */
  471. if (drvdata->mode == CS_MODE_SYSFS)
  472. tmc_etb_disable_hw(drvdata);
  473. drvdata->reading = true;
  474. out:
  475. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  476. return ret;
  477. }
  478. int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
  479. {
  480. char *buf = NULL;
  481. enum tmc_mode mode;
  482. unsigned long flags;
  483. /* config types are set a boot time and never change */
  484. if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB &&
  485. drvdata->config_type != TMC_CONFIG_TYPE_ETF))
  486. return -EINVAL;
  487. spin_lock_irqsave(&drvdata->spinlock, flags);
  488. /* There is no point in reading a TMC in HW FIFO mode */
  489. mode = readl_relaxed(drvdata->base + TMC_MODE);
  490. if (mode != TMC_MODE_CIRCULAR_BUFFER) {
  491. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  492. return -EINVAL;
  493. }
  494. /* Re-enable the TMC if need be */
  495. if (drvdata->mode == CS_MODE_SYSFS) {
  496. /*
  497. * The trace run will continue with the same allocated trace
  498. * buffer. As such zero-out the buffer so that we don't end
  499. * up with stale data.
  500. *
  501. * Since the tracer is still enabled drvdata::buf
  502. * can't be NULL.
  503. */
  504. memset(drvdata->buf, 0, drvdata->size);
  505. tmc_etb_enable_hw(drvdata);
  506. } else {
  507. /*
  508. * The ETB/ETF is not tracing and the buffer was just read.
  509. * As such prepare to free the trace buffer.
  510. */
  511. buf = drvdata->buf;
  512. drvdata->buf = NULL;
  513. }
  514. drvdata->reading = false;
  515. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  516. /*
  517. * Free allocated memory outside of the spinlock. There is no need
  518. * to assert the validity of 'buf' since calling kfree(NULL) is safe.
  519. */
  520. kfree(buf);
  521. return 0;
  522. }