zx_hdmi.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762
  1. /*
  2. * Copyright 2016 Linaro Ltd.
  3. * Copyright 2016 ZTE Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/component.h>
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/hdmi.h>
  15. #include <linux/irq.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/module.h>
  18. #include <linux/mutex.h>
  19. #include <linux/of_device.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc_helper.h>
  22. #include <drm/drm_edid.h>
  23. #include <drm/drm_of.h>
  24. #include <drm/drmP.h>
  25. #include <sound/hdmi-codec.h>
  26. #include "zx_hdmi_regs.h"
  27. #include "zx_vou.h"
  28. #define ZX_HDMI_INFOFRAME_SIZE 31
  29. #define DDC_SEGMENT_ADDR 0x30
  30. struct zx_hdmi_i2c {
  31. struct i2c_adapter adap;
  32. struct mutex lock;
  33. };
  34. struct zx_hdmi {
  35. struct drm_connector connector;
  36. struct drm_encoder encoder;
  37. struct zx_hdmi_i2c *ddc;
  38. struct device *dev;
  39. struct drm_device *drm;
  40. void __iomem *mmio;
  41. struct clk *cec_clk;
  42. struct clk *osc_clk;
  43. struct clk *xclk;
  44. bool sink_is_hdmi;
  45. bool sink_has_audio;
  46. struct platform_device *audio_pdev;
  47. };
  48. #define to_zx_hdmi(x) container_of(x, struct zx_hdmi, x)
  49. static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset)
  50. {
  51. return readl_relaxed(hdmi->mmio + offset * 4);
  52. }
  53. static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val)
  54. {
  55. writel_relaxed(val, hdmi->mmio + offset * 4);
  56. }
  57. static inline void hdmi_writeb_mask(struct zx_hdmi *hdmi, u16 offset,
  58. u8 mask, u8 val)
  59. {
  60. u8 tmp;
  61. tmp = hdmi_readb(hdmi, offset);
  62. tmp = (tmp & ~mask) | (val & mask);
  63. hdmi_writeb(hdmi, offset, tmp);
  64. }
  65. static int zx_hdmi_infoframe_trans(struct zx_hdmi *hdmi,
  66. union hdmi_infoframe *frame, u8 fsel)
  67. {
  68. u8 buffer[ZX_HDMI_INFOFRAME_SIZE];
  69. int num;
  70. int i;
  71. hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel);
  72. num = hdmi_infoframe_pack(frame, buffer, ZX_HDMI_INFOFRAME_SIZE);
  73. if (num < 0) {
  74. DRM_DEV_ERROR(hdmi->dev, "failed to pack infoframe: %d\n", num);
  75. return num;
  76. }
  77. for (i = 0; i < num; i++)
  78. hdmi_writeb(hdmi, TPI_INFO_B0 + i, buffer[i]);
  79. hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_RPT,
  80. TPI_INFO_TRANS_RPT);
  81. hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_EN,
  82. TPI_INFO_TRANS_EN);
  83. return num;
  84. }
  85. static int zx_hdmi_config_video_vsi(struct zx_hdmi *hdmi,
  86. struct drm_display_mode *mode)
  87. {
  88. union hdmi_infoframe frame;
  89. int ret;
  90. ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
  91. mode);
  92. if (ret) {
  93. DRM_DEV_ERROR(hdmi->dev, "failed to get vendor infoframe: %d\n",
  94. ret);
  95. return ret;
  96. }
  97. return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_VSIF);
  98. }
  99. static int zx_hdmi_config_video_avi(struct zx_hdmi *hdmi,
  100. struct drm_display_mode *mode)
  101. {
  102. union hdmi_infoframe frame;
  103. int ret;
  104. ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
  105. if (ret) {
  106. DRM_DEV_ERROR(hdmi->dev, "failed to get avi infoframe: %d\n",
  107. ret);
  108. return ret;
  109. }
  110. /* We always use YUV444 for HDMI output. */
  111. frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
  112. return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AVI);
  113. }
  114. static void zx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
  115. struct drm_display_mode *mode,
  116. struct drm_display_mode *adj_mode)
  117. {
  118. struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
  119. if (hdmi->sink_is_hdmi) {
  120. zx_hdmi_config_video_avi(hdmi, mode);
  121. zx_hdmi_config_video_vsi(hdmi, mode);
  122. }
  123. }
  124. static void zx_hdmi_phy_start(struct zx_hdmi *hdmi)
  125. {
  126. /* Copy from ZTE BSP code */
  127. hdmi_writeb(hdmi, 0x222, 0x0);
  128. hdmi_writeb(hdmi, 0x224, 0x4);
  129. hdmi_writeb(hdmi, 0x909, 0x0);
  130. hdmi_writeb(hdmi, 0x7b0, 0x90);
  131. hdmi_writeb(hdmi, 0x7b1, 0x00);
  132. hdmi_writeb(hdmi, 0x7b2, 0xa7);
  133. hdmi_writeb(hdmi, 0x7b8, 0xaa);
  134. hdmi_writeb(hdmi, 0x7b2, 0xa7);
  135. hdmi_writeb(hdmi, 0x7b3, 0x0f);
  136. hdmi_writeb(hdmi, 0x7b4, 0x0f);
  137. hdmi_writeb(hdmi, 0x7b5, 0x55);
  138. hdmi_writeb(hdmi, 0x7b7, 0x03);
  139. hdmi_writeb(hdmi, 0x7b9, 0x12);
  140. hdmi_writeb(hdmi, 0x7ba, 0x32);
  141. hdmi_writeb(hdmi, 0x7bc, 0x68);
  142. hdmi_writeb(hdmi, 0x7be, 0x40);
  143. hdmi_writeb(hdmi, 0x7bf, 0x84);
  144. hdmi_writeb(hdmi, 0x7c1, 0x0f);
  145. hdmi_writeb(hdmi, 0x7c8, 0x02);
  146. hdmi_writeb(hdmi, 0x7c9, 0x03);
  147. hdmi_writeb(hdmi, 0x7ca, 0x40);
  148. hdmi_writeb(hdmi, 0x7dc, 0x31);
  149. hdmi_writeb(hdmi, 0x7e2, 0x04);
  150. hdmi_writeb(hdmi, 0x7e0, 0x06);
  151. hdmi_writeb(hdmi, 0x7cb, 0x68);
  152. hdmi_writeb(hdmi, 0x7f9, 0x02);
  153. hdmi_writeb(hdmi, 0x7b6, 0x02);
  154. hdmi_writeb(hdmi, 0x7f3, 0x0);
  155. }
  156. static void zx_hdmi_hw_enable(struct zx_hdmi *hdmi)
  157. {
  158. /* Enable pclk */
  159. hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, CLKPWD_PDIDCK);
  160. /* Enable HDMI for TX */
  161. hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, FUNC_HDMI_EN);
  162. /* Enable deep color packet */
  163. hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
  164. /* Enable HDMI/MHL mode for output */
  165. hdmi_writeb_mask(hdmi, TEST_TXCTRL, TEST_TXCTRL_HDMI_MODE,
  166. TEST_TXCTRL_HDMI_MODE);
  167. /* Configure reg_qc_sel */
  168. hdmi_writeb(hdmi, HDMICTL4, 0x3);
  169. /* Enable interrupt */
  170. hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT,
  171. INTR1_MONITOR_DETECT);
  172. /* Start up phy */
  173. zx_hdmi_phy_start(hdmi);
  174. }
  175. static void zx_hdmi_hw_disable(struct zx_hdmi *hdmi)
  176. {
  177. /* Disable interrupt */
  178. hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT, 0);
  179. /* Disable deep color packet */
  180. hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
  181. /* Disable HDMI for TX */
  182. hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, 0);
  183. /* Disable pclk */
  184. hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, 0);
  185. }
  186. static void zx_hdmi_encoder_enable(struct drm_encoder *encoder)
  187. {
  188. struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
  189. clk_prepare_enable(hdmi->cec_clk);
  190. clk_prepare_enable(hdmi->osc_clk);
  191. clk_prepare_enable(hdmi->xclk);
  192. zx_hdmi_hw_enable(hdmi);
  193. vou_inf_enable(VOU_HDMI, encoder->crtc);
  194. }
  195. static void zx_hdmi_encoder_disable(struct drm_encoder *encoder)
  196. {
  197. struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
  198. vou_inf_disable(VOU_HDMI, encoder->crtc);
  199. zx_hdmi_hw_disable(hdmi);
  200. clk_disable_unprepare(hdmi->xclk);
  201. clk_disable_unprepare(hdmi->osc_clk);
  202. clk_disable_unprepare(hdmi->cec_clk);
  203. }
  204. static const struct drm_encoder_helper_funcs zx_hdmi_encoder_helper_funcs = {
  205. .enable = zx_hdmi_encoder_enable,
  206. .disable = zx_hdmi_encoder_disable,
  207. .mode_set = zx_hdmi_encoder_mode_set,
  208. };
  209. static const struct drm_encoder_funcs zx_hdmi_encoder_funcs = {
  210. .destroy = drm_encoder_cleanup,
  211. };
  212. static int zx_hdmi_connector_get_modes(struct drm_connector *connector)
  213. {
  214. struct zx_hdmi *hdmi = to_zx_hdmi(connector);
  215. struct edid *edid;
  216. int ret;
  217. edid = drm_get_edid(connector, &hdmi->ddc->adap);
  218. if (!edid)
  219. return 0;
  220. hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
  221. hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
  222. drm_mode_connector_update_edid_property(connector, edid);
  223. ret = drm_add_edid_modes(connector, edid);
  224. kfree(edid);
  225. return ret;
  226. }
  227. static enum drm_mode_status
  228. zx_hdmi_connector_mode_valid(struct drm_connector *connector,
  229. struct drm_display_mode *mode)
  230. {
  231. return MODE_OK;
  232. }
  233. static struct drm_connector_helper_funcs zx_hdmi_connector_helper_funcs = {
  234. .get_modes = zx_hdmi_connector_get_modes,
  235. .mode_valid = zx_hdmi_connector_mode_valid,
  236. };
  237. static enum drm_connector_status
  238. zx_hdmi_connector_detect(struct drm_connector *connector, bool force)
  239. {
  240. struct zx_hdmi *hdmi = to_zx_hdmi(connector);
  241. return (hdmi_readb(hdmi, TPI_HPD_RSEN) & TPI_HPD_CONNECTION) ?
  242. connector_status_connected : connector_status_disconnected;
  243. }
  244. static const struct drm_connector_funcs zx_hdmi_connector_funcs = {
  245. .fill_modes = drm_helper_probe_single_connector_modes,
  246. .detect = zx_hdmi_connector_detect,
  247. .destroy = drm_connector_cleanup,
  248. .reset = drm_atomic_helper_connector_reset,
  249. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  250. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  251. };
  252. static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi)
  253. {
  254. struct drm_encoder *encoder = &hdmi->encoder;
  255. encoder->possible_crtcs = VOU_CRTC_MASK;
  256. drm_encoder_init(drm, encoder, &zx_hdmi_encoder_funcs,
  257. DRM_MODE_ENCODER_TMDS, NULL);
  258. drm_encoder_helper_add(encoder, &zx_hdmi_encoder_helper_funcs);
  259. hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
  260. drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs,
  261. DRM_MODE_CONNECTOR_HDMIA);
  262. drm_connector_helper_add(&hdmi->connector,
  263. &zx_hdmi_connector_helper_funcs);
  264. drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
  265. return 0;
  266. }
  267. static irqreturn_t zx_hdmi_irq_thread(int irq, void *dev_id)
  268. {
  269. struct zx_hdmi *hdmi = dev_id;
  270. drm_helper_hpd_irq_event(hdmi->connector.dev);
  271. return IRQ_HANDLED;
  272. }
  273. static irqreturn_t zx_hdmi_irq_handler(int irq, void *dev_id)
  274. {
  275. struct zx_hdmi *hdmi = dev_id;
  276. u8 lstat;
  277. lstat = hdmi_readb(hdmi, L1_INTR_STAT);
  278. /* Monitor detect/HPD interrupt */
  279. if (lstat & L1_INTR_STAT_INTR1) {
  280. u8 stat;
  281. stat = hdmi_readb(hdmi, INTR1_STAT);
  282. hdmi_writeb(hdmi, INTR1_STAT, stat);
  283. if (stat & INTR1_MONITOR_DETECT)
  284. return IRQ_WAKE_THREAD;
  285. }
  286. return IRQ_NONE;
  287. }
  288. static int zx_hdmi_audio_startup(struct device *dev, void *data)
  289. {
  290. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  291. struct drm_encoder *encoder = &hdmi->encoder;
  292. vou_inf_hdmi_audio_sel(encoder->crtc, VOU_HDMI_AUD_SPDIF);
  293. return 0;
  294. }
  295. static void zx_hdmi_audio_shutdown(struct device *dev, void *data)
  296. {
  297. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  298. /* Disable audio input */
  299. hdmi_writeb_mask(hdmi, AUD_EN, AUD_IN_EN, 0);
  300. }
  301. static inline int zx_hdmi_audio_get_n(unsigned int fs)
  302. {
  303. unsigned int n;
  304. if (fs && (fs % 44100) == 0)
  305. n = 6272 * (fs / 44100);
  306. else
  307. n = fs * 128 / 1000;
  308. return n;
  309. }
  310. static int zx_hdmi_audio_hw_params(struct device *dev,
  311. void *data,
  312. struct hdmi_codec_daifmt *daifmt,
  313. struct hdmi_codec_params *params)
  314. {
  315. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  316. struct hdmi_audio_infoframe *cea = &params->cea;
  317. union hdmi_infoframe frame;
  318. int n;
  319. /* We only support spdif for now */
  320. if (daifmt->fmt != HDMI_SPDIF) {
  321. DRM_DEV_ERROR(hdmi->dev, "invalid daifmt %d\n", daifmt->fmt);
  322. return -EINVAL;
  323. }
  324. switch (params->sample_width) {
  325. case 16:
  326. hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
  327. SPDIF_SAMPLE_SIZE_16BIT);
  328. break;
  329. case 20:
  330. hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
  331. SPDIF_SAMPLE_SIZE_20BIT);
  332. break;
  333. case 24:
  334. hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
  335. SPDIF_SAMPLE_SIZE_24BIT);
  336. break;
  337. default:
  338. DRM_DEV_ERROR(hdmi->dev, "invalid sample width %d\n",
  339. params->sample_width);
  340. return -EINVAL;
  341. }
  342. /* CTS is calculated by hardware, and we only need to take care of N */
  343. n = zx_hdmi_audio_get_n(params->sample_rate);
  344. hdmi_writeb(hdmi, N_SVAL1, n & 0xff);
  345. hdmi_writeb(hdmi, N_SVAL2, (n >> 8) & 0xff);
  346. hdmi_writeb(hdmi, N_SVAL3, (n >> 16) & 0xf);
  347. /* Enable spdif mode */
  348. hdmi_writeb_mask(hdmi, AUD_MODE, SPDIF_EN, SPDIF_EN);
  349. /* Enable audio input */
  350. hdmi_writeb_mask(hdmi, AUD_EN, AUD_IN_EN, AUD_IN_EN);
  351. memcpy(&frame.audio, cea, sizeof(*cea));
  352. return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AUDIO);
  353. }
  354. static int zx_hdmi_audio_digital_mute(struct device *dev, void *data,
  355. bool enable)
  356. {
  357. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  358. if (enable)
  359. hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, TPI_AUD_MUTE,
  360. TPI_AUD_MUTE);
  361. else
  362. hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, TPI_AUD_MUTE, 0);
  363. return 0;
  364. }
  365. static int zx_hdmi_audio_get_eld(struct device *dev, void *data,
  366. uint8_t *buf, size_t len)
  367. {
  368. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  369. struct drm_connector *connector = &hdmi->connector;
  370. memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
  371. return 0;
  372. }
  373. static const struct hdmi_codec_ops zx_hdmi_codec_ops = {
  374. .audio_startup = zx_hdmi_audio_startup,
  375. .hw_params = zx_hdmi_audio_hw_params,
  376. .audio_shutdown = zx_hdmi_audio_shutdown,
  377. .digital_mute = zx_hdmi_audio_digital_mute,
  378. .get_eld = zx_hdmi_audio_get_eld,
  379. };
  380. static struct hdmi_codec_pdata zx_hdmi_codec_pdata = {
  381. .ops = &zx_hdmi_codec_ops,
  382. .spdif = 1,
  383. };
  384. static int zx_hdmi_audio_register(struct zx_hdmi *hdmi)
  385. {
  386. struct platform_device *pdev;
  387. pdev = platform_device_register_data(hdmi->dev, HDMI_CODEC_DRV_NAME,
  388. PLATFORM_DEVID_AUTO,
  389. &zx_hdmi_codec_pdata,
  390. sizeof(zx_hdmi_codec_pdata));
  391. if (IS_ERR(pdev))
  392. return PTR_ERR(pdev);
  393. hdmi->audio_pdev = pdev;
  394. return 0;
  395. }
  396. static int zx_hdmi_i2c_read(struct zx_hdmi *hdmi, struct i2c_msg *msg)
  397. {
  398. int len = msg->len;
  399. u8 *buf = msg->buf;
  400. int retry = 0;
  401. int ret = 0;
  402. /* Bits [9:8] of bytes */
  403. hdmi_writeb(hdmi, ZX_DDC_DIN_CNT2, (len >> 8) & 0xff);
  404. /* Bits [7:0] of bytes */
  405. hdmi_writeb(hdmi, ZX_DDC_DIN_CNT1, len & 0xff);
  406. /* Clear FIFO */
  407. hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK, DDC_CMD_CLEAR_FIFO);
  408. /* Kick off the read */
  409. hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK,
  410. DDC_CMD_SEQUENTIAL_READ);
  411. while (len > 0) {
  412. int cnt, i;
  413. /* FIFO needs some time to get ready */
  414. usleep_range(500, 1000);
  415. cnt = hdmi_readb(hdmi, ZX_DDC_DOUT_CNT) & DDC_DOUT_CNT_MASK;
  416. if (cnt == 0) {
  417. if (++retry > 5) {
  418. DRM_DEV_ERROR(hdmi->dev,
  419. "DDC FIFO read timed out!");
  420. return -ETIMEDOUT;
  421. }
  422. continue;
  423. }
  424. for (i = 0; i < cnt; i++)
  425. *buf++ = hdmi_readb(hdmi, ZX_DDC_DATA);
  426. len -= cnt;
  427. }
  428. return ret;
  429. }
  430. static int zx_hdmi_i2c_write(struct zx_hdmi *hdmi, struct i2c_msg *msg)
  431. {
  432. /*
  433. * The DDC I2C adapter is only for reading EDID data, so we assume
  434. * that the write to this adapter must be the EDID data offset.
  435. */
  436. if ((msg->len != 1) ||
  437. ((msg->addr != DDC_ADDR) && (msg->addr != DDC_SEGMENT_ADDR)))
  438. return -EINVAL;
  439. if (msg->addr == DDC_SEGMENT_ADDR)
  440. hdmi_writeb(hdmi, ZX_DDC_SEGM, msg->addr << 1);
  441. else if (msg->addr == DDC_ADDR)
  442. hdmi_writeb(hdmi, ZX_DDC_ADDR, msg->addr << 1);
  443. hdmi_writeb(hdmi, ZX_DDC_OFFSET, msg->buf[0]);
  444. return 0;
  445. }
  446. static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
  447. int num)
  448. {
  449. struct zx_hdmi *hdmi = i2c_get_adapdata(adap);
  450. struct zx_hdmi_i2c *ddc = hdmi->ddc;
  451. int i, ret = 0;
  452. mutex_lock(&ddc->lock);
  453. /* Enable DDC master access */
  454. hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, HW_DDC_MASTER);
  455. for (i = 0; i < num; i++) {
  456. DRM_DEV_DEBUG(hdmi->dev,
  457. "xfer: num: %d/%d, len: %d, flags: %#x\n",
  458. i + 1, num, msgs[i].len, msgs[i].flags);
  459. if (msgs[i].flags & I2C_M_RD)
  460. ret = zx_hdmi_i2c_read(hdmi, &msgs[i]);
  461. else
  462. ret = zx_hdmi_i2c_write(hdmi, &msgs[i]);
  463. if (ret < 0)
  464. break;
  465. }
  466. if (!ret)
  467. ret = num;
  468. /* Disable DDC master access */
  469. hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, 0);
  470. mutex_unlock(&ddc->lock);
  471. return ret;
  472. }
  473. static u32 zx_hdmi_i2c_func(struct i2c_adapter *adapter)
  474. {
  475. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  476. }
  477. static const struct i2c_algorithm zx_hdmi_algorithm = {
  478. .master_xfer = zx_hdmi_i2c_xfer,
  479. .functionality = zx_hdmi_i2c_func,
  480. };
  481. static int zx_hdmi_ddc_register(struct zx_hdmi *hdmi)
  482. {
  483. struct i2c_adapter *adap;
  484. struct zx_hdmi_i2c *ddc;
  485. int ret;
  486. ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
  487. if (!ddc)
  488. return -ENOMEM;
  489. hdmi->ddc = ddc;
  490. mutex_init(&ddc->lock);
  491. adap = &ddc->adap;
  492. adap->owner = THIS_MODULE;
  493. adap->class = I2C_CLASS_DDC;
  494. adap->dev.parent = hdmi->dev;
  495. adap->algo = &zx_hdmi_algorithm;
  496. snprintf(adap->name, sizeof(adap->name), "zx hdmi i2c");
  497. ret = i2c_add_adapter(adap);
  498. if (ret) {
  499. DRM_DEV_ERROR(hdmi->dev, "failed to add I2C adapter: %d\n",
  500. ret);
  501. return ret;
  502. }
  503. i2c_set_adapdata(adap, hdmi);
  504. return 0;
  505. }
  506. static int zx_hdmi_bind(struct device *dev, struct device *master, void *data)
  507. {
  508. struct platform_device *pdev = to_platform_device(dev);
  509. struct drm_device *drm = data;
  510. struct resource *res;
  511. struct zx_hdmi *hdmi;
  512. int irq;
  513. int ret;
  514. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  515. if (!hdmi)
  516. return -ENOMEM;
  517. hdmi->dev = dev;
  518. hdmi->drm = drm;
  519. dev_set_drvdata(dev, hdmi);
  520. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  521. hdmi->mmio = devm_ioremap_resource(dev, res);
  522. if (IS_ERR(hdmi->mmio)) {
  523. ret = PTR_ERR(hdmi->mmio);
  524. DRM_DEV_ERROR(dev, "failed to remap hdmi region: %d\n", ret);
  525. return ret;
  526. }
  527. irq = platform_get_irq(pdev, 0);
  528. if (irq < 0)
  529. return irq;
  530. hdmi->cec_clk = devm_clk_get(hdmi->dev, "osc_cec");
  531. if (IS_ERR(hdmi->cec_clk)) {
  532. ret = PTR_ERR(hdmi->cec_clk);
  533. DRM_DEV_ERROR(dev, "failed to get cec_clk: %d\n", ret);
  534. return ret;
  535. }
  536. hdmi->osc_clk = devm_clk_get(hdmi->dev, "osc_clk");
  537. if (IS_ERR(hdmi->osc_clk)) {
  538. ret = PTR_ERR(hdmi->osc_clk);
  539. DRM_DEV_ERROR(dev, "failed to get osc_clk: %d\n", ret);
  540. return ret;
  541. }
  542. hdmi->xclk = devm_clk_get(hdmi->dev, "xclk");
  543. if (IS_ERR(hdmi->xclk)) {
  544. ret = PTR_ERR(hdmi->xclk);
  545. DRM_DEV_ERROR(dev, "failed to get xclk: %d\n", ret);
  546. return ret;
  547. }
  548. ret = zx_hdmi_ddc_register(hdmi);
  549. if (ret) {
  550. DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
  551. return ret;
  552. }
  553. ret = zx_hdmi_audio_register(hdmi);
  554. if (ret) {
  555. DRM_DEV_ERROR(dev, "failed to register audio: %d\n", ret);
  556. return ret;
  557. }
  558. ret = zx_hdmi_register(drm, hdmi);
  559. if (ret) {
  560. DRM_DEV_ERROR(dev, "failed to register hdmi: %d\n", ret);
  561. return ret;
  562. }
  563. ret = devm_request_threaded_irq(dev, irq, zx_hdmi_irq_handler,
  564. zx_hdmi_irq_thread, IRQF_SHARED,
  565. dev_name(dev), hdmi);
  566. if (ret) {
  567. DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
  568. return ret;
  569. }
  570. return 0;
  571. }
  572. static void zx_hdmi_unbind(struct device *dev, struct device *master,
  573. void *data)
  574. {
  575. struct zx_hdmi *hdmi = dev_get_drvdata(dev);
  576. hdmi->connector.funcs->destroy(&hdmi->connector);
  577. hdmi->encoder.funcs->destroy(&hdmi->encoder);
  578. if (hdmi->audio_pdev)
  579. platform_device_unregister(hdmi->audio_pdev);
  580. }
  581. static const struct component_ops zx_hdmi_component_ops = {
  582. .bind = zx_hdmi_bind,
  583. .unbind = zx_hdmi_unbind,
  584. };
  585. static int zx_hdmi_probe(struct platform_device *pdev)
  586. {
  587. return component_add(&pdev->dev, &zx_hdmi_component_ops);
  588. }
  589. static int zx_hdmi_remove(struct platform_device *pdev)
  590. {
  591. component_del(&pdev->dev, &zx_hdmi_component_ops);
  592. return 0;
  593. }
  594. static const struct of_device_id zx_hdmi_of_match[] = {
  595. { .compatible = "zte,zx296718-hdmi", },
  596. { /* end */ },
  597. };
  598. MODULE_DEVICE_TABLE(of, zx_hdmi_of_match);
  599. struct platform_driver zx_hdmi_driver = {
  600. .probe = zx_hdmi_probe,
  601. .remove = zx_hdmi_remove,
  602. .driver = {
  603. .name = "zx-hdmi",
  604. .of_match_table = zx_hdmi_of_match,
  605. },
  606. };