vic.c 8.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407
  1. /*
  2. * Copyright (c) 2015, NVIDIA Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/host1x.h>
  10. #include <linux/iommu.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/reset.h>
  18. #include <soc/tegra/pmc.h>
  19. #include "drm.h"
  20. #include "falcon.h"
  21. #include "vic.h"
  22. struct vic_config {
  23. const char *firmware;
  24. };
  25. struct vic {
  26. struct falcon falcon;
  27. bool booted;
  28. void __iomem *regs;
  29. struct tegra_drm_client client;
  30. struct host1x_channel *channel;
  31. struct iommu_domain *domain;
  32. struct device *dev;
  33. struct clk *clk;
  34. /* Platform configuration */
  35. const struct vic_config *config;
  36. };
  37. static inline struct vic *to_vic(struct tegra_drm_client *client)
  38. {
  39. return container_of(client, struct vic, client);
  40. }
  41. static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
  42. {
  43. writel(value, vic->regs + offset);
  44. }
  45. static int vic_runtime_resume(struct device *dev)
  46. {
  47. struct vic *vic = dev_get_drvdata(dev);
  48. return clk_prepare_enable(vic->clk);
  49. }
  50. static int vic_runtime_suspend(struct device *dev)
  51. {
  52. struct vic *vic = dev_get_drvdata(dev);
  53. clk_disable_unprepare(vic->clk);
  54. vic->booted = false;
  55. return 0;
  56. }
  57. static int vic_boot(struct vic *vic)
  58. {
  59. u32 fce_ucode_size, fce_bin_data_offset;
  60. void *hdr;
  61. int err = 0;
  62. if (vic->booted)
  63. return 0;
  64. /* setup clockgating registers */
  65. vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
  66. CG_IDLE_CG_EN |
  67. CG_WAKEUP_DLY_CNT(4),
  68. NV_PVIC_MISC_PRI_VIC_CG);
  69. err = falcon_boot(&vic->falcon);
  70. if (err < 0)
  71. return err;
  72. hdr = vic->falcon.firmware.vaddr;
  73. fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
  74. hdr = vic->falcon.firmware.vaddr +
  75. *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
  76. fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
  77. falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
  78. falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
  79. fce_ucode_size);
  80. falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
  81. (vic->falcon.firmware.paddr + fce_bin_data_offset)
  82. >> 8);
  83. err = falcon_wait_idle(&vic->falcon);
  84. if (err < 0) {
  85. dev_err(vic->dev,
  86. "failed to set application ID and FCE base\n");
  87. return err;
  88. }
  89. vic->booted = true;
  90. return 0;
  91. }
  92. static void *vic_falcon_alloc(struct falcon *falcon, size_t size,
  93. dma_addr_t *iova)
  94. {
  95. struct tegra_drm *tegra = falcon->data;
  96. return tegra_drm_alloc(tegra, size, iova);
  97. }
  98. static void vic_falcon_free(struct falcon *falcon, size_t size,
  99. dma_addr_t iova, void *va)
  100. {
  101. struct tegra_drm *tegra = falcon->data;
  102. return tegra_drm_free(tegra, size, va, iova);
  103. }
  104. static const struct falcon_ops vic_falcon_ops = {
  105. .alloc = vic_falcon_alloc,
  106. .free = vic_falcon_free
  107. };
  108. static int vic_init(struct host1x_client *client)
  109. {
  110. struct tegra_drm_client *drm = host1x_to_drm_client(client);
  111. struct drm_device *dev = dev_get_drvdata(client->parent);
  112. struct tegra_drm *tegra = dev->dev_private;
  113. struct vic *vic = to_vic(drm);
  114. int err;
  115. if (tegra->domain) {
  116. err = iommu_attach_device(tegra->domain, vic->dev);
  117. if (err < 0) {
  118. dev_err(vic->dev, "failed to attach to domain: %d\n",
  119. err);
  120. return err;
  121. }
  122. vic->domain = tegra->domain;
  123. }
  124. if (!vic->falcon.data) {
  125. vic->falcon.data = tegra;
  126. err = falcon_load_firmware(&vic->falcon);
  127. if (err < 0)
  128. goto detach_device;
  129. }
  130. vic->channel = host1x_channel_request(client->dev);
  131. if (!vic->channel) {
  132. err = -ENOMEM;
  133. goto detach_device;
  134. }
  135. client->syncpts[0] = host1x_syncpt_request(client->dev, 0);
  136. if (!client->syncpts[0]) {
  137. err = -ENOMEM;
  138. goto free_channel;
  139. }
  140. err = tegra_drm_register_client(tegra, drm);
  141. if (err < 0)
  142. goto free_syncpt;
  143. return 0;
  144. free_syncpt:
  145. host1x_syncpt_free(client->syncpts[0]);
  146. free_channel:
  147. host1x_channel_put(vic->channel);
  148. detach_device:
  149. if (tegra->domain)
  150. iommu_detach_device(tegra->domain, vic->dev);
  151. return err;
  152. }
  153. static int vic_exit(struct host1x_client *client)
  154. {
  155. struct tegra_drm_client *drm = host1x_to_drm_client(client);
  156. struct drm_device *dev = dev_get_drvdata(client->parent);
  157. struct tegra_drm *tegra = dev->dev_private;
  158. struct vic *vic = to_vic(drm);
  159. int err;
  160. err = tegra_drm_unregister_client(tegra, drm);
  161. if (err < 0)
  162. return err;
  163. host1x_syncpt_free(client->syncpts[0]);
  164. host1x_channel_put(vic->channel);
  165. if (vic->domain) {
  166. iommu_detach_device(vic->domain, vic->dev);
  167. vic->domain = NULL;
  168. }
  169. return 0;
  170. }
  171. static const struct host1x_client_ops vic_client_ops = {
  172. .init = vic_init,
  173. .exit = vic_exit,
  174. };
  175. static int vic_open_channel(struct tegra_drm_client *client,
  176. struct tegra_drm_context *context)
  177. {
  178. struct vic *vic = to_vic(client);
  179. int err;
  180. err = pm_runtime_get_sync(vic->dev);
  181. if (err < 0)
  182. return err;
  183. err = vic_boot(vic);
  184. if (err < 0) {
  185. pm_runtime_put(vic->dev);
  186. return err;
  187. }
  188. context->channel = host1x_channel_get(vic->channel);
  189. if (!context->channel) {
  190. pm_runtime_put(vic->dev);
  191. return -ENOMEM;
  192. }
  193. return 0;
  194. }
  195. static void vic_close_channel(struct tegra_drm_context *context)
  196. {
  197. struct vic *vic = to_vic(context->client);
  198. host1x_channel_put(context->channel);
  199. pm_runtime_put(vic->dev);
  200. }
  201. static const struct tegra_drm_client_ops vic_ops = {
  202. .open_channel = vic_open_channel,
  203. .close_channel = vic_close_channel,
  204. .submit = tegra_drm_submit,
  205. };
  206. #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
  207. static const struct vic_config vic_t124_config = {
  208. .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
  209. };
  210. #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
  211. static const struct vic_config vic_t210_config = {
  212. .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
  213. };
  214. static const struct of_device_id vic_match[] = {
  215. { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
  216. { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
  217. { },
  218. };
  219. static int vic_probe(struct platform_device *pdev)
  220. {
  221. struct vic_config *vic_config = NULL;
  222. struct device *dev = &pdev->dev;
  223. struct host1x_syncpt **syncpts;
  224. struct resource *regs;
  225. const struct of_device_id *match;
  226. struct vic *vic;
  227. int err;
  228. match = of_match_device(vic_match, dev);
  229. vic_config = (struct vic_config *)match->data;
  230. vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
  231. if (!vic)
  232. return -ENOMEM;
  233. syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
  234. if (!syncpts)
  235. return -ENOMEM;
  236. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  237. if (!regs) {
  238. dev_err(&pdev->dev, "failed to get registers\n");
  239. return -ENXIO;
  240. }
  241. vic->regs = devm_ioremap_resource(dev, regs);
  242. if (IS_ERR(vic->regs))
  243. return PTR_ERR(vic->regs);
  244. vic->clk = devm_clk_get(dev, NULL);
  245. if (IS_ERR(vic->clk)) {
  246. dev_err(&pdev->dev, "failed to get clock\n");
  247. return PTR_ERR(vic->clk);
  248. }
  249. vic->falcon.dev = dev;
  250. vic->falcon.regs = vic->regs;
  251. vic->falcon.ops = &vic_falcon_ops;
  252. err = falcon_init(&vic->falcon);
  253. if (err < 0)
  254. return err;
  255. err = falcon_read_firmware(&vic->falcon, vic_config->firmware);
  256. if (err < 0)
  257. goto exit_falcon;
  258. platform_set_drvdata(pdev, vic);
  259. INIT_LIST_HEAD(&vic->client.base.list);
  260. vic->client.base.ops = &vic_client_ops;
  261. vic->client.base.dev = dev;
  262. vic->client.base.class = HOST1X_CLASS_VIC;
  263. vic->client.base.syncpts = syncpts;
  264. vic->client.base.num_syncpts = 1;
  265. vic->dev = dev;
  266. vic->config = vic_config;
  267. INIT_LIST_HEAD(&vic->client.list);
  268. vic->client.ops = &vic_ops;
  269. err = host1x_client_register(&vic->client.base);
  270. if (err < 0) {
  271. dev_err(dev, "failed to register host1x client: %d\n", err);
  272. platform_set_drvdata(pdev, NULL);
  273. goto exit_falcon;
  274. }
  275. pm_runtime_enable(&pdev->dev);
  276. if (!pm_runtime_enabled(&pdev->dev)) {
  277. err = vic_runtime_resume(&pdev->dev);
  278. if (err < 0)
  279. goto unregister_client;
  280. }
  281. return 0;
  282. unregister_client:
  283. host1x_client_unregister(&vic->client.base);
  284. exit_falcon:
  285. falcon_exit(&vic->falcon);
  286. return err;
  287. }
  288. static int vic_remove(struct platform_device *pdev)
  289. {
  290. struct vic *vic = platform_get_drvdata(pdev);
  291. int err;
  292. err = host1x_client_unregister(&vic->client.base);
  293. if (err < 0) {
  294. dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
  295. err);
  296. return err;
  297. }
  298. if (pm_runtime_enabled(&pdev->dev))
  299. pm_runtime_disable(&pdev->dev);
  300. else
  301. vic_runtime_suspend(&pdev->dev);
  302. falcon_exit(&vic->falcon);
  303. return 0;
  304. }
  305. static const struct dev_pm_ops vic_pm_ops = {
  306. SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
  307. };
  308. struct platform_driver tegra_vic_driver = {
  309. .driver = {
  310. .name = "tegra-vic",
  311. .of_match_table = vic_match,
  312. .pm = &vic_pm_ops
  313. },
  314. .probe = vic_probe,
  315. .remove = vic_remove,
  316. };
  317. #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
  318. MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
  319. #endif
  320. #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
  321. MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
  322. #endif