dsi.c 41 KB

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  1. /*
  2. * Copyright (C) 2013 NVIDIA Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/debugfs.h>
  10. #include <linux/host1x.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/reset.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <drm/drm_atomic_helper.h>
  19. #include <drm/drm_mipi_dsi.h>
  20. #include <drm/drm_panel.h>
  21. #include <video/mipi_display.h>
  22. #include "dc.h"
  23. #include "drm.h"
  24. #include "dsi.h"
  25. #include "mipi-phy.h"
  26. #include "trace.h"
  27. struct tegra_dsi_state {
  28. struct drm_connector_state base;
  29. struct mipi_dphy_timing timing;
  30. unsigned long period;
  31. unsigned int vrefresh;
  32. unsigned int lanes;
  33. unsigned long pclk;
  34. unsigned long bclk;
  35. enum tegra_dsi_format format;
  36. unsigned int mul;
  37. unsigned int div;
  38. };
  39. static inline struct tegra_dsi_state *
  40. to_dsi_state(struct drm_connector_state *state)
  41. {
  42. return container_of(state, struct tegra_dsi_state, base);
  43. }
  44. struct tegra_dsi {
  45. struct host1x_client client;
  46. struct tegra_output output;
  47. struct device *dev;
  48. void __iomem *regs;
  49. struct reset_control *rst;
  50. struct clk *clk_parent;
  51. struct clk *clk_lp;
  52. struct clk *clk;
  53. struct drm_info_list *debugfs_files;
  54. struct drm_minor *minor;
  55. struct dentry *debugfs;
  56. unsigned long flags;
  57. enum mipi_dsi_pixel_format format;
  58. unsigned int lanes;
  59. struct tegra_mipi_device *mipi;
  60. struct mipi_dsi_host host;
  61. struct regulator *vdd;
  62. unsigned int video_fifo_depth;
  63. unsigned int host_fifo_depth;
  64. /* for ganged-mode support */
  65. struct tegra_dsi *master;
  66. struct tegra_dsi *slave;
  67. };
  68. static inline struct tegra_dsi *
  69. host1x_client_to_dsi(struct host1x_client *client)
  70. {
  71. return container_of(client, struct tegra_dsi, client);
  72. }
  73. static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
  74. {
  75. return container_of(host, struct tegra_dsi, host);
  76. }
  77. static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
  78. {
  79. return container_of(output, struct tegra_dsi, output);
  80. }
  81. static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
  82. {
  83. return to_dsi_state(dsi->output.connector.state);
  84. }
  85. static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
  86. {
  87. u32 value = readl(dsi->regs + (offset << 2));
  88. trace_dsi_readl(dsi->dev, offset, value);
  89. return value;
  90. }
  91. static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
  92. unsigned int offset)
  93. {
  94. trace_dsi_writel(dsi->dev, offset, value);
  95. writel(value, dsi->regs + (offset << 2));
  96. }
  97. static int tegra_dsi_show_regs(struct seq_file *s, void *data)
  98. {
  99. struct drm_info_node *node = s->private;
  100. struct tegra_dsi *dsi = node->info_ent->data;
  101. struct drm_crtc *crtc = dsi->output.encoder.crtc;
  102. struct drm_device *drm = node->minor->dev;
  103. int err = 0;
  104. drm_modeset_lock_all(drm);
  105. if (!crtc || !crtc->state->active) {
  106. err = -EBUSY;
  107. goto unlock;
  108. }
  109. #define DUMP_REG(name) \
  110. seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
  111. tegra_dsi_readl(dsi, name))
  112. DUMP_REG(DSI_INCR_SYNCPT);
  113. DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
  114. DUMP_REG(DSI_INCR_SYNCPT_ERROR);
  115. DUMP_REG(DSI_CTXSW);
  116. DUMP_REG(DSI_RD_DATA);
  117. DUMP_REG(DSI_WR_DATA);
  118. DUMP_REG(DSI_POWER_CONTROL);
  119. DUMP_REG(DSI_INT_ENABLE);
  120. DUMP_REG(DSI_INT_STATUS);
  121. DUMP_REG(DSI_INT_MASK);
  122. DUMP_REG(DSI_HOST_CONTROL);
  123. DUMP_REG(DSI_CONTROL);
  124. DUMP_REG(DSI_SOL_DELAY);
  125. DUMP_REG(DSI_MAX_THRESHOLD);
  126. DUMP_REG(DSI_TRIGGER);
  127. DUMP_REG(DSI_TX_CRC);
  128. DUMP_REG(DSI_STATUS);
  129. DUMP_REG(DSI_INIT_SEQ_CONTROL);
  130. DUMP_REG(DSI_INIT_SEQ_DATA_0);
  131. DUMP_REG(DSI_INIT_SEQ_DATA_1);
  132. DUMP_REG(DSI_INIT_SEQ_DATA_2);
  133. DUMP_REG(DSI_INIT_SEQ_DATA_3);
  134. DUMP_REG(DSI_INIT_SEQ_DATA_4);
  135. DUMP_REG(DSI_INIT_SEQ_DATA_5);
  136. DUMP_REG(DSI_INIT_SEQ_DATA_6);
  137. DUMP_REG(DSI_INIT_SEQ_DATA_7);
  138. DUMP_REG(DSI_PKT_SEQ_0_LO);
  139. DUMP_REG(DSI_PKT_SEQ_0_HI);
  140. DUMP_REG(DSI_PKT_SEQ_1_LO);
  141. DUMP_REG(DSI_PKT_SEQ_1_HI);
  142. DUMP_REG(DSI_PKT_SEQ_2_LO);
  143. DUMP_REG(DSI_PKT_SEQ_2_HI);
  144. DUMP_REG(DSI_PKT_SEQ_3_LO);
  145. DUMP_REG(DSI_PKT_SEQ_3_HI);
  146. DUMP_REG(DSI_PKT_SEQ_4_LO);
  147. DUMP_REG(DSI_PKT_SEQ_4_HI);
  148. DUMP_REG(DSI_PKT_SEQ_5_LO);
  149. DUMP_REG(DSI_PKT_SEQ_5_HI);
  150. DUMP_REG(DSI_DCS_CMDS);
  151. DUMP_REG(DSI_PKT_LEN_0_1);
  152. DUMP_REG(DSI_PKT_LEN_2_3);
  153. DUMP_REG(DSI_PKT_LEN_4_5);
  154. DUMP_REG(DSI_PKT_LEN_6_7);
  155. DUMP_REG(DSI_PHY_TIMING_0);
  156. DUMP_REG(DSI_PHY_TIMING_1);
  157. DUMP_REG(DSI_PHY_TIMING_2);
  158. DUMP_REG(DSI_BTA_TIMING);
  159. DUMP_REG(DSI_TIMEOUT_0);
  160. DUMP_REG(DSI_TIMEOUT_1);
  161. DUMP_REG(DSI_TO_TALLY);
  162. DUMP_REG(DSI_PAD_CONTROL_0);
  163. DUMP_REG(DSI_PAD_CONTROL_CD);
  164. DUMP_REG(DSI_PAD_CD_STATUS);
  165. DUMP_REG(DSI_VIDEO_MODE_CONTROL);
  166. DUMP_REG(DSI_PAD_CONTROL_1);
  167. DUMP_REG(DSI_PAD_CONTROL_2);
  168. DUMP_REG(DSI_PAD_CONTROL_3);
  169. DUMP_REG(DSI_PAD_CONTROL_4);
  170. DUMP_REG(DSI_GANGED_MODE_CONTROL);
  171. DUMP_REG(DSI_GANGED_MODE_START);
  172. DUMP_REG(DSI_GANGED_MODE_SIZE);
  173. DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
  174. DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
  175. DUMP_REG(DSI_INIT_SEQ_DATA_8);
  176. DUMP_REG(DSI_INIT_SEQ_DATA_9);
  177. DUMP_REG(DSI_INIT_SEQ_DATA_10);
  178. DUMP_REG(DSI_INIT_SEQ_DATA_11);
  179. DUMP_REG(DSI_INIT_SEQ_DATA_12);
  180. DUMP_REG(DSI_INIT_SEQ_DATA_13);
  181. DUMP_REG(DSI_INIT_SEQ_DATA_14);
  182. DUMP_REG(DSI_INIT_SEQ_DATA_15);
  183. #undef DUMP_REG
  184. unlock:
  185. drm_modeset_unlock_all(drm);
  186. return err;
  187. }
  188. static struct drm_info_list debugfs_files[] = {
  189. { "regs", tegra_dsi_show_regs, 0, NULL },
  190. };
  191. static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
  192. struct drm_minor *minor)
  193. {
  194. const char *name = dev_name(dsi->dev);
  195. unsigned int i;
  196. int err;
  197. dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
  198. if (!dsi->debugfs)
  199. return -ENOMEM;
  200. dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
  201. GFP_KERNEL);
  202. if (!dsi->debugfs_files) {
  203. err = -ENOMEM;
  204. goto remove;
  205. }
  206. for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
  207. dsi->debugfs_files[i].data = dsi;
  208. err = drm_debugfs_create_files(dsi->debugfs_files,
  209. ARRAY_SIZE(debugfs_files),
  210. dsi->debugfs, minor);
  211. if (err < 0)
  212. goto free;
  213. dsi->minor = minor;
  214. return 0;
  215. free:
  216. kfree(dsi->debugfs_files);
  217. dsi->debugfs_files = NULL;
  218. remove:
  219. debugfs_remove(dsi->debugfs);
  220. dsi->debugfs = NULL;
  221. return err;
  222. }
  223. static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
  224. {
  225. drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
  226. dsi->minor);
  227. dsi->minor = NULL;
  228. kfree(dsi->debugfs_files);
  229. dsi->debugfs_files = NULL;
  230. debugfs_remove(dsi->debugfs);
  231. dsi->debugfs = NULL;
  232. }
  233. #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
  234. #define PKT_LEN0(len) (((len) & 0x07) << 0)
  235. #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
  236. #define PKT_LEN1(len) (((len) & 0x07) << 10)
  237. #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
  238. #define PKT_LEN2(len) (((len) & 0x07) << 20)
  239. #define PKT_LP (1 << 30)
  240. #define NUM_PKT_SEQ 12
  241. /*
  242. * non-burst mode with sync pulses
  243. */
  244. static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
  245. [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
  246. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  247. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  248. PKT_LP,
  249. [ 1] = 0,
  250. [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
  251. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  252. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  253. PKT_LP,
  254. [ 3] = 0,
  255. [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  256. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  257. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  258. PKT_LP,
  259. [ 5] = 0,
  260. [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  261. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  262. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
  263. [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
  264. PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
  265. PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
  266. [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  267. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  268. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  269. PKT_LP,
  270. [ 9] = 0,
  271. [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  272. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  273. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
  274. [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
  275. PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
  276. PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
  277. };
  278. /*
  279. * non-burst mode with sync events
  280. */
  281. static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
  282. [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
  283. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  284. PKT_LP,
  285. [ 1] = 0,
  286. [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  287. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  288. PKT_LP,
  289. [ 3] = 0,
  290. [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  291. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  292. PKT_LP,
  293. [ 5] = 0,
  294. [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  295. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
  296. PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
  297. [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
  298. [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  299. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  300. PKT_LP,
  301. [ 9] = 0,
  302. [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  303. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
  304. PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
  305. [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
  306. };
  307. static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
  308. [ 0] = 0,
  309. [ 1] = 0,
  310. [ 2] = 0,
  311. [ 3] = 0,
  312. [ 4] = 0,
  313. [ 5] = 0,
  314. [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
  315. [ 7] = 0,
  316. [ 8] = 0,
  317. [ 9] = 0,
  318. [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
  319. [11] = 0,
  320. };
  321. static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
  322. unsigned long period,
  323. const struct mipi_dphy_timing *timing)
  324. {
  325. u32 value;
  326. value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
  327. DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
  328. DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
  329. DSI_TIMING_FIELD(timing->hsprepare, period, 1);
  330. tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
  331. value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
  332. DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
  333. DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
  334. DSI_TIMING_FIELD(timing->lpx, period, 1);
  335. tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
  336. value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
  337. DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
  338. DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
  339. tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
  340. value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
  341. DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
  342. DSI_TIMING_FIELD(timing->tago, period, 1);
  343. tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
  344. if (dsi->slave)
  345. tegra_dsi_set_phy_timing(dsi->slave, period, timing);
  346. }
  347. static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
  348. unsigned int *mulp, unsigned int *divp)
  349. {
  350. switch (format) {
  351. case MIPI_DSI_FMT_RGB666_PACKED:
  352. case MIPI_DSI_FMT_RGB888:
  353. *mulp = 3;
  354. *divp = 1;
  355. break;
  356. case MIPI_DSI_FMT_RGB565:
  357. *mulp = 2;
  358. *divp = 1;
  359. break;
  360. case MIPI_DSI_FMT_RGB666:
  361. *mulp = 9;
  362. *divp = 4;
  363. break;
  364. default:
  365. return -EINVAL;
  366. }
  367. return 0;
  368. }
  369. static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
  370. enum tegra_dsi_format *fmt)
  371. {
  372. switch (format) {
  373. case MIPI_DSI_FMT_RGB888:
  374. *fmt = TEGRA_DSI_FORMAT_24P;
  375. break;
  376. case MIPI_DSI_FMT_RGB666:
  377. *fmt = TEGRA_DSI_FORMAT_18NP;
  378. break;
  379. case MIPI_DSI_FMT_RGB666_PACKED:
  380. *fmt = TEGRA_DSI_FORMAT_18P;
  381. break;
  382. case MIPI_DSI_FMT_RGB565:
  383. *fmt = TEGRA_DSI_FORMAT_16P;
  384. break;
  385. default:
  386. return -EINVAL;
  387. }
  388. return 0;
  389. }
  390. static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
  391. unsigned int size)
  392. {
  393. u32 value;
  394. tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
  395. tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
  396. value = DSI_GANGED_MODE_CONTROL_ENABLE;
  397. tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
  398. }
  399. static void tegra_dsi_enable(struct tegra_dsi *dsi)
  400. {
  401. u32 value;
  402. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  403. value |= DSI_POWER_CONTROL_ENABLE;
  404. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  405. if (dsi->slave)
  406. tegra_dsi_enable(dsi->slave);
  407. }
  408. static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
  409. {
  410. if (dsi->master)
  411. return dsi->master->lanes + dsi->lanes;
  412. if (dsi->slave)
  413. return dsi->lanes + dsi->slave->lanes;
  414. return dsi->lanes;
  415. }
  416. static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
  417. const struct drm_display_mode *mode)
  418. {
  419. unsigned int hact, hsw, hbp, hfp, i, mul, div;
  420. struct tegra_dsi_state *state;
  421. const u32 *pkt_seq;
  422. u32 value;
  423. /* XXX: pass in state into this function? */
  424. if (dsi->master)
  425. state = tegra_dsi_get_state(dsi->master);
  426. else
  427. state = tegra_dsi_get_state(dsi);
  428. mul = state->mul;
  429. div = state->div;
  430. if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
  431. DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
  432. pkt_seq = pkt_seq_video_non_burst_sync_pulses;
  433. } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
  434. DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
  435. pkt_seq = pkt_seq_video_non_burst_sync_events;
  436. } else {
  437. DRM_DEBUG_KMS("Command mode\n");
  438. pkt_seq = pkt_seq_command_mode;
  439. }
  440. value = DSI_CONTROL_CHANNEL(0) |
  441. DSI_CONTROL_FORMAT(state->format) |
  442. DSI_CONTROL_LANES(dsi->lanes - 1) |
  443. DSI_CONTROL_SOURCE(pipe);
  444. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  445. tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
  446. value = DSI_HOST_CONTROL_HS;
  447. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  448. value = tegra_dsi_readl(dsi, DSI_CONTROL);
  449. if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
  450. value |= DSI_CONTROL_HS_CLK_CTRL;
  451. value &= ~DSI_CONTROL_TX_TRIG(3);
  452. /* enable DCS commands for command mode */
  453. if (dsi->flags & MIPI_DSI_MODE_VIDEO)
  454. value &= ~DSI_CONTROL_DCS_ENABLE;
  455. else
  456. value |= DSI_CONTROL_DCS_ENABLE;
  457. value |= DSI_CONTROL_VIDEO_ENABLE;
  458. value &= ~DSI_CONTROL_HOST_ENABLE;
  459. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  460. for (i = 0; i < NUM_PKT_SEQ; i++)
  461. tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
  462. if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
  463. /* horizontal active pixels */
  464. hact = mode->hdisplay * mul / div;
  465. /* horizontal sync width */
  466. hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
  467. /* horizontal back porch */
  468. hbp = (mode->htotal - mode->hsync_end) * mul / div;
  469. if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
  470. hbp += hsw;
  471. /* horizontal front porch */
  472. hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
  473. /* subtract packet overhead */
  474. hsw -= 10;
  475. hbp -= 14;
  476. hfp -= 8;
  477. tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
  478. tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
  479. tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
  480. tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
  481. /* set SOL delay (for non-burst mode only) */
  482. tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
  483. /* TODO: implement ganged mode */
  484. } else {
  485. u16 bytes;
  486. if (dsi->master || dsi->slave) {
  487. /*
  488. * For ganged mode, assume symmetric left-right mode.
  489. */
  490. bytes = 1 + (mode->hdisplay / 2) * mul / div;
  491. } else {
  492. /* 1 byte (DCS command) + pixel data */
  493. bytes = 1 + mode->hdisplay * mul / div;
  494. }
  495. tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
  496. tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
  497. tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
  498. tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
  499. value = MIPI_DCS_WRITE_MEMORY_START << 8 |
  500. MIPI_DCS_WRITE_MEMORY_CONTINUE;
  501. tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
  502. /* set SOL delay */
  503. if (dsi->master || dsi->slave) {
  504. unsigned long delay, bclk, bclk_ganged;
  505. unsigned int lanes = state->lanes;
  506. /* SOL to valid, valid to FIFO and FIFO write delay */
  507. delay = 4 + 4 + 2;
  508. delay = DIV_ROUND_UP(delay * mul, div * lanes);
  509. /* FIFO read delay */
  510. delay = delay + 6;
  511. bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
  512. bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
  513. value = bclk - bclk_ganged + delay + 20;
  514. } else {
  515. /* TODO: revisit for non-ganged mode */
  516. value = 8 * mul / div;
  517. }
  518. tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
  519. }
  520. if (dsi->slave) {
  521. tegra_dsi_configure(dsi->slave, pipe, mode);
  522. /*
  523. * TODO: Support modes other than symmetrical left-right
  524. * split.
  525. */
  526. tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
  527. tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
  528. mode->hdisplay / 2);
  529. }
  530. }
  531. static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
  532. {
  533. u32 value;
  534. timeout = jiffies + msecs_to_jiffies(timeout);
  535. while (time_before(jiffies, timeout)) {
  536. value = tegra_dsi_readl(dsi, DSI_STATUS);
  537. if (value & DSI_STATUS_IDLE)
  538. return 0;
  539. usleep_range(1000, 2000);
  540. }
  541. return -ETIMEDOUT;
  542. }
  543. static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
  544. {
  545. u32 value;
  546. value = tegra_dsi_readl(dsi, DSI_CONTROL);
  547. value &= ~DSI_CONTROL_VIDEO_ENABLE;
  548. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  549. if (dsi->slave)
  550. tegra_dsi_video_disable(dsi->slave);
  551. }
  552. static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
  553. {
  554. tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
  555. tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
  556. tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
  557. }
  558. static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
  559. {
  560. u32 value;
  561. value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
  562. tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
  563. return 0;
  564. }
  565. static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
  566. {
  567. u32 value;
  568. /*
  569. * XXX Is this still needed? The module reset is deasserted right
  570. * before this function is called.
  571. */
  572. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
  573. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
  574. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
  575. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
  576. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
  577. /* start calibration */
  578. tegra_dsi_pad_enable(dsi);
  579. value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
  580. DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
  581. DSI_PAD_OUT_CLK(0x0);
  582. tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
  583. value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
  584. DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
  585. tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
  586. return tegra_mipi_calibrate(dsi->mipi);
  587. }
  588. static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
  589. unsigned int vrefresh)
  590. {
  591. unsigned int timeout;
  592. u32 value;
  593. /* one frame high-speed transmission timeout */
  594. timeout = (bclk / vrefresh) / 512;
  595. value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
  596. tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
  597. /* 2 ms peripheral timeout for panel */
  598. timeout = 2 * bclk / 512 * 1000;
  599. value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
  600. tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
  601. value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
  602. tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
  603. if (dsi->slave)
  604. tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
  605. }
  606. static void tegra_dsi_disable(struct tegra_dsi *dsi)
  607. {
  608. u32 value;
  609. if (dsi->slave) {
  610. tegra_dsi_ganged_disable(dsi->slave);
  611. tegra_dsi_ganged_disable(dsi);
  612. }
  613. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  614. value &= ~DSI_POWER_CONTROL_ENABLE;
  615. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  616. if (dsi->slave)
  617. tegra_dsi_disable(dsi->slave);
  618. usleep_range(5000, 10000);
  619. }
  620. static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
  621. {
  622. u32 value;
  623. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  624. value &= ~DSI_POWER_CONTROL_ENABLE;
  625. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  626. usleep_range(300, 1000);
  627. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  628. value |= DSI_POWER_CONTROL_ENABLE;
  629. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  630. usleep_range(300, 1000);
  631. value = tegra_dsi_readl(dsi, DSI_TRIGGER);
  632. if (value)
  633. tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
  634. if (dsi->slave)
  635. tegra_dsi_soft_reset(dsi->slave);
  636. }
  637. static void tegra_dsi_connector_reset(struct drm_connector *connector)
  638. {
  639. struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
  640. if (!state)
  641. return;
  642. if (connector->state) {
  643. __drm_atomic_helper_connector_destroy_state(connector->state);
  644. kfree(connector->state);
  645. }
  646. __drm_atomic_helper_connector_reset(connector, &state->base);
  647. }
  648. static struct drm_connector_state *
  649. tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
  650. {
  651. struct tegra_dsi_state *state = to_dsi_state(connector->state);
  652. struct tegra_dsi_state *copy;
  653. copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
  654. if (!copy)
  655. return NULL;
  656. __drm_atomic_helper_connector_duplicate_state(connector,
  657. &copy->base);
  658. return &copy->base;
  659. }
  660. static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
  661. .reset = tegra_dsi_connector_reset,
  662. .detect = tegra_output_connector_detect,
  663. .fill_modes = drm_helper_probe_single_connector_modes,
  664. .destroy = tegra_output_connector_destroy,
  665. .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
  666. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  667. };
  668. static enum drm_mode_status
  669. tegra_dsi_connector_mode_valid(struct drm_connector *connector,
  670. struct drm_display_mode *mode)
  671. {
  672. return MODE_OK;
  673. }
  674. static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
  675. .get_modes = tegra_output_connector_get_modes,
  676. .mode_valid = tegra_dsi_connector_mode_valid,
  677. };
  678. static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
  679. .destroy = tegra_output_encoder_destroy,
  680. };
  681. static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
  682. {
  683. int err;
  684. if (dsi->slave)
  685. tegra_dsi_unprepare(dsi->slave);
  686. err = tegra_mipi_disable(dsi->mipi);
  687. if (err < 0)
  688. dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
  689. err);
  690. pm_runtime_put(dsi->dev);
  691. }
  692. static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
  693. {
  694. struct tegra_output *output = encoder_to_output(encoder);
  695. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  696. struct tegra_dsi *dsi = to_dsi(output);
  697. u32 value;
  698. int err;
  699. if (output->panel)
  700. drm_panel_disable(output->panel);
  701. tegra_dsi_video_disable(dsi);
  702. /*
  703. * The following accesses registers of the display controller, so make
  704. * sure it's only executed when the output is attached to one.
  705. */
  706. if (dc) {
  707. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  708. value &= ~DSI_ENABLE;
  709. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  710. tegra_dc_commit(dc);
  711. }
  712. err = tegra_dsi_wait_idle(dsi, 100);
  713. if (err < 0)
  714. dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
  715. tegra_dsi_soft_reset(dsi);
  716. if (output->panel)
  717. drm_panel_unprepare(output->panel);
  718. tegra_dsi_disable(dsi);
  719. tegra_dsi_unprepare(dsi);
  720. }
  721. static void tegra_dsi_prepare(struct tegra_dsi *dsi)
  722. {
  723. int err;
  724. pm_runtime_get_sync(dsi->dev);
  725. err = tegra_mipi_enable(dsi->mipi);
  726. if (err < 0)
  727. dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
  728. err);
  729. err = tegra_dsi_pad_calibrate(dsi);
  730. if (err < 0)
  731. dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
  732. if (dsi->slave)
  733. tegra_dsi_prepare(dsi->slave);
  734. }
  735. static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
  736. {
  737. struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
  738. struct tegra_output *output = encoder_to_output(encoder);
  739. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  740. struct tegra_dsi *dsi = to_dsi(output);
  741. struct tegra_dsi_state *state;
  742. u32 value;
  743. tegra_dsi_prepare(dsi);
  744. state = tegra_dsi_get_state(dsi);
  745. tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
  746. /*
  747. * The D-PHY timing fields are expressed in byte-clock cycles, so
  748. * multiply the period by 8.
  749. */
  750. tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
  751. if (output->panel)
  752. drm_panel_prepare(output->panel);
  753. tegra_dsi_configure(dsi, dc->pipe, mode);
  754. /* enable display controller */
  755. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  756. value |= DSI_ENABLE;
  757. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  758. tegra_dc_commit(dc);
  759. /* enable DSI controller */
  760. tegra_dsi_enable(dsi);
  761. if (output->panel)
  762. drm_panel_enable(output->panel);
  763. }
  764. static int
  765. tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
  766. struct drm_crtc_state *crtc_state,
  767. struct drm_connector_state *conn_state)
  768. {
  769. struct tegra_output *output = encoder_to_output(encoder);
  770. struct tegra_dsi_state *state = to_dsi_state(conn_state);
  771. struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
  772. struct tegra_dsi *dsi = to_dsi(output);
  773. unsigned int scdiv;
  774. unsigned long plld;
  775. int err;
  776. state->pclk = crtc_state->mode.clock * 1000;
  777. err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
  778. if (err < 0)
  779. return err;
  780. state->lanes = tegra_dsi_get_lanes(dsi);
  781. err = tegra_dsi_get_format(dsi->format, &state->format);
  782. if (err < 0)
  783. return err;
  784. state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
  785. /* compute byte clock */
  786. state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
  787. DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
  788. state->lanes);
  789. DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
  790. state->vrefresh);
  791. DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
  792. /*
  793. * Compute bit clock and round up to the next MHz.
  794. */
  795. plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
  796. state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
  797. err = mipi_dphy_timing_get_default(&state->timing, state->period);
  798. if (err < 0)
  799. return err;
  800. err = mipi_dphy_timing_validate(&state->timing, state->period);
  801. if (err < 0) {
  802. dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
  803. return err;
  804. }
  805. /*
  806. * We divide the frequency by two here, but we make up for that by
  807. * setting the shift clock divider (further below) to half of the
  808. * correct value.
  809. */
  810. plld /= 2;
  811. /*
  812. * Derive pixel clock from bit clock using the shift clock divider.
  813. * Note that this is only half of what we would expect, but we need
  814. * that to make up for the fact that we divided the bit clock by a
  815. * factor of two above.
  816. *
  817. * It's not clear exactly why this is necessary, but the display is
  818. * not working properly otherwise. Perhaps the PLLs cannot generate
  819. * frequencies sufficiently high.
  820. */
  821. scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
  822. err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
  823. plld, scdiv);
  824. if (err < 0) {
  825. dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
  826. return err;
  827. }
  828. return err;
  829. }
  830. static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
  831. .disable = tegra_dsi_encoder_disable,
  832. .enable = tegra_dsi_encoder_enable,
  833. .atomic_check = tegra_dsi_encoder_atomic_check,
  834. };
  835. static int tegra_dsi_init(struct host1x_client *client)
  836. {
  837. struct drm_device *drm = dev_get_drvdata(client->parent);
  838. struct tegra_dsi *dsi = host1x_client_to_dsi(client);
  839. int err;
  840. /* Gangsters must not register their own outputs. */
  841. if (!dsi->master) {
  842. dsi->output.dev = client->dev;
  843. drm_connector_init(drm, &dsi->output.connector,
  844. &tegra_dsi_connector_funcs,
  845. DRM_MODE_CONNECTOR_DSI);
  846. drm_connector_helper_add(&dsi->output.connector,
  847. &tegra_dsi_connector_helper_funcs);
  848. dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
  849. drm_encoder_init(drm, &dsi->output.encoder,
  850. &tegra_dsi_encoder_funcs,
  851. DRM_MODE_ENCODER_DSI, NULL);
  852. drm_encoder_helper_add(&dsi->output.encoder,
  853. &tegra_dsi_encoder_helper_funcs);
  854. drm_mode_connector_attach_encoder(&dsi->output.connector,
  855. &dsi->output.encoder);
  856. drm_connector_register(&dsi->output.connector);
  857. err = tegra_output_init(drm, &dsi->output);
  858. if (err < 0)
  859. dev_err(dsi->dev, "failed to initialize output: %d\n",
  860. err);
  861. dsi->output.encoder.possible_crtcs = 0x3;
  862. }
  863. if (IS_ENABLED(CONFIG_DEBUG_FS)) {
  864. err = tegra_dsi_debugfs_init(dsi, drm->primary);
  865. if (err < 0)
  866. dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
  867. }
  868. return 0;
  869. }
  870. static int tegra_dsi_exit(struct host1x_client *client)
  871. {
  872. struct tegra_dsi *dsi = host1x_client_to_dsi(client);
  873. tegra_output_exit(&dsi->output);
  874. if (IS_ENABLED(CONFIG_DEBUG_FS))
  875. tegra_dsi_debugfs_exit(dsi);
  876. regulator_disable(dsi->vdd);
  877. return 0;
  878. }
  879. static const struct host1x_client_ops dsi_client_ops = {
  880. .init = tegra_dsi_init,
  881. .exit = tegra_dsi_exit,
  882. };
  883. static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
  884. {
  885. struct clk *parent;
  886. int err;
  887. parent = clk_get_parent(dsi->clk);
  888. if (!parent)
  889. return -EINVAL;
  890. err = clk_set_parent(parent, dsi->clk_parent);
  891. if (err < 0)
  892. return err;
  893. return 0;
  894. }
  895. static const char * const error_report[16] = {
  896. "SoT Error",
  897. "SoT Sync Error",
  898. "EoT Sync Error",
  899. "Escape Mode Entry Command Error",
  900. "Low-Power Transmit Sync Error",
  901. "Peripheral Timeout Error",
  902. "False Control Error",
  903. "Contention Detected",
  904. "ECC Error, single-bit",
  905. "ECC Error, multi-bit",
  906. "Checksum Error",
  907. "DSI Data Type Not Recognized",
  908. "DSI VC ID Invalid",
  909. "Invalid Transmission Length",
  910. "Reserved",
  911. "DSI Protocol Violation",
  912. };
  913. static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
  914. const struct mipi_dsi_msg *msg,
  915. size_t count)
  916. {
  917. u8 *rx = msg->rx_buf;
  918. unsigned int i, j, k;
  919. size_t size = 0;
  920. u16 errors;
  921. u32 value;
  922. /* read and parse packet header */
  923. value = tegra_dsi_readl(dsi, DSI_RD_DATA);
  924. switch (value & 0x3f) {
  925. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  926. errors = (value >> 8) & 0xffff;
  927. dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
  928. errors);
  929. for (i = 0; i < ARRAY_SIZE(error_report); i++)
  930. if (errors & BIT(i))
  931. dev_dbg(dsi->dev, " %2u: %s\n", i,
  932. error_report[i]);
  933. break;
  934. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  935. rx[0] = (value >> 8) & 0xff;
  936. size = 1;
  937. break;
  938. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  939. rx[0] = (value >> 8) & 0xff;
  940. rx[1] = (value >> 16) & 0xff;
  941. size = 2;
  942. break;
  943. case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
  944. size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
  945. break;
  946. case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
  947. size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
  948. break;
  949. default:
  950. dev_err(dsi->dev, "unhandled response type: %02x\n",
  951. value & 0x3f);
  952. return -EPROTO;
  953. }
  954. size = min(size, msg->rx_len);
  955. if (msg->rx_buf && size > 0) {
  956. for (i = 0, j = 0; i < count - 1; i++, j += 4) {
  957. u8 *rx = msg->rx_buf + j;
  958. value = tegra_dsi_readl(dsi, DSI_RD_DATA);
  959. for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
  960. rx[j + k] = (value >> (k << 3)) & 0xff;
  961. }
  962. }
  963. return size;
  964. }
  965. static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
  966. {
  967. tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
  968. timeout = jiffies + msecs_to_jiffies(timeout);
  969. while (time_before(jiffies, timeout)) {
  970. u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
  971. if ((value & DSI_TRIGGER_HOST) == 0)
  972. return 0;
  973. usleep_range(1000, 2000);
  974. }
  975. DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
  976. return -ETIMEDOUT;
  977. }
  978. static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
  979. unsigned long timeout)
  980. {
  981. timeout = jiffies + msecs_to_jiffies(250);
  982. while (time_before(jiffies, timeout)) {
  983. u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
  984. u8 count = value & 0x1f;
  985. if (count > 0)
  986. return count;
  987. usleep_range(1000, 2000);
  988. }
  989. DRM_DEBUG_KMS("peripheral returned no data\n");
  990. return -ETIMEDOUT;
  991. }
  992. static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
  993. const void *buffer, size_t size)
  994. {
  995. const u8 *buf = buffer;
  996. size_t i, j;
  997. u32 value;
  998. for (j = 0; j < size; j += 4) {
  999. value = 0;
  1000. for (i = 0; i < 4 && j + i < size; i++)
  1001. value |= buf[j + i] << (i << 3);
  1002. tegra_dsi_writel(dsi, value, DSI_WR_DATA);
  1003. }
  1004. }
  1005. static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
  1006. const struct mipi_dsi_msg *msg)
  1007. {
  1008. struct tegra_dsi *dsi = host_to_tegra(host);
  1009. struct mipi_dsi_packet packet;
  1010. const u8 *header;
  1011. size_t count;
  1012. ssize_t err;
  1013. u32 value;
  1014. err = mipi_dsi_create_packet(&packet, msg);
  1015. if (err < 0)
  1016. return err;
  1017. header = packet.header;
  1018. /* maximum FIFO depth is 1920 words */
  1019. if (packet.size > dsi->video_fifo_depth * 4)
  1020. return -ENOSPC;
  1021. /* reset underflow/overflow flags */
  1022. value = tegra_dsi_readl(dsi, DSI_STATUS);
  1023. if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
  1024. value = DSI_HOST_CONTROL_FIFO_RESET;
  1025. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  1026. usleep_range(10, 20);
  1027. }
  1028. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  1029. value |= DSI_POWER_CONTROL_ENABLE;
  1030. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  1031. usleep_range(5000, 10000);
  1032. value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
  1033. DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
  1034. if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
  1035. value |= DSI_HOST_CONTROL_HS;
  1036. /*
  1037. * The host FIFO has a maximum of 64 words, so larger transmissions
  1038. * need to use the video FIFO.
  1039. */
  1040. if (packet.size > dsi->host_fifo_depth * 4)
  1041. value |= DSI_HOST_CONTROL_FIFO_SEL;
  1042. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  1043. /*
  1044. * For reads and messages with explicitly requested ACK, generate a
  1045. * BTA sequence after the transmission of the packet.
  1046. */
  1047. if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
  1048. (msg->rx_buf && msg->rx_len > 0)) {
  1049. value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
  1050. value |= DSI_HOST_CONTROL_PKT_BTA;
  1051. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  1052. }
  1053. value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
  1054. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  1055. /* write packet header, ECC is generated by hardware */
  1056. value = header[2] << 16 | header[1] << 8 | header[0];
  1057. tegra_dsi_writel(dsi, value, DSI_WR_DATA);
  1058. /* write payload (if any) */
  1059. if (packet.payload_length > 0)
  1060. tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
  1061. packet.payload_length);
  1062. err = tegra_dsi_transmit(dsi, 250);
  1063. if (err < 0)
  1064. return err;
  1065. if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
  1066. (msg->rx_buf && msg->rx_len > 0)) {
  1067. err = tegra_dsi_wait_for_response(dsi, 250);
  1068. if (err < 0)
  1069. return err;
  1070. count = err;
  1071. value = tegra_dsi_readl(dsi, DSI_RD_DATA);
  1072. switch (value) {
  1073. case 0x84:
  1074. /*
  1075. dev_dbg(dsi->dev, "ACK\n");
  1076. */
  1077. break;
  1078. case 0x87:
  1079. /*
  1080. dev_dbg(dsi->dev, "ESCAPE\n");
  1081. */
  1082. break;
  1083. default:
  1084. dev_err(dsi->dev, "unknown status: %08x\n", value);
  1085. break;
  1086. }
  1087. if (count > 1) {
  1088. err = tegra_dsi_read_response(dsi, msg, count);
  1089. if (err < 0)
  1090. dev_err(dsi->dev,
  1091. "failed to parse response: %zd\n",
  1092. err);
  1093. else {
  1094. /*
  1095. * For read commands, return the number of
  1096. * bytes returned by the peripheral.
  1097. */
  1098. count = err;
  1099. }
  1100. }
  1101. } else {
  1102. /*
  1103. * For write commands, we have transmitted the 4-byte header
  1104. * plus the variable-length payload.
  1105. */
  1106. count = 4 + packet.payload_length;
  1107. }
  1108. return count;
  1109. }
  1110. static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
  1111. {
  1112. struct clk *parent;
  1113. int err;
  1114. /* make sure both DSI controllers share the same PLL */
  1115. parent = clk_get_parent(dsi->slave->clk);
  1116. if (!parent)
  1117. return -EINVAL;
  1118. err = clk_set_parent(parent, dsi->clk_parent);
  1119. if (err < 0)
  1120. return err;
  1121. return 0;
  1122. }
  1123. static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
  1124. struct mipi_dsi_device *device)
  1125. {
  1126. struct tegra_dsi *dsi = host_to_tegra(host);
  1127. dsi->flags = device->mode_flags;
  1128. dsi->format = device->format;
  1129. dsi->lanes = device->lanes;
  1130. if (dsi->slave) {
  1131. int err;
  1132. dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
  1133. dev_name(&device->dev));
  1134. err = tegra_dsi_ganged_setup(dsi);
  1135. if (err < 0) {
  1136. dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
  1137. err);
  1138. return err;
  1139. }
  1140. }
  1141. /*
  1142. * Slaves don't have a panel associated with them, so they provide
  1143. * merely the second channel.
  1144. */
  1145. if (!dsi->master) {
  1146. struct tegra_output *output = &dsi->output;
  1147. output->panel = of_drm_find_panel(device->dev.of_node);
  1148. if (output->panel && output->connector.dev) {
  1149. drm_panel_attach(output->panel, &output->connector);
  1150. drm_helper_hpd_irq_event(output->connector.dev);
  1151. }
  1152. }
  1153. return 0;
  1154. }
  1155. static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
  1156. struct mipi_dsi_device *device)
  1157. {
  1158. struct tegra_dsi *dsi = host_to_tegra(host);
  1159. struct tegra_output *output = &dsi->output;
  1160. if (output->panel && &device->dev == output->panel->dev) {
  1161. output->panel = NULL;
  1162. if (output->connector.dev)
  1163. drm_helper_hpd_irq_event(output->connector.dev);
  1164. }
  1165. return 0;
  1166. }
  1167. static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
  1168. .attach = tegra_dsi_host_attach,
  1169. .detach = tegra_dsi_host_detach,
  1170. .transfer = tegra_dsi_host_transfer,
  1171. };
  1172. static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
  1173. {
  1174. struct device_node *np;
  1175. np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
  1176. if (np) {
  1177. struct platform_device *gangster = of_find_device_by_node(np);
  1178. dsi->slave = platform_get_drvdata(gangster);
  1179. of_node_put(np);
  1180. if (!dsi->slave)
  1181. return -EPROBE_DEFER;
  1182. dsi->slave->master = dsi;
  1183. }
  1184. return 0;
  1185. }
  1186. static int tegra_dsi_probe(struct platform_device *pdev)
  1187. {
  1188. struct tegra_dsi *dsi;
  1189. struct resource *regs;
  1190. int err;
  1191. dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
  1192. if (!dsi)
  1193. return -ENOMEM;
  1194. dsi->output.dev = dsi->dev = &pdev->dev;
  1195. dsi->video_fifo_depth = 1920;
  1196. dsi->host_fifo_depth = 64;
  1197. err = tegra_dsi_ganged_probe(dsi);
  1198. if (err < 0)
  1199. return err;
  1200. err = tegra_output_probe(&dsi->output);
  1201. if (err < 0)
  1202. return err;
  1203. dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
  1204. /*
  1205. * Assume these values by default. When a DSI peripheral driver
  1206. * attaches to the DSI host, the parameters will be taken from
  1207. * the attached device.
  1208. */
  1209. dsi->flags = MIPI_DSI_MODE_VIDEO;
  1210. dsi->format = MIPI_DSI_FMT_RGB888;
  1211. dsi->lanes = 4;
  1212. if (!pdev->dev.pm_domain) {
  1213. dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
  1214. if (IS_ERR(dsi->rst))
  1215. return PTR_ERR(dsi->rst);
  1216. }
  1217. dsi->clk = devm_clk_get(&pdev->dev, NULL);
  1218. if (IS_ERR(dsi->clk)) {
  1219. dev_err(&pdev->dev, "cannot get DSI clock\n");
  1220. return PTR_ERR(dsi->clk);
  1221. }
  1222. dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
  1223. if (IS_ERR(dsi->clk_lp)) {
  1224. dev_err(&pdev->dev, "cannot get low-power clock\n");
  1225. return PTR_ERR(dsi->clk_lp);
  1226. }
  1227. dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
  1228. if (IS_ERR(dsi->clk_parent)) {
  1229. dev_err(&pdev->dev, "cannot get parent clock\n");
  1230. return PTR_ERR(dsi->clk_parent);
  1231. }
  1232. dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
  1233. if (IS_ERR(dsi->vdd)) {
  1234. dev_err(&pdev->dev, "cannot get VDD supply\n");
  1235. return PTR_ERR(dsi->vdd);
  1236. }
  1237. err = tegra_dsi_setup_clocks(dsi);
  1238. if (err < 0) {
  1239. dev_err(&pdev->dev, "cannot setup clocks\n");
  1240. return err;
  1241. }
  1242. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1243. dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
  1244. if (IS_ERR(dsi->regs))
  1245. return PTR_ERR(dsi->regs);
  1246. dsi->mipi = tegra_mipi_request(&pdev->dev);
  1247. if (IS_ERR(dsi->mipi))
  1248. return PTR_ERR(dsi->mipi);
  1249. dsi->host.ops = &tegra_dsi_host_ops;
  1250. dsi->host.dev = &pdev->dev;
  1251. err = mipi_dsi_host_register(&dsi->host);
  1252. if (err < 0) {
  1253. dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
  1254. goto mipi_free;
  1255. }
  1256. platform_set_drvdata(pdev, dsi);
  1257. pm_runtime_enable(&pdev->dev);
  1258. INIT_LIST_HEAD(&dsi->client.list);
  1259. dsi->client.ops = &dsi_client_ops;
  1260. dsi->client.dev = &pdev->dev;
  1261. err = host1x_client_register(&dsi->client);
  1262. if (err < 0) {
  1263. dev_err(&pdev->dev, "failed to register host1x client: %d\n",
  1264. err);
  1265. goto unregister;
  1266. }
  1267. return 0;
  1268. unregister:
  1269. mipi_dsi_host_unregister(&dsi->host);
  1270. mipi_free:
  1271. tegra_mipi_free(dsi->mipi);
  1272. return err;
  1273. }
  1274. static int tegra_dsi_remove(struct platform_device *pdev)
  1275. {
  1276. struct tegra_dsi *dsi = platform_get_drvdata(pdev);
  1277. int err;
  1278. pm_runtime_disable(&pdev->dev);
  1279. err = host1x_client_unregister(&dsi->client);
  1280. if (err < 0) {
  1281. dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
  1282. err);
  1283. return err;
  1284. }
  1285. tegra_output_remove(&dsi->output);
  1286. mipi_dsi_host_unregister(&dsi->host);
  1287. tegra_mipi_free(dsi->mipi);
  1288. return 0;
  1289. }
  1290. #ifdef CONFIG_PM
  1291. static int tegra_dsi_suspend(struct device *dev)
  1292. {
  1293. struct tegra_dsi *dsi = dev_get_drvdata(dev);
  1294. int err;
  1295. if (dsi->rst) {
  1296. err = reset_control_assert(dsi->rst);
  1297. if (err < 0) {
  1298. dev_err(dev, "failed to assert reset: %d\n", err);
  1299. return err;
  1300. }
  1301. }
  1302. usleep_range(1000, 2000);
  1303. clk_disable_unprepare(dsi->clk_lp);
  1304. clk_disable_unprepare(dsi->clk);
  1305. regulator_disable(dsi->vdd);
  1306. return 0;
  1307. }
  1308. static int tegra_dsi_resume(struct device *dev)
  1309. {
  1310. struct tegra_dsi *dsi = dev_get_drvdata(dev);
  1311. int err;
  1312. err = regulator_enable(dsi->vdd);
  1313. if (err < 0) {
  1314. dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err);
  1315. return err;
  1316. }
  1317. err = clk_prepare_enable(dsi->clk);
  1318. if (err < 0) {
  1319. dev_err(dev, "cannot enable DSI clock: %d\n", err);
  1320. goto disable_vdd;
  1321. }
  1322. err = clk_prepare_enable(dsi->clk_lp);
  1323. if (err < 0) {
  1324. dev_err(dev, "cannot enable low-power clock: %d\n", err);
  1325. goto disable_clk;
  1326. }
  1327. usleep_range(1000, 2000);
  1328. if (dsi->rst) {
  1329. err = reset_control_deassert(dsi->rst);
  1330. if (err < 0) {
  1331. dev_err(dev, "cannot assert reset: %d\n", err);
  1332. goto disable_clk_lp;
  1333. }
  1334. }
  1335. return 0;
  1336. disable_clk_lp:
  1337. clk_disable_unprepare(dsi->clk_lp);
  1338. disable_clk:
  1339. clk_disable_unprepare(dsi->clk);
  1340. disable_vdd:
  1341. regulator_disable(dsi->vdd);
  1342. return err;
  1343. }
  1344. #endif
  1345. static const struct dev_pm_ops tegra_dsi_pm_ops = {
  1346. SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL)
  1347. };
  1348. static const struct of_device_id tegra_dsi_of_match[] = {
  1349. { .compatible = "nvidia,tegra210-dsi", },
  1350. { .compatible = "nvidia,tegra132-dsi", },
  1351. { .compatible = "nvidia,tegra124-dsi", },
  1352. { .compatible = "nvidia,tegra114-dsi", },
  1353. { },
  1354. };
  1355. MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
  1356. struct platform_driver tegra_dsi_driver = {
  1357. .driver = {
  1358. .name = "tegra-dsi",
  1359. .of_match_table = tegra_dsi_of_match,
  1360. .pm = &tegra_dsi_pm_ops,
  1361. },
  1362. .probe = tegra_dsi_probe,
  1363. .remove = tegra_dsi_remove,
  1364. };