armada_overlay.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498
  1. /*
  2. * Copyright (C) 2012 Russell King
  3. * Rewritten from the dovefb driver, and Armada510 manuals.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <drm/drmP.h>
  10. #include <drm/drm_plane_helper.h>
  11. #include "armada_crtc.h"
  12. #include "armada_drm.h"
  13. #include "armada_fb.h"
  14. #include "armada_gem.h"
  15. #include "armada_hw.h"
  16. #include <drm/armada_drm.h>
  17. #include "armada_ioctlP.h"
  18. #include "armada_trace.h"
  19. struct armada_ovl_plane_properties {
  20. uint32_t colorkey_yr;
  21. uint32_t colorkey_ug;
  22. uint32_t colorkey_vb;
  23. #define K2R(val) (((val) >> 0) & 0xff)
  24. #define K2G(val) (((val) >> 8) & 0xff)
  25. #define K2B(val) (((val) >> 16) & 0xff)
  26. int16_t brightness;
  27. uint16_t contrast;
  28. uint16_t saturation;
  29. uint32_t colorkey_mode;
  30. };
  31. struct armada_ovl_plane {
  32. struct armada_plane base;
  33. struct drm_framebuffer *old_fb;
  34. struct {
  35. struct armada_plane_work work;
  36. struct armada_regs regs[13];
  37. } vbl;
  38. struct armada_ovl_plane_properties prop;
  39. };
  40. #define drm_to_armada_ovl_plane(p) \
  41. container_of(p, struct armada_ovl_plane, base.base)
  42. static void
  43. armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
  44. struct armada_crtc *dcrtc)
  45. {
  46. writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
  47. writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
  48. writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
  49. writel_relaxed(prop->brightness << 16 | prop->contrast,
  50. dcrtc->base + LCD_SPU_CONTRAST);
  51. /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
  52. writel_relaxed(prop->saturation << 16,
  53. dcrtc->base + LCD_SPU_SATURATION);
  54. writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
  55. spin_lock_irq(&dcrtc->irq_lock);
  56. armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
  57. CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
  58. dcrtc->base + LCD_SPU_DMA_CTRL1);
  59. armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
  60. spin_unlock_irq(&dcrtc->irq_lock);
  61. }
  62. static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
  63. struct drm_framebuffer *fb)
  64. {
  65. struct drm_framebuffer *old_fb;
  66. old_fb = xchg(&dplane->old_fb, fb);
  67. if (old_fb)
  68. armada_drm_queue_unref_work(dplane->base.base.dev, old_fb);
  69. }
  70. /* === Plane support === */
  71. static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
  72. struct armada_plane *plane, struct armada_plane_work *work)
  73. {
  74. struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base);
  75. trace_armada_ovl_plane_work(&dcrtc->crtc, &plane->base);
  76. armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
  77. armada_ovl_retire_fb(dplane, NULL);
  78. }
  79. static int
  80. armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  81. struct drm_framebuffer *fb,
  82. int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
  83. uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
  84. struct drm_modeset_acquire_ctx *ctx)
  85. {
  86. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  87. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  88. struct drm_rect src = {
  89. .x1 = src_x,
  90. .y1 = src_y,
  91. .x2 = src_x + src_w,
  92. .y2 = src_y + src_h,
  93. };
  94. struct drm_rect dest = {
  95. .x1 = crtc_x,
  96. .y1 = crtc_y,
  97. .x2 = crtc_x + crtc_w,
  98. .y2 = crtc_y + crtc_h,
  99. };
  100. const struct drm_rect clip = {
  101. .x2 = crtc->mode.hdisplay,
  102. .y2 = crtc->mode.vdisplay,
  103. };
  104. uint32_t val, ctrl0;
  105. unsigned idx = 0;
  106. bool visible;
  107. int ret;
  108. trace_armada_ovl_plane_update(plane, crtc, fb,
  109. crtc_x, crtc_y, crtc_w, crtc_h,
  110. src_x, src_y, src_w, src_h);
  111. ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
  112. DRM_MODE_ROTATE_0,
  113. 0, INT_MAX, true, false, &visible);
  114. if (ret)
  115. return ret;
  116. ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
  117. CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
  118. CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
  119. /* Does the position/size result in nothing to display? */
  120. if (!visible)
  121. ctrl0 &= ~CFG_DMA_ENA;
  122. if (!dcrtc->plane) {
  123. dcrtc->plane = plane;
  124. armada_ovl_update_attr(&dplane->prop, dcrtc);
  125. }
  126. /* FIXME: overlay on an interlaced display */
  127. /* Just updating the position/size? */
  128. if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) {
  129. val = (drm_rect_height(&src) & 0xffff0000) |
  130. drm_rect_width(&src) >> 16;
  131. dplane->base.state.src_hw = val;
  132. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
  133. val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
  134. dplane->base.state.dst_hw = val;
  135. writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
  136. val = dest.y1 << 16 | dest.x1;
  137. dplane->base.state.dst_yx = val;
  138. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
  139. return 0;
  140. } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
  141. /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
  142. armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
  143. dcrtc->base + LCD_SPU_SRAM_PARA1);
  144. }
  145. if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
  146. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  147. if (plane->fb != fb) {
  148. u32 addrs[3], pixel_format;
  149. int num_planes, hsub;
  150. /*
  151. * Take a reference on the new framebuffer - we want to
  152. * hold on to it while the hardware is displaying it.
  153. */
  154. drm_framebuffer_reference(fb);
  155. if (plane->fb)
  156. armada_ovl_retire_fb(dplane, plane->fb);
  157. src_y = src.y1 >> 16;
  158. src_x = src.x1 >> 16;
  159. armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y);
  160. pixel_format = fb->format->format;
  161. hsub = drm_format_horz_chroma_subsampling(pixel_format);
  162. num_planes = fb->format->num_planes;
  163. /*
  164. * Annoyingly, shifting a YUYV-format image by one pixel
  165. * causes the U/V planes to toggle. Toggle the UV swap.
  166. * (Unfortunately, this causes momentary colour flickering.)
  167. */
  168. if (src_x & (hsub - 1) && num_planes == 1)
  169. ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
  170. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0],
  171. LCD_SPU_DMA_START_ADDR_Y0);
  172. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1],
  173. LCD_SPU_DMA_START_ADDR_U0);
  174. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2],
  175. LCD_SPU_DMA_START_ADDR_V0);
  176. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0],
  177. LCD_SPU_DMA_START_ADDR_Y1);
  178. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1],
  179. LCD_SPU_DMA_START_ADDR_U1);
  180. armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2],
  181. LCD_SPU_DMA_START_ADDR_V1);
  182. val = fb->pitches[0] << 16 | fb->pitches[0];
  183. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  184. LCD_SPU_DMA_PITCH_YC);
  185. val = fb->pitches[1] << 16 | fb->pitches[2];
  186. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  187. LCD_SPU_DMA_PITCH_UV);
  188. }
  189. val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
  190. if (dplane->base.state.src_hw != val) {
  191. dplane->base.state.src_hw = val;
  192. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  193. LCD_SPU_DMA_HPXL_VLN);
  194. }
  195. val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
  196. if (dplane->base.state.dst_hw != val) {
  197. dplane->base.state.dst_hw = val;
  198. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  199. LCD_SPU_DZM_HPXL_VLN);
  200. }
  201. val = dest.y1 << 16 | dest.x1;
  202. if (dplane->base.state.dst_yx != val) {
  203. dplane->base.state.dst_yx = val;
  204. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  205. LCD_SPU_DMA_OVSA_HPXL_VLN);
  206. }
  207. if (dplane->base.state.ctrl0 != ctrl0) {
  208. dplane->base.state.ctrl0 = ctrl0;
  209. armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
  210. CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
  211. CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
  212. CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
  213. CFG_YUV2RGB) | CFG_DMA_ENA,
  214. LCD_SPU_DMA_CTRL0);
  215. }
  216. if (idx) {
  217. armada_reg_queue_end(dplane->vbl.regs, idx);
  218. armada_drm_plane_work_queue(dcrtc, &dplane->base,
  219. &dplane->vbl.work);
  220. }
  221. return 0;
  222. }
  223. static int armada_ovl_plane_disable(struct drm_plane *plane,
  224. struct drm_modeset_acquire_ctx *ctx)
  225. {
  226. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  227. struct drm_framebuffer *fb;
  228. struct armada_crtc *dcrtc;
  229. if (!dplane->base.base.crtc)
  230. return 0;
  231. dcrtc = drm_to_armada_crtc(dplane->base.base.crtc);
  232. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  233. armada_drm_crtc_plane_disable(dcrtc, plane);
  234. dcrtc->plane = NULL;
  235. dplane->base.state.ctrl0 = 0;
  236. fb = xchg(&dplane->old_fb, NULL);
  237. if (fb)
  238. drm_framebuffer_unreference(fb);
  239. return 0;
  240. }
  241. static void armada_ovl_plane_destroy(struct drm_plane *plane)
  242. {
  243. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  244. drm_plane_cleanup(plane);
  245. kfree(dplane);
  246. }
  247. static int armada_ovl_plane_set_property(struct drm_plane *plane,
  248. struct drm_property *property, uint64_t val)
  249. {
  250. struct armada_private *priv = plane->dev->dev_private;
  251. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  252. bool update_attr = false;
  253. if (property == priv->colorkey_prop) {
  254. #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
  255. dplane->prop.colorkey_yr = CCC(K2R(val));
  256. dplane->prop.colorkey_ug = CCC(K2G(val));
  257. dplane->prop.colorkey_vb = CCC(K2B(val));
  258. #undef CCC
  259. update_attr = true;
  260. } else if (property == priv->colorkey_min_prop) {
  261. dplane->prop.colorkey_yr &= ~0x00ff0000;
  262. dplane->prop.colorkey_yr |= K2R(val) << 16;
  263. dplane->prop.colorkey_ug &= ~0x00ff0000;
  264. dplane->prop.colorkey_ug |= K2G(val) << 16;
  265. dplane->prop.colorkey_vb &= ~0x00ff0000;
  266. dplane->prop.colorkey_vb |= K2B(val) << 16;
  267. update_attr = true;
  268. } else if (property == priv->colorkey_max_prop) {
  269. dplane->prop.colorkey_yr &= ~0xff000000;
  270. dplane->prop.colorkey_yr |= K2R(val) << 24;
  271. dplane->prop.colorkey_ug &= ~0xff000000;
  272. dplane->prop.colorkey_ug |= K2G(val) << 24;
  273. dplane->prop.colorkey_vb &= ~0xff000000;
  274. dplane->prop.colorkey_vb |= K2B(val) << 24;
  275. update_attr = true;
  276. } else if (property == priv->colorkey_val_prop) {
  277. dplane->prop.colorkey_yr &= ~0x0000ff00;
  278. dplane->prop.colorkey_yr |= K2R(val) << 8;
  279. dplane->prop.colorkey_ug &= ~0x0000ff00;
  280. dplane->prop.colorkey_ug |= K2G(val) << 8;
  281. dplane->prop.colorkey_vb &= ~0x0000ff00;
  282. dplane->prop.colorkey_vb |= K2B(val) << 8;
  283. update_attr = true;
  284. } else if (property == priv->colorkey_alpha_prop) {
  285. dplane->prop.colorkey_yr &= ~0x000000ff;
  286. dplane->prop.colorkey_yr |= K2R(val);
  287. dplane->prop.colorkey_ug &= ~0x000000ff;
  288. dplane->prop.colorkey_ug |= K2G(val);
  289. dplane->prop.colorkey_vb &= ~0x000000ff;
  290. dplane->prop.colorkey_vb |= K2B(val);
  291. update_attr = true;
  292. } else if (property == priv->colorkey_mode_prop) {
  293. dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
  294. dplane->prop.colorkey_mode |= CFG_CKMODE(val);
  295. update_attr = true;
  296. } else if (property == priv->brightness_prop) {
  297. dplane->prop.brightness = val - 256;
  298. update_attr = true;
  299. } else if (property == priv->contrast_prop) {
  300. dplane->prop.contrast = val;
  301. update_attr = true;
  302. } else if (property == priv->saturation_prop) {
  303. dplane->prop.saturation = val;
  304. update_attr = true;
  305. }
  306. if (update_attr && dplane->base.base.crtc)
  307. armada_ovl_update_attr(&dplane->prop,
  308. drm_to_armada_crtc(dplane->base.base.crtc));
  309. return 0;
  310. }
  311. static const struct drm_plane_funcs armada_ovl_plane_funcs = {
  312. .update_plane = armada_ovl_plane_update,
  313. .disable_plane = armada_ovl_plane_disable,
  314. .destroy = armada_ovl_plane_destroy,
  315. .set_property = armada_ovl_plane_set_property,
  316. };
  317. static const uint32_t armada_ovl_formats[] = {
  318. DRM_FORMAT_UYVY,
  319. DRM_FORMAT_YUYV,
  320. DRM_FORMAT_YUV420,
  321. DRM_FORMAT_YVU420,
  322. DRM_FORMAT_YUV422,
  323. DRM_FORMAT_YVU422,
  324. DRM_FORMAT_VYUY,
  325. DRM_FORMAT_YVYU,
  326. DRM_FORMAT_ARGB8888,
  327. DRM_FORMAT_ABGR8888,
  328. DRM_FORMAT_XRGB8888,
  329. DRM_FORMAT_XBGR8888,
  330. DRM_FORMAT_RGB888,
  331. DRM_FORMAT_BGR888,
  332. DRM_FORMAT_ARGB1555,
  333. DRM_FORMAT_ABGR1555,
  334. DRM_FORMAT_RGB565,
  335. DRM_FORMAT_BGR565,
  336. };
  337. static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
  338. { CKMODE_DISABLE, "disabled" },
  339. { CKMODE_Y, "Y component" },
  340. { CKMODE_U, "U component" },
  341. { CKMODE_V, "V component" },
  342. { CKMODE_RGB, "RGB" },
  343. { CKMODE_R, "R component" },
  344. { CKMODE_G, "G component" },
  345. { CKMODE_B, "B component" },
  346. };
  347. static int armada_overlay_create_properties(struct drm_device *dev)
  348. {
  349. struct armada_private *priv = dev->dev_private;
  350. if (priv->colorkey_prop)
  351. return 0;
  352. priv->colorkey_prop = drm_property_create_range(dev, 0,
  353. "colorkey", 0, 0xffffff);
  354. priv->colorkey_min_prop = drm_property_create_range(dev, 0,
  355. "colorkey_min", 0, 0xffffff);
  356. priv->colorkey_max_prop = drm_property_create_range(dev, 0,
  357. "colorkey_max", 0, 0xffffff);
  358. priv->colorkey_val_prop = drm_property_create_range(dev, 0,
  359. "colorkey_val", 0, 0xffffff);
  360. priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
  361. "colorkey_alpha", 0, 0xffffff);
  362. priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
  363. "colorkey_mode",
  364. armada_drm_colorkey_enum_list,
  365. ARRAY_SIZE(armada_drm_colorkey_enum_list));
  366. priv->brightness_prop = drm_property_create_range(dev, 0,
  367. "brightness", 0, 256 + 255);
  368. priv->contrast_prop = drm_property_create_range(dev, 0,
  369. "contrast", 0, 0x7fff);
  370. priv->saturation_prop = drm_property_create_range(dev, 0,
  371. "saturation", 0, 0x7fff);
  372. if (!priv->colorkey_prop)
  373. return -ENOMEM;
  374. return 0;
  375. }
  376. int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
  377. {
  378. struct armada_private *priv = dev->dev_private;
  379. struct drm_mode_object *mobj;
  380. struct armada_ovl_plane *dplane;
  381. int ret;
  382. ret = armada_overlay_create_properties(dev);
  383. if (ret)
  384. return ret;
  385. dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
  386. if (!dplane)
  387. return -ENOMEM;
  388. ret = armada_drm_plane_init(&dplane->base);
  389. if (ret) {
  390. kfree(dplane);
  391. return ret;
  392. }
  393. dplane->vbl.work.fn = armada_ovl_plane_work;
  394. ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
  395. &armada_ovl_plane_funcs,
  396. armada_ovl_formats,
  397. ARRAY_SIZE(armada_ovl_formats),
  398. NULL,
  399. DRM_PLANE_TYPE_OVERLAY, NULL);
  400. if (ret) {
  401. kfree(dplane);
  402. return ret;
  403. }
  404. dplane->prop.colorkey_yr = 0xfefefe00;
  405. dplane->prop.colorkey_ug = 0x01010100;
  406. dplane->prop.colorkey_vb = 0x01010100;
  407. dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
  408. dplane->prop.brightness = 0;
  409. dplane->prop.contrast = 0x4000;
  410. dplane->prop.saturation = 0x4000;
  411. mobj = &dplane->base.base.base;
  412. drm_object_attach_property(mobj, priv->colorkey_prop,
  413. 0x0101fe);
  414. drm_object_attach_property(mobj, priv->colorkey_min_prop,
  415. 0x0101fe);
  416. drm_object_attach_property(mobj, priv->colorkey_max_prop,
  417. 0x0101fe);
  418. drm_object_attach_property(mobj, priv->colorkey_val_prop,
  419. 0x0101fe);
  420. drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
  421. 0x000000);
  422. drm_object_attach_property(mobj, priv->colorkey_mode_prop,
  423. CKMODE_RGB);
  424. drm_object_attach_property(mobj, priv->brightness_prop, 256);
  425. drm_object_attach_property(mobj, priv->contrast_prop,
  426. dplane->prop.contrast);
  427. drm_object_attach_property(mobj, priv->saturation_prop,
  428. dplane->prop.saturation);
  429. return 0;
  430. }