kfd_mqd_manager_cik.c 12 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/printk.h>
  24. #include <linux/slab.h>
  25. #include <linux/mm_types.h>
  26. #include "kfd_priv.h"
  27. #include "kfd_mqd_manager.h"
  28. #include "cik_regs.h"
  29. #include "cik_structs.h"
  30. #include "oss/oss_2_4_sh_mask.h"
  31. static inline struct cik_mqd *get_mqd(void *mqd)
  32. {
  33. return (struct cik_mqd *)mqd;
  34. }
  35. static int init_mqd(struct mqd_manager *mm, void **mqd,
  36. struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
  37. struct queue_properties *q)
  38. {
  39. uint64_t addr;
  40. struct cik_mqd *m;
  41. int retval;
  42. retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd),
  43. mqd_mem_obj);
  44. if (retval != 0)
  45. return -ENOMEM;
  46. m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr;
  47. addr = (*mqd_mem_obj)->gpu_addr;
  48. memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
  49. m->header = 0xC0310800;
  50. m->compute_pipelinestat_enable = 1;
  51. m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
  52. m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
  53. m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
  54. m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
  55. /*
  56. * Make sure to use the last queue state saved on mqd when the cp
  57. * reassigns the queue, so when queue is switched on/off (e.g over
  58. * subscription or quantum timeout) the context will be consistent
  59. */
  60. m->cp_hqd_persistent_state =
  61. DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ;
  62. m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN;
  63. m->cp_mqd_base_addr_lo = lower_32_bits(addr);
  64. m->cp_mqd_base_addr_hi = upper_32_bits(addr);
  65. m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE | IB_ATC_EN;
  66. /* Although WinKFD writes this, I suspect it should not be necessary */
  67. m->cp_hqd_ib_control = IB_ATC_EN | DEFAULT_MIN_IB_AVAIL_SIZE;
  68. m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
  69. QUANTUM_DURATION(10);
  70. /*
  71. * Pipe Priority
  72. * Identifies the pipe relative priority when this queue is connected
  73. * to the pipeline. The pipe priority is against the GFX pipe and HP3D.
  74. * In KFD we are using a fixed pipe priority set to CS_MEDIUM.
  75. * 0 = CS_LOW (typically below GFX)
  76. * 1 = CS_MEDIUM (typically between HP3D and GFX
  77. * 2 = CS_HIGH (typically above HP3D)
  78. */
  79. m->cp_hqd_pipe_priority = 1;
  80. m->cp_hqd_queue_priority = 15;
  81. if (q->format == KFD_QUEUE_FORMAT_AQL)
  82. m->cp_hqd_iq_rptr = AQL_ENABLE;
  83. *mqd = m;
  84. if (gart_addr)
  85. *gart_addr = addr;
  86. retval = mm->update_mqd(mm, m, q);
  87. return retval;
  88. }
  89. static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
  90. struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
  91. struct queue_properties *q)
  92. {
  93. int retval;
  94. struct cik_sdma_rlc_registers *m;
  95. retval = kfd_gtt_sa_allocate(mm->dev,
  96. sizeof(struct cik_sdma_rlc_registers),
  97. mqd_mem_obj);
  98. if (retval != 0)
  99. return -ENOMEM;
  100. m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr;
  101. memset(m, 0, sizeof(struct cik_sdma_rlc_registers));
  102. *mqd = m;
  103. if (gart_addr)
  104. *gart_addr = (*mqd_mem_obj)->gpu_addr;
  105. retval = mm->update_mqd(mm, m, q);
  106. return retval;
  107. }
  108. static void uninit_mqd(struct mqd_manager *mm, void *mqd,
  109. struct kfd_mem_obj *mqd_mem_obj)
  110. {
  111. kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
  112. }
  113. static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
  114. struct kfd_mem_obj *mqd_mem_obj)
  115. {
  116. kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
  117. }
  118. static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id,
  119. uint32_t queue_id, struct queue_properties *p,
  120. struct mm_struct *mms)
  121. {
  122. /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
  123. uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
  124. uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1);
  125. return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
  126. (uint32_t __user *)p->write_ptr,
  127. wptr_shift, wptr_mask, mms);
  128. }
  129. static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
  130. uint32_t pipe_id, uint32_t queue_id,
  131. struct queue_properties *p, struct mm_struct *mms)
  132. {
  133. return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd);
  134. }
  135. static int update_mqd(struct mqd_manager *mm, void *mqd,
  136. struct queue_properties *q)
  137. {
  138. struct cik_mqd *m;
  139. m = get_mqd(mqd);
  140. m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
  141. DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN;
  142. /*
  143. * Calculating queue size which is log base 2 of actual queue size -1
  144. * dwords and another -1 for ffs
  145. */
  146. m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
  147. - 1 - 1;
  148. m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
  149. m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
  150. m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
  151. m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
  152. m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);
  153. m->cp_hqd_vmid = q->vmid;
  154. if (q->format == KFD_QUEUE_FORMAT_AQL)
  155. m->cp_hqd_pq_control |= NO_UPDATE_RPTR;
  156. q->is_active = false;
  157. if (q->queue_size > 0 &&
  158. q->queue_address != 0 &&
  159. q->queue_percent > 0) {
  160. q->is_active = true;
  161. }
  162. return 0;
  163. }
  164. static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
  165. struct queue_properties *q)
  166. {
  167. struct cik_sdma_rlc_registers *m;
  168. m = get_sdma_mqd(mqd);
  169. m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
  170. SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
  171. q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
  172. 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
  173. 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
  174. m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
  175. m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
  176. m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
  177. m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
  178. m->sdma_rlc_doorbell = q->doorbell_off <<
  179. SDMA0_RLC0_DOORBELL__OFFSET__SHIFT |
  180. 1 << SDMA0_RLC0_DOORBELL__ENABLE__SHIFT;
  181. m->sdma_rlc_virtual_addr = q->sdma_vm_addr;
  182. m->sdma_engine_id = q->sdma_engine_id;
  183. m->sdma_queue_id = q->sdma_queue_id;
  184. q->is_active = false;
  185. if (q->queue_size > 0 &&
  186. q->queue_address != 0 &&
  187. q->queue_percent > 0) {
  188. m->sdma_rlc_rb_cntl |=
  189. 1 << SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT;
  190. q->is_active = true;
  191. }
  192. return 0;
  193. }
  194. static int destroy_mqd(struct mqd_manager *mm, void *mqd,
  195. enum kfd_preempt_type type,
  196. unsigned int timeout, uint32_t pipe_id,
  197. uint32_t queue_id)
  198. {
  199. return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout,
  200. pipe_id, queue_id);
  201. }
  202. /*
  203. * preempt type here is ignored because there is only one way
  204. * to preempt sdma queue
  205. */
  206. static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
  207. enum kfd_preempt_type type,
  208. unsigned int timeout, uint32_t pipe_id,
  209. uint32_t queue_id)
  210. {
  211. return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
  212. }
  213. static bool is_occupied(struct mqd_manager *mm, void *mqd,
  214. uint64_t queue_address, uint32_t pipe_id,
  215. uint32_t queue_id)
  216. {
  217. return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address,
  218. pipe_id, queue_id);
  219. }
  220. static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
  221. uint64_t queue_address, uint32_t pipe_id,
  222. uint32_t queue_id)
  223. {
  224. return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
  225. }
  226. /*
  227. * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation.
  228. * The HIQ queue in Kaveri is using the same MQD structure as all the user mode
  229. * queues but with different initial values.
  230. */
  231. static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
  232. struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
  233. struct queue_properties *q)
  234. {
  235. uint64_t addr;
  236. struct cik_mqd *m;
  237. int retval;
  238. retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd),
  239. mqd_mem_obj);
  240. if (retval != 0)
  241. return -ENOMEM;
  242. m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr;
  243. addr = (*mqd_mem_obj)->gpu_addr;
  244. memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
  245. m->header = 0xC0310800;
  246. m->compute_pipelinestat_enable = 1;
  247. m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
  248. m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
  249. m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
  250. m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
  251. m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE |
  252. PRELOAD_REQ;
  253. m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
  254. QUANTUM_DURATION(10);
  255. m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN;
  256. m->cp_mqd_base_addr_lo = lower_32_bits(addr);
  257. m->cp_mqd_base_addr_hi = upper_32_bits(addr);
  258. m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE;
  259. /*
  260. * Pipe Priority
  261. * Identifies the pipe relative priority when this queue is connected
  262. * to the pipeline. The pipe priority is against the GFX pipe and HP3D.
  263. * In KFD we are using a fixed pipe priority set to CS_MEDIUM.
  264. * 0 = CS_LOW (typically below GFX)
  265. * 1 = CS_MEDIUM (typically between HP3D and GFX
  266. * 2 = CS_HIGH (typically above HP3D)
  267. */
  268. m->cp_hqd_pipe_priority = 1;
  269. m->cp_hqd_queue_priority = 15;
  270. *mqd = m;
  271. if (gart_addr)
  272. *gart_addr = addr;
  273. retval = mm->update_mqd(mm, m, q);
  274. return retval;
  275. }
  276. static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
  277. struct queue_properties *q)
  278. {
  279. struct cik_mqd *m;
  280. m = get_mqd(mqd);
  281. m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
  282. DEFAULT_MIN_AVAIL_SIZE |
  283. PRIV_STATE |
  284. KMD_QUEUE;
  285. /*
  286. * Calculating queue size which is log base 2 of actual queue
  287. * size -1 dwords
  288. */
  289. m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
  290. - 1 - 1;
  291. m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
  292. m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
  293. m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
  294. m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
  295. m->cp_hqd_pq_doorbell_control = DOORBELL_EN |
  296. DOORBELL_OFFSET(q->doorbell_off);
  297. m->cp_hqd_vmid = q->vmid;
  298. m->cp_hqd_active = 0;
  299. q->is_active = false;
  300. if (q->queue_size > 0 &&
  301. q->queue_address != 0 &&
  302. q->queue_percent > 0) {
  303. m->cp_hqd_active = 1;
  304. q->is_active = true;
  305. }
  306. return 0;
  307. }
  308. struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
  309. {
  310. struct cik_sdma_rlc_registers *m;
  311. m = (struct cik_sdma_rlc_registers *)mqd;
  312. return m;
  313. }
  314. struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
  315. struct kfd_dev *dev)
  316. {
  317. struct mqd_manager *mqd;
  318. if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
  319. return NULL;
  320. mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
  321. if (!mqd)
  322. return NULL;
  323. mqd->dev = dev;
  324. switch (type) {
  325. case KFD_MQD_TYPE_CP:
  326. case KFD_MQD_TYPE_COMPUTE:
  327. mqd->init_mqd = init_mqd;
  328. mqd->uninit_mqd = uninit_mqd;
  329. mqd->load_mqd = load_mqd;
  330. mqd->update_mqd = update_mqd;
  331. mqd->destroy_mqd = destroy_mqd;
  332. mqd->is_occupied = is_occupied;
  333. break;
  334. case KFD_MQD_TYPE_HIQ:
  335. mqd->init_mqd = init_mqd_hiq;
  336. mqd->uninit_mqd = uninit_mqd;
  337. mqd->load_mqd = load_mqd;
  338. mqd->update_mqd = update_mqd_hiq;
  339. mqd->destroy_mqd = destroy_mqd;
  340. mqd->is_occupied = is_occupied;
  341. break;
  342. case KFD_MQD_TYPE_SDMA:
  343. mqd->init_mqd = init_mqd_sdma;
  344. mqd->uninit_mqd = uninit_mqd_sdma;
  345. mqd->load_mqd = load_mqd_sdma;
  346. mqd->update_mqd = update_mqd_sdma;
  347. mqd->destroy_mqd = destroy_mqd_sdma;
  348. mqd->is_occupied = is_occupied_sdma;
  349. break;
  350. default:
  351. kfree(mqd);
  352. return NULL;
  353. }
  354. return mqd;
  355. }