s3c2410_udc.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * linux/drivers/usb/gadget/s3c2410_udc.c
  4. *
  5. * Samsung S3C24xx series on-chip full speed USB device controllers
  6. *
  7. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  8. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  9. */
  10. #define pr_fmt(fmt) "s3c2410_udc: " fmt
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/ioport.h>
  15. #include <linux/sched.h>
  16. #include <linux/slab.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/timer.h>
  20. #include <linux/list.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/gpio.h>
  25. #include <linux/prefetch.h>
  26. #include <linux/io.h>
  27. #include <linux/debugfs.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/usb.h>
  30. #include <linux/usb/gadget.h>
  31. #include <asm/byteorder.h>
  32. #include <asm/irq.h>
  33. #include <asm/unaligned.h>
  34. #include <mach/irqs.h>
  35. #include <mach/hardware.h>
  36. #include <plat/regs-udc.h>
  37. #include <linux/platform_data/usb-s3c2410_udc.h>
  38. #include "s3c2410_udc.h"
  39. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  40. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  41. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  42. static const char gadget_name[] = "s3c2410_udc";
  43. static const char driver_desc[] = DRIVER_DESC;
  44. static struct s3c2410_udc *the_controller;
  45. static struct clk *udc_clock;
  46. static struct clk *usb_bus_clock;
  47. static void __iomem *base_addr;
  48. static u64 rsrc_start;
  49. static u64 rsrc_len;
  50. static struct dentry *s3c2410_udc_debugfs_root;
  51. static inline u32 udc_read(u32 reg)
  52. {
  53. return readb(base_addr + reg);
  54. }
  55. static inline void udc_write(u32 value, u32 reg)
  56. {
  57. writeb(value, base_addr + reg);
  58. }
  59. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  60. {
  61. writeb(value, base + reg);
  62. }
  63. static struct s3c2410_udc_mach_info *udc_info;
  64. /*************************** DEBUG FUNCTION ***************************/
  65. #define DEBUG_NORMAL 1
  66. #define DEBUG_VERBOSE 2
  67. #ifdef CONFIG_USB_S3C2410_DEBUG
  68. #define USB_S3C2410_DEBUG_LEVEL 0
  69. static uint32_t s3c2410_ticks = 0;
  70. __printf(2, 3)
  71. static void dprintk(int level, const char *fmt, ...)
  72. {
  73. static long prevticks;
  74. static int invocation;
  75. struct va_format vaf;
  76. va_list args;
  77. if (level > USB_S3C2410_DEBUG_LEVEL)
  78. return;
  79. va_start(args, fmt);
  80. vaf.fmt = fmt;
  81. vaf.va = &args;
  82. if (s3c2410_ticks != prevticks) {
  83. prevticks = s3c2410_ticks;
  84. invocation = 0;
  85. }
  86. pr_debug("%1lu.%02d USB: %pV", prevticks, invocation++, &vaf);
  87. va_end(args);
  88. }
  89. #else
  90. __printf(2, 3)
  91. static void dprintk(int level, const char *fmt, ...)
  92. {
  93. }
  94. #endif
  95. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  96. {
  97. u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
  98. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  99. u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
  100. u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
  101. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  102. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  103. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  104. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  105. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  106. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  107. udc_write(0, S3C2410_UDC_INDEX_REG);
  108. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  109. udc_write(1, S3C2410_UDC_INDEX_REG);
  110. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  111. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  112. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  113. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  114. udc_write(2, S3C2410_UDC_INDEX_REG);
  115. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  116. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  117. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  118. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  119. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  120. "PWR_REG : 0x%04X\n"
  121. "EP_INT_REG : 0x%04X\n"
  122. "USB_INT_REG : 0x%04X\n"
  123. "EP_INT_EN_REG : 0x%04X\n"
  124. "USB_INT_EN_REG : 0x%04X\n"
  125. "EP0_CSR : 0x%04X\n"
  126. "EP1_I_CSR1 : 0x%04X\n"
  127. "EP1_I_CSR2 : 0x%04X\n"
  128. "EP1_O_CSR1 : 0x%04X\n"
  129. "EP1_O_CSR2 : 0x%04X\n"
  130. "EP2_I_CSR1 : 0x%04X\n"
  131. "EP2_I_CSR2 : 0x%04X\n"
  132. "EP2_O_CSR1 : 0x%04X\n"
  133. "EP2_O_CSR2 : 0x%04X\n",
  134. addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
  135. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  136. ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
  137. ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
  138. );
  139. return 0;
  140. }
  141. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  142. struct file *file)
  143. {
  144. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  145. }
  146. static const struct file_operations s3c2410_udc_debugfs_fops = {
  147. .open = s3c2410_udc_debugfs_fops_open,
  148. .read = seq_read,
  149. .llseek = seq_lseek,
  150. .release = single_release,
  151. .owner = THIS_MODULE,
  152. };
  153. /* io macros */
  154. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  155. {
  156. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  157. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  158. S3C2410_UDC_EP0_CSR_REG);
  159. }
  160. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  161. {
  162. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  163. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  164. }
  165. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  166. {
  167. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  168. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  169. }
  170. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  171. {
  172. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  173. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  174. }
  175. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  176. {
  177. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  178. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  179. }
  180. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  181. {
  182. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  183. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  184. }
  185. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  186. {
  187. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  188. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  189. | S3C2410_UDC_EP0_CSR_DE),
  190. S3C2410_UDC_EP0_CSR_REG);
  191. }
  192. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  193. {
  194. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  195. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  196. | S3C2410_UDC_EP0_CSR_DE),
  197. S3C2410_UDC_EP0_CSR_REG);
  198. }
  199. /*------------------------- I/O ----------------------------------*/
  200. /*
  201. * s3c2410_udc_done
  202. */
  203. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  204. struct s3c2410_request *req, int status)
  205. {
  206. unsigned halted = ep->halted;
  207. list_del_init(&req->queue);
  208. if (likely(req->req.status == -EINPROGRESS))
  209. req->req.status = status;
  210. else
  211. status = req->req.status;
  212. ep->halted = 1;
  213. usb_gadget_giveback_request(&ep->ep, &req->req);
  214. ep->halted = halted;
  215. }
  216. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  217. struct s3c2410_ep *ep, int status)
  218. {
  219. /* Sanity check */
  220. if (&ep->queue == NULL)
  221. return;
  222. while (!list_empty(&ep->queue)) {
  223. struct s3c2410_request *req;
  224. req = list_entry(ep->queue.next, struct s3c2410_request,
  225. queue);
  226. s3c2410_udc_done(ep, req, status);
  227. }
  228. }
  229. static inline int s3c2410_udc_fifo_count_out(void)
  230. {
  231. int tmp;
  232. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  233. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  234. return tmp;
  235. }
  236. /*
  237. * s3c2410_udc_write_packet
  238. */
  239. static inline int s3c2410_udc_write_packet(int fifo,
  240. struct s3c2410_request *req,
  241. unsigned max)
  242. {
  243. unsigned len = min(req->req.length - req->req.actual, max);
  244. u8 *buf = req->req.buf + req->req.actual;
  245. prefetch(buf);
  246. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  247. req->req.actual, req->req.length, len, req->req.actual + len);
  248. req->req.actual += len;
  249. udelay(5);
  250. writesb(base_addr + fifo, buf, len);
  251. return len;
  252. }
  253. /*
  254. * s3c2410_udc_write_fifo
  255. *
  256. * return: 0 = still running, 1 = completed, negative = errno
  257. */
  258. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  259. struct s3c2410_request *req)
  260. {
  261. unsigned count;
  262. int is_last;
  263. u32 idx;
  264. int fifo_reg;
  265. u32 ep_csr;
  266. idx = ep->bEndpointAddress & 0x7F;
  267. switch (idx) {
  268. default:
  269. idx = 0;
  270. case 0:
  271. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  272. break;
  273. case 1:
  274. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  275. break;
  276. case 2:
  277. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  278. break;
  279. case 3:
  280. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  281. break;
  282. case 4:
  283. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  284. break;
  285. }
  286. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  287. /* last packet is often short (sometimes a zlp) */
  288. if (count != ep->ep.maxpacket)
  289. is_last = 1;
  290. else if (req->req.length != req->req.actual || req->req.zero)
  291. is_last = 0;
  292. else
  293. is_last = 2;
  294. /* Only ep0 debug messages are interesting */
  295. if (idx == 0)
  296. dprintk(DEBUG_NORMAL,
  297. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  298. idx, count, req->req.actual, req->req.length,
  299. is_last, req->req.zero);
  300. if (is_last) {
  301. /* The order is important. It prevents sending 2 packets
  302. * at the same time */
  303. if (idx == 0) {
  304. /* Reset signal => no need to say 'data sent' */
  305. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  306. & S3C2410_UDC_USBINT_RESET))
  307. s3c2410_udc_set_ep0_de_in(base_addr);
  308. ep->dev->ep0state = EP0_IDLE;
  309. } else {
  310. udc_write(idx, S3C2410_UDC_INDEX_REG);
  311. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  312. udc_write(idx, S3C2410_UDC_INDEX_REG);
  313. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  314. S3C2410_UDC_IN_CSR1_REG);
  315. }
  316. s3c2410_udc_done(ep, req, 0);
  317. is_last = 1;
  318. } else {
  319. if (idx == 0) {
  320. /* Reset signal => no need to say 'data sent' */
  321. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  322. & S3C2410_UDC_USBINT_RESET))
  323. s3c2410_udc_set_ep0_ipr(base_addr);
  324. } else {
  325. udc_write(idx, S3C2410_UDC_INDEX_REG);
  326. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  327. udc_write(idx, S3C2410_UDC_INDEX_REG);
  328. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  329. S3C2410_UDC_IN_CSR1_REG);
  330. }
  331. }
  332. return is_last;
  333. }
  334. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  335. struct s3c2410_request *req, unsigned avail)
  336. {
  337. unsigned len;
  338. len = min(req->req.length - req->req.actual, avail);
  339. req->req.actual += len;
  340. readsb(fifo + base_addr, buf, len);
  341. return len;
  342. }
  343. /*
  344. * return: 0 = still running, 1 = queue empty, negative = errno
  345. */
  346. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  347. struct s3c2410_request *req)
  348. {
  349. u8 *buf;
  350. u32 ep_csr;
  351. unsigned bufferspace;
  352. int is_last = 1;
  353. unsigned avail;
  354. int fifo_count = 0;
  355. u32 idx;
  356. int fifo_reg;
  357. idx = ep->bEndpointAddress & 0x7F;
  358. switch (idx) {
  359. default:
  360. idx = 0;
  361. case 0:
  362. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  363. break;
  364. case 1:
  365. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  366. break;
  367. case 2:
  368. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  369. break;
  370. case 3:
  371. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  372. break;
  373. case 4:
  374. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  375. break;
  376. }
  377. if (!req->req.length)
  378. return 1;
  379. buf = req->req.buf + req->req.actual;
  380. bufferspace = req->req.length - req->req.actual;
  381. if (!bufferspace) {
  382. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  383. return -1;
  384. }
  385. udc_write(idx, S3C2410_UDC_INDEX_REG);
  386. fifo_count = s3c2410_udc_fifo_count_out();
  387. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  388. if (fifo_count > ep->ep.maxpacket)
  389. avail = ep->ep.maxpacket;
  390. else
  391. avail = fifo_count;
  392. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  393. /* checking this with ep0 is not accurate as we already
  394. * read a control request
  395. **/
  396. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  397. is_last = 1;
  398. /* overflowed this request? flush extra data */
  399. if (fifo_count != avail)
  400. req->req.status = -EOVERFLOW;
  401. } else {
  402. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  403. }
  404. udc_write(idx, S3C2410_UDC_INDEX_REG);
  405. fifo_count = s3c2410_udc_fifo_count_out();
  406. /* Only ep0 debug messages are interesting */
  407. if (idx == 0)
  408. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  409. __func__, fifo_count, is_last);
  410. if (is_last) {
  411. if (idx == 0) {
  412. s3c2410_udc_set_ep0_de_out(base_addr);
  413. ep->dev->ep0state = EP0_IDLE;
  414. } else {
  415. udc_write(idx, S3C2410_UDC_INDEX_REG);
  416. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  417. udc_write(idx, S3C2410_UDC_INDEX_REG);
  418. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  419. S3C2410_UDC_OUT_CSR1_REG);
  420. }
  421. s3c2410_udc_done(ep, req, 0);
  422. } else {
  423. if (idx == 0) {
  424. s3c2410_udc_clear_ep0_opr(base_addr);
  425. } else {
  426. udc_write(idx, S3C2410_UDC_INDEX_REG);
  427. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  428. udc_write(idx, S3C2410_UDC_INDEX_REG);
  429. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  430. S3C2410_UDC_OUT_CSR1_REG);
  431. }
  432. }
  433. return is_last;
  434. }
  435. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  436. {
  437. unsigned char *outbuf = (unsigned char *)crq;
  438. int bytes_read = 0;
  439. udc_write(0, S3C2410_UDC_INDEX_REG);
  440. bytes_read = s3c2410_udc_fifo_count_out();
  441. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  442. if (bytes_read > sizeof(struct usb_ctrlrequest))
  443. bytes_read = sizeof(struct usb_ctrlrequest);
  444. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  445. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  446. bytes_read, crq->bRequest, crq->bRequestType,
  447. crq->wValue, crq->wIndex, crq->wLength);
  448. return bytes_read;
  449. }
  450. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  451. struct usb_ctrlrequest *crq)
  452. {
  453. u16 status = 0;
  454. u8 ep_num = crq->wIndex & 0x7F;
  455. u8 is_in = crq->wIndex & USB_DIR_IN;
  456. switch (crq->bRequestType & USB_RECIP_MASK) {
  457. case USB_RECIP_INTERFACE:
  458. break;
  459. case USB_RECIP_DEVICE:
  460. status = dev->devstatus;
  461. break;
  462. case USB_RECIP_ENDPOINT:
  463. if (ep_num > 4 || crq->wLength > 2)
  464. return 1;
  465. if (ep_num == 0) {
  466. udc_write(0, S3C2410_UDC_INDEX_REG);
  467. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  468. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  469. } else {
  470. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  471. if (is_in) {
  472. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  473. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  474. } else {
  475. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  476. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  477. }
  478. }
  479. status = status ? 1 : 0;
  480. break;
  481. default:
  482. return 1;
  483. }
  484. /* Seems to be needed to get it working. ouch :( */
  485. udelay(5);
  486. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  487. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  488. s3c2410_udc_set_ep0_de_in(base_addr);
  489. return 0;
  490. }
  491. /*------------------------- usb state machine -------------------------------*/
  492. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  493. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  494. struct s3c2410_ep *ep,
  495. struct usb_ctrlrequest *crq,
  496. u32 ep0csr)
  497. {
  498. int len, ret, tmp;
  499. /* start control request? */
  500. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  501. return;
  502. s3c2410_udc_nuke(dev, ep, -EPROTO);
  503. len = s3c2410_udc_read_fifo_crq(crq);
  504. if (len != sizeof(*crq)) {
  505. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  506. " wanted %d bytes got %d. Stalling out...\n",
  507. sizeof(*crq), len);
  508. s3c2410_udc_set_ep0_ss(base_addr);
  509. return;
  510. }
  511. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  512. crq->bRequest, crq->bRequestType, crq->wLength);
  513. /* cope with automagic for some standard requests. */
  514. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  515. == USB_TYPE_STANDARD;
  516. dev->req_config = 0;
  517. dev->req_pending = 1;
  518. switch (crq->bRequest) {
  519. case USB_REQ_SET_CONFIGURATION:
  520. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
  521. if (crq->bRequestType == USB_RECIP_DEVICE) {
  522. dev->req_config = 1;
  523. s3c2410_udc_set_ep0_de_out(base_addr);
  524. }
  525. break;
  526. case USB_REQ_SET_INTERFACE:
  527. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
  528. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  529. dev->req_config = 1;
  530. s3c2410_udc_set_ep0_de_out(base_addr);
  531. }
  532. break;
  533. case USB_REQ_SET_ADDRESS:
  534. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
  535. if (crq->bRequestType == USB_RECIP_DEVICE) {
  536. tmp = crq->wValue & 0x7F;
  537. dev->address = tmp;
  538. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  539. S3C2410_UDC_FUNC_ADDR_REG);
  540. s3c2410_udc_set_ep0_de_out(base_addr);
  541. return;
  542. }
  543. break;
  544. case USB_REQ_GET_STATUS:
  545. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
  546. s3c2410_udc_clear_ep0_opr(base_addr);
  547. if (dev->req_std) {
  548. if (!s3c2410_udc_get_status(dev, crq))
  549. return;
  550. }
  551. break;
  552. case USB_REQ_CLEAR_FEATURE:
  553. s3c2410_udc_clear_ep0_opr(base_addr);
  554. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  555. break;
  556. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  557. break;
  558. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  559. s3c2410_udc_set_ep0_de_out(base_addr);
  560. return;
  561. case USB_REQ_SET_FEATURE:
  562. s3c2410_udc_clear_ep0_opr(base_addr);
  563. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  564. break;
  565. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  566. break;
  567. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  568. s3c2410_udc_set_ep0_de_out(base_addr);
  569. return;
  570. default:
  571. s3c2410_udc_clear_ep0_opr(base_addr);
  572. break;
  573. }
  574. if (crq->bRequestType & USB_DIR_IN)
  575. dev->ep0state = EP0_IN_DATA_PHASE;
  576. else
  577. dev->ep0state = EP0_OUT_DATA_PHASE;
  578. if (!dev->driver)
  579. return;
  580. /* deliver the request to the gadget driver */
  581. ret = dev->driver->setup(&dev->gadget, crq);
  582. if (ret < 0) {
  583. if (dev->req_config) {
  584. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  585. crq->bRequest, ret);
  586. return;
  587. }
  588. if (ret == -EOPNOTSUPP)
  589. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  590. else
  591. dprintk(DEBUG_NORMAL,
  592. "dev->driver->setup failed. (%d)\n", ret);
  593. udelay(5);
  594. s3c2410_udc_set_ep0_ss(base_addr);
  595. s3c2410_udc_set_ep0_de_out(base_addr);
  596. dev->ep0state = EP0_IDLE;
  597. /* deferred i/o == no response yet */
  598. } else if (dev->req_pending) {
  599. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  600. dev->req_pending = 0;
  601. }
  602. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  603. }
  604. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  605. {
  606. u32 ep0csr;
  607. struct s3c2410_ep *ep = &dev->ep[0];
  608. struct s3c2410_request *req;
  609. struct usb_ctrlrequest crq;
  610. if (list_empty(&ep->queue))
  611. req = NULL;
  612. else
  613. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  614. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  615. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  616. udc_write(0, S3C2410_UDC_INDEX_REG);
  617. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  618. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  619. ep0csr, ep0states[dev->ep0state]);
  620. /* clear stall status */
  621. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  622. s3c2410_udc_nuke(dev, ep, -EPIPE);
  623. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  624. s3c2410_udc_clear_ep0_sst(base_addr);
  625. dev->ep0state = EP0_IDLE;
  626. return;
  627. }
  628. /* clear setup end */
  629. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  630. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  631. s3c2410_udc_nuke(dev, ep, 0);
  632. s3c2410_udc_clear_ep0_se(base_addr);
  633. dev->ep0state = EP0_IDLE;
  634. }
  635. switch (dev->ep0state) {
  636. case EP0_IDLE:
  637. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  638. break;
  639. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  640. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  641. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
  642. s3c2410_udc_write_fifo(ep, req);
  643. break;
  644. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  645. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  646. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
  647. s3c2410_udc_read_fifo(ep, req);
  648. break;
  649. case EP0_END_XFER:
  650. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  651. dev->ep0state = EP0_IDLE;
  652. break;
  653. case EP0_STALL:
  654. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  655. dev->ep0state = EP0_IDLE;
  656. break;
  657. }
  658. }
  659. /*
  660. * handle_ep - Manage I/O endpoints
  661. */
  662. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  663. {
  664. struct s3c2410_request *req;
  665. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  666. u32 ep_csr1;
  667. u32 idx;
  668. if (likely(!list_empty(&ep->queue)))
  669. req = list_entry(ep->queue.next,
  670. struct s3c2410_request, queue);
  671. else
  672. req = NULL;
  673. idx = ep->bEndpointAddress & 0x7F;
  674. if (is_in) {
  675. udc_write(idx, S3C2410_UDC_INDEX_REG);
  676. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  677. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  678. idx, ep_csr1, req ? 1 : 0);
  679. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  680. dprintk(DEBUG_VERBOSE, "st\n");
  681. udc_write(idx, S3C2410_UDC_INDEX_REG);
  682. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  683. S3C2410_UDC_IN_CSR1_REG);
  684. return;
  685. }
  686. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
  687. s3c2410_udc_write_fifo(ep, req);
  688. } else {
  689. udc_write(idx, S3C2410_UDC_INDEX_REG);
  690. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  691. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  692. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  693. udc_write(idx, S3C2410_UDC_INDEX_REG);
  694. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  695. S3C2410_UDC_OUT_CSR1_REG);
  696. return;
  697. }
  698. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
  699. s3c2410_udc_read_fifo(ep, req);
  700. }
  701. }
  702. #include <mach/regs-irq.h>
  703. /*
  704. * s3c2410_udc_irq - interrupt handler
  705. */
  706. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  707. {
  708. struct s3c2410_udc *dev = _dev;
  709. int usb_status;
  710. int usbd_status;
  711. int pwr_reg;
  712. int ep0csr;
  713. int i;
  714. u32 idx, idx2;
  715. unsigned long flags;
  716. spin_lock_irqsave(&dev->lock, flags);
  717. /* Driver connected ? */
  718. if (!dev->driver) {
  719. /* Clear interrupts */
  720. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  721. S3C2410_UDC_USB_INT_REG);
  722. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  723. S3C2410_UDC_EP_INT_REG);
  724. }
  725. /* Save index */
  726. idx = udc_read(S3C2410_UDC_INDEX_REG);
  727. /* Read status registers */
  728. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  729. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  730. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  731. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  732. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  733. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  734. usb_status, usbd_status, pwr_reg, ep0csr);
  735. /*
  736. * Now, handle interrupts. There's two types :
  737. * - Reset, Resume, Suspend coming -> usb_int_reg
  738. * - EP -> ep_int_reg
  739. */
  740. /* RESET */
  741. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  742. /* two kind of reset :
  743. * - reset start -> pwr reg = 8
  744. * - reset end -> pwr reg = 0
  745. **/
  746. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  747. ep0csr, pwr_reg);
  748. dev->gadget.speed = USB_SPEED_UNKNOWN;
  749. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  750. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  751. S3C2410_UDC_MAXP_REG);
  752. dev->address = 0;
  753. dev->ep0state = EP0_IDLE;
  754. dev->gadget.speed = USB_SPEED_FULL;
  755. /* clear interrupt */
  756. udc_write(S3C2410_UDC_USBINT_RESET,
  757. S3C2410_UDC_USB_INT_REG);
  758. udc_write(idx, S3C2410_UDC_INDEX_REG);
  759. spin_unlock_irqrestore(&dev->lock, flags);
  760. return IRQ_HANDLED;
  761. }
  762. /* RESUME */
  763. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  764. dprintk(DEBUG_NORMAL, "USB resume\n");
  765. /* clear interrupt */
  766. udc_write(S3C2410_UDC_USBINT_RESUME,
  767. S3C2410_UDC_USB_INT_REG);
  768. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  769. && dev->driver
  770. && dev->driver->resume)
  771. dev->driver->resume(&dev->gadget);
  772. }
  773. /* SUSPEND */
  774. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  775. dprintk(DEBUG_NORMAL, "USB suspend\n");
  776. /* clear interrupt */
  777. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  778. S3C2410_UDC_USB_INT_REG);
  779. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  780. && dev->driver
  781. && dev->driver->suspend)
  782. dev->driver->suspend(&dev->gadget);
  783. dev->ep0state = EP0_IDLE;
  784. }
  785. /* EP */
  786. /* control traffic */
  787. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  788. * generate an interrupt
  789. */
  790. if (usbd_status & S3C2410_UDC_INT_EP0) {
  791. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  792. /* Clear the interrupt bit by setting it to 1 */
  793. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  794. s3c2410_udc_handle_ep0(dev);
  795. }
  796. /* endpoint data transfers */
  797. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  798. u32 tmp = 1 << i;
  799. if (usbd_status & tmp) {
  800. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  801. /* Clear the interrupt bit by setting it to 1 */
  802. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  803. s3c2410_udc_handle_ep(&dev->ep[i]);
  804. }
  805. }
  806. /* what else causes this interrupt? a receive! who is it? */
  807. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  808. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  809. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  810. udc_write(i, S3C2410_UDC_INDEX_REG);
  811. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  812. s3c2410_udc_handle_ep(&dev->ep[i]);
  813. /* restore index */
  814. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  815. }
  816. }
  817. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  818. /* Restore old index */
  819. udc_write(idx, S3C2410_UDC_INDEX_REG);
  820. spin_unlock_irqrestore(&dev->lock, flags);
  821. return IRQ_HANDLED;
  822. }
  823. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  824. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  825. {
  826. return container_of(ep, struct s3c2410_ep, ep);
  827. }
  828. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  829. {
  830. return container_of(gadget, struct s3c2410_udc, gadget);
  831. }
  832. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  833. {
  834. return container_of(req, struct s3c2410_request, req);
  835. }
  836. /*
  837. * s3c2410_udc_ep_enable
  838. */
  839. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  840. const struct usb_endpoint_descriptor *desc)
  841. {
  842. struct s3c2410_udc *dev;
  843. struct s3c2410_ep *ep;
  844. u32 max, tmp;
  845. unsigned long flags;
  846. u32 csr1, csr2;
  847. u32 int_en_reg;
  848. ep = to_s3c2410_ep(_ep);
  849. if (!_ep || !desc
  850. || _ep->name == ep0name
  851. || desc->bDescriptorType != USB_DT_ENDPOINT)
  852. return -EINVAL;
  853. dev = ep->dev;
  854. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  855. return -ESHUTDOWN;
  856. max = usb_endpoint_maxp(desc);
  857. local_irq_save(flags);
  858. _ep->maxpacket = max;
  859. ep->ep.desc = desc;
  860. ep->halted = 0;
  861. ep->bEndpointAddress = desc->bEndpointAddress;
  862. /* set max packet */
  863. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  864. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  865. /* set type, direction, address; reset fifo counters */
  866. if (desc->bEndpointAddress & USB_DIR_IN) {
  867. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  868. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  869. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  870. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  871. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  872. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  873. } else {
  874. /* don't flush in fifo or it will cause endpoint interrupt */
  875. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  876. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  877. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  878. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  879. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  880. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  881. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  882. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  883. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  884. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  885. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  886. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  887. }
  888. /* enable irqs */
  889. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  890. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  891. /* print some debug message */
  892. tmp = desc->bEndpointAddress;
  893. dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  894. _ep->name, ep->num, tmp,
  895. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  896. local_irq_restore(flags);
  897. s3c2410_udc_set_halt(_ep, 0);
  898. return 0;
  899. }
  900. /*
  901. * s3c2410_udc_ep_disable
  902. */
  903. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  904. {
  905. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  906. unsigned long flags;
  907. u32 int_en_reg;
  908. if (!_ep || !ep->ep.desc) {
  909. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  910. _ep ? ep->ep.name : NULL);
  911. return -EINVAL;
  912. }
  913. local_irq_save(flags);
  914. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  915. ep->ep.desc = NULL;
  916. ep->halted = 1;
  917. s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
  918. /* disable irqs */
  919. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  920. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  921. local_irq_restore(flags);
  922. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  923. return 0;
  924. }
  925. /*
  926. * s3c2410_udc_alloc_request
  927. */
  928. static struct usb_request *
  929. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  930. {
  931. struct s3c2410_request *req;
  932. dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
  933. if (!_ep)
  934. return NULL;
  935. req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
  936. if (!req)
  937. return NULL;
  938. INIT_LIST_HEAD(&req->queue);
  939. return &req->req;
  940. }
  941. /*
  942. * s3c2410_udc_free_request
  943. */
  944. static void
  945. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  946. {
  947. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  948. struct s3c2410_request *req = to_s3c2410_req(_req);
  949. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  950. if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
  951. return;
  952. WARN_ON(!list_empty(&req->queue));
  953. kfree(req);
  954. }
  955. /*
  956. * s3c2410_udc_queue
  957. */
  958. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  959. gfp_t gfp_flags)
  960. {
  961. struct s3c2410_request *req = to_s3c2410_req(_req);
  962. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  963. struct s3c2410_udc *dev;
  964. u32 ep_csr = 0;
  965. int fifo_count = 0;
  966. unsigned long flags;
  967. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  968. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  969. return -EINVAL;
  970. }
  971. dev = ep->dev;
  972. if (unlikely(!dev->driver
  973. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  974. return -ESHUTDOWN;
  975. }
  976. local_irq_save(flags);
  977. if (unlikely(!_req || !_req->complete
  978. || !_req->buf || !list_empty(&req->queue))) {
  979. if (!_req)
  980. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  981. else {
  982. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  983. __func__, !_req->complete, !_req->buf,
  984. !list_empty(&req->queue));
  985. }
  986. local_irq_restore(flags);
  987. return -EINVAL;
  988. }
  989. _req->status = -EINPROGRESS;
  990. _req->actual = 0;
  991. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  992. __func__, ep->bEndpointAddress, _req->length);
  993. if (ep->bEndpointAddress) {
  994. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  995. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  996. ? S3C2410_UDC_IN_CSR1_REG
  997. : S3C2410_UDC_OUT_CSR1_REG);
  998. fifo_count = s3c2410_udc_fifo_count_out();
  999. } else {
  1000. udc_write(0, S3C2410_UDC_INDEX_REG);
  1001. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1002. fifo_count = s3c2410_udc_fifo_count_out();
  1003. }
  1004. /* kickstart this i/o queue? */
  1005. if (list_empty(&ep->queue) && !ep->halted) {
  1006. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1007. switch (dev->ep0state) {
  1008. case EP0_IN_DATA_PHASE:
  1009. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1010. && s3c2410_udc_write_fifo(ep,
  1011. req)) {
  1012. dev->ep0state = EP0_IDLE;
  1013. req = NULL;
  1014. }
  1015. break;
  1016. case EP0_OUT_DATA_PHASE:
  1017. if ((!_req->length)
  1018. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1019. && s3c2410_udc_read_fifo(ep,
  1020. req))) {
  1021. dev->ep0state = EP0_IDLE;
  1022. req = NULL;
  1023. }
  1024. break;
  1025. default:
  1026. local_irq_restore(flags);
  1027. return -EL2HLT;
  1028. }
  1029. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1030. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1031. && s3c2410_udc_write_fifo(ep, req)) {
  1032. req = NULL;
  1033. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1034. && fifo_count
  1035. && s3c2410_udc_read_fifo(ep, req)) {
  1036. req = NULL;
  1037. }
  1038. }
  1039. /* pio or dma irq handler advances the queue. */
  1040. if (likely(req))
  1041. list_add_tail(&req->queue, &ep->queue);
  1042. local_irq_restore(flags);
  1043. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1044. return 0;
  1045. }
  1046. /*
  1047. * s3c2410_udc_dequeue
  1048. */
  1049. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1050. {
  1051. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1052. struct s3c2410_udc *udc;
  1053. int retval = -EINVAL;
  1054. unsigned long flags;
  1055. struct s3c2410_request *req = NULL;
  1056. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1057. if (!the_controller->driver)
  1058. return -ESHUTDOWN;
  1059. if (!_ep || !_req)
  1060. return retval;
  1061. udc = to_s3c2410_udc(ep->gadget);
  1062. local_irq_save(flags);
  1063. list_for_each_entry(req, &ep->queue, queue) {
  1064. if (&req->req == _req) {
  1065. list_del_init(&req->queue);
  1066. _req->status = -ECONNRESET;
  1067. retval = 0;
  1068. break;
  1069. }
  1070. }
  1071. if (retval == 0) {
  1072. dprintk(DEBUG_VERBOSE,
  1073. "dequeued req %p from %s, len %d buf %p\n",
  1074. req, _ep->name, _req->length, _req->buf);
  1075. s3c2410_udc_done(ep, req, -ECONNRESET);
  1076. }
  1077. local_irq_restore(flags);
  1078. return retval;
  1079. }
  1080. /*
  1081. * s3c2410_udc_set_halt
  1082. */
  1083. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1084. {
  1085. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1086. u32 ep_csr = 0;
  1087. unsigned long flags;
  1088. u32 idx;
  1089. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  1090. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1091. return -EINVAL;
  1092. }
  1093. local_irq_save(flags);
  1094. idx = ep->bEndpointAddress & 0x7F;
  1095. if (idx == 0) {
  1096. s3c2410_udc_set_ep0_ss(base_addr);
  1097. s3c2410_udc_set_ep0_de_out(base_addr);
  1098. } else {
  1099. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1100. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1101. ? S3C2410_UDC_IN_CSR1_REG
  1102. : S3C2410_UDC_OUT_CSR1_REG);
  1103. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1104. if (value)
  1105. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1106. S3C2410_UDC_IN_CSR1_REG);
  1107. else {
  1108. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1109. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1110. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1111. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1112. }
  1113. } else {
  1114. if (value)
  1115. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1116. S3C2410_UDC_OUT_CSR1_REG);
  1117. else {
  1118. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1119. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1120. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1121. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1122. }
  1123. }
  1124. }
  1125. ep->halted = value ? 1 : 0;
  1126. local_irq_restore(flags);
  1127. return 0;
  1128. }
  1129. static const struct usb_ep_ops s3c2410_ep_ops = {
  1130. .enable = s3c2410_udc_ep_enable,
  1131. .disable = s3c2410_udc_ep_disable,
  1132. .alloc_request = s3c2410_udc_alloc_request,
  1133. .free_request = s3c2410_udc_free_request,
  1134. .queue = s3c2410_udc_queue,
  1135. .dequeue = s3c2410_udc_dequeue,
  1136. .set_halt = s3c2410_udc_set_halt,
  1137. };
  1138. /*------------------------- usb_gadget_ops ----------------------------------*/
  1139. /*
  1140. * s3c2410_udc_get_frame
  1141. */
  1142. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1143. {
  1144. int tmp;
  1145. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1146. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1147. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1148. return tmp;
  1149. }
  1150. /*
  1151. * s3c2410_udc_wakeup
  1152. */
  1153. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1154. {
  1155. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1156. return 0;
  1157. }
  1158. /*
  1159. * s3c2410_udc_set_selfpowered
  1160. */
  1161. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1162. {
  1163. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1164. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1165. gadget->is_selfpowered = (value != 0);
  1166. if (value)
  1167. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1168. else
  1169. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1170. return 0;
  1171. }
  1172. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1173. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1174. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1175. {
  1176. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1177. if (udc_info && (udc_info->udc_command ||
  1178. gpio_is_valid(udc_info->pullup_pin))) {
  1179. if (is_on)
  1180. s3c2410_udc_enable(udc);
  1181. else {
  1182. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1183. if (udc->driver && udc->driver->disconnect)
  1184. udc->driver->disconnect(&udc->gadget);
  1185. }
  1186. s3c2410_udc_disable(udc);
  1187. }
  1188. } else {
  1189. return -EOPNOTSUPP;
  1190. }
  1191. return 0;
  1192. }
  1193. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1194. {
  1195. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1196. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1197. udc->vbus = (is_active != 0);
  1198. s3c2410_udc_set_pullup(udc, is_active);
  1199. return 0;
  1200. }
  1201. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1202. {
  1203. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1204. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1205. s3c2410_udc_set_pullup(udc, is_on);
  1206. return 0;
  1207. }
  1208. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1209. {
  1210. struct s3c2410_udc *dev = _dev;
  1211. unsigned int value;
  1212. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1213. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1214. if (udc_info->vbus_pin_inverted)
  1215. value = !value;
  1216. if (value != dev->vbus)
  1217. s3c2410_udc_vbus_session(&dev->gadget, value);
  1218. return IRQ_HANDLED;
  1219. }
  1220. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1221. {
  1222. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1223. if (udc_info && udc_info->vbus_draw) {
  1224. udc_info->vbus_draw(ma);
  1225. return 0;
  1226. }
  1227. return -ENOTSUPP;
  1228. }
  1229. static int s3c2410_udc_start(struct usb_gadget *g,
  1230. struct usb_gadget_driver *driver);
  1231. static int s3c2410_udc_stop(struct usb_gadget *g);
  1232. static const struct usb_gadget_ops s3c2410_ops = {
  1233. .get_frame = s3c2410_udc_get_frame,
  1234. .wakeup = s3c2410_udc_wakeup,
  1235. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1236. .pullup = s3c2410_udc_pullup,
  1237. .vbus_session = s3c2410_udc_vbus_session,
  1238. .vbus_draw = s3c2410_vbus_draw,
  1239. .udc_start = s3c2410_udc_start,
  1240. .udc_stop = s3c2410_udc_stop,
  1241. };
  1242. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1243. {
  1244. if (!udc_info)
  1245. return;
  1246. if (udc_info->udc_command) {
  1247. udc_info->udc_command(cmd);
  1248. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1249. int value;
  1250. switch (cmd) {
  1251. case S3C2410_UDC_P_ENABLE:
  1252. value = 1;
  1253. break;
  1254. case S3C2410_UDC_P_DISABLE:
  1255. value = 0;
  1256. break;
  1257. default:
  1258. return;
  1259. }
  1260. value ^= udc_info->pullup_pin_inverted;
  1261. gpio_set_value(udc_info->pullup_pin, value);
  1262. }
  1263. }
  1264. /*------------------------- gadget driver handling---------------------------*/
  1265. /*
  1266. * s3c2410_udc_disable
  1267. */
  1268. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1269. {
  1270. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1271. /* Disable all interrupts */
  1272. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1273. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1274. /* Clear the interrupt registers */
  1275. udc_write(S3C2410_UDC_USBINT_RESET
  1276. | S3C2410_UDC_USBINT_RESUME
  1277. | S3C2410_UDC_USBINT_SUSPEND,
  1278. S3C2410_UDC_USB_INT_REG);
  1279. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1280. /* Good bye, cruel world */
  1281. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1282. /* Set speed to unknown */
  1283. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1284. }
  1285. /*
  1286. * s3c2410_udc_reinit
  1287. */
  1288. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1289. {
  1290. u32 i;
  1291. /* device/ep0 records init */
  1292. INIT_LIST_HEAD(&dev->gadget.ep_list);
  1293. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  1294. dev->ep0state = EP0_IDLE;
  1295. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1296. struct s3c2410_ep *ep = &dev->ep[i];
  1297. if (i != 0)
  1298. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1299. ep->dev = dev;
  1300. ep->ep.desc = NULL;
  1301. ep->halted = 0;
  1302. INIT_LIST_HEAD(&ep->queue);
  1303. usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
  1304. }
  1305. }
  1306. /*
  1307. * s3c2410_udc_enable
  1308. */
  1309. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1310. {
  1311. int i;
  1312. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1313. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1314. dev->gadget.speed = USB_SPEED_FULL;
  1315. /* Set MAXP for all endpoints */
  1316. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1317. udc_write(i, S3C2410_UDC_INDEX_REG);
  1318. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1319. S3C2410_UDC_MAXP_REG);
  1320. }
  1321. /* Set default power state */
  1322. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1323. /* Enable reset and suspend interrupt interrupts */
  1324. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1325. S3C2410_UDC_USB_INT_EN_REG);
  1326. /* Enable ep0 interrupt */
  1327. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1328. /* time to say "hello, world" */
  1329. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1330. }
  1331. static int s3c2410_udc_start(struct usb_gadget *g,
  1332. struct usb_gadget_driver *driver)
  1333. {
  1334. struct s3c2410_udc *udc = to_s3c2410(g);
  1335. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1336. /* Hook the driver */
  1337. udc->driver = driver;
  1338. /* Enable udc */
  1339. s3c2410_udc_enable(udc);
  1340. return 0;
  1341. }
  1342. static int s3c2410_udc_stop(struct usb_gadget *g)
  1343. {
  1344. struct s3c2410_udc *udc = to_s3c2410(g);
  1345. udc->driver = NULL;
  1346. /* Disable udc */
  1347. s3c2410_udc_disable(udc);
  1348. return 0;
  1349. }
  1350. /*---------------------------------------------------------------------------*/
  1351. static struct s3c2410_udc memory = {
  1352. .gadget = {
  1353. .ops = &s3c2410_ops,
  1354. .ep0 = &memory.ep[0].ep,
  1355. .name = gadget_name,
  1356. .dev = {
  1357. .init_name = "gadget",
  1358. },
  1359. },
  1360. /* control endpoint */
  1361. .ep[0] = {
  1362. .num = 0,
  1363. .ep = {
  1364. .name = ep0name,
  1365. .ops = &s3c2410_ep_ops,
  1366. .maxpacket = EP0_FIFO_SIZE,
  1367. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
  1368. USB_EP_CAPS_DIR_ALL),
  1369. },
  1370. .dev = &memory,
  1371. },
  1372. /* first group of endpoints */
  1373. .ep[1] = {
  1374. .num = 1,
  1375. .ep = {
  1376. .name = "ep1-bulk",
  1377. .ops = &s3c2410_ep_ops,
  1378. .maxpacket = EP_FIFO_SIZE,
  1379. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1380. USB_EP_CAPS_DIR_ALL),
  1381. },
  1382. .dev = &memory,
  1383. .fifo_size = EP_FIFO_SIZE,
  1384. .bEndpointAddress = 1,
  1385. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1386. },
  1387. .ep[2] = {
  1388. .num = 2,
  1389. .ep = {
  1390. .name = "ep2-bulk",
  1391. .ops = &s3c2410_ep_ops,
  1392. .maxpacket = EP_FIFO_SIZE,
  1393. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1394. USB_EP_CAPS_DIR_ALL),
  1395. },
  1396. .dev = &memory,
  1397. .fifo_size = EP_FIFO_SIZE,
  1398. .bEndpointAddress = 2,
  1399. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1400. },
  1401. .ep[3] = {
  1402. .num = 3,
  1403. .ep = {
  1404. .name = "ep3-bulk",
  1405. .ops = &s3c2410_ep_ops,
  1406. .maxpacket = EP_FIFO_SIZE,
  1407. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1408. USB_EP_CAPS_DIR_ALL),
  1409. },
  1410. .dev = &memory,
  1411. .fifo_size = EP_FIFO_SIZE,
  1412. .bEndpointAddress = 3,
  1413. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1414. },
  1415. .ep[4] = {
  1416. .num = 4,
  1417. .ep = {
  1418. .name = "ep4-bulk",
  1419. .ops = &s3c2410_ep_ops,
  1420. .maxpacket = EP_FIFO_SIZE,
  1421. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1422. USB_EP_CAPS_DIR_ALL),
  1423. },
  1424. .dev = &memory,
  1425. .fifo_size = EP_FIFO_SIZE,
  1426. .bEndpointAddress = 4,
  1427. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1428. }
  1429. };
  1430. /*
  1431. * probe - binds to the platform device
  1432. */
  1433. static int s3c2410_udc_probe(struct platform_device *pdev)
  1434. {
  1435. struct s3c2410_udc *udc = &memory;
  1436. struct device *dev = &pdev->dev;
  1437. int retval;
  1438. int irq;
  1439. dev_dbg(dev, "%s()\n", __func__);
  1440. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1441. if (IS_ERR(usb_bus_clock)) {
  1442. dev_err(dev, "failed to get usb bus clock source\n");
  1443. return PTR_ERR(usb_bus_clock);
  1444. }
  1445. clk_prepare_enable(usb_bus_clock);
  1446. udc_clock = clk_get(NULL, "usb-device");
  1447. if (IS_ERR(udc_clock)) {
  1448. dev_err(dev, "failed to get udc clock source\n");
  1449. return PTR_ERR(udc_clock);
  1450. }
  1451. clk_prepare_enable(udc_clock);
  1452. mdelay(10);
  1453. dev_dbg(dev, "got and enabled clocks\n");
  1454. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1455. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1456. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1457. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1458. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1459. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1460. }
  1461. spin_lock_init(&udc->lock);
  1462. udc_info = dev_get_platdata(&pdev->dev);
  1463. rsrc_start = S3C2410_PA_USBDEV;
  1464. rsrc_len = S3C24XX_SZ_USBDEV;
  1465. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1466. return -EBUSY;
  1467. base_addr = ioremap(rsrc_start, rsrc_len);
  1468. if (!base_addr) {
  1469. retval = -ENOMEM;
  1470. goto err_mem;
  1471. }
  1472. the_controller = udc;
  1473. platform_set_drvdata(pdev, udc);
  1474. s3c2410_udc_disable(udc);
  1475. s3c2410_udc_reinit(udc);
  1476. /* irq setup after old hardware state is cleaned up */
  1477. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1478. 0, gadget_name, udc);
  1479. if (retval != 0) {
  1480. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1481. retval = -EBUSY;
  1482. goto err_map;
  1483. }
  1484. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1485. if (udc_info && udc_info->vbus_pin > 0) {
  1486. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1487. if (retval < 0) {
  1488. dev_err(dev, "cannot claim vbus pin\n");
  1489. goto err_int;
  1490. }
  1491. irq = gpio_to_irq(udc_info->vbus_pin);
  1492. if (irq < 0) {
  1493. dev_err(dev, "no irq for gpio vbus pin\n");
  1494. retval = irq;
  1495. goto err_gpio_claim;
  1496. }
  1497. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1498. IRQF_TRIGGER_RISING
  1499. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1500. gadget_name, udc);
  1501. if (retval != 0) {
  1502. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1503. irq, retval);
  1504. retval = -EBUSY;
  1505. goto err_gpio_claim;
  1506. }
  1507. dev_dbg(dev, "got irq %i\n", irq);
  1508. } else {
  1509. udc->vbus = 1;
  1510. }
  1511. if (udc_info && !udc_info->udc_command &&
  1512. gpio_is_valid(udc_info->pullup_pin)) {
  1513. retval = gpio_request_one(udc_info->pullup_pin,
  1514. udc_info->vbus_pin_inverted ?
  1515. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1516. "udc pullup");
  1517. if (retval)
  1518. goto err_vbus_irq;
  1519. }
  1520. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1521. if (retval)
  1522. goto err_add_udc;
  1523. if (s3c2410_udc_debugfs_root) {
  1524. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1525. s3c2410_udc_debugfs_root,
  1526. udc, &s3c2410_udc_debugfs_fops);
  1527. if (!udc->regs_info)
  1528. dev_warn(dev, "debugfs file creation failed\n");
  1529. }
  1530. dev_dbg(dev, "probe ok\n");
  1531. return 0;
  1532. err_add_udc:
  1533. if (udc_info && !udc_info->udc_command &&
  1534. gpio_is_valid(udc_info->pullup_pin))
  1535. gpio_free(udc_info->pullup_pin);
  1536. err_vbus_irq:
  1537. if (udc_info && udc_info->vbus_pin > 0)
  1538. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1539. err_gpio_claim:
  1540. if (udc_info && udc_info->vbus_pin > 0)
  1541. gpio_free(udc_info->vbus_pin);
  1542. err_int:
  1543. free_irq(IRQ_USBD, udc);
  1544. err_map:
  1545. iounmap(base_addr);
  1546. err_mem:
  1547. release_mem_region(rsrc_start, rsrc_len);
  1548. return retval;
  1549. }
  1550. /*
  1551. * s3c2410_udc_remove
  1552. */
  1553. static int s3c2410_udc_remove(struct platform_device *pdev)
  1554. {
  1555. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1556. unsigned int irq;
  1557. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1558. if (udc->driver)
  1559. return -EBUSY;
  1560. usb_del_gadget_udc(&udc->gadget);
  1561. debugfs_remove(udc->regs_info);
  1562. if (udc_info && !udc_info->udc_command &&
  1563. gpio_is_valid(udc_info->pullup_pin))
  1564. gpio_free(udc_info->pullup_pin);
  1565. if (udc_info && udc_info->vbus_pin > 0) {
  1566. irq = gpio_to_irq(udc_info->vbus_pin);
  1567. free_irq(irq, udc);
  1568. }
  1569. free_irq(IRQ_USBD, udc);
  1570. iounmap(base_addr);
  1571. release_mem_region(rsrc_start, rsrc_len);
  1572. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1573. clk_disable_unprepare(udc_clock);
  1574. clk_put(udc_clock);
  1575. udc_clock = NULL;
  1576. }
  1577. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1578. clk_disable_unprepare(usb_bus_clock);
  1579. clk_put(usb_bus_clock);
  1580. usb_bus_clock = NULL;
  1581. }
  1582. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1583. return 0;
  1584. }
  1585. #ifdef CONFIG_PM
  1586. static int
  1587. s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1588. {
  1589. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1590. return 0;
  1591. }
  1592. static int s3c2410_udc_resume(struct platform_device *pdev)
  1593. {
  1594. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1595. return 0;
  1596. }
  1597. #else
  1598. #define s3c2410_udc_suspend NULL
  1599. #define s3c2410_udc_resume NULL
  1600. #endif
  1601. static const struct platform_device_id s3c_udc_ids[] = {
  1602. { "s3c2410-usbgadget", },
  1603. { "s3c2440-usbgadget", },
  1604. { }
  1605. };
  1606. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1607. static struct platform_driver udc_driver_24x0 = {
  1608. .driver = {
  1609. .name = "s3c24x0-usbgadget",
  1610. },
  1611. .probe = s3c2410_udc_probe,
  1612. .remove = s3c2410_udc_remove,
  1613. .suspend = s3c2410_udc_suspend,
  1614. .resume = s3c2410_udc_resume,
  1615. .id_table = s3c_udc_ids,
  1616. };
  1617. static int __init udc_init(void)
  1618. {
  1619. int retval;
  1620. dprintk(DEBUG_NORMAL, "%s\n", gadget_name);
  1621. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1622. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1623. pr_err("%s: debugfs dir creation failed %ld\n",
  1624. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1625. s3c2410_udc_debugfs_root = NULL;
  1626. }
  1627. retval = platform_driver_register(&udc_driver_24x0);
  1628. if (retval)
  1629. goto err;
  1630. return 0;
  1631. err:
  1632. debugfs_remove(s3c2410_udc_debugfs_root);
  1633. return retval;
  1634. }
  1635. static void __exit udc_exit(void)
  1636. {
  1637. platform_driver_unregister(&udc_driver_24x0);
  1638. debugfs_remove(s3c2410_udc_debugfs_root);
  1639. }
  1640. module_init(udc_init);
  1641. module_exit(udc_exit);
  1642. MODULE_AUTHOR(DRIVER_AUTHOR);
  1643. MODULE_DESCRIPTION(DRIVER_DESC);
  1644. MODULE_LICENSE("GPL");