fsl_mxc_udc.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. *
  6. * Description:
  7. * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
  8. * driver to function correctly on these systems.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/err.h>
  13. #include <linux/fsl_devices.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/io.h>
  16. #include "fsl_usb2_udc.h"
  17. static struct clk *mxc_ahb_clk;
  18. static struct clk *mxc_per_clk;
  19. static struct clk *mxc_ipg_clk;
  20. /* workaround ENGcm09152 for i.MX35 */
  21. #define MX35_USBPHYCTRL_OFFSET 0x600
  22. #define USBPHYCTRL_OTGBASE_OFFSET 0x8
  23. #define USBPHYCTRL_EVDO (1 << 23)
  24. int fsl_udc_clk_init(struct platform_device *pdev)
  25. {
  26. struct fsl_usb2_platform_data *pdata;
  27. unsigned long freq;
  28. int ret;
  29. pdata = dev_get_platdata(&pdev->dev);
  30. mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  31. if (IS_ERR(mxc_ipg_clk)) {
  32. dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
  33. return PTR_ERR(mxc_ipg_clk);
  34. }
  35. mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
  36. if (IS_ERR(mxc_ahb_clk)) {
  37. dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
  38. return PTR_ERR(mxc_ahb_clk);
  39. }
  40. mxc_per_clk = devm_clk_get(&pdev->dev, "per");
  41. if (IS_ERR(mxc_per_clk)) {
  42. dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
  43. return PTR_ERR(mxc_per_clk);
  44. }
  45. clk_prepare_enable(mxc_ipg_clk);
  46. clk_prepare_enable(mxc_ahb_clk);
  47. clk_prepare_enable(mxc_per_clk);
  48. /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
  49. if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
  50. freq = clk_get_rate(mxc_per_clk);
  51. if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
  52. (freq < 59999000 || freq > 60001000)) {
  53. dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
  54. ret = -EINVAL;
  55. goto eclkrate;
  56. }
  57. }
  58. return 0;
  59. eclkrate:
  60. clk_disable_unprepare(mxc_ipg_clk);
  61. clk_disable_unprepare(mxc_ahb_clk);
  62. clk_disable_unprepare(mxc_per_clk);
  63. mxc_per_clk = NULL;
  64. return ret;
  65. }
  66. int fsl_udc_clk_finalize(struct platform_device *pdev)
  67. {
  68. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  69. int ret = 0;
  70. /* workaround ENGcm09152 for i.MX35 */
  71. if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
  72. unsigned int v;
  73. struct resource *res = platform_get_resource
  74. (pdev, IORESOURCE_MEM, 0);
  75. void __iomem *phy_regs = ioremap(res->start +
  76. MX35_USBPHYCTRL_OFFSET, 512);
  77. if (!phy_regs) {
  78. dev_err(&pdev->dev, "ioremap for phy address fails\n");
  79. ret = -EINVAL;
  80. goto ioremap_err;
  81. }
  82. v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
  83. writel(v | USBPHYCTRL_EVDO,
  84. phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
  85. iounmap(phy_regs);
  86. }
  87. ioremap_err:
  88. /* ULPI transceivers don't need usbpll */
  89. if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
  90. clk_disable_unprepare(mxc_per_clk);
  91. mxc_per_clk = NULL;
  92. }
  93. return ret;
  94. }
  95. void fsl_udc_clk_release(void)
  96. {
  97. if (mxc_per_clk)
  98. clk_disable_unprepare(mxc_per_clk);
  99. clk_disable_unprepare(mxc_ahb_clk);
  100. clk_disable_unprepare(mxc_ipg_clk);
  101. }