smsc75xx.c 56 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/mii.h>
  26. #include <linux/usb.h>
  27. #include <linux/bitrev.h>
  28. #include <linux/crc16.h>
  29. #include <linux/crc32.h>
  30. #include <linux/usb/usbnet.h>
  31. #include <linux/slab.h>
  32. #include "smsc75xx.h"
  33. #define SMSC_CHIPNAME "smsc75xx"
  34. #define SMSC_DRIVER_VERSION "1.0.0"
  35. #define HS_USB_PKT_SIZE (512)
  36. #define FS_USB_PKT_SIZE (64)
  37. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  38. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  39. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  40. #define MAX_SINGLE_PACKET_SIZE (9000)
  41. #define LAN75XX_EEPROM_MAGIC (0x7500)
  42. #define EEPROM_MAC_OFFSET (0x01)
  43. #define DEFAULT_TX_CSUM_ENABLE (true)
  44. #define DEFAULT_RX_CSUM_ENABLE (true)
  45. #define SMSC75XX_INTERNAL_PHY_ID (1)
  46. #define SMSC75XX_TX_OVERHEAD (8)
  47. #define MAX_RX_FIFO_SIZE (20 * 1024)
  48. #define MAX_TX_FIFO_SIZE (12 * 1024)
  49. #define USB_VENDOR_ID_SMSC (0x0424)
  50. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  51. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  52. #define RXW_PADDING 2
  53. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  54. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  55. #define SUSPEND_SUSPEND0 (0x01)
  56. #define SUSPEND_SUSPEND1 (0x02)
  57. #define SUSPEND_SUSPEND2 (0x04)
  58. #define SUSPEND_SUSPEND3 (0x08)
  59. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  60. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  61. struct smsc75xx_priv {
  62. struct usbnet *dev;
  63. u32 rfe_ctl;
  64. u32 wolopts;
  65. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  66. struct mutex dataport_mutex;
  67. spinlock_t rfe_ctl_lock;
  68. struct work_struct set_multicast;
  69. u8 suspend_flags;
  70. };
  71. struct usb_context {
  72. struct usb_ctrlrequest req;
  73. struct usbnet *dev;
  74. };
  75. static bool turbo_mode = true;
  76. module_param(turbo_mode, bool, 0644);
  77. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  78. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  79. u32 *data, int in_pm)
  80. {
  81. u32 buf;
  82. int ret;
  83. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  84. BUG_ON(!dev);
  85. if (!in_pm)
  86. fn = usbnet_read_cmd;
  87. else
  88. fn = usbnet_read_cmd_nopm;
  89. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  90. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  91. 0, index, &buf, 4);
  92. if (unlikely(ret < 0))
  93. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  94. index, ret);
  95. le32_to_cpus(&buf);
  96. *data = buf;
  97. return ret;
  98. }
  99. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  100. u32 data, int in_pm)
  101. {
  102. u32 buf;
  103. int ret;
  104. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  105. BUG_ON(!dev);
  106. if (!in_pm)
  107. fn = usbnet_write_cmd;
  108. else
  109. fn = usbnet_write_cmd_nopm;
  110. buf = data;
  111. cpu_to_le32s(&buf);
  112. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  113. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  114. 0, index, &buf, 4);
  115. if (unlikely(ret < 0))
  116. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  117. index, ret);
  118. return ret;
  119. }
  120. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  121. u32 *data)
  122. {
  123. return __smsc75xx_read_reg(dev, index, data, 1);
  124. }
  125. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  126. u32 data)
  127. {
  128. return __smsc75xx_write_reg(dev, index, data, 1);
  129. }
  130. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  131. u32 *data)
  132. {
  133. return __smsc75xx_read_reg(dev, index, data, 0);
  134. }
  135. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  136. u32 data)
  137. {
  138. return __smsc75xx_write_reg(dev, index, data, 0);
  139. }
  140. /* Loop until the read is completed with timeout
  141. * called with phy_mutex held */
  142. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  143. int in_pm)
  144. {
  145. unsigned long start_time = jiffies;
  146. u32 val;
  147. int ret;
  148. do {
  149. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  150. if (ret < 0) {
  151. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  152. return ret;
  153. }
  154. if (!(val & MII_ACCESS_BUSY))
  155. return 0;
  156. } while (!time_after(jiffies, start_time + HZ));
  157. return -EIO;
  158. }
  159. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  160. int in_pm)
  161. {
  162. struct usbnet *dev = netdev_priv(netdev);
  163. u32 val, addr;
  164. int ret;
  165. mutex_lock(&dev->phy_mutex);
  166. /* confirm MII not busy */
  167. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  168. if (ret < 0) {
  169. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  170. goto done;
  171. }
  172. /* set the address, index & direction (read from PHY) */
  173. phy_id &= dev->mii.phy_id_mask;
  174. idx &= dev->mii.reg_num_mask;
  175. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  176. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  177. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  178. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  179. if (ret < 0) {
  180. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  181. goto done;
  182. }
  183. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  184. if (ret < 0) {
  185. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  186. goto done;
  187. }
  188. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  189. if (ret < 0) {
  190. netdev_warn(dev->net, "Error reading MII_DATA\n");
  191. goto done;
  192. }
  193. ret = (u16)(val & 0xFFFF);
  194. done:
  195. mutex_unlock(&dev->phy_mutex);
  196. return ret;
  197. }
  198. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  199. int idx, int regval, int in_pm)
  200. {
  201. struct usbnet *dev = netdev_priv(netdev);
  202. u32 val, addr;
  203. int ret;
  204. mutex_lock(&dev->phy_mutex);
  205. /* confirm MII not busy */
  206. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  207. if (ret < 0) {
  208. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  209. goto done;
  210. }
  211. val = regval;
  212. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  213. if (ret < 0) {
  214. netdev_warn(dev->net, "Error writing MII_DATA\n");
  215. goto done;
  216. }
  217. /* set the address, index & direction (write to PHY) */
  218. phy_id &= dev->mii.phy_id_mask;
  219. idx &= dev->mii.reg_num_mask;
  220. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  221. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  222. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  223. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  224. if (ret < 0) {
  225. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  226. goto done;
  227. }
  228. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  229. if (ret < 0) {
  230. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  231. goto done;
  232. }
  233. done:
  234. mutex_unlock(&dev->phy_mutex);
  235. }
  236. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  237. int idx)
  238. {
  239. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  240. }
  241. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  242. int idx, int regval)
  243. {
  244. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  245. }
  246. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  247. {
  248. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  249. }
  250. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  251. int regval)
  252. {
  253. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  254. }
  255. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  256. {
  257. unsigned long start_time = jiffies;
  258. u32 val;
  259. int ret;
  260. do {
  261. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  262. if (ret < 0) {
  263. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  264. return ret;
  265. }
  266. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  267. break;
  268. udelay(40);
  269. } while (!time_after(jiffies, start_time + HZ));
  270. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  271. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  272. return -EIO;
  273. }
  274. return 0;
  275. }
  276. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  277. {
  278. unsigned long start_time = jiffies;
  279. u32 val;
  280. int ret;
  281. do {
  282. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  283. if (ret < 0) {
  284. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  285. return ret;
  286. }
  287. if (!(val & E2P_CMD_BUSY))
  288. return 0;
  289. udelay(40);
  290. } while (!time_after(jiffies, start_time + HZ));
  291. netdev_warn(dev->net, "EEPROM is busy\n");
  292. return -EIO;
  293. }
  294. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  295. u8 *data)
  296. {
  297. u32 val;
  298. int i, ret;
  299. BUG_ON(!dev);
  300. BUG_ON(!data);
  301. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  302. if (ret)
  303. return ret;
  304. for (i = 0; i < length; i++) {
  305. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  306. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  307. if (ret < 0) {
  308. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  309. return ret;
  310. }
  311. ret = smsc75xx_wait_eeprom(dev);
  312. if (ret < 0)
  313. return ret;
  314. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  315. if (ret < 0) {
  316. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  317. return ret;
  318. }
  319. data[i] = val & 0xFF;
  320. offset++;
  321. }
  322. return 0;
  323. }
  324. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  325. u8 *data)
  326. {
  327. u32 val;
  328. int i, ret;
  329. BUG_ON(!dev);
  330. BUG_ON(!data);
  331. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  332. if (ret)
  333. return ret;
  334. /* Issue write/erase enable command */
  335. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  336. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  337. if (ret < 0) {
  338. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  339. return ret;
  340. }
  341. ret = smsc75xx_wait_eeprom(dev);
  342. if (ret < 0)
  343. return ret;
  344. for (i = 0; i < length; i++) {
  345. /* Fill data register */
  346. val = data[i];
  347. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  348. if (ret < 0) {
  349. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  350. return ret;
  351. }
  352. /* Send "write" command */
  353. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  354. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  355. if (ret < 0) {
  356. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  357. return ret;
  358. }
  359. ret = smsc75xx_wait_eeprom(dev);
  360. if (ret < 0)
  361. return ret;
  362. offset++;
  363. }
  364. return 0;
  365. }
  366. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  367. {
  368. int i, ret;
  369. for (i = 0; i < 100; i++) {
  370. u32 dp_sel;
  371. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  372. if (ret < 0) {
  373. netdev_warn(dev->net, "Error reading DP_SEL\n");
  374. return ret;
  375. }
  376. if (dp_sel & DP_SEL_DPRDY)
  377. return 0;
  378. udelay(40);
  379. }
  380. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  381. return -EIO;
  382. }
  383. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  384. u32 length, u32 *buf)
  385. {
  386. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  387. u32 dp_sel;
  388. int i, ret;
  389. mutex_lock(&pdata->dataport_mutex);
  390. ret = smsc75xx_dataport_wait_not_busy(dev);
  391. if (ret < 0) {
  392. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  393. goto done;
  394. }
  395. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  396. if (ret < 0) {
  397. netdev_warn(dev->net, "Error reading DP_SEL\n");
  398. goto done;
  399. }
  400. dp_sel &= ~DP_SEL_RSEL;
  401. dp_sel |= ram_select;
  402. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  403. if (ret < 0) {
  404. netdev_warn(dev->net, "Error writing DP_SEL\n");
  405. goto done;
  406. }
  407. for (i = 0; i < length; i++) {
  408. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  409. if (ret < 0) {
  410. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  411. goto done;
  412. }
  413. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  414. if (ret < 0) {
  415. netdev_warn(dev->net, "Error writing DP_DATA\n");
  416. goto done;
  417. }
  418. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  419. if (ret < 0) {
  420. netdev_warn(dev->net, "Error writing DP_CMD\n");
  421. goto done;
  422. }
  423. ret = smsc75xx_dataport_wait_not_busy(dev);
  424. if (ret < 0) {
  425. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  426. goto done;
  427. }
  428. }
  429. done:
  430. mutex_unlock(&pdata->dataport_mutex);
  431. return ret;
  432. }
  433. /* returns hash bit number for given MAC address */
  434. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  435. {
  436. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  437. }
  438. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  439. {
  440. struct smsc75xx_priv *pdata =
  441. container_of(param, struct smsc75xx_priv, set_multicast);
  442. struct usbnet *dev = pdata->dev;
  443. int ret;
  444. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  445. pdata->rfe_ctl);
  446. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  447. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  448. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  449. if (ret < 0)
  450. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  451. }
  452. static void smsc75xx_set_multicast(struct net_device *netdev)
  453. {
  454. struct usbnet *dev = netdev_priv(netdev);
  455. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  456. unsigned long flags;
  457. int i;
  458. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  459. pdata->rfe_ctl &=
  460. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  461. pdata->rfe_ctl |= RFE_CTL_AB;
  462. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  463. pdata->multicast_hash_table[i] = 0;
  464. if (dev->net->flags & IFF_PROMISC) {
  465. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  466. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  467. } else if (dev->net->flags & IFF_ALLMULTI) {
  468. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  469. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  470. } else if (!netdev_mc_empty(dev->net)) {
  471. struct netdev_hw_addr *ha;
  472. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  473. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  474. netdev_for_each_mc_addr(ha, netdev) {
  475. u32 bitnum = smsc75xx_hash(ha->addr);
  476. pdata->multicast_hash_table[bitnum / 32] |=
  477. (1 << (bitnum % 32));
  478. }
  479. } else {
  480. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  481. pdata->rfe_ctl |= RFE_CTL_DPF;
  482. }
  483. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  484. /* defer register writes to a sleepable context */
  485. schedule_work(&pdata->set_multicast);
  486. }
  487. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  488. u16 lcladv, u16 rmtadv)
  489. {
  490. u32 flow = 0, fct_flow = 0;
  491. int ret;
  492. if (duplex == DUPLEX_FULL) {
  493. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  494. if (cap & FLOW_CTRL_TX) {
  495. flow = (FLOW_TX_FCEN | 0xFFFF);
  496. /* set fct_flow thresholds to 20% and 80% */
  497. fct_flow = (8 << 8) | 32;
  498. }
  499. if (cap & FLOW_CTRL_RX)
  500. flow |= FLOW_RX_FCEN;
  501. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  502. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  503. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  504. } else {
  505. netif_dbg(dev, link, dev->net, "half duplex\n");
  506. }
  507. ret = smsc75xx_write_reg(dev, FLOW, flow);
  508. if (ret < 0) {
  509. netdev_warn(dev->net, "Error writing FLOW\n");
  510. return ret;
  511. }
  512. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  513. if (ret < 0) {
  514. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  515. return ret;
  516. }
  517. return 0;
  518. }
  519. static int smsc75xx_link_reset(struct usbnet *dev)
  520. {
  521. struct mii_if_info *mii = &dev->mii;
  522. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  523. u16 lcladv, rmtadv;
  524. int ret;
  525. /* write to clear phy interrupt status */
  526. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  527. PHY_INT_SRC_CLEAR_ALL);
  528. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  529. if (ret < 0) {
  530. netdev_warn(dev->net, "Error writing INT_STS\n");
  531. return ret;
  532. }
  533. mii_check_media(mii, 1, 1);
  534. mii_ethtool_gset(&dev->mii, &ecmd);
  535. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  536. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  537. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  538. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  539. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  540. }
  541. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  542. {
  543. u32 intdata;
  544. if (urb->actual_length != 4) {
  545. netdev_warn(dev->net, "unexpected urb length %d\n",
  546. urb->actual_length);
  547. return;
  548. }
  549. memcpy(&intdata, urb->transfer_buffer, 4);
  550. le32_to_cpus(&intdata);
  551. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  552. if (intdata & INT_ENP_PHY_INT)
  553. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  554. else
  555. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  556. intdata);
  557. }
  558. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  559. {
  560. return MAX_EEPROM_SIZE;
  561. }
  562. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  563. struct ethtool_eeprom *ee, u8 *data)
  564. {
  565. struct usbnet *dev = netdev_priv(netdev);
  566. ee->magic = LAN75XX_EEPROM_MAGIC;
  567. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  568. }
  569. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  570. struct ethtool_eeprom *ee, u8 *data)
  571. {
  572. struct usbnet *dev = netdev_priv(netdev);
  573. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  574. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  575. ee->magic);
  576. return -EINVAL;
  577. }
  578. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  579. }
  580. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  581. struct ethtool_wolinfo *wolinfo)
  582. {
  583. struct usbnet *dev = netdev_priv(net);
  584. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  585. wolinfo->supported = SUPPORTED_WAKE;
  586. wolinfo->wolopts = pdata->wolopts;
  587. }
  588. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  589. struct ethtool_wolinfo *wolinfo)
  590. {
  591. struct usbnet *dev = netdev_priv(net);
  592. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  593. int ret;
  594. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  595. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  596. if (ret < 0)
  597. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  598. return ret;
  599. }
  600. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  601. .get_link = usbnet_get_link,
  602. .nway_reset = usbnet_nway_reset,
  603. .get_drvinfo = usbnet_get_drvinfo,
  604. .get_msglevel = usbnet_get_msglevel,
  605. .set_msglevel = usbnet_set_msglevel,
  606. .get_settings = usbnet_get_settings,
  607. .set_settings = usbnet_set_settings,
  608. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  609. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  610. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  611. .get_wol = smsc75xx_ethtool_get_wol,
  612. .set_wol = smsc75xx_ethtool_set_wol,
  613. };
  614. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  615. {
  616. struct usbnet *dev = netdev_priv(netdev);
  617. if (!netif_running(netdev))
  618. return -EINVAL;
  619. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  620. }
  621. static void smsc75xx_init_mac_address(struct usbnet *dev)
  622. {
  623. /* try reading mac address from EEPROM */
  624. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  625. dev->net->dev_addr) == 0) {
  626. if (is_valid_ether_addr(dev->net->dev_addr)) {
  627. /* eeprom values are valid so use them */
  628. netif_dbg(dev, ifup, dev->net,
  629. "MAC address read from EEPROM\n");
  630. return;
  631. }
  632. }
  633. /* no eeprom, or eeprom values are invalid. generate random MAC */
  634. eth_hw_addr_random(dev->net);
  635. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  636. }
  637. static int smsc75xx_set_mac_address(struct usbnet *dev)
  638. {
  639. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  640. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  641. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  642. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  643. if (ret < 0) {
  644. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  645. return ret;
  646. }
  647. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  648. if (ret < 0) {
  649. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  650. return ret;
  651. }
  652. addr_hi |= ADDR_FILTX_FB_VALID;
  653. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  654. if (ret < 0) {
  655. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  656. return ret;
  657. }
  658. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  659. if (ret < 0)
  660. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  661. return ret;
  662. }
  663. static int smsc75xx_phy_initialize(struct usbnet *dev)
  664. {
  665. int bmcr, ret, timeout = 0;
  666. /* Initialize MII structure */
  667. dev->mii.dev = dev->net;
  668. dev->mii.mdio_read = smsc75xx_mdio_read;
  669. dev->mii.mdio_write = smsc75xx_mdio_write;
  670. dev->mii.phy_id_mask = 0x1f;
  671. dev->mii.reg_num_mask = 0x1f;
  672. dev->mii.supports_gmii = 1;
  673. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  674. /* reset phy and wait for reset to complete */
  675. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  676. do {
  677. msleep(10);
  678. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  679. if (bmcr < 0) {
  680. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  681. return bmcr;
  682. }
  683. timeout++;
  684. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  685. if (timeout >= 100) {
  686. netdev_warn(dev->net, "timeout on PHY Reset\n");
  687. return -EIO;
  688. }
  689. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  690. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  691. ADVERTISE_PAUSE_ASYM);
  692. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  693. ADVERTISE_1000FULL);
  694. /* read and write to clear phy interrupt status */
  695. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  696. if (ret < 0) {
  697. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  698. return ret;
  699. }
  700. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  701. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  702. PHY_INT_MASK_DEFAULT);
  703. mii_nway_restart(&dev->mii);
  704. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  705. return 0;
  706. }
  707. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  708. {
  709. int ret = 0;
  710. u32 buf;
  711. bool rxenabled;
  712. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  713. if (ret < 0) {
  714. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  715. return ret;
  716. }
  717. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  718. if (rxenabled) {
  719. buf &= ~MAC_RX_RXEN;
  720. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  721. if (ret < 0) {
  722. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  723. return ret;
  724. }
  725. }
  726. /* add 4 to size for FCS */
  727. buf &= ~MAC_RX_MAX_SIZE;
  728. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  729. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  730. if (ret < 0) {
  731. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  732. return ret;
  733. }
  734. if (rxenabled) {
  735. buf |= MAC_RX_RXEN;
  736. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  737. if (ret < 0) {
  738. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  739. return ret;
  740. }
  741. }
  742. return 0;
  743. }
  744. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  745. {
  746. struct usbnet *dev = netdev_priv(netdev);
  747. int ret;
  748. if (new_mtu > MAX_SINGLE_PACKET_SIZE)
  749. return -EINVAL;
  750. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  751. if (ret < 0) {
  752. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  753. return ret;
  754. }
  755. return usbnet_change_mtu(netdev, new_mtu);
  756. }
  757. /* Enable or disable Rx checksum offload engine */
  758. static int smsc75xx_set_features(struct net_device *netdev,
  759. netdev_features_t features)
  760. {
  761. struct usbnet *dev = netdev_priv(netdev);
  762. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  763. unsigned long flags;
  764. int ret;
  765. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  766. if (features & NETIF_F_RXCSUM)
  767. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  768. else
  769. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  770. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  771. /* it's racing here! */
  772. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  773. if (ret < 0)
  774. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  775. return ret;
  776. }
  777. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  778. {
  779. int timeout = 0;
  780. do {
  781. u32 buf;
  782. int ret;
  783. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  784. if (ret < 0) {
  785. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  786. return ret;
  787. }
  788. if (buf & PMT_CTL_DEV_RDY)
  789. return 0;
  790. msleep(10);
  791. timeout++;
  792. } while (timeout < 100);
  793. netdev_warn(dev->net, "timeout waiting for device ready\n");
  794. return -EIO;
  795. }
  796. static int smsc75xx_reset(struct usbnet *dev)
  797. {
  798. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  799. u32 buf;
  800. int ret = 0, timeout;
  801. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  802. ret = smsc75xx_wait_ready(dev, 0);
  803. if (ret < 0) {
  804. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  805. return ret;
  806. }
  807. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  808. if (ret < 0) {
  809. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  810. return ret;
  811. }
  812. buf |= HW_CFG_LRST;
  813. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  814. if (ret < 0) {
  815. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  816. return ret;
  817. }
  818. timeout = 0;
  819. do {
  820. msleep(10);
  821. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  822. if (ret < 0) {
  823. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  824. return ret;
  825. }
  826. timeout++;
  827. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  828. if (timeout >= 100) {
  829. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  830. return -EIO;
  831. }
  832. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  833. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  834. if (ret < 0) {
  835. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  836. return ret;
  837. }
  838. buf |= PMT_CTL_PHY_RST;
  839. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  840. if (ret < 0) {
  841. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  842. return ret;
  843. }
  844. timeout = 0;
  845. do {
  846. msleep(10);
  847. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  848. if (ret < 0) {
  849. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  850. return ret;
  851. }
  852. timeout++;
  853. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  854. if (timeout >= 100) {
  855. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  856. return -EIO;
  857. }
  858. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  859. ret = smsc75xx_set_mac_address(dev);
  860. if (ret < 0) {
  861. netdev_warn(dev->net, "Failed to set mac address\n");
  862. return ret;
  863. }
  864. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  865. dev->net->dev_addr);
  866. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  867. if (ret < 0) {
  868. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  869. return ret;
  870. }
  871. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  872. buf);
  873. buf |= HW_CFG_BIR;
  874. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  875. if (ret < 0) {
  876. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  877. return ret;
  878. }
  879. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  880. if (ret < 0) {
  881. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  882. return ret;
  883. }
  884. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  885. buf);
  886. if (!turbo_mode) {
  887. buf = 0;
  888. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  889. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  890. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  891. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  892. } else {
  893. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  894. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  895. }
  896. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  897. (ulong)dev->rx_urb_size);
  898. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  899. if (ret < 0) {
  900. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  901. return ret;
  902. }
  903. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  904. if (ret < 0) {
  905. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  906. return ret;
  907. }
  908. netif_dbg(dev, ifup, dev->net,
  909. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  910. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  911. if (ret < 0) {
  912. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  913. return ret;
  914. }
  915. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  916. if (ret < 0) {
  917. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  918. return ret;
  919. }
  920. netif_dbg(dev, ifup, dev->net,
  921. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  922. if (turbo_mode) {
  923. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  924. if (ret < 0) {
  925. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  926. return ret;
  927. }
  928. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  929. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  930. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  931. if (ret < 0) {
  932. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  933. return ret;
  934. }
  935. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  936. if (ret < 0) {
  937. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  938. return ret;
  939. }
  940. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  941. }
  942. /* set FIFO sizes */
  943. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  944. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  945. if (ret < 0) {
  946. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  947. return ret;
  948. }
  949. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  950. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  951. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  952. if (ret < 0) {
  953. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  954. return ret;
  955. }
  956. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  957. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  958. if (ret < 0) {
  959. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  960. return ret;
  961. }
  962. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  963. if (ret < 0) {
  964. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  965. return ret;
  966. }
  967. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  968. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  969. if (ret < 0) {
  970. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  971. return ret;
  972. }
  973. /* only set default GPIO/LED settings if no EEPROM is detected */
  974. if (!(buf & E2P_CMD_LOADED)) {
  975. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  976. if (ret < 0) {
  977. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  978. return ret;
  979. }
  980. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  981. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  982. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  983. if (ret < 0) {
  984. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  985. return ret;
  986. }
  987. }
  988. ret = smsc75xx_write_reg(dev, FLOW, 0);
  989. if (ret < 0) {
  990. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  991. return ret;
  992. }
  993. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  994. if (ret < 0) {
  995. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  996. return ret;
  997. }
  998. /* Don't need rfe_ctl_lock during initialisation */
  999. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1000. if (ret < 0) {
  1001. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1002. return ret;
  1003. }
  1004. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1005. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1006. if (ret < 0) {
  1007. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1008. return ret;
  1009. }
  1010. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1011. if (ret < 0) {
  1012. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1013. return ret;
  1014. }
  1015. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1016. pdata->rfe_ctl);
  1017. /* Enable or disable checksum offload engines */
  1018. smsc75xx_set_features(dev->net, dev->net->features);
  1019. smsc75xx_set_multicast(dev->net);
  1020. ret = smsc75xx_phy_initialize(dev);
  1021. if (ret < 0) {
  1022. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1023. return ret;
  1024. }
  1025. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1026. if (ret < 0) {
  1027. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1028. return ret;
  1029. }
  1030. /* enable PHY interrupts */
  1031. buf |= INT_ENP_PHY_INT;
  1032. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1033. if (ret < 0) {
  1034. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1035. return ret;
  1036. }
  1037. /* allow mac to detect speed and duplex from phy */
  1038. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1039. if (ret < 0) {
  1040. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1041. return ret;
  1042. }
  1043. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1044. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1045. if (ret < 0) {
  1046. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1047. return ret;
  1048. }
  1049. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1050. if (ret < 0) {
  1051. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1052. return ret;
  1053. }
  1054. buf |= MAC_TX_TXEN;
  1055. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1056. if (ret < 0) {
  1057. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1058. return ret;
  1059. }
  1060. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1061. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1062. if (ret < 0) {
  1063. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1064. return ret;
  1065. }
  1066. buf |= FCT_TX_CTL_EN;
  1067. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1068. if (ret < 0) {
  1069. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1070. return ret;
  1071. }
  1072. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1073. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1074. if (ret < 0) {
  1075. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1076. return ret;
  1077. }
  1078. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1079. if (ret < 0) {
  1080. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1081. return ret;
  1082. }
  1083. buf |= MAC_RX_RXEN;
  1084. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1085. if (ret < 0) {
  1086. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1087. return ret;
  1088. }
  1089. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1090. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1091. if (ret < 0) {
  1092. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1093. return ret;
  1094. }
  1095. buf |= FCT_RX_CTL_EN;
  1096. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1097. if (ret < 0) {
  1098. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1099. return ret;
  1100. }
  1101. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1102. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1103. return 0;
  1104. }
  1105. static const struct net_device_ops smsc75xx_netdev_ops = {
  1106. .ndo_open = usbnet_open,
  1107. .ndo_stop = usbnet_stop,
  1108. .ndo_start_xmit = usbnet_start_xmit,
  1109. .ndo_tx_timeout = usbnet_tx_timeout,
  1110. .ndo_change_mtu = smsc75xx_change_mtu,
  1111. .ndo_set_mac_address = eth_mac_addr,
  1112. .ndo_validate_addr = eth_validate_addr,
  1113. .ndo_do_ioctl = smsc75xx_ioctl,
  1114. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1115. .ndo_set_features = smsc75xx_set_features,
  1116. };
  1117. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1118. {
  1119. struct smsc75xx_priv *pdata = NULL;
  1120. int ret;
  1121. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1122. ret = usbnet_get_endpoints(dev, intf);
  1123. if (ret < 0) {
  1124. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1125. return ret;
  1126. }
  1127. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1128. GFP_KERNEL);
  1129. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1130. if (!pdata)
  1131. return -ENOMEM;
  1132. pdata->dev = dev;
  1133. spin_lock_init(&pdata->rfe_ctl_lock);
  1134. mutex_init(&pdata->dataport_mutex);
  1135. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1136. if (DEFAULT_TX_CSUM_ENABLE)
  1137. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1138. if (DEFAULT_RX_CSUM_ENABLE)
  1139. dev->net->features |= NETIF_F_RXCSUM;
  1140. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1141. NETIF_F_RXCSUM;
  1142. ret = smsc75xx_wait_ready(dev, 0);
  1143. if (ret < 0) {
  1144. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1145. return ret;
  1146. }
  1147. smsc75xx_init_mac_address(dev);
  1148. /* Init all registers */
  1149. ret = smsc75xx_reset(dev);
  1150. if (ret < 0) {
  1151. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1152. return ret;
  1153. }
  1154. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1155. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1156. dev->net->flags |= IFF_MULTICAST;
  1157. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1158. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1159. return 0;
  1160. }
  1161. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1162. {
  1163. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1164. if (pdata) {
  1165. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1166. kfree(pdata);
  1167. pdata = NULL;
  1168. dev->data[0] = 0;
  1169. }
  1170. }
  1171. static u16 smsc_crc(const u8 *buffer, size_t len)
  1172. {
  1173. return bitrev16(crc16(0xFFFF, buffer, len));
  1174. }
  1175. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1176. u32 wuf_mask1)
  1177. {
  1178. int cfg_base = WUF_CFGX + filter * 4;
  1179. int mask_base = WUF_MASKX + filter * 16;
  1180. int ret;
  1181. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1182. if (ret < 0) {
  1183. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1184. return ret;
  1185. }
  1186. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1187. if (ret < 0) {
  1188. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1189. return ret;
  1190. }
  1191. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1192. if (ret < 0) {
  1193. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1194. return ret;
  1195. }
  1196. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1197. if (ret < 0) {
  1198. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1199. return ret;
  1200. }
  1201. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1202. if (ret < 0) {
  1203. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1204. return ret;
  1205. }
  1206. return 0;
  1207. }
  1208. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1209. {
  1210. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1211. u32 val;
  1212. int ret;
  1213. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1214. if (ret < 0) {
  1215. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1216. return ret;
  1217. }
  1218. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1219. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1220. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1221. if (ret < 0) {
  1222. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1223. return ret;
  1224. }
  1225. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1226. return 0;
  1227. }
  1228. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1229. {
  1230. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1231. u32 val;
  1232. int ret;
  1233. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1234. if (ret < 0) {
  1235. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1236. return ret;
  1237. }
  1238. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1239. val |= PMT_CTL_SUS_MODE_1;
  1240. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1241. if (ret < 0) {
  1242. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1243. return ret;
  1244. }
  1245. /* clear wol status, enable energy detection */
  1246. val &= ~PMT_CTL_WUPS;
  1247. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1248. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1249. if (ret < 0) {
  1250. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1251. return ret;
  1252. }
  1253. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1254. return 0;
  1255. }
  1256. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1257. {
  1258. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1259. u32 val;
  1260. int ret;
  1261. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1262. if (ret < 0) {
  1263. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1264. return ret;
  1265. }
  1266. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1267. val |= PMT_CTL_SUS_MODE_2;
  1268. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1269. if (ret < 0) {
  1270. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1271. return ret;
  1272. }
  1273. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1274. return 0;
  1275. }
  1276. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1277. {
  1278. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1279. u32 val;
  1280. int ret;
  1281. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1282. if (ret < 0) {
  1283. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1284. return ret;
  1285. }
  1286. if (val & FCT_RX_CTL_RXUSED) {
  1287. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1288. return -EBUSY;
  1289. }
  1290. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1291. if (ret < 0) {
  1292. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1293. return ret;
  1294. }
  1295. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1296. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1297. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1298. if (ret < 0) {
  1299. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1300. return ret;
  1301. }
  1302. /* clear wol status */
  1303. val &= ~PMT_CTL_WUPS;
  1304. val |= PMT_CTL_WUPS_WOL;
  1305. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1306. if (ret < 0) {
  1307. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1308. return ret;
  1309. }
  1310. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1311. return 0;
  1312. }
  1313. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1314. {
  1315. struct mii_if_info *mii = &dev->mii;
  1316. int ret;
  1317. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1318. /* read to clear */
  1319. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1320. if (ret < 0) {
  1321. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1322. return ret;
  1323. }
  1324. /* enable interrupt source */
  1325. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1326. if (ret < 0) {
  1327. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1328. return ret;
  1329. }
  1330. ret |= mask;
  1331. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1332. return 0;
  1333. }
  1334. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1335. {
  1336. struct mii_if_info *mii = &dev->mii;
  1337. int ret;
  1338. /* first, a dummy read, needed to latch some MII phys */
  1339. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1340. if (ret < 0) {
  1341. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1342. return ret;
  1343. }
  1344. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1345. if (ret < 0) {
  1346. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1347. return ret;
  1348. }
  1349. return !!(ret & BMSR_LSTATUS);
  1350. }
  1351. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1352. {
  1353. int ret;
  1354. if (!netif_running(dev->net)) {
  1355. /* interface is ifconfig down so fully power down hw */
  1356. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1357. return smsc75xx_enter_suspend2(dev);
  1358. }
  1359. if (!link_up) {
  1360. /* link is down so enter EDPD mode */
  1361. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1362. /* enable PHY wakeup events for if cable is attached */
  1363. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1364. PHY_INT_MASK_ANEG_COMP);
  1365. if (ret < 0) {
  1366. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1367. return ret;
  1368. }
  1369. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1370. return smsc75xx_enter_suspend1(dev);
  1371. }
  1372. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1373. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1374. PHY_INT_MASK_LINK_DOWN);
  1375. if (ret < 0) {
  1376. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1377. return ret;
  1378. }
  1379. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1380. return smsc75xx_enter_suspend3(dev);
  1381. }
  1382. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1383. {
  1384. struct usbnet *dev = usb_get_intfdata(intf);
  1385. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1386. u32 val, link_up;
  1387. int ret;
  1388. ret = usbnet_suspend(intf, message);
  1389. if (ret < 0) {
  1390. netdev_warn(dev->net, "usbnet_suspend error\n");
  1391. return ret;
  1392. }
  1393. if (pdata->suspend_flags) {
  1394. netdev_warn(dev->net, "error during last resume\n");
  1395. pdata->suspend_flags = 0;
  1396. }
  1397. /* determine if link is up using only _nopm functions */
  1398. link_up = smsc75xx_link_ok_nopm(dev);
  1399. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1400. ret = smsc75xx_autosuspend(dev, link_up);
  1401. goto done;
  1402. }
  1403. /* if we get this far we're not autosuspending */
  1404. /* if no wol options set, or if link is down and we're not waking on
  1405. * PHY activity, enter lowest power SUSPEND2 mode
  1406. */
  1407. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1408. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1409. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1410. /* disable energy detect (link up) & wake up events */
  1411. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1412. if (ret < 0) {
  1413. netdev_warn(dev->net, "Error reading WUCSR\n");
  1414. goto done;
  1415. }
  1416. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1417. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1418. if (ret < 0) {
  1419. netdev_warn(dev->net, "Error writing WUCSR\n");
  1420. goto done;
  1421. }
  1422. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1423. if (ret < 0) {
  1424. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1425. goto done;
  1426. }
  1427. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1428. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1429. if (ret < 0) {
  1430. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1431. goto done;
  1432. }
  1433. ret = smsc75xx_enter_suspend2(dev);
  1434. goto done;
  1435. }
  1436. if (pdata->wolopts & WAKE_PHY) {
  1437. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1438. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1439. if (ret < 0) {
  1440. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1441. goto done;
  1442. }
  1443. /* if link is down then configure EDPD and enter SUSPEND1,
  1444. * otherwise enter SUSPEND0 below
  1445. */
  1446. if (!link_up) {
  1447. struct mii_if_info *mii = &dev->mii;
  1448. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1449. /* enable energy detect power-down mode */
  1450. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1451. PHY_MODE_CTRL_STS);
  1452. if (ret < 0) {
  1453. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1454. goto done;
  1455. }
  1456. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1457. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1458. PHY_MODE_CTRL_STS, ret);
  1459. /* enter SUSPEND1 mode */
  1460. ret = smsc75xx_enter_suspend1(dev);
  1461. goto done;
  1462. }
  1463. }
  1464. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1465. int i, filter = 0;
  1466. /* disable all filters */
  1467. for (i = 0; i < WUF_NUM; i++) {
  1468. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1469. if (ret < 0) {
  1470. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1471. goto done;
  1472. }
  1473. }
  1474. if (pdata->wolopts & WAKE_MCAST) {
  1475. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1476. netdev_info(dev->net, "enabling multicast detection\n");
  1477. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1478. | smsc_crc(mcast, 3);
  1479. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1480. if (ret < 0) {
  1481. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1482. goto done;
  1483. }
  1484. }
  1485. if (pdata->wolopts & WAKE_ARP) {
  1486. const u8 arp[] = {0x08, 0x06};
  1487. netdev_info(dev->net, "enabling ARP detection\n");
  1488. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1489. | smsc_crc(arp, 2);
  1490. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1491. if (ret < 0) {
  1492. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1493. goto done;
  1494. }
  1495. }
  1496. /* clear any pending pattern match packet status */
  1497. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1498. if (ret < 0) {
  1499. netdev_warn(dev->net, "Error reading WUCSR\n");
  1500. goto done;
  1501. }
  1502. val |= WUCSR_WUFR;
  1503. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1504. if (ret < 0) {
  1505. netdev_warn(dev->net, "Error writing WUCSR\n");
  1506. goto done;
  1507. }
  1508. netdev_info(dev->net, "enabling packet match detection\n");
  1509. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1510. if (ret < 0) {
  1511. netdev_warn(dev->net, "Error reading WUCSR\n");
  1512. goto done;
  1513. }
  1514. val |= WUCSR_WUEN;
  1515. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1516. if (ret < 0) {
  1517. netdev_warn(dev->net, "Error writing WUCSR\n");
  1518. goto done;
  1519. }
  1520. } else {
  1521. netdev_info(dev->net, "disabling packet match detection\n");
  1522. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1523. if (ret < 0) {
  1524. netdev_warn(dev->net, "Error reading WUCSR\n");
  1525. goto done;
  1526. }
  1527. val &= ~WUCSR_WUEN;
  1528. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1529. if (ret < 0) {
  1530. netdev_warn(dev->net, "Error writing WUCSR\n");
  1531. goto done;
  1532. }
  1533. }
  1534. /* disable magic, bcast & unicast wakeup sources */
  1535. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1536. if (ret < 0) {
  1537. netdev_warn(dev->net, "Error reading WUCSR\n");
  1538. goto done;
  1539. }
  1540. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1541. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1542. if (ret < 0) {
  1543. netdev_warn(dev->net, "Error writing WUCSR\n");
  1544. goto done;
  1545. }
  1546. if (pdata->wolopts & WAKE_PHY) {
  1547. netdev_info(dev->net, "enabling PHY wakeup\n");
  1548. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1549. if (ret < 0) {
  1550. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1551. goto done;
  1552. }
  1553. /* clear wol status, enable energy detection */
  1554. val &= ~PMT_CTL_WUPS;
  1555. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1556. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1557. if (ret < 0) {
  1558. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1559. goto done;
  1560. }
  1561. }
  1562. if (pdata->wolopts & WAKE_MAGIC) {
  1563. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1564. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1565. if (ret < 0) {
  1566. netdev_warn(dev->net, "Error reading WUCSR\n");
  1567. goto done;
  1568. }
  1569. /* clear any pending magic packet status */
  1570. val |= WUCSR_MPR | WUCSR_MPEN;
  1571. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1572. if (ret < 0) {
  1573. netdev_warn(dev->net, "Error writing WUCSR\n");
  1574. goto done;
  1575. }
  1576. }
  1577. if (pdata->wolopts & WAKE_BCAST) {
  1578. netdev_info(dev->net, "enabling broadcast detection\n");
  1579. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1580. if (ret < 0) {
  1581. netdev_warn(dev->net, "Error reading WUCSR\n");
  1582. goto done;
  1583. }
  1584. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1585. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1586. if (ret < 0) {
  1587. netdev_warn(dev->net, "Error writing WUCSR\n");
  1588. goto done;
  1589. }
  1590. }
  1591. if (pdata->wolopts & WAKE_UCAST) {
  1592. netdev_info(dev->net, "enabling unicast detection\n");
  1593. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1594. if (ret < 0) {
  1595. netdev_warn(dev->net, "Error reading WUCSR\n");
  1596. goto done;
  1597. }
  1598. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1599. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1600. if (ret < 0) {
  1601. netdev_warn(dev->net, "Error writing WUCSR\n");
  1602. goto done;
  1603. }
  1604. }
  1605. /* enable receiver to enable frame reception */
  1606. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1607. if (ret < 0) {
  1608. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1609. goto done;
  1610. }
  1611. val |= MAC_RX_RXEN;
  1612. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1613. if (ret < 0) {
  1614. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1615. goto done;
  1616. }
  1617. /* some wol options are enabled, so enter SUSPEND0 */
  1618. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1619. ret = smsc75xx_enter_suspend0(dev);
  1620. done:
  1621. /*
  1622. * TODO: resume() might need to handle the suspend failure
  1623. * in system sleep
  1624. */
  1625. if (ret && PMSG_IS_AUTO(message))
  1626. usbnet_resume(intf);
  1627. return ret;
  1628. }
  1629. static int smsc75xx_resume(struct usb_interface *intf)
  1630. {
  1631. struct usbnet *dev = usb_get_intfdata(intf);
  1632. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1633. u8 suspend_flags = pdata->suspend_flags;
  1634. int ret;
  1635. u32 val;
  1636. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1637. /* do this first to ensure it's cleared even in error case */
  1638. pdata->suspend_flags = 0;
  1639. if (suspend_flags & SUSPEND_ALLMODES) {
  1640. /* Disable wakeup sources */
  1641. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1642. if (ret < 0) {
  1643. netdev_warn(dev->net, "Error reading WUCSR\n");
  1644. return ret;
  1645. }
  1646. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1647. | WUCSR_BCST_EN);
  1648. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1649. if (ret < 0) {
  1650. netdev_warn(dev->net, "Error writing WUCSR\n");
  1651. return ret;
  1652. }
  1653. /* clear wake-up status */
  1654. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1655. if (ret < 0) {
  1656. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1657. return ret;
  1658. }
  1659. val &= ~PMT_CTL_WOL_EN;
  1660. val |= PMT_CTL_WUPS;
  1661. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1662. if (ret < 0) {
  1663. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1664. return ret;
  1665. }
  1666. }
  1667. if (suspend_flags & SUSPEND_SUSPEND2) {
  1668. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1669. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1670. if (ret < 0) {
  1671. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1672. return ret;
  1673. }
  1674. val |= PMT_CTL_PHY_PWRUP;
  1675. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1676. if (ret < 0) {
  1677. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1678. return ret;
  1679. }
  1680. }
  1681. ret = smsc75xx_wait_ready(dev, 1);
  1682. if (ret < 0) {
  1683. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1684. return ret;
  1685. }
  1686. return usbnet_resume(intf);
  1687. }
  1688. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1689. u32 rx_cmd_a, u32 rx_cmd_b)
  1690. {
  1691. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1692. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1693. skb->ip_summed = CHECKSUM_NONE;
  1694. } else {
  1695. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1696. skb->ip_summed = CHECKSUM_COMPLETE;
  1697. }
  1698. }
  1699. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1700. {
  1701. while (skb->len > 0) {
  1702. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1703. struct sk_buff *ax_skb;
  1704. unsigned char *packet;
  1705. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1706. le32_to_cpus(&rx_cmd_a);
  1707. skb_pull(skb, 4);
  1708. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1709. le32_to_cpus(&rx_cmd_b);
  1710. skb_pull(skb, 4 + RXW_PADDING);
  1711. packet = skb->data;
  1712. /* get the packet length */
  1713. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1714. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1715. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1716. netif_dbg(dev, rx_err, dev->net,
  1717. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1718. dev->net->stats.rx_errors++;
  1719. dev->net->stats.rx_dropped++;
  1720. if (rx_cmd_a & RX_CMD_A_FCS)
  1721. dev->net->stats.rx_crc_errors++;
  1722. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1723. dev->net->stats.rx_frame_errors++;
  1724. } else {
  1725. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1726. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1727. netif_dbg(dev, rx_err, dev->net,
  1728. "size err rx_cmd_a=0x%08x\n",
  1729. rx_cmd_a);
  1730. return 0;
  1731. }
  1732. /* last frame in this batch */
  1733. if (skb->len == size) {
  1734. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1735. rx_cmd_b);
  1736. skb_trim(skb, skb->len - 4); /* remove fcs */
  1737. skb->truesize = size + sizeof(struct sk_buff);
  1738. return 1;
  1739. }
  1740. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1741. if (unlikely(!ax_skb)) {
  1742. netdev_warn(dev->net, "Error allocating skb\n");
  1743. return 0;
  1744. }
  1745. ax_skb->len = size;
  1746. ax_skb->data = packet;
  1747. skb_set_tail_pointer(ax_skb, size);
  1748. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1749. rx_cmd_b);
  1750. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1751. ax_skb->truesize = size + sizeof(struct sk_buff);
  1752. usbnet_skb_return(dev, ax_skb);
  1753. }
  1754. skb_pull(skb, size);
  1755. /* padding bytes before the next frame starts */
  1756. if (skb->len)
  1757. skb_pull(skb, align_count);
  1758. }
  1759. if (unlikely(skb->len < 0)) {
  1760. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1761. return 0;
  1762. }
  1763. return 1;
  1764. }
  1765. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1766. struct sk_buff *skb, gfp_t flags)
  1767. {
  1768. u32 tx_cmd_a, tx_cmd_b;
  1769. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1770. struct sk_buff *skb2 =
  1771. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1772. dev_kfree_skb_any(skb);
  1773. skb = skb2;
  1774. if (!skb)
  1775. return NULL;
  1776. }
  1777. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1778. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1779. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1780. if (skb_is_gso(skb)) {
  1781. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1782. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1783. tx_cmd_a |= TX_CMD_A_LSO;
  1784. } else {
  1785. tx_cmd_b = 0;
  1786. }
  1787. skb_push(skb, 4);
  1788. cpu_to_le32s(&tx_cmd_b);
  1789. memcpy(skb->data, &tx_cmd_b, 4);
  1790. skb_push(skb, 4);
  1791. cpu_to_le32s(&tx_cmd_a);
  1792. memcpy(skb->data, &tx_cmd_a, 4);
  1793. return skb;
  1794. }
  1795. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1796. {
  1797. dev->intf->needs_remote_wakeup = on;
  1798. return 0;
  1799. }
  1800. static const struct driver_info smsc75xx_info = {
  1801. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1802. .bind = smsc75xx_bind,
  1803. .unbind = smsc75xx_unbind,
  1804. .link_reset = smsc75xx_link_reset,
  1805. .reset = smsc75xx_reset,
  1806. .rx_fixup = smsc75xx_rx_fixup,
  1807. .tx_fixup = smsc75xx_tx_fixup,
  1808. .status = smsc75xx_status,
  1809. .manage_power = smsc75xx_manage_power,
  1810. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1811. };
  1812. static const struct usb_device_id products[] = {
  1813. {
  1814. /* SMSC7500 USB Gigabit Ethernet Device */
  1815. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1816. .driver_info = (unsigned long) &smsc75xx_info,
  1817. },
  1818. {
  1819. /* SMSC7500 USB Gigabit Ethernet Device */
  1820. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1821. .driver_info = (unsigned long) &smsc75xx_info,
  1822. },
  1823. { }, /* END */
  1824. };
  1825. MODULE_DEVICE_TABLE(usb, products);
  1826. static struct usb_driver smsc75xx_driver = {
  1827. .name = SMSC_CHIPNAME,
  1828. .id_table = products,
  1829. .probe = usbnet_probe,
  1830. .suspend = smsc75xx_suspend,
  1831. .resume = smsc75xx_resume,
  1832. .reset_resume = smsc75xx_resume,
  1833. .disconnect = usbnet_disconnect,
  1834. .disable_hub_initiated_lpm = 1,
  1835. .supports_autosuspend = 1,
  1836. };
  1837. module_usb_driver(smsc75xx_driver);
  1838. MODULE_AUTHOR("Nancy Lin");
  1839. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1840. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1841. MODULE_LICENSE("GPL");