caamalg.c 65 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206
  1. /*
  2. * caam - Freescale FSL CAAM support for crypto API
  3. *
  4. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  5. *
  6. * Based on talitos crypto API driver.
  7. *
  8. * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
  9. *
  10. * --------------- ---------------
  11. * | JobDesc #1 |-------------------->| ShareDesc |
  12. * | *(packet 1) | | (PDB) |
  13. * --------------- |------------->| (hashKey) |
  14. * . | | (cipherKey) |
  15. * . | |-------->| (operation) |
  16. * --------------- | | ---------------
  17. * | JobDesc #2 |------| |
  18. * | *(packet 2) | |
  19. * --------------- |
  20. * . |
  21. * . |
  22. * --------------- |
  23. * | JobDesc #3 |------------
  24. * | *(packet 3) |
  25. * ---------------
  26. *
  27. * The SharedDesc never changes for a connection unless rekeyed, but
  28. * each packet will likely be in a different place. So all we need
  29. * to know to process the packet is where the input is, where the
  30. * output goes, and what context we want to process with. Context is
  31. * in the SharedDesc, packet references in the JobDesc.
  32. *
  33. * So, a job desc looks like:
  34. *
  35. * ---------------------
  36. * | Header |
  37. * | ShareDesc Pointer |
  38. * | SEQ_OUT_PTR |
  39. * | (output buffer) |
  40. * | (output length) |
  41. * | SEQ_IN_PTR |
  42. * | (input buffer) |
  43. * | (input length) |
  44. * ---------------------
  45. */
  46. #include "compat.h"
  47. #include "regs.h"
  48. #include "intern.h"
  49. #include "desc_constr.h"
  50. #include "jr.h"
  51. #include "error.h"
  52. #include "sg_sw_sec4.h"
  53. #include "key_gen.h"
  54. /*
  55. * crypto alg
  56. */
  57. #define CAAM_CRA_PRIORITY 3000
  58. /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
  59. #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
  60. SHA512_DIGEST_SIZE * 2)
  61. /* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
  62. #define CAAM_MAX_IV_LENGTH 16
  63. /* length of descriptors text */
  64. #define DESC_AEAD_BASE (4 * CAAM_CMD_SZ)
  65. #define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ)
  66. #define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ)
  67. #define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
  68. #define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ)
  69. #define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \
  70. 20 * CAAM_CMD_SZ)
  71. #define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \
  72. 15 * CAAM_CMD_SZ)
  73. #define DESC_MAX_USED_BYTES (DESC_AEAD_GIVENC_LEN + \
  74. CAAM_MAX_KEY_SIZE)
  75. #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
  76. #ifdef DEBUG
  77. /* for print_hex_dumps with line references */
  78. #define debug(format, arg...) printk(format, arg)
  79. #else
  80. #define debug(format, arg...)
  81. #endif
  82. static struct list_head alg_list;
  83. /* Set DK bit in class 1 operation if shared */
  84. static inline void append_dec_op1(u32 *desc, u32 type)
  85. {
  86. u32 *jump_cmd, *uncond_jump_cmd;
  87. jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
  88. append_operation(desc, type | OP_ALG_AS_INITFINAL |
  89. OP_ALG_DECRYPT);
  90. uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL);
  91. set_jump_tgt_here(desc, jump_cmd);
  92. append_operation(desc, type | OP_ALG_AS_INITFINAL |
  93. OP_ALG_DECRYPT | OP_ALG_AAI_DK);
  94. set_jump_tgt_here(desc, uncond_jump_cmd);
  95. }
  96. /*
  97. * Wait for completion of class 1 key loading before allowing
  98. * error propagation
  99. */
  100. static inline void append_dec_shr_done(u32 *desc)
  101. {
  102. u32 *jump_cmd;
  103. jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL);
  104. set_jump_tgt_here(desc, jump_cmd);
  105. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  106. }
  107. /*
  108. * For aead functions, read payload and write payload,
  109. * both of which are specified in req->src and req->dst
  110. */
  111. static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
  112. {
  113. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
  114. KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
  115. append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
  116. }
  117. /*
  118. * For aead encrypt and decrypt, read iv for both classes
  119. */
  120. static inline void aead_append_ld_iv(u32 *desc, int ivsize)
  121. {
  122. append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
  123. LDST_CLASS_1_CCB | ivsize);
  124. append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
  125. }
  126. /*
  127. * For ablkcipher encrypt and decrypt, read from req->src and
  128. * write to req->dst
  129. */
  130. static inline void ablkcipher_append_src_dst(u32 *desc)
  131. {
  132. append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  133. append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  134. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
  135. KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
  136. append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
  137. }
  138. /*
  139. * If all data, including src (with assoc and iv) or dst (with iv only) are
  140. * contiguous
  141. */
  142. #define GIV_SRC_CONTIG 1
  143. #define GIV_DST_CONTIG (1 << 1)
  144. /*
  145. * per-session context
  146. */
  147. struct caam_ctx {
  148. struct device *jrdev;
  149. u32 sh_desc_enc[DESC_MAX_USED_LEN];
  150. u32 sh_desc_dec[DESC_MAX_USED_LEN];
  151. u32 sh_desc_givenc[DESC_MAX_USED_LEN];
  152. dma_addr_t sh_desc_enc_dma;
  153. dma_addr_t sh_desc_dec_dma;
  154. dma_addr_t sh_desc_givenc_dma;
  155. u32 class1_alg_type;
  156. u32 class2_alg_type;
  157. u32 alg_op;
  158. u8 key[CAAM_MAX_KEY_SIZE];
  159. dma_addr_t key_dma;
  160. unsigned int enckeylen;
  161. unsigned int split_key_len;
  162. unsigned int split_key_pad_len;
  163. unsigned int authsize;
  164. };
  165. static void append_key_aead(u32 *desc, struct caam_ctx *ctx,
  166. int keys_fit_inline)
  167. {
  168. if (keys_fit_inline) {
  169. append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
  170. ctx->split_key_len, CLASS_2 |
  171. KEY_DEST_MDHA_SPLIT | KEY_ENC);
  172. append_key_as_imm(desc, (void *)ctx->key +
  173. ctx->split_key_pad_len, ctx->enckeylen,
  174. ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
  175. } else {
  176. append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
  177. KEY_DEST_MDHA_SPLIT | KEY_ENC);
  178. append_key(desc, ctx->key_dma + ctx->split_key_pad_len,
  179. ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
  180. }
  181. }
  182. static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx,
  183. int keys_fit_inline)
  184. {
  185. u32 *key_jump_cmd;
  186. init_sh_desc(desc, HDR_SHARE_SERIAL);
  187. /* Skip if already shared */
  188. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  189. JUMP_COND_SHRD);
  190. append_key_aead(desc, ctx, keys_fit_inline);
  191. set_jump_tgt_here(desc, key_jump_cmd);
  192. /* Propagate errors from shared to job descriptor */
  193. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  194. }
  195. static int aead_set_sh_desc(struct crypto_aead *aead)
  196. {
  197. struct aead_tfm *tfm = &aead->base.crt_aead;
  198. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  199. struct device *jrdev = ctx->jrdev;
  200. bool keys_fit_inline = false;
  201. u32 *key_jump_cmd, *jump_cmd;
  202. u32 geniv, moveiv;
  203. u32 *desc;
  204. if (!ctx->enckeylen || !ctx->authsize)
  205. return 0;
  206. /*
  207. * Job Descriptor and Shared Descriptors
  208. * must all fit into the 64-word Descriptor h/w Buffer
  209. */
  210. if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN +
  211. ctx->split_key_pad_len + ctx->enckeylen <=
  212. CAAM_DESC_BYTES_MAX)
  213. keys_fit_inline = true;
  214. /* aead_encrypt shared descriptor */
  215. desc = ctx->sh_desc_enc;
  216. init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
  217. /* Class 2 operation */
  218. append_operation(desc, ctx->class2_alg_type |
  219. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  220. /* cryptlen = seqoutlen - authsize */
  221. append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
  222. /* assoclen + cryptlen = seqinlen - ivsize */
  223. append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
  224. /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */
  225. append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ);
  226. /* read assoc before reading payload */
  227. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
  228. KEY_VLF);
  229. aead_append_ld_iv(desc, tfm->ivsize);
  230. /* Class 1 operation */
  231. append_operation(desc, ctx->class1_alg_type |
  232. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  233. /* Read and write cryptlen bytes */
  234. append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
  235. append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
  236. aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
  237. /* Write ICV */
  238. append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
  239. LDST_SRCDST_BYTE_CONTEXT);
  240. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  241. desc_bytes(desc),
  242. DMA_TO_DEVICE);
  243. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  244. dev_err(jrdev, "unable to map shared descriptor\n");
  245. return -ENOMEM;
  246. }
  247. #ifdef DEBUG
  248. print_hex_dump(KERN_ERR, "aead enc shdesc@"__stringify(__LINE__)": ",
  249. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  250. desc_bytes(desc), 1);
  251. #endif
  252. /*
  253. * Job Descriptor and Shared Descriptors
  254. * must all fit into the 64-word Descriptor h/w Buffer
  255. */
  256. if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN +
  257. ctx->split_key_pad_len + ctx->enckeylen <=
  258. CAAM_DESC_BYTES_MAX)
  259. keys_fit_inline = true;
  260. desc = ctx->sh_desc_dec;
  261. /* aead_decrypt shared descriptor */
  262. init_sh_desc(desc, HDR_SHARE_SERIAL);
  263. /* Skip if already shared */
  264. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  265. JUMP_COND_SHRD);
  266. append_key_aead(desc, ctx, keys_fit_inline);
  267. /* Only propagate error immediately if shared */
  268. jump_cmd = append_jump(desc, JUMP_TEST_ALL);
  269. set_jump_tgt_here(desc, key_jump_cmd);
  270. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  271. set_jump_tgt_here(desc, jump_cmd);
  272. /* Class 2 operation */
  273. append_operation(desc, ctx->class2_alg_type |
  274. OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
  275. /* assoclen + cryptlen = seqinlen - ivsize */
  276. append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
  277. ctx->authsize + tfm->ivsize)
  278. /* assoclen = (assoclen + cryptlen) - cryptlen */
  279. append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
  280. append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
  281. /* read assoc before reading payload */
  282. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
  283. KEY_VLF);
  284. aead_append_ld_iv(desc, tfm->ivsize);
  285. append_dec_op1(desc, ctx->class1_alg_type);
  286. /* Read and write cryptlen bytes */
  287. append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
  288. append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
  289. aead_append_src_dst(desc, FIFOLD_TYPE_MSG);
  290. /* Load ICV */
  291. append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
  292. FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
  293. append_dec_shr_done(desc);
  294. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  295. desc_bytes(desc),
  296. DMA_TO_DEVICE);
  297. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  298. dev_err(jrdev, "unable to map shared descriptor\n");
  299. return -ENOMEM;
  300. }
  301. #ifdef DEBUG
  302. print_hex_dump(KERN_ERR, "aead dec shdesc@"__stringify(__LINE__)": ",
  303. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  304. desc_bytes(desc), 1);
  305. #endif
  306. /*
  307. * Job Descriptor and Shared Descriptors
  308. * must all fit into the 64-word Descriptor h/w Buffer
  309. */
  310. if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN +
  311. ctx->split_key_pad_len + ctx->enckeylen <=
  312. CAAM_DESC_BYTES_MAX)
  313. keys_fit_inline = true;
  314. /* aead_givencrypt shared descriptor */
  315. desc = ctx->sh_desc_givenc;
  316. init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
  317. /* Generate IV */
  318. geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
  319. NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
  320. NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
  321. append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
  322. LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
  323. append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
  324. append_move(desc, MOVE_SRC_INFIFO |
  325. MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT));
  326. append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
  327. /* Copy IV to class 1 context */
  328. append_move(desc, MOVE_SRC_CLASS1CTX |
  329. MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT));
  330. /* Return to encryption */
  331. append_operation(desc, ctx->class2_alg_type |
  332. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  333. /* ivsize + cryptlen = seqoutlen - authsize */
  334. append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
  335. /* assoclen = seqinlen - (ivsize + cryptlen) */
  336. append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
  337. /* read assoc before reading payload */
  338. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
  339. KEY_VLF);
  340. /* Copy iv from class 1 ctx to class 2 fifo*/
  341. moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
  342. NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
  343. append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
  344. LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
  345. append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB |
  346. LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
  347. /* Class 1 operation */
  348. append_operation(desc, ctx->class1_alg_type |
  349. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  350. /* Will write ivsize + cryptlen */
  351. append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  352. /* Not need to reload iv */
  353. append_seq_fifo_load(desc, tfm->ivsize,
  354. FIFOLD_CLASS_SKIP);
  355. /* Will read cryptlen */
  356. append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  357. aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
  358. /* Write ICV */
  359. append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
  360. LDST_SRCDST_BYTE_CONTEXT);
  361. ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
  362. desc_bytes(desc),
  363. DMA_TO_DEVICE);
  364. if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
  365. dev_err(jrdev, "unable to map shared descriptor\n");
  366. return -ENOMEM;
  367. }
  368. #ifdef DEBUG
  369. print_hex_dump(KERN_ERR, "aead givenc shdesc@"__stringify(__LINE__)": ",
  370. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  371. desc_bytes(desc), 1);
  372. #endif
  373. return 0;
  374. }
  375. static int aead_setauthsize(struct crypto_aead *authenc,
  376. unsigned int authsize)
  377. {
  378. struct caam_ctx *ctx = crypto_aead_ctx(authenc);
  379. ctx->authsize = authsize;
  380. aead_set_sh_desc(authenc);
  381. return 0;
  382. }
  383. static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in,
  384. u32 authkeylen)
  385. {
  386. return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
  387. ctx->split_key_pad_len, key_in, authkeylen,
  388. ctx->alg_op);
  389. }
  390. static int aead_setkey(struct crypto_aead *aead,
  391. const u8 *key, unsigned int keylen)
  392. {
  393. /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
  394. static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
  395. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  396. struct device *jrdev = ctx->jrdev;
  397. struct rtattr *rta = (void *)key;
  398. struct crypto_authenc_key_param *param;
  399. unsigned int authkeylen;
  400. unsigned int enckeylen;
  401. int ret = 0;
  402. param = RTA_DATA(rta);
  403. enckeylen = be32_to_cpu(param->enckeylen);
  404. key += RTA_ALIGN(rta->rta_len);
  405. keylen -= RTA_ALIGN(rta->rta_len);
  406. if (keylen < enckeylen)
  407. goto badkey;
  408. authkeylen = keylen - enckeylen;
  409. if (keylen > CAAM_MAX_KEY_SIZE)
  410. goto badkey;
  411. /* Pick class 2 key length from algorithm submask */
  412. ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
  413. OP_ALG_ALGSEL_SHIFT] * 2;
  414. ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
  415. #ifdef DEBUG
  416. printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
  417. keylen, enckeylen, authkeylen);
  418. printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
  419. ctx->split_key_len, ctx->split_key_pad_len);
  420. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  421. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  422. #endif
  423. ret = gen_split_aead_key(ctx, key, authkeylen);
  424. if (ret) {
  425. goto badkey;
  426. }
  427. /* postpend encryption key to auth split key */
  428. memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen);
  429. ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
  430. enckeylen, DMA_TO_DEVICE);
  431. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  432. dev_err(jrdev, "unable to map key i/o memory\n");
  433. return -ENOMEM;
  434. }
  435. #ifdef DEBUG
  436. print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
  437. DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
  438. ctx->split_key_pad_len + enckeylen, 1);
  439. #endif
  440. ctx->enckeylen = enckeylen;
  441. ret = aead_set_sh_desc(aead);
  442. if (ret) {
  443. dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len +
  444. enckeylen, DMA_TO_DEVICE);
  445. }
  446. return ret;
  447. badkey:
  448. crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
  449. return -EINVAL;
  450. }
  451. static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
  452. const u8 *key, unsigned int keylen)
  453. {
  454. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  455. struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher;
  456. struct device *jrdev = ctx->jrdev;
  457. int ret = 0;
  458. u32 *key_jump_cmd, *jump_cmd;
  459. u32 *desc;
  460. #ifdef DEBUG
  461. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  462. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  463. #endif
  464. memcpy(ctx->key, key, keylen);
  465. ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
  466. DMA_TO_DEVICE);
  467. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  468. dev_err(jrdev, "unable to map key i/o memory\n");
  469. return -ENOMEM;
  470. }
  471. ctx->enckeylen = keylen;
  472. /* ablkcipher_encrypt shared descriptor */
  473. desc = ctx->sh_desc_enc;
  474. init_sh_desc(desc, HDR_SHARE_SERIAL);
  475. /* Skip if already shared */
  476. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  477. JUMP_COND_SHRD);
  478. /* Load class1 key only */
  479. append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
  480. ctx->enckeylen, CLASS_1 |
  481. KEY_DEST_CLASS_REG);
  482. set_jump_tgt_here(desc, key_jump_cmd);
  483. /* Propagate errors from shared to job descriptor */
  484. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  485. /* Load iv */
  486. append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
  487. LDST_CLASS_1_CCB | tfm->ivsize);
  488. /* Load operation */
  489. append_operation(desc, ctx->class1_alg_type |
  490. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  491. /* Perform operation */
  492. ablkcipher_append_src_dst(desc);
  493. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  494. desc_bytes(desc),
  495. DMA_TO_DEVICE);
  496. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  497. dev_err(jrdev, "unable to map shared descriptor\n");
  498. return -ENOMEM;
  499. }
  500. #ifdef DEBUG
  501. print_hex_dump(KERN_ERR,
  502. "ablkcipher enc shdesc@"__stringify(__LINE__)": ",
  503. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  504. desc_bytes(desc), 1);
  505. #endif
  506. /* ablkcipher_decrypt shared descriptor */
  507. desc = ctx->sh_desc_dec;
  508. init_sh_desc(desc, HDR_SHARE_SERIAL);
  509. /* Skip if already shared */
  510. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  511. JUMP_COND_SHRD);
  512. /* Load class1 key only */
  513. append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
  514. ctx->enckeylen, CLASS_1 |
  515. KEY_DEST_CLASS_REG);
  516. /* For aead, only propagate error immediately if shared */
  517. jump_cmd = append_jump(desc, JUMP_TEST_ALL);
  518. set_jump_tgt_here(desc, key_jump_cmd);
  519. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  520. set_jump_tgt_here(desc, jump_cmd);
  521. /* load IV */
  522. append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
  523. LDST_CLASS_1_CCB | tfm->ivsize);
  524. /* Choose operation */
  525. append_dec_op1(desc, ctx->class1_alg_type);
  526. /* Perform operation */
  527. ablkcipher_append_src_dst(desc);
  528. /* Wait for key to load before allowing propagating error */
  529. append_dec_shr_done(desc);
  530. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  531. desc_bytes(desc),
  532. DMA_TO_DEVICE);
  533. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  534. dev_err(jrdev, "unable to map shared descriptor\n");
  535. return -ENOMEM;
  536. }
  537. #ifdef DEBUG
  538. print_hex_dump(KERN_ERR,
  539. "ablkcipher dec shdesc@"__stringify(__LINE__)": ",
  540. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  541. desc_bytes(desc), 1);
  542. #endif
  543. return ret;
  544. }
  545. /*
  546. * aead_edesc - s/w-extended aead descriptor
  547. * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
  548. * @assoc_chained: if source is chained
  549. * @src_nents: number of segments in input scatterlist
  550. * @src_chained: if source is chained
  551. * @dst_nents: number of segments in output scatterlist
  552. * @dst_chained: if destination is chained
  553. * @iv_dma: dma address of iv for checking continuity and link table
  554. * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
  555. * @sec4_sg_bytes: length of dma mapped sec4_sg space
  556. * @sec4_sg_dma: bus physical mapped address of h/w link table
  557. * @hw_desc: the h/w job descriptor followed by any referenced link tables
  558. */
  559. struct aead_edesc {
  560. int assoc_nents;
  561. bool assoc_chained;
  562. int src_nents;
  563. bool src_chained;
  564. int dst_nents;
  565. bool dst_chained;
  566. dma_addr_t iv_dma;
  567. int sec4_sg_bytes;
  568. dma_addr_t sec4_sg_dma;
  569. struct sec4_sg_entry *sec4_sg;
  570. u32 hw_desc[0];
  571. };
  572. /*
  573. * ablkcipher_edesc - s/w-extended ablkcipher descriptor
  574. * @src_nents: number of segments in input scatterlist
  575. * @src_chained: if source is chained
  576. * @dst_nents: number of segments in output scatterlist
  577. * @dst_chained: if destination is chained
  578. * @iv_dma: dma address of iv for checking continuity and link table
  579. * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
  580. * @sec4_sg_bytes: length of dma mapped sec4_sg space
  581. * @sec4_sg_dma: bus physical mapped address of h/w link table
  582. * @hw_desc: the h/w job descriptor followed by any referenced link tables
  583. */
  584. struct ablkcipher_edesc {
  585. int src_nents;
  586. bool src_chained;
  587. int dst_nents;
  588. bool dst_chained;
  589. dma_addr_t iv_dma;
  590. int sec4_sg_bytes;
  591. dma_addr_t sec4_sg_dma;
  592. struct sec4_sg_entry *sec4_sg;
  593. u32 hw_desc[0];
  594. };
  595. static void caam_unmap(struct device *dev, struct scatterlist *src,
  596. struct scatterlist *dst, int src_nents,
  597. bool src_chained, int dst_nents, bool dst_chained,
  598. dma_addr_t iv_dma, int ivsize, dma_addr_t sec4_sg_dma,
  599. int sec4_sg_bytes)
  600. {
  601. if (dst != src) {
  602. dma_unmap_sg_chained(dev, src, src_nents ? : 1, DMA_TO_DEVICE,
  603. src_chained);
  604. dma_unmap_sg_chained(dev, dst, dst_nents ? : 1, DMA_FROM_DEVICE,
  605. dst_chained);
  606. } else {
  607. dma_unmap_sg_chained(dev, src, src_nents ? : 1,
  608. DMA_BIDIRECTIONAL, src_chained);
  609. }
  610. if (iv_dma)
  611. dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
  612. if (sec4_sg_bytes)
  613. dma_unmap_single(dev, sec4_sg_dma, sec4_sg_bytes,
  614. DMA_TO_DEVICE);
  615. }
  616. static void aead_unmap(struct device *dev,
  617. struct aead_edesc *edesc,
  618. struct aead_request *req)
  619. {
  620. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  621. int ivsize = crypto_aead_ivsize(aead);
  622. dma_unmap_sg_chained(dev, req->assoc, edesc->assoc_nents,
  623. DMA_TO_DEVICE, edesc->assoc_chained);
  624. caam_unmap(dev, req->src, req->dst,
  625. edesc->src_nents, edesc->src_chained, edesc->dst_nents,
  626. edesc->dst_chained, edesc->iv_dma, ivsize,
  627. edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
  628. }
  629. static void ablkcipher_unmap(struct device *dev,
  630. struct ablkcipher_edesc *edesc,
  631. struct ablkcipher_request *req)
  632. {
  633. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  634. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  635. caam_unmap(dev, req->src, req->dst,
  636. edesc->src_nents, edesc->src_chained, edesc->dst_nents,
  637. edesc->dst_chained, edesc->iv_dma, ivsize,
  638. edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
  639. }
  640. static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
  641. void *context)
  642. {
  643. struct aead_request *req = context;
  644. struct aead_edesc *edesc;
  645. #ifdef DEBUG
  646. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  647. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  648. int ivsize = crypto_aead_ivsize(aead);
  649. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  650. #endif
  651. edesc = (struct aead_edesc *)((char *)desc -
  652. offsetof(struct aead_edesc, hw_desc));
  653. if (err) {
  654. char tmp[CAAM_ERROR_STR_MAX];
  655. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  656. }
  657. aead_unmap(jrdev, edesc, req);
  658. #ifdef DEBUG
  659. print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
  660. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
  661. req->assoclen , 1);
  662. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  663. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize,
  664. edesc->src_nents ? 100 : ivsize, 1);
  665. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  666. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  667. edesc->src_nents ? 100 : req->cryptlen +
  668. ctx->authsize + 4, 1);
  669. #endif
  670. kfree(edesc);
  671. aead_request_complete(req, err);
  672. }
  673. static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
  674. void *context)
  675. {
  676. struct aead_request *req = context;
  677. struct aead_edesc *edesc;
  678. #ifdef DEBUG
  679. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  680. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  681. int ivsize = crypto_aead_ivsize(aead);
  682. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  683. #endif
  684. edesc = (struct aead_edesc *)((char *)desc -
  685. offsetof(struct aead_edesc, hw_desc));
  686. #ifdef DEBUG
  687. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  688. DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
  689. ivsize, 1);
  690. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  691. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst),
  692. req->cryptlen, 1);
  693. #endif
  694. if (err) {
  695. char tmp[CAAM_ERROR_STR_MAX];
  696. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  697. }
  698. aead_unmap(jrdev, edesc, req);
  699. /*
  700. * verify hw auth check passed else return -EBADMSG
  701. */
  702. if ((err & JRSTA_CCBERR_ERRID_MASK) == JRSTA_CCBERR_ERRID_ICVCHK)
  703. err = -EBADMSG;
  704. #ifdef DEBUG
  705. print_hex_dump(KERN_ERR, "iphdrout@"__stringify(__LINE__)": ",
  706. DUMP_PREFIX_ADDRESS, 16, 4,
  707. ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)),
  708. sizeof(struct iphdr) + req->assoclen +
  709. ((req->cryptlen > 1500) ? 1500 : req->cryptlen) +
  710. ctx->authsize + 36, 1);
  711. if (!err && edesc->sec4_sg_bytes) {
  712. struct scatterlist *sg = sg_last(req->src, edesc->src_nents);
  713. print_hex_dump(KERN_ERR, "sglastout@"__stringify(__LINE__)": ",
  714. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg),
  715. sg->length + ctx->authsize + 16, 1);
  716. }
  717. #endif
  718. kfree(edesc);
  719. aead_request_complete(req, err);
  720. }
  721. static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
  722. void *context)
  723. {
  724. struct ablkcipher_request *req = context;
  725. struct ablkcipher_edesc *edesc;
  726. #ifdef DEBUG
  727. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  728. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  729. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  730. #endif
  731. edesc = (struct ablkcipher_edesc *)((char *)desc -
  732. offsetof(struct ablkcipher_edesc, hw_desc));
  733. if (err) {
  734. char tmp[CAAM_ERROR_STR_MAX];
  735. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  736. }
  737. #ifdef DEBUG
  738. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  739. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  740. edesc->src_nents > 1 ? 100 : ivsize, 1);
  741. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  742. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  743. edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
  744. #endif
  745. ablkcipher_unmap(jrdev, edesc, req);
  746. kfree(edesc);
  747. ablkcipher_request_complete(req, err);
  748. }
  749. static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
  750. void *context)
  751. {
  752. struct ablkcipher_request *req = context;
  753. struct ablkcipher_edesc *edesc;
  754. #ifdef DEBUG
  755. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  756. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  757. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  758. #endif
  759. edesc = (struct ablkcipher_edesc *)((char *)desc -
  760. offsetof(struct ablkcipher_edesc, hw_desc));
  761. if (err) {
  762. char tmp[CAAM_ERROR_STR_MAX];
  763. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  764. }
  765. #ifdef DEBUG
  766. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  767. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  768. ivsize, 1);
  769. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  770. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  771. edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
  772. #endif
  773. ablkcipher_unmap(jrdev, edesc, req);
  774. kfree(edesc);
  775. ablkcipher_request_complete(req, err);
  776. }
  777. /*
  778. * Fill in aead job descriptor
  779. */
  780. static void init_aead_job(u32 *sh_desc, dma_addr_t ptr,
  781. struct aead_edesc *edesc,
  782. struct aead_request *req,
  783. bool all_contig, bool encrypt)
  784. {
  785. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  786. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  787. int ivsize = crypto_aead_ivsize(aead);
  788. int authsize = ctx->authsize;
  789. u32 *desc = edesc->hw_desc;
  790. u32 out_options = 0, in_options;
  791. dma_addr_t dst_dma, src_dma;
  792. int len, sec4_sg_index = 0;
  793. #ifdef DEBUG
  794. debug("assoclen %d cryptlen %d authsize %d\n",
  795. req->assoclen, req->cryptlen, authsize);
  796. print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
  797. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
  798. req->assoclen , 1);
  799. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  800. DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
  801. edesc->src_nents ? 100 : ivsize, 1);
  802. print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
  803. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  804. edesc->src_nents ? 100 : req->cryptlen, 1);
  805. print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ",
  806. DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
  807. desc_bytes(sh_desc), 1);
  808. #endif
  809. len = desc_len(sh_desc);
  810. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  811. if (all_contig) {
  812. src_dma = sg_dma_address(req->assoc);
  813. in_options = 0;
  814. } else {
  815. src_dma = edesc->sec4_sg_dma;
  816. sec4_sg_index += (edesc->assoc_nents ? : 1) + 1 +
  817. (edesc->src_nents ? : 1);
  818. in_options = LDST_SGF;
  819. }
  820. if (encrypt)
  821. append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
  822. req->cryptlen - authsize, in_options);
  823. else
  824. append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
  825. req->cryptlen, in_options);
  826. if (likely(req->src == req->dst)) {
  827. if (all_contig) {
  828. dst_dma = sg_dma_address(req->src);
  829. } else {
  830. dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
  831. ((edesc->assoc_nents ? : 1) + 1);
  832. out_options = LDST_SGF;
  833. }
  834. } else {
  835. if (!edesc->dst_nents) {
  836. dst_dma = sg_dma_address(req->dst);
  837. } else {
  838. dst_dma = edesc->sec4_sg_dma +
  839. sec4_sg_index *
  840. sizeof(struct sec4_sg_entry);
  841. out_options = LDST_SGF;
  842. }
  843. }
  844. if (encrypt)
  845. append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options);
  846. else
  847. append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize,
  848. out_options);
  849. }
  850. /*
  851. * Fill in aead givencrypt job descriptor
  852. */
  853. static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr,
  854. struct aead_edesc *edesc,
  855. struct aead_request *req,
  856. int contig)
  857. {
  858. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  859. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  860. int ivsize = crypto_aead_ivsize(aead);
  861. int authsize = ctx->authsize;
  862. u32 *desc = edesc->hw_desc;
  863. u32 out_options = 0, in_options;
  864. dma_addr_t dst_dma, src_dma;
  865. int len, sec4_sg_index = 0;
  866. #ifdef DEBUG
  867. debug("assoclen %d cryptlen %d authsize %d\n",
  868. req->assoclen, req->cryptlen, authsize);
  869. print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
  870. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
  871. req->assoclen , 1);
  872. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  873. DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
  874. print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
  875. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  876. edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
  877. print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ",
  878. DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
  879. desc_bytes(sh_desc), 1);
  880. #endif
  881. len = desc_len(sh_desc);
  882. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  883. if (contig & GIV_SRC_CONTIG) {
  884. src_dma = sg_dma_address(req->assoc);
  885. in_options = 0;
  886. } else {
  887. src_dma = edesc->sec4_sg_dma;
  888. sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents;
  889. in_options = LDST_SGF;
  890. }
  891. append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
  892. req->cryptlen - authsize, in_options);
  893. if (contig & GIV_DST_CONTIG) {
  894. dst_dma = edesc->iv_dma;
  895. } else {
  896. if (likely(req->src == req->dst)) {
  897. dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
  898. edesc->assoc_nents;
  899. out_options = LDST_SGF;
  900. } else {
  901. dst_dma = edesc->sec4_sg_dma +
  902. sec4_sg_index *
  903. sizeof(struct sec4_sg_entry);
  904. out_options = LDST_SGF;
  905. }
  906. }
  907. append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options);
  908. }
  909. /*
  910. * Fill in ablkcipher job descriptor
  911. */
  912. static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr,
  913. struct ablkcipher_edesc *edesc,
  914. struct ablkcipher_request *req,
  915. bool iv_contig)
  916. {
  917. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  918. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  919. u32 *desc = edesc->hw_desc;
  920. u32 out_options = 0, in_options;
  921. dma_addr_t dst_dma, src_dma;
  922. int len, sec4_sg_index = 0;
  923. #ifdef DEBUG
  924. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  925. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  926. ivsize, 1);
  927. print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
  928. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  929. edesc->src_nents ? 100 : req->nbytes, 1);
  930. #endif
  931. len = desc_len(sh_desc);
  932. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  933. if (iv_contig) {
  934. src_dma = edesc->iv_dma;
  935. in_options = 0;
  936. } else {
  937. src_dma = edesc->sec4_sg_dma;
  938. sec4_sg_index += (iv_contig ? 0 : 1) + edesc->src_nents;
  939. in_options = LDST_SGF;
  940. }
  941. append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
  942. if (likely(req->src == req->dst)) {
  943. if (!edesc->src_nents && iv_contig) {
  944. dst_dma = sg_dma_address(req->src);
  945. } else {
  946. dst_dma = edesc->sec4_sg_dma +
  947. sizeof(struct sec4_sg_entry);
  948. out_options = LDST_SGF;
  949. }
  950. } else {
  951. if (!edesc->dst_nents) {
  952. dst_dma = sg_dma_address(req->dst);
  953. } else {
  954. dst_dma = edesc->sec4_sg_dma +
  955. sec4_sg_index * sizeof(struct sec4_sg_entry);
  956. out_options = LDST_SGF;
  957. }
  958. }
  959. append_seq_out_ptr(desc, dst_dma, req->nbytes, out_options);
  960. }
  961. /*
  962. * allocate and map the aead extended descriptor
  963. */
  964. static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
  965. int desc_bytes, bool *all_contig_ptr)
  966. {
  967. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  968. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  969. struct device *jrdev = ctx->jrdev;
  970. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  971. CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
  972. int assoc_nents, src_nents, dst_nents = 0;
  973. struct aead_edesc *edesc;
  974. dma_addr_t iv_dma = 0;
  975. int sgc;
  976. bool all_contig = true;
  977. bool assoc_chained = false, src_chained = false, dst_chained = false;
  978. int ivsize = crypto_aead_ivsize(aead);
  979. int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
  980. assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
  981. src_nents = sg_count(req->src, req->cryptlen, &src_chained);
  982. if (unlikely(req->dst != req->src))
  983. dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
  984. sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
  985. DMA_TO_DEVICE, assoc_chained);
  986. if (likely(req->src == req->dst)) {
  987. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  988. DMA_BIDIRECTIONAL, src_chained);
  989. } else {
  990. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  991. DMA_TO_DEVICE, src_chained);
  992. sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
  993. DMA_FROM_DEVICE, dst_chained);
  994. }
  995. /* Check if data are contiguous */
  996. iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
  997. if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
  998. iv_dma || src_nents || iv_dma + ivsize !=
  999. sg_dma_address(req->src)) {
  1000. all_contig = false;
  1001. assoc_nents = assoc_nents ? : 1;
  1002. src_nents = src_nents ? : 1;
  1003. sec4_sg_len = assoc_nents + 1 + src_nents;
  1004. }
  1005. sec4_sg_len += dst_nents;
  1006. sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
  1007. /* allocate space for base edesc and hw desc commands, link tables */
  1008. edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
  1009. sec4_sg_bytes, GFP_DMA | flags);
  1010. if (!edesc) {
  1011. dev_err(jrdev, "could not allocate extended descriptor\n");
  1012. return ERR_PTR(-ENOMEM);
  1013. }
  1014. edesc->assoc_nents = assoc_nents;
  1015. edesc->assoc_chained = assoc_chained;
  1016. edesc->src_nents = src_nents;
  1017. edesc->src_chained = src_chained;
  1018. edesc->dst_nents = dst_nents;
  1019. edesc->dst_chained = dst_chained;
  1020. edesc->iv_dma = iv_dma;
  1021. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1022. edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
  1023. desc_bytes;
  1024. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1025. sec4_sg_bytes, DMA_TO_DEVICE);
  1026. *all_contig_ptr = all_contig;
  1027. sec4_sg_index = 0;
  1028. if (!all_contig) {
  1029. sg_to_sec4_sg(req->assoc,
  1030. (assoc_nents ? : 1),
  1031. edesc->sec4_sg +
  1032. sec4_sg_index, 0);
  1033. sec4_sg_index += assoc_nents ? : 1;
  1034. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1035. iv_dma, ivsize, 0);
  1036. sec4_sg_index += 1;
  1037. sg_to_sec4_sg_last(req->src,
  1038. (src_nents ? : 1),
  1039. edesc->sec4_sg +
  1040. sec4_sg_index, 0);
  1041. sec4_sg_index += src_nents ? : 1;
  1042. }
  1043. if (dst_nents) {
  1044. sg_to_sec4_sg_last(req->dst, dst_nents,
  1045. edesc->sec4_sg + sec4_sg_index, 0);
  1046. }
  1047. return edesc;
  1048. }
  1049. static int aead_encrypt(struct aead_request *req)
  1050. {
  1051. struct aead_edesc *edesc;
  1052. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1053. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1054. struct device *jrdev = ctx->jrdev;
  1055. bool all_contig;
  1056. u32 *desc;
  1057. int ret = 0;
  1058. req->cryptlen += ctx->authsize;
  1059. /* allocate extended descriptor */
  1060. edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
  1061. CAAM_CMD_SZ, &all_contig);
  1062. if (IS_ERR(edesc))
  1063. return PTR_ERR(edesc);
  1064. /* Create and submit job descriptor */
  1065. init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req,
  1066. all_contig, true);
  1067. #ifdef DEBUG
  1068. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1069. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1070. desc_bytes(edesc->hw_desc), 1);
  1071. #endif
  1072. desc = edesc->hw_desc;
  1073. ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
  1074. if (!ret) {
  1075. ret = -EINPROGRESS;
  1076. } else {
  1077. aead_unmap(jrdev, edesc, req);
  1078. kfree(edesc);
  1079. }
  1080. return ret;
  1081. }
  1082. static int aead_decrypt(struct aead_request *req)
  1083. {
  1084. struct aead_edesc *edesc;
  1085. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1086. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1087. struct device *jrdev = ctx->jrdev;
  1088. bool all_contig;
  1089. u32 *desc;
  1090. int ret = 0;
  1091. /* allocate extended descriptor */
  1092. edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
  1093. CAAM_CMD_SZ, &all_contig);
  1094. if (IS_ERR(edesc))
  1095. return PTR_ERR(edesc);
  1096. #ifdef DEBUG
  1097. print_hex_dump(KERN_ERR, "dec src@"__stringify(__LINE__)": ",
  1098. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  1099. req->cryptlen, 1);
  1100. #endif
  1101. /* Create and submit job descriptor*/
  1102. init_aead_job(ctx->sh_desc_dec,
  1103. ctx->sh_desc_dec_dma, edesc, req, all_contig, false);
  1104. #ifdef DEBUG
  1105. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1106. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1107. desc_bytes(edesc->hw_desc), 1);
  1108. #endif
  1109. desc = edesc->hw_desc;
  1110. ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
  1111. if (!ret) {
  1112. ret = -EINPROGRESS;
  1113. } else {
  1114. aead_unmap(jrdev, edesc, req);
  1115. kfree(edesc);
  1116. }
  1117. return ret;
  1118. }
  1119. /*
  1120. * allocate and map the aead extended descriptor for aead givencrypt
  1121. */
  1122. static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
  1123. *greq, int desc_bytes,
  1124. u32 *contig_ptr)
  1125. {
  1126. struct aead_request *req = &greq->areq;
  1127. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1128. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1129. struct device *jrdev = ctx->jrdev;
  1130. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1131. CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
  1132. int assoc_nents, src_nents, dst_nents = 0;
  1133. struct aead_edesc *edesc;
  1134. dma_addr_t iv_dma = 0;
  1135. int sgc;
  1136. u32 contig = GIV_SRC_CONTIG | GIV_DST_CONTIG;
  1137. int ivsize = crypto_aead_ivsize(aead);
  1138. bool assoc_chained = false, src_chained = false, dst_chained = false;
  1139. int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
  1140. assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
  1141. src_nents = sg_count(req->src, req->cryptlen, &src_chained);
  1142. if (unlikely(req->dst != req->src))
  1143. dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
  1144. sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
  1145. DMA_TO_DEVICE, assoc_chained);
  1146. if (likely(req->src == req->dst)) {
  1147. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1148. DMA_BIDIRECTIONAL, src_chained);
  1149. } else {
  1150. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1151. DMA_TO_DEVICE, src_chained);
  1152. sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
  1153. DMA_FROM_DEVICE, dst_chained);
  1154. }
  1155. /* Check if data are contiguous */
  1156. iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
  1157. if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
  1158. iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src))
  1159. contig &= ~GIV_SRC_CONTIG;
  1160. if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst))
  1161. contig &= ~GIV_DST_CONTIG;
  1162. if (unlikely(req->src != req->dst)) {
  1163. dst_nents = dst_nents ? : 1;
  1164. sec4_sg_len += 1;
  1165. }
  1166. if (!(contig & GIV_SRC_CONTIG)) {
  1167. assoc_nents = assoc_nents ? : 1;
  1168. src_nents = src_nents ? : 1;
  1169. sec4_sg_len += assoc_nents + 1 + src_nents;
  1170. if (likely(req->src == req->dst))
  1171. contig &= ~GIV_DST_CONTIG;
  1172. }
  1173. sec4_sg_len += dst_nents;
  1174. sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
  1175. /* allocate space for base edesc and hw desc commands, link tables */
  1176. edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
  1177. sec4_sg_bytes, GFP_DMA | flags);
  1178. if (!edesc) {
  1179. dev_err(jrdev, "could not allocate extended descriptor\n");
  1180. return ERR_PTR(-ENOMEM);
  1181. }
  1182. edesc->assoc_nents = assoc_nents;
  1183. edesc->assoc_chained = assoc_chained;
  1184. edesc->src_nents = src_nents;
  1185. edesc->src_chained = src_chained;
  1186. edesc->dst_nents = dst_nents;
  1187. edesc->dst_chained = dst_chained;
  1188. edesc->iv_dma = iv_dma;
  1189. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1190. edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
  1191. desc_bytes;
  1192. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1193. sec4_sg_bytes, DMA_TO_DEVICE);
  1194. *contig_ptr = contig;
  1195. sec4_sg_index = 0;
  1196. if (!(contig & GIV_SRC_CONTIG)) {
  1197. sg_to_sec4_sg(req->assoc, assoc_nents,
  1198. edesc->sec4_sg +
  1199. sec4_sg_index, 0);
  1200. sec4_sg_index += assoc_nents;
  1201. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1202. iv_dma, ivsize, 0);
  1203. sec4_sg_index += 1;
  1204. sg_to_sec4_sg_last(req->src, src_nents,
  1205. edesc->sec4_sg +
  1206. sec4_sg_index, 0);
  1207. sec4_sg_index += src_nents;
  1208. }
  1209. if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) {
  1210. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1211. iv_dma, ivsize, 0);
  1212. sec4_sg_index += 1;
  1213. sg_to_sec4_sg_last(req->dst, dst_nents,
  1214. edesc->sec4_sg + sec4_sg_index, 0);
  1215. }
  1216. return edesc;
  1217. }
  1218. static int aead_givencrypt(struct aead_givcrypt_request *areq)
  1219. {
  1220. struct aead_request *req = &areq->areq;
  1221. struct aead_edesc *edesc;
  1222. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1223. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1224. struct device *jrdev = ctx->jrdev;
  1225. u32 contig;
  1226. u32 *desc;
  1227. int ret = 0;
  1228. req->cryptlen += ctx->authsize;
  1229. /* allocate extended descriptor */
  1230. edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN *
  1231. CAAM_CMD_SZ, &contig);
  1232. if (IS_ERR(edesc))
  1233. return PTR_ERR(edesc);
  1234. #ifdef DEBUG
  1235. print_hex_dump(KERN_ERR, "giv src@"__stringify(__LINE__)": ",
  1236. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  1237. req->cryptlen, 1);
  1238. #endif
  1239. /* Create and submit job descriptor*/
  1240. init_aead_giv_job(ctx->sh_desc_givenc,
  1241. ctx->sh_desc_givenc_dma, edesc, req, contig);
  1242. #ifdef DEBUG
  1243. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1244. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1245. desc_bytes(edesc->hw_desc), 1);
  1246. #endif
  1247. desc = edesc->hw_desc;
  1248. ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
  1249. if (!ret) {
  1250. ret = -EINPROGRESS;
  1251. } else {
  1252. aead_unmap(jrdev, edesc, req);
  1253. kfree(edesc);
  1254. }
  1255. return ret;
  1256. }
  1257. /*
  1258. * allocate and map the ablkcipher extended descriptor for ablkcipher
  1259. */
  1260. static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
  1261. *req, int desc_bytes,
  1262. bool *iv_contig_out)
  1263. {
  1264. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1265. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1266. struct device *jrdev = ctx->jrdev;
  1267. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1268. CRYPTO_TFM_REQ_MAY_SLEEP)) ?
  1269. GFP_KERNEL : GFP_ATOMIC;
  1270. int src_nents, dst_nents = 0, sec4_sg_bytes;
  1271. struct ablkcipher_edesc *edesc;
  1272. dma_addr_t iv_dma = 0;
  1273. bool iv_contig = false;
  1274. int sgc;
  1275. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  1276. bool src_chained = false, dst_chained = false;
  1277. int sec4_sg_index;
  1278. src_nents = sg_count(req->src, req->nbytes, &src_chained);
  1279. if (req->dst != req->src)
  1280. dst_nents = sg_count(req->dst, req->nbytes, &dst_chained);
  1281. if (likely(req->src == req->dst)) {
  1282. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1283. DMA_BIDIRECTIONAL, src_chained);
  1284. } else {
  1285. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1286. DMA_TO_DEVICE, src_chained);
  1287. sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
  1288. DMA_FROM_DEVICE, dst_chained);
  1289. }
  1290. /*
  1291. * Check if iv can be contiguous with source and destination.
  1292. * If so, include it. If not, create scatterlist.
  1293. */
  1294. iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
  1295. if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
  1296. iv_contig = true;
  1297. else
  1298. src_nents = src_nents ? : 1;
  1299. sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
  1300. sizeof(struct sec4_sg_entry);
  1301. /* allocate space for base edesc and hw desc commands, link tables */
  1302. edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
  1303. sec4_sg_bytes, GFP_DMA | flags);
  1304. if (!edesc) {
  1305. dev_err(jrdev, "could not allocate extended descriptor\n");
  1306. return ERR_PTR(-ENOMEM);
  1307. }
  1308. edesc->src_nents = src_nents;
  1309. edesc->src_chained = src_chained;
  1310. edesc->dst_nents = dst_nents;
  1311. edesc->dst_chained = dst_chained;
  1312. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1313. edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
  1314. desc_bytes;
  1315. sec4_sg_index = 0;
  1316. if (!iv_contig) {
  1317. dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
  1318. sg_to_sec4_sg_last(req->src, src_nents,
  1319. edesc->sec4_sg + 1, 0);
  1320. sec4_sg_index += 1 + src_nents;
  1321. }
  1322. if (dst_nents) {
  1323. sg_to_sec4_sg_last(req->dst, dst_nents,
  1324. edesc->sec4_sg + sec4_sg_index, 0);
  1325. }
  1326. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1327. sec4_sg_bytes, DMA_TO_DEVICE);
  1328. edesc->iv_dma = iv_dma;
  1329. #ifdef DEBUG
  1330. print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"__stringify(__LINE__)": ",
  1331. DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
  1332. sec4_sg_bytes, 1);
  1333. #endif
  1334. *iv_contig_out = iv_contig;
  1335. return edesc;
  1336. }
  1337. static int ablkcipher_encrypt(struct ablkcipher_request *req)
  1338. {
  1339. struct ablkcipher_edesc *edesc;
  1340. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1341. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1342. struct device *jrdev = ctx->jrdev;
  1343. bool iv_contig;
  1344. u32 *desc;
  1345. int ret = 0;
  1346. /* allocate extended descriptor */
  1347. edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
  1348. CAAM_CMD_SZ, &iv_contig);
  1349. if (IS_ERR(edesc))
  1350. return PTR_ERR(edesc);
  1351. /* Create and submit job descriptor*/
  1352. init_ablkcipher_job(ctx->sh_desc_enc,
  1353. ctx->sh_desc_enc_dma, edesc, req, iv_contig);
  1354. #ifdef DEBUG
  1355. print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
  1356. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1357. desc_bytes(edesc->hw_desc), 1);
  1358. #endif
  1359. desc = edesc->hw_desc;
  1360. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
  1361. if (!ret) {
  1362. ret = -EINPROGRESS;
  1363. } else {
  1364. ablkcipher_unmap(jrdev, edesc, req);
  1365. kfree(edesc);
  1366. }
  1367. return ret;
  1368. }
  1369. static int ablkcipher_decrypt(struct ablkcipher_request *req)
  1370. {
  1371. struct ablkcipher_edesc *edesc;
  1372. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1373. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1374. struct device *jrdev = ctx->jrdev;
  1375. bool iv_contig;
  1376. u32 *desc;
  1377. int ret = 0;
  1378. /* allocate extended descriptor */
  1379. edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
  1380. CAAM_CMD_SZ, &iv_contig);
  1381. if (IS_ERR(edesc))
  1382. return PTR_ERR(edesc);
  1383. /* Create and submit job descriptor*/
  1384. init_ablkcipher_job(ctx->sh_desc_dec,
  1385. ctx->sh_desc_dec_dma, edesc, req, iv_contig);
  1386. desc = edesc->hw_desc;
  1387. #ifdef DEBUG
  1388. print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
  1389. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1390. desc_bytes(edesc->hw_desc), 1);
  1391. #endif
  1392. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_decrypt_done, req);
  1393. if (!ret) {
  1394. ret = -EINPROGRESS;
  1395. } else {
  1396. ablkcipher_unmap(jrdev, edesc, req);
  1397. kfree(edesc);
  1398. }
  1399. return ret;
  1400. }
  1401. #define template_aead template_u.aead
  1402. #define template_ablkcipher template_u.ablkcipher
  1403. struct caam_alg_template {
  1404. char name[CRYPTO_MAX_ALG_NAME];
  1405. char driver_name[CRYPTO_MAX_ALG_NAME];
  1406. unsigned int blocksize;
  1407. u32 type;
  1408. union {
  1409. struct ablkcipher_alg ablkcipher;
  1410. struct aead_alg aead;
  1411. struct blkcipher_alg blkcipher;
  1412. struct cipher_alg cipher;
  1413. struct compress_alg compress;
  1414. struct rng_alg rng;
  1415. } template_u;
  1416. u32 class1_alg_type;
  1417. u32 class2_alg_type;
  1418. u32 alg_op;
  1419. };
  1420. static struct caam_alg_template driver_algs[] = {
  1421. /* single-pass ipsec_esp descriptor */
  1422. {
  1423. .name = "authenc(hmac(md5),cbc(aes))",
  1424. .driver_name = "authenc-hmac-md5-cbc-aes-caam",
  1425. .blocksize = AES_BLOCK_SIZE,
  1426. .type = CRYPTO_ALG_TYPE_AEAD,
  1427. .template_aead = {
  1428. .setkey = aead_setkey,
  1429. .setauthsize = aead_setauthsize,
  1430. .encrypt = aead_encrypt,
  1431. .decrypt = aead_decrypt,
  1432. .givencrypt = aead_givencrypt,
  1433. .geniv = "<built-in>",
  1434. .ivsize = AES_BLOCK_SIZE,
  1435. .maxauthsize = MD5_DIGEST_SIZE,
  1436. },
  1437. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1438. .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
  1439. .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
  1440. },
  1441. {
  1442. .name = "authenc(hmac(sha1),cbc(aes))",
  1443. .driver_name = "authenc-hmac-sha1-cbc-aes-caam",
  1444. .blocksize = AES_BLOCK_SIZE,
  1445. .type = CRYPTO_ALG_TYPE_AEAD,
  1446. .template_aead = {
  1447. .setkey = aead_setkey,
  1448. .setauthsize = aead_setauthsize,
  1449. .encrypt = aead_encrypt,
  1450. .decrypt = aead_decrypt,
  1451. .givencrypt = aead_givencrypt,
  1452. .geniv = "<built-in>",
  1453. .ivsize = AES_BLOCK_SIZE,
  1454. .maxauthsize = SHA1_DIGEST_SIZE,
  1455. },
  1456. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1457. .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
  1458. .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
  1459. },
  1460. {
  1461. .name = "authenc(hmac(sha224),cbc(aes))",
  1462. .driver_name = "authenc-hmac-sha224-cbc-aes-caam",
  1463. .blocksize = AES_BLOCK_SIZE,
  1464. .type = CRYPTO_ALG_TYPE_AEAD,
  1465. .template_aead = {
  1466. .setkey = aead_setkey,
  1467. .setauthsize = aead_setauthsize,
  1468. .encrypt = aead_encrypt,
  1469. .decrypt = aead_decrypt,
  1470. .givencrypt = aead_givencrypt,
  1471. .geniv = "<built-in>",
  1472. .ivsize = AES_BLOCK_SIZE,
  1473. .maxauthsize = SHA224_DIGEST_SIZE,
  1474. },
  1475. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1476. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1477. OP_ALG_AAI_HMAC_PRECOMP,
  1478. .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
  1479. },
  1480. {
  1481. .name = "authenc(hmac(sha256),cbc(aes))",
  1482. .driver_name = "authenc-hmac-sha256-cbc-aes-caam",
  1483. .blocksize = AES_BLOCK_SIZE,
  1484. .type = CRYPTO_ALG_TYPE_AEAD,
  1485. .template_aead = {
  1486. .setkey = aead_setkey,
  1487. .setauthsize = aead_setauthsize,
  1488. .encrypt = aead_encrypt,
  1489. .decrypt = aead_decrypt,
  1490. .givencrypt = aead_givencrypt,
  1491. .geniv = "<built-in>",
  1492. .ivsize = AES_BLOCK_SIZE,
  1493. .maxauthsize = SHA256_DIGEST_SIZE,
  1494. },
  1495. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1496. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1497. OP_ALG_AAI_HMAC_PRECOMP,
  1498. .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
  1499. },
  1500. {
  1501. .name = "authenc(hmac(sha384),cbc(aes))",
  1502. .driver_name = "authenc-hmac-sha384-cbc-aes-caam",
  1503. .blocksize = AES_BLOCK_SIZE,
  1504. .type = CRYPTO_ALG_TYPE_AEAD,
  1505. .template_aead = {
  1506. .setkey = aead_setkey,
  1507. .setauthsize = aead_setauthsize,
  1508. .encrypt = aead_encrypt,
  1509. .decrypt = aead_decrypt,
  1510. .givencrypt = aead_givencrypt,
  1511. .geniv = "<built-in>",
  1512. .ivsize = AES_BLOCK_SIZE,
  1513. .maxauthsize = SHA384_DIGEST_SIZE,
  1514. },
  1515. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1516. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1517. OP_ALG_AAI_HMAC_PRECOMP,
  1518. .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
  1519. },
  1520. {
  1521. .name = "authenc(hmac(sha512),cbc(aes))",
  1522. .driver_name = "authenc-hmac-sha512-cbc-aes-caam",
  1523. .blocksize = AES_BLOCK_SIZE,
  1524. .type = CRYPTO_ALG_TYPE_AEAD,
  1525. .template_aead = {
  1526. .setkey = aead_setkey,
  1527. .setauthsize = aead_setauthsize,
  1528. .encrypt = aead_encrypt,
  1529. .decrypt = aead_decrypt,
  1530. .givencrypt = aead_givencrypt,
  1531. .geniv = "<built-in>",
  1532. .ivsize = AES_BLOCK_SIZE,
  1533. .maxauthsize = SHA512_DIGEST_SIZE,
  1534. },
  1535. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1536. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1537. OP_ALG_AAI_HMAC_PRECOMP,
  1538. .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
  1539. },
  1540. {
  1541. .name = "authenc(hmac(md5),cbc(des3_ede))",
  1542. .driver_name = "authenc-hmac-md5-cbc-des3_ede-caam",
  1543. .blocksize = DES3_EDE_BLOCK_SIZE,
  1544. .type = CRYPTO_ALG_TYPE_AEAD,
  1545. .template_aead = {
  1546. .setkey = aead_setkey,
  1547. .setauthsize = aead_setauthsize,
  1548. .encrypt = aead_encrypt,
  1549. .decrypt = aead_decrypt,
  1550. .givencrypt = aead_givencrypt,
  1551. .geniv = "<built-in>",
  1552. .ivsize = DES3_EDE_BLOCK_SIZE,
  1553. .maxauthsize = MD5_DIGEST_SIZE,
  1554. },
  1555. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1556. .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
  1557. .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
  1558. },
  1559. {
  1560. .name = "authenc(hmac(sha1),cbc(des3_ede))",
  1561. .driver_name = "authenc-hmac-sha1-cbc-des3_ede-caam",
  1562. .blocksize = DES3_EDE_BLOCK_SIZE,
  1563. .type = CRYPTO_ALG_TYPE_AEAD,
  1564. .template_aead = {
  1565. .setkey = aead_setkey,
  1566. .setauthsize = aead_setauthsize,
  1567. .encrypt = aead_encrypt,
  1568. .decrypt = aead_decrypt,
  1569. .givencrypt = aead_givencrypt,
  1570. .geniv = "<built-in>",
  1571. .ivsize = DES3_EDE_BLOCK_SIZE,
  1572. .maxauthsize = SHA1_DIGEST_SIZE,
  1573. },
  1574. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1575. .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
  1576. .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
  1577. },
  1578. {
  1579. .name = "authenc(hmac(sha224),cbc(des3_ede))",
  1580. .driver_name = "authenc-hmac-sha224-cbc-des3_ede-caam",
  1581. .blocksize = DES3_EDE_BLOCK_SIZE,
  1582. .type = CRYPTO_ALG_TYPE_AEAD,
  1583. .template_aead = {
  1584. .setkey = aead_setkey,
  1585. .setauthsize = aead_setauthsize,
  1586. .encrypt = aead_encrypt,
  1587. .decrypt = aead_decrypt,
  1588. .givencrypt = aead_givencrypt,
  1589. .geniv = "<built-in>",
  1590. .ivsize = DES3_EDE_BLOCK_SIZE,
  1591. .maxauthsize = SHA224_DIGEST_SIZE,
  1592. },
  1593. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1594. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1595. OP_ALG_AAI_HMAC_PRECOMP,
  1596. .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
  1597. },
  1598. {
  1599. .name = "authenc(hmac(sha256),cbc(des3_ede))",
  1600. .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam",
  1601. .blocksize = DES3_EDE_BLOCK_SIZE,
  1602. .type = CRYPTO_ALG_TYPE_AEAD,
  1603. .template_aead = {
  1604. .setkey = aead_setkey,
  1605. .setauthsize = aead_setauthsize,
  1606. .encrypt = aead_encrypt,
  1607. .decrypt = aead_decrypt,
  1608. .givencrypt = aead_givencrypt,
  1609. .geniv = "<built-in>",
  1610. .ivsize = DES3_EDE_BLOCK_SIZE,
  1611. .maxauthsize = SHA256_DIGEST_SIZE,
  1612. },
  1613. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1614. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1615. OP_ALG_AAI_HMAC_PRECOMP,
  1616. .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
  1617. },
  1618. {
  1619. .name = "authenc(hmac(sha384),cbc(des3_ede))",
  1620. .driver_name = "authenc-hmac-sha384-cbc-des3_ede-caam",
  1621. .blocksize = DES3_EDE_BLOCK_SIZE,
  1622. .type = CRYPTO_ALG_TYPE_AEAD,
  1623. .template_aead = {
  1624. .setkey = aead_setkey,
  1625. .setauthsize = aead_setauthsize,
  1626. .encrypt = aead_encrypt,
  1627. .decrypt = aead_decrypt,
  1628. .givencrypt = aead_givencrypt,
  1629. .geniv = "<built-in>",
  1630. .ivsize = DES3_EDE_BLOCK_SIZE,
  1631. .maxauthsize = SHA384_DIGEST_SIZE,
  1632. },
  1633. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1634. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1635. OP_ALG_AAI_HMAC_PRECOMP,
  1636. .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
  1637. },
  1638. {
  1639. .name = "authenc(hmac(sha512),cbc(des3_ede))",
  1640. .driver_name = "authenc-hmac-sha512-cbc-des3_ede-caam",
  1641. .blocksize = DES3_EDE_BLOCK_SIZE,
  1642. .type = CRYPTO_ALG_TYPE_AEAD,
  1643. .template_aead = {
  1644. .setkey = aead_setkey,
  1645. .setauthsize = aead_setauthsize,
  1646. .encrypt = aead_encrypt,
  1647. .decrypt = aead_decrypt,
  1648. .givencrypt = aead_givencrypt,
  1649. .geniv = "<built-in>",
  1650. .ivsize = DES3_EDE_BLOCK_SIZE,
  1651. .maxauthsize = SHA512_DIGEST_SIZE,
  1652. },
  1653. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1654. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1655. OP_ALG_AAI_HMAC_PRECOMP,
  1656. .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
  1657. },
  1658. {
  1659. .name = "authenc(hmac(md5),cbc(des))",
  1660. .driver_name = "authenc-hmac-md5-cbc-des-caam",
  1661. .blocksize = DES_BLOCK_SIZE,
  1662. .type = CRYPTO_ALG_TYPE_AEAD,
  1663. .template_aead = {
  1664. .setkey = aead_setkey,
  1665. .setauthsize = aead_setauthsize,
  1666. .encrypt = aead_encrypt,
  1667. .decrypt = aead_decrypt,
  1668. .givencrypt = aead_givencrypt,
  1669. .geniv = "<built-in>",
  1670. .ivsize = DES_BLOCK_SIZE,
  1671. .maxauthsize = MD5_DIGEST_SIZE,
  1672. },
  1673. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1674. .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
  1675. .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
  1676. },
  1677. {
  1678. .name = "authenc(hmac(sha1),cbc(des))",
  1679. .driver_name = "authenc-hmac-sha1-cbc-des-caam",
  1680. .blocksize = DES_BLOCK_SIZE,
  1681. .type = CRYPTO_ALG_TYPE_AEAD,
  1682. .template_aead = {
  1683. .setkey = aead_setkey,
  1684. .setauthsize = aead_setauthsize,
  1685. .encrypt = aead_encrypt,
  1686. .decrypt = aead_decrypt,
  1687. .givencrypt = aead_givencrypt,
  1688. .geniv = "<built-in>",
  1689. .ivsize = DES_BLOCK_SIZE,
  1690. .maxauthsize = SHA1_DIGEST_SIZE,
  1691. },
  1692. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1693. .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
  1694. .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
  1695. },
  1696. {
  1697. .name = "authenc(hmac(sha224),cbc(des))",
  1698. .driver_name = "authenc-hmac-sha224-cbc-des-caam",
  1699. .blocksize = DES_BLOCK_SIZE,
  1700. .type = CRYPTO_ALG_TYPE_AEAD,
  1701. .template_aead = {
  1702. .setkey = aead_setkey,
  1703. .setauthsize = aead_setauthsize,
  1704. .encrypt = aead_encrypt,
  1705. .decrypt = aead_decrypt,
  1706. .givencrypt = aead_givencrypt,
  1707. .geniv = "<built-in>",
  1708. .ivsize = DES_BLOCK_SIZE,
  1709. .maxauthsize = SHA224_DIGEST_SIZE,
  1710. },
  1711. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1712. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1713. OP_ALG_AAI_HMAC_PRECOMP,
  1714. .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
  1715. },
  1716. {
  1717. .name = "authenc(hmac(sha256),cbc(des))",
  1718. .driver_name = "authenc-hmac-sha256-cbc-des-caam",
  1719. .blocksize = DES_BLOCK_SIZE,
  1720. .type = CRYPTO_ALG_TYPE_AEAD,
  1721. .template_aead = {
  1722. .setkey = aead_setkey,
  1723. .setauthsize = aead_setauthsize,
  1724. .encrypt = aead_encrypt,
  1725. .decrypt = aead_decrypt,
  1726. .givencrypt = aead_givencrypt,
  1727. .geniv = "<built-in>",
  1728. .ivsize = DES_BLOCK_SIZE,
  1729. .maxauthsize = SHA256_DIGEST_SIZE,
  1730. },
  1731. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1732. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1733. OP_ALG_AAI_HMAC_PRECOMP,
  1734. .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
  1735. },
  1736. {
  1737. .name = "authenc(hmac(sha384),cbc(des))",
  1738. .driver_name = "authenc-hmac-sha384-cbc-des-caam",
  1739. .blocksize = DES_BLOCK_SIZE,
  1740. .type = CRYPTO_ALG_TYPE_AEAD,
  1741. .template_aead = {
  1742. .setkey = aead_setkey,
  1743. .setauthsize = aead_setauthsize,
  1744. .encrypt = aead_encrypt,
  1745. .decrypt = aead_decrypt,
  1746. .givencrypt = aead_givencrypt,
  1747. .geniv = "<built-in>",
  1748. .ivsize = DES_BLOCK_SIZE,
  1749. .maxauthsize = SHA384_DIGEST_SIZE,
  1750. },
  1751. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1752. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1753. OP_ALG_AAI_HMAC_PRECOMP,
  1754. .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
  1755. },
  1756. {
  1757. .name = "authenc(hmac(sha512),cbc(des))",
  1758. .driver_name = "authenc-hmac-sha512-cbc-des-caam",
  1759. .blocksize = DES_BLOCK_SIZE,
  1760. .type = CRYPTO_ALG_TYPE_AEAD,
  1761. .template_aead = {
  1762. .setkey = aead_setkey,
  1763. .setauthsize = aead_setauthsize,
  1764. .encrypt = aead_encrypt,
  1765. .decrypt = aead_decrypt,
  1766. .givencrypt = aead_givencrypt,
  1767. .geniv = "<built-in>",
  1768. .ivsize = DES_BLOCK_SIZE,
  1769. .maxauthsize = SHA512_DIGEST_SIZE,
  1770. },
  1771. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1772. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1773. OP_ALG_AAI_HMAC_PRECOMP,
  1774. .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
  1775. },
  1776. /* ablkcipher descriptor */
  1777. {
  1778. .name = "cbc(aes)",
  1779. .driver_name = "cbc-aes-caam",
  1780. .blocksize = AES_BLOCK_SIZE,
  1781. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1782. .template_ablkcipher = {
  1783. .setkey = ablkcipher_setkey,
  1784. .encrypt = ablkcipher_encrypt,
  1785. .decrypt = ablkcipher_decrypt,
  1786. .geniv = "eseqiv",
  1787. .min_keysize = AES_MIN_KEY_SIZE,
  1788. .max_keysize = AES_MAX_KEY_SIZE,
  1789. .ivsize = AES_BLOCK_SIZE,
  1790. },
  1791. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1792. },
  1793. {
  1794. .name = "cbc(des3_ede)",
  1795. .driver_name = "cbc-3des-caam",
  1796. .blocksize = DES3_EDE_BLOCK_SIZE,
  1797. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1798. .template_ablkcipher = {
  1799. .setkey = ablkcipher_setkey,
  1800. .encrypt = ablkcipher_encrypt,
  1801. .decrypt = ablkcipher_decrypt,
  1802. .geniv = "eseqiv",
  1803. .min_keysize = DES3_EDE_KEY_SIZE,
  1804. .max_keysize = DES3_EDE_KEY_SIZE,
  1805. .ivsize = DES3_EDE_BLOCK_SIZE,
  1806. },
  1807. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1808. },
  1809. {
  1810. .name = "cbc(des)",
  1811. .driver_name = "cbc-des-caam",
  1812. .blocksize = DES_BLOCK_SIZE,
  1813. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1814. .template_ablkcipher = {
  1815. .setkey = ablkcipher_setkey,
  1816. .encrypt = ablkcipher_encrypt,
  1817. .decrypt = ablkcipher_decrypt,
  1818. .geniv = "eseqiv",
  1819. .min_keysize = DES_KEY_SIZE,
  1820. .max_keysize = DES_KEY_SIZE,
  1821. .ivsize = DES_BLOCK_SIZE,
  1822. },
  1823. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1824. }
  1825. };
  1826. struct caam_crypto_alg {
  1827. struct list_head entry;
  1828. int class1_alg_type;
  1829. int class2_alg_type;
  1830. int alg_op;
  1831. struct crypto_alg crypto_alg;
  1832. };
  1833. static int caam_cra_init(struct crypto_tfm *tfm)
  1834. {
  1835. struct crypto_alg *alg = tfm->__crt_alg;
  1836. struct caam_crypto_alg *caam_alg =
  1837. container_of(alg, struct caam_crypto_alg, crypto_alg);
  1838. struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
  1839. ctx->jrdev = caam_jr_alloc();
  1840. if (IS_ERR(ctx->jrdev)) {
  1841. pr_err("Job Ring Device allocation for transform failed\n");
  1842. return PTR_ERR(ctx->jrdev);
  1843. }
  1844. /* copy descriptor header template value */
  1845. ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
  1846. ctx->class2_alg_type = OP_TYPE_CLASS2_ALG | caam_alg->class2_alg_type;
  1847. ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_alg->alg_op;
  1848. return 0;
  1849. }
  1850. static void caam_cra_exit(struct crypto_tfm *tfm)
  1851. {
  1852. struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
  1853. if (ctx->sh_desc_enc_dma &&
  1854. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma))
  1855. dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma,
  1856. desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
  1857. if (ctx->sh_desc_dec_dma &&
  1858. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma))
  1859. dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma,
  1860. desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE);
  1861. if (ctx->sh_desc_givenc_dma &&
  1862. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma))
  1863. dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
  1864. desc_bytes(ctx->sh_desc_givenc),
  1865. DMA_TO_DEVICE);
  1866. caam_jr_free(ctx->jrdev);
  1867. }
  1868. static void __exit caam_algapi_exit(void)
  1869. {
  1870. struct caam_crypto_alg *t_alg, *n;
  1871. if (!alg_list.next)
  1872. return;
  1873. list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
  1874. crypto_unregister_alg(&t_alg->crypto_alg);
  1875. list_del(&t_alg->entry);
  1876. kfree(t_alg);
  1877. }
  1878. }
  1879. static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
  1880. *template)
  1881. {
  1882. struct caam_crypto_alg *t_alg;
  1883. struct crypto_alg *alg;
  1884. t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
  1885. if (!t_alg) {
  1886. pr_err("failed to allocate t_alg\n");
  1887. return ERR_PTR(-ENOMEM);
  1888. }
  1889. alg = &t_alg->crypto_alg;
  1890. snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
  1891. snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
  1892. template->driver_name);
  1893. alg->cra_module = THIS_MODULE;
  1894. alg->cra_init = caam_cra_init;
  1895. alg->cra_exit = caam_cra_exit;
  1896. alg->cra_priority = CAAM_CRA_PRIORITY;
  1897. alg->cra_blocksize = template->blocksize;
  1898. alg->cra_alignmask = 0;
  1899. alg->cra_ctxsize = sizeof(struct caam_ctx);
  1900. alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
  1901. template->type;
  1902. switch (template->type) {
  1903. case CRYPTO_ALG_TYPE_ABLKCIPHER:
  1904. alg->cra_type = &crypto_ablkcipher_type;
  1905. alg->cra_ablkcipher = template->template_ablkcipher;
  1906. break;
  1907. case CRYPTO_ALG_TYPE_AEAD:
  1908. alg->cra_type = &crypto_aead_type;
  1909. alg->cra_aead = template->template_aead;
  1910. break;
  1911. }
  1912. t_alg->class1_alg_type = template->class1_alg_type;
  1913. t_alg->class2_alg_type = template->class2_alg_type;
  1914. t_alg->alg_op = template->alg_op;
  1915. return t_alg;
  1916. }
  1917. static int __init caam_algapi_init(void)
  1918. {
  1919. int i = 0, err = 0;
  1920. INIT_LIST_HEAD(&alg_list);
  1921. /* register crypto algorithms the device supports */
  1922. for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
  1923. /* TODO: check if h/w supports alg */
  1924. struct caam_crypto_alg *t_alg;
  1925. t_alg = caam_alg_alloc(&driver_algs[i]);
  1926. if (IS_ERR(t_alg)) {
  1927. err = PTR_ERR(t_alg);
  1928. pr_warn("%s alg allocation failed\n",
  1929. driver_algs[i].driver_name);
  1930. continue;
  1931. }
  1932. err = crypto_register_alg(&t_alg->crypto_alg);
  1933. if (err) {
  1934. pr_warn("%s alg registration failed\n",
  1935. t_alg->crypto_alg.cra_driver_name);
  1936. kfree(t_alg);
  1937. } else
  1938. list_add_tail(&t_alg->entry, &alg_list);
  1939. }
  1940. if (!list_empty(&alg_list))
  1941. pr_info("caam algorithms registered in /proc/crypto\n");
  1942. return err;
  1943. }
  1944. module_init(caam_algapi_init);
  1945. module_exit(caam_algapi_exit);
  1946. MODULE_LICENSE("GPL");
  1947. MODULE_DESCRIPTION("FSL CAAM support for crypto API");
  1948. MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");