scheduler.h 4.2 KB

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  1. /*
  2. * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21. * SOFTWARE.
  22. *
  23. * Authors:
  24. * Zhi Wang <zhi.a.wang@intel.com>
  25. *
  26. * Contributors:
  27. * Ping Gao <ping.a.gao@intel.com>
  28. * Tina Zhang <tina.zhang@intel.com>
  29. * Chanbin Du <changbin.du@intel.com>
  30. * Min He <min.he@intel.com>
  31. * Bing Niu <bing.niu@intel.com>
  32. * Zhenyu Wang <zhenyuw@linux.intel.com>
  33. *
  34. */
  35. #ifndef _GVT_SCHEDULER_H_
  36. #define _GVT_SCHEDULER_H_
  37. struct intel_gvt_workload_scheduler {
  38. struct intel_vgpu *current_vgpu;
  39. struct intel_vgpu *next_vgpu;
  40. struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
  41. bool need_reschedule;
  42. spinlock_t mmio_context_lock;
  43. /* can be null when owner is host */
  44. struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
  45. wait_queue_head_t workload_complete_wq;
  46. struct task_struct *thread[I915_NUM_ENGINES];
  47. wait_queue_head_t waitq[I915_NUM_ENGINES];
  48. void *sched_data;
  49. struct intel_gvt_sched_policy_ops *sched_ops;
  50. };
  51. #define INDIRECT_CTX_ADDR_MASK 0xffffffc0
  52. #define INDIRECT_CTX_SIZE_MASK 0x3f
  53. struct shadow_indirect_ctx {
  54. struct drm_i915_gem_object *obj;
  55. unsigned long guest_gma;
  56. unsigned long shadow_gma;
  57. void *shadow_va;
  58. uint32_t size;
  59. };
  60. #define PER_CTX_ADDR_MASK 0xfffff000
  61. struct shadow_per_ctx {
  62. unsigned long guest_gma;
  63. unsigned long shadow_gma;
  64. unsigned valid;
  65. };
  66. struct intel_shadow_wa_ctx {
  67. struct shadow_indirect_ctx indirect_ctx;
  68. struct shadow_per_ctx per_ctx;
  69. };
  70. struct intel_vgpu_workload {
  71. struct intel_vgpu *vgpu;
  72. int ring_id;
  73. struct drm_i915_gem_request *req;
  74. /* if this workload has been dispatched to i915? */
  75. bool dispatched;
  76. bool shadowed;
  77. int status;
  78. struct intel_vgpu_mm *shadow_mm;
  79. /* different submission model may need different handler */
  80. int (*prepare)(struct intel_vgpu_workload *);
  81. int (*complete)(struct intel_vgpu_workload *);
  82. struct list_head list;
  83. DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
  84. void *shadow_ring_buffer_va;
  85. /* execlist context information */
  86. struct execlist_ctx_descriptor_format ctx_desc;
  87. struct execlist_ring_context *ring_context;
  88. unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
  89. bool restore_inhibit;
  90. struct intel_vgpu_elsp_dwords elsp_dwords;
  91. bool emulate_schedule_in;
  92. atomic_t shadow_ctx_active;
  93. wait_queue_head_t shadow_ctx_status_wq;
  94. u64 ring_context_gpa;
  95. /* shadow batch buffer */
  96. struct list_head shadow_bb;
  97. struct intel_shadow_wa_ctx wa_ctx;
  98. };
  99. /* Intel shadow batch buffer is a i915 gem object */
  100. struct intel_shadow_bb_entry {
  101. struct list_head list;
  102. struct drm_i915_gem_object *obj;
  103. void *va;
  104. unsigned long len;
  105. u32 *bb_start_cmd_va;
  106. };
  107. #define workload_q_head(vgpu, ring_id) \
  108. (&(vgpu->workload_q_head[ring_id]))
  109. #define queue_workload(workload) do { \
  110. list_add_tail(&workload->list, \
  111. workload_q_head(workload->vgpu, workload->ring_id)); \
  112. wake_up(&workload->vgpu->gvt-> \
  113. scheduler.waitq[workload->ring_id]); \
  114. } while (0)
  115. int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
  116. void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
  117. void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu);
  118. int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu);
  119. void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);
  120. #endif