omap_drv.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969
  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/wait.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include "omap_dmm_tiler.h"
  25. #include "omap_drv.h"
  26. #define DRIVER_NAME MODULE_NAME
  27. #define DRIVER_DESC "OMAP DRM"
  28. #define DRIVER_DATE "20110917"
  29. #define DRIVER_MAJOR 1
  30. #define DRIVER_MINOR 0
  31. #define DRIVER_PATCHLEVEL 0
  32. static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
  33. MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
  34. module_param(num_crtc, int, 0600);
  35. /*
  36. * mode config funcs
  37. */
  38. /* Notes about mapping DSS and DRM entities:
  39. * CRTC: overlay
  40. * encoder: manager.. with some extension to allow one primary CRTC
  41. * and zero or more video CRTC's to be mapped to one encoder?
  42. * connector: dssdev.. manager can be attached/detached from different
  43. * devices
  44. */
  45. static void omap_fb_output_poll_changed(struct drm_device *dev)
  46. {
  47. struct omap_drm_private *priv = dev->dev_private;
  48. DBG("dev=%p", dev);
  49. if (priv->fbdev)
  50. drm_fb_helper_hotplug_event(priv->fbdev);
  51. }
  52. struct omap_atomic_state_commit {
  53. struct work_struct work;
  54. struct drm_device *dev;
  55. struct drm_atomic_state *state;
  56. u32 crtcs;
  57. };
  58. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  59. struct drm_atomic_state *old_state)
  60. {
  61. struct drm_crtc_state *old_crtc_state;
  62. struct drm_crtc *crtc;
  63. unsigned int i;
  64. int ret;
  65. for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  66. if (!crtc->state->enable)
  67. continue;
  68. ret = omap_crtc_wait_pending(crtc);
  69. if (!ret)
  70. dev_warn(dev->dev,
  71. "atomic complete timeout (pipe %u)!\n", i);
  72. }
  73. }
  74. static void omap_atomic_complete(struct omap_atomic_state_commit *commit)
  75. {
  76. struct drm_device *dev = commit->dev;
  77. struct omap_drm_private *priv = dev->dev_private;
  78. struct drm_atomic_state *old_state = commit->state;
  79. /* Apply the atomic update. */
  80. dispc_runtime_get();
  81. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  82. drm_atomic_helper_commit_planes(dev, old_state, 0);
  83. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  84. omap_atomic_wait_for_completion(dev, old_state);
  85. drm_atomic_helper_cleanup_planes(dev, old_state);
  86. dispc_runtime_put();
  87. drm_atomic_state_put(old_state);
  88. /* Complete the commit, wake up any waiter. */
  89. spin_lock(&priv->commit.lock);
  90. priv->commit.pending &= ~commit->crtcs;
  91. spin_unlock(&priv->commit.lock);
  92. wake_up_all(&priv->commit.wait);
  93. kfree(commit);
  94. }
  95. static void omap_atomic_work(struct work_struct *work)
  96. {
  97. struct omap_atomic_state_commit *commit =
  98. container_of(work, struct omap_atomic_state_commit, work);
  99. omap_atomic_complete(commit);
  100. }
  101. static bool omap_atomic_is_pending(struct omap_drm_private *priv,
  102. struct omap_atomic_state_commit *commit)
  103. {
  104. bool pending;
  105. spin_lock(&priv->commit.lock);
  106. pending = priv->commit.pending & commit->crtcs;
  107. spin_unlock(&priv->commit.lock);
  108. return pending;
  109. }
  110. static int omap_atomic_commit(struct drm_device *dev,
  111. struct drm_atomic_state *state, bool nonblock)
  112. {
  113. struct omap_drm_private *priv = dev->dev_private;
  114. struct omap_atomic_state_commit *commit;
  115. struct drm_crtc *crtc;
  116. struct drm_crtc_state *crtc_state;
  117. int i, ret;
  118. ret = drm_atomic_helper_prepare_planes(dev, state);
  119. if (ret)
  120. return ret;
  121. /* Allocate the commit object. */
  122. commit = kzalloc(sizeof(*commit), GFP_KERNEL);
  123. if (commit == NULL) {
  124. ret = -ENOMEM;
  125. goto error;
  126. }
  127. INIT_WORK(&commit->work, omap_atomic_work);
  128. commit->dev = dev;
  129. commit->state = state;
  130. /* Wait until all affected CRTCs have completed previous commits and
  131. * mark them as pending.
  132. */
  133. for_each_crtc_in_state(state, crtc, crtc_state, i)
  134. commit->crtcs |= drm_crtc_mask(crtc);
  135. wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
  136. spin_lock(&priv->commit.lock);
  137. priv->commit.pending |= commit->crtcs;
  138. spin_unlock(&priv->commit.lock);
  139. /* Swap the state, this is the point of no return. */
  140. drm_atomic_helper_swap_state(state, true);
  141. drm_atomic_state_get(state);
  142. if (nonblock)
  143. schedule_work(&commit->work);
  144. else
  145. omap_atomic_complete(commit);
  146. return 0;
  147. error:
  148. drm_atomic_helper_cleanup_planes(dev, state);
  149. return ret;
  150. }
  151. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  152. .fb_create = omap_framebuffer_create,
  153. .output_poll_changed = omap_fb_output_poll_changed,
  154. .atomic_check = drm_atomic_helper_check,
  155. .atomic_commit = omap_atomic_commit,
  156. };
  157. static int get_connector_type(struct omap_dss_device *dssdev)
  158. {
  159. switch (dssdev->type) {
  160. case OMAP_DISPLAY_TYPE_HDMI:
  161. return DRM_MODE_CONNECTOR_HDMIA;
  162. case OMAP_DISPLAY_TYPE_DVI:
  163. return DRM_MODE_CONNECTOR_DVID;
  164. case OMAP_DISPLAY_TYPE_DSI:
  165. return DRM_MODE_CONNECTOR_DSI;
  166. default:
  167. return DRM_MODE_CONNECTOR_Unknown;
  168. }
  169. }
  170. static bool channel_used(struct drm_device *dev, enum omap_channel channel)
  171. {
  172. struct omap_drm_private *priv = dev->dev_private;
  173. int i;
  174. for (i = 0; i < priv->num_crtcs; i++) {
  175. struct drm_crtc *crtc = priv->crtcs[i];
  176. if (omap_crtc_channel(crtc) == channel)
  177. return true;
  178. }
  179. return false;
  180. }
  181. static void omap_disconnect_dssdevs(void)
  182. {
  183. struct omap_dss_device *dssdev = NULL;
  184. for_each_dss_dev(dssdev)
  185. dssdev->driver->disconnect(dssdev);
  186. }
  187. static int omap_connect_dssdevs(void)
  188. {
  189. int r;
  190. struct omap_dss_device *dssdev = NULL;
  191. bool no_displays = true;
  192. for_each_dss_dev(dssdev) {
  193. r = dssdev->driver->connect(dssdev);
  194. if (r == -EPROBE_DEFER) {
  195. omap_dss_put_device(dssdev);
  196. goto cleanup;
  197. } else if (r) {
  198. dev_warn(dssdev->dev, "could not connect display: %s\n",
  199. dssdev->name);
  200. } else {
  201. no_displays = false;
  202. }
  203. }
  204. if (no_displays)
  205. return -EPROBE_DEFER;
  206. return 0;
  207. cleanup:
  208. /*
  209. * if we are deferring probe, we disconnect the devices we previously
  210. * connected
  211. */
  212. omap_disconnect_dssdevs();
  213. return r;
  214. }
  215. static int omap_modeset_create_crtc(struct drm_device *dev, int id,
  216. enum omap_channel channel,
  217. u32 possible_crtcs)
  218. {
  219. struct omap_drm_private *priv = dev->dev_private;
  220. struct drm_plane *plane;
  221. struct drm_crtc *crtc;
  222. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY,
  223. possible_crtcs);
  224. if (IS_ERR(plane))
  225. return PTR_ERR(plane);
  226. crtc = omap_crtc_init(dev, plane, channel, id);
  227. BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
  228. priv->crtcs[id] = crtc;
  229. priv->num_crtcs++;
  230. priv->planes[id] = plane;
  231. priv->num_planes++;
  232. return 0;
  233. }
  234. static int omap_modeset_init_properties(struct drm_device *dev)
  235. {
  236. struct omap_drm_private *priv = dev->dev_private;
  237. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
  238. if (!priv->zorder_prop)
  239. return -ENOMEM;
  240. return 0;
  241. }
  242. static int omap_modeset_init(struct drm_device *dev)
  243. {
  244. struct omap_drm_private *priv = dev->dev_private;
  245. struct omap_dss_device *dssdev = NULL;
  246. int num_ovls = dss_feat_get_num_ovls();
  247. int num_mgrs = dss_feat_get_num_mgrs();
  248. int num_crtcs;
  249. int i, id = 0;
  250. int ret;
  251. u32 possible_crtcs;
  252. drm_mode_config_init(dev);
  253. ret = omap_modeset_init_properties(dev);
  254. if (ret < 0)
  255. return ret;
  256. /*
  257. * We usually don't want to create a CRTC for each manager, at least
  258. * not until we have a way to expose private planes to userspace.
  259. * Otherwise there would not be enough video pipes left for drm planes.
  260. * We use the num_crtc argument to limit the number of crtcs we create.
  261. */
  262. num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
  263. possible_crtcs = (1 << num_crtcs) - 1;
  264. dssdev = NULL;
  265. for_each_dss_dev(dssdev) {
  266. struct drm_connector *connector;
  267. struct drm_encoder *encoder;
  268. enum omap_channel channel;
  269. struct omap_dss_device *out;
  270. if (!omapdss_device_is_connected(dssdev))
  271. continue;
  272. encoder = omap_encoder_init(dev, dssdev);
  273. if (!encoder) {
  274. dev_err(dev->dev, "could not create encoder: %s\n",
  275. dssdev->name);
  276. return -ENOMEM;
  277. }
  278. connector = omap_connector_init(dev,
  279. get_connector_type(dssdev), dssdev, encoder);
  280. if (!connector) {
  281. dev_err(dev->dev, "could not create connector: %s\n",
  282. dssdev->name);
  283. return -ENOMEM;
  284. }
  285. BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
  286. BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
  287. priv->encoders[priv->num_encoders++] = encoder;
  288. priv->connectors[priv->num_connectors++] = connector;
  289. drm_mode_connector_attach_encoder(connector, encoder);
  290. /*
  291. * if we have reached the limit of the crtcs we are allowed to
  292. * create, let's not try to look for a crtc for this
  293. * panel/encoder and onwards, we will, of course, populate the
  294. * the possible_crtcs field for all the encoders with the final
  295. * set of crtcs we create
  296. */
  297. if (id == num_crtcs)
  298. continue;
  299. /*
  300. * get the recommended DISPC channel for this encoder. For now,
  301. * we only try to get create a crtc out of the recommended, the
  302. * other possible channels to which the encoder can connect are
  303. * not considered.
  304. */
  305. out = omapdss_find_output_from_display(dssdev);
  306. channel = out->dispc_channel;
  307. omap_dss_put_device(out);
  308. /*
  309. * if this channel hasn't already been taken by a previously
  310. * allocated crtc, we create a new crtc for it
  311. */
  312. if (!channel_used(dev, channel)) {
  313. ret = omap_modeset_create_crtc(dev, id, channel,
  314. possible_crtcs);
  315. if (ret < 0) {
  316. dev_err(dev->dev,
  317. "could not create CRTC (channel %u)\n",
  318. channel);
  319. return ret;
  320. }
  321. id++;
  322. }
  323. }
  324. /*
  325. * we have allocated crtcs according to the need of the panels/encoders,
  326. * adding more crtcs here if needed
  327. */
  328. for (; id < num_crtcs; id++) {
  329. /* find a free manager for this crtc */
  330. for (i = 0; i < num_mgrs; i++) {
  331. if (!channel_used(dev, i))
  332. break;
  333. }
  334. if (i == num_mgrs) {
  335. /* this shouldn't really happen */
  336. dev_err(dev->dev, "no managers left for crtc\n");
  337. return -ENOMEM;
  338. }
  339. ret = omap_modeset_create_crtc(dev, id, i,
  340. possible_crtcs);
  341. if (ret < 0) {
  342. dev_err(dev->dev,
  343. "could not create CRTC (channel %u)\n", i);
  344. return ret;
  345. }
  346. }
  347. /*
  348. * Create normal planes for the remaining overlays:
  349. */
  350. for (; id < num_ovls; id++) {
  351. struct drm_plane *plane;
  352. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY,
  353. possible_crtcs);
  354. if (IS_ERR(plane))
  355. return PTR_ERR(plane);
  356. BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
  357. priv->planes[priv->num_planes++] = plane;
  358. }
  359. for (i = 0; i < priv->num_encoders; i++) {
  360. struct drm_encoder *encoder = priv->encoders[i];
  361. struct omap_dss_device *dssdev =
  362. omap_encoder_get_dssdev(encoder);
  363. struct omap_dss_device *output;
  364. output = omapdss_find_output_from_display(dssdev);
  365. /* figure out which crtc's we can connect the encoder to: */
  366. encoder->possible_crtcs = 0;
  367. for (id = 0; id < priv->num_crtcs; id++) {
  368. struct drm_crtc *crtc = priv->crtcs[id];
  369. enum omap_channel crtc_channel;
  370. crtc_channel = omap_crtc_channel(crtc);
  371. if (output->dispc_channel == crtc_channel) {
  372. encoder->possible_crtcs |= (1 << id);
  373. break;
  374. }
  375. }
  376. omap_dss_put_device(output);
  377. }
  378. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  379. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  380. priv->num_connectors);
  381. dev->mode_config.min_width = 32;
  382. dev->mode_config.min_height = 32;
  383. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  384. * to fill in these limits properly on different OMAP generations..
  385. */
  386. dev->mode_config.max_width = 2048;
  387. dev->mode_config.max_height = 2048;
  388. dev->mode_config.funcs = &omap_mode_config_funcs;
  389. drm_mode_config_reset(dev);
  390. omap_drm_irq_install(dev);
  391. return 0;
  392. }
  393. /*
  394. * drm ioctl funcs
  395. */
  396. static int ioctl_get_param(struct drm_device *dev, void *data,
  397. struct drm_file *file_priv)
  398. {
  399. struct omap_drm_private *priv = dev->dev_private;
  400. struct drm_omap_param *args = data;
  401. DBG("%p: param=%llu", dev, args->param);
  402. switch (args->param) {
  403. case OMAP_PARAM_CHIPSET_ID:
  404. args->value = priv->omaprev;
  405. break;
  406. default:
  407. DBG("unknown parameter %lld", args->param);
  408. return -EINVAL;
  409. }
  410. return 0;
  411. }
  412. static int ioctl_set_param(struct drm_device *dev, void *data,
  413. struct drm_file *file_priv)
  414. {
  415. struct drm_omap_param *args = data;
  416. switch (args->param) {
  417. default:
  418. DBG("unknown parameter %lld", args->param);
  419. return -EINVAL;
  420. }
  421. return 0;
  422. }
  423. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  424. static int ioctl_gem_new(struct drm_device *dev, void *data,
  425. struct drm_file *file_priv)
  426. {
  427. struct drm_omap_gem_new *args = data;
  428. u32 flags = args->flags & OMAP_BO_USER_MASK;
  429. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  430. args->size.bytes, flags);
  431. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  432. &args->handle);
  433. }
  434. static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  435. struct drm_file *file_priv)
  436. {
  437. struct drm_omap_gem_cpu_prep *args = data;
  438. struct drm_gem_object *obj;
  439. int ret;
  440. VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
  441. obj = drm_gem_object_lookup(file_priv, args->handle);
  442. if (!obj)
  443. return -ENOENT;
  444. ret = omap_gem_op_sync(obj, args->op);
  445. if (!ret)
  446. ret = omap_gem_op_start(obj, args->op);
  447. drm_gem_object_unreference_unlocked(obj);
  448. return ret;
  449. }
  450. static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  451. struct drm_file *file_priv)
  452. {
  453. struct drm_omap_gem_cpu_fini *args = data;
  454. struct drm_gem_object *obj;
  455. int ret;
  456. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  457. obj = drm_gem_object_lookup(file_priv, args->handle);
  458. if (!obj)
  459. return -ENOENT;
  460. /* XXX flushy, flushy */
  461. ret = 0;
  462. if (!ret)
  463. ret = omap_gem_op_finish(obj, args->op);
  464. drm_gem_object_unreference_unlocked(obj);
  465. return ret;
  466. }
  467. static int ioctl_gem_info(struct drm_device *dev, void *data,
  468. struct drm_file *file_priv)
  469. {
  470. struct drm_omap_gem_info *args = data;
  471. struct drm_gem_object *obj;
  472. int ret = 0;
  473. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  474. obj = drm_gem_object_lookup(file_priv, args->handle);
  475. if (!obj)
  476. return -ENOENT;
  477. args->size = omap_gem_mmap_size(obj);
  478. args->offset = omap_gem_mmap_offset(obj);
  479. drm_gem_object_unreference_unlocked(obj);
  480. return ret;
  481. }
  482. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  483. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_AUTH),
  484. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  485. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH),
  486. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_AUTH),
  487. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_AUTH),
  488. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH),
  489. };
  490. /*
  491. * drm driver funcs
  492. */
  493. static int dev_open(struct drm_device *dev, struct drm_file *file)
  494. {
  495. file->driver_priv = NULL;
  496. DBG("open: dev=%p, file=%p", dev, file);
  497. return 0;
  498. }
  499. /**
  500. * lastclose - clean up after all DRM clients have exited
  501. * @dev: DRM device
  502. *
  503. * Take care of cleaning up after all DRM clients have exited. In the
  504. * mode setting case, we want to restore the kernel's initial mode (just
  505. * in case the last client left us in a bad state).
  506. */
  507. static void dev_lastclose(struct drm_device *dev)
  508. {
  509. int i;
  510. /* we don't support vga_switcheroo.. so just make sure the fbdev
  511. * mode is active
  512. */
  513. struct omap_drm_private *priv = dev->dev_private;
  514. int ret;
  515. DBG("lastclose: dev=%p", dev);
  516. /* need to restore default rotation state.. not sure
  517. * if there is a cleaner way to restore properties to
  518. * default state? Maybe a flag that properties should
  519. * automatically be restored to default state on
  520. * lastclose?
  521. */
  522. for (i = 0; i < priv->num_crtcs; i++) {
  523. struct drm_crtc *crtc = priv->crtcs[i];
  524. if (!crtc->primary->rotation_property)
  525. continue;
  526. drm_object_property_set_value(&crtc->base,
  527. crtc->primary->rotation_property,
  528. DRM_ROTATE_0);
  529. }
  530. for (i = 0; i < priv->num_planes; i++) {
  531. struct drm_plane *plane = priv->planes[i];
  532. if (!plane->rotation_property)
  533. continue;
  534. drm_object_property_set_value(&plane->base,
  535. plane->rotation_property,
  536. DRM_ROTATE_0);
  537. }
  538. if (priv->fbdev) {
  539. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  540. if (ret)
  541. DBG("failed to restore crtc mode");
  542. }
  543. }
  544. static const struct vm_operations_struct omap_gem_vm_ops = {
  545. .fault = omap_gem_fault,
  546. .open = drm_gem_vm_open,
  547. .close = drm_gem_vm_close,
  548. };
  549. static const struct file_operations omapdriver_fops = {
  550. .owner = THIS_MODULE,
  551. .open = drm_open,
  552. .unlocked_ioctl = drm_ioctl,
  553. .release = drm_release,
  554. .mmap = omap_gem_mmap,
  555. .poll = drm_poll,
  556. .read = drm_read,
  557. .llseek = noop_llseek,
  558. };
  559. static struct drm_driver omap_drm_driver = {
  560. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  561. DRIVER_ATOMIC,
  562. .open = dev_open,
  563. .lastclose = dev_lastclose,
  564. .get_vblank_counter = drm_vblank_no_hw_counter,
  565. .enable_vblank = omap_irq_enable_vblank,
  566. .disable_vblank = omap_irq_disable_vblank,
  567. #ifdef CONFIG_DEBUG_FS
  568. .debugfs_init = omap_debugfs_init,
  569. #endif
  570. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  571. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  572. .gem_prime_export = omap_gem_prime_export,
  573. .gem_prime_import = omap_gem_prime_import,
  574. .gem_free_object = omap_gem_free_object,
  575. .gem_vm_ops = &omap_gem_vm_ops,
  576. .dumb_create = omap_gem_dumb_create,
  577. .dumb_map_offset = omap_gem_dumb_map_offset,
  578. .dumb_destroy = drm_gem_dumb_destroy,
  579. .ioctls = ioctls,
  580. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  581. .fops = &omapdriver_fops,
  582. .name = DRIVER_NAME,
  583. .desc = DRIVER_DESC,
  584. .date = DRIVER_DATE,
  585. .major = DRIVER_MAJOR,
  586. .minor = DRIVER_MINOR,
  587. .patchlevel = DRIVER_PATCHLEVEL,
  588. };
  589. static int pdev_probe(struct platform_device *pdev)
  590. {
  591. struct omap_drm_platform_data *pdata = pdev->dev.platform_data;
  592. struct omap_drm_private *priv;
  593. struct drm_device *ddev;
  594. unsigned int i;
  595. int ret;
  596. DBG("%s", pdev->name);
  597. if (omapdss_is_initialized() == false)
  598. return -EPROBE_DEFER;
  599. omap_crtc_pre_init();
  600. ret = omap_connect_dssdevs();
  601. if (ret)
  602. goto err_crtc_uninit;
  603. /* Allocate and initialize the driver private structure. */
  604. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  605. if (!priv) {
  606. ret = -ENOMEM;
  607. goto err_disconnect_dssdevs;
  608. }
  609. priv->omaprev = pdata->omaprev;
  610. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  611. init_waitqueue_head(&priv->commit.wait);
  612. spin_lock_init(&priv->commit.lock);
  613. spin_lock_init(&priv->list_lock);
  614. INIT_LIST_HEAD(&priv->obj_list);
  615. /* Allocate and initialize the DRM device. */
  616. ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev);
  617. if (IS_ERR(ddev)) {
  618. ret = PTR_ERR(ddev);
  619. goto err_free_priv;
  620. }
  621. ddev->dev_private = priv;
  622. platform_set_drvdata(pdev, ddev);
  623. omap_gem_init(ddev);
  624. ret = omap_modeset_init(ddev);
  625. if (ret) {
  626. dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  627. goto err_free_drm_dev;
  628. }
  629. /* Initialize vblank handling, start with all CRTCs disabled. */
  630. ret = drm_vblank_init(ddev, priv->num_crtcs);
  631. if (ret) {
  632. dev_err(&pdev->dev, "could not init vblank\n");
  633. goto err_cleanup_modeset;
  634. }
  635. for (i = 0; i < priv->num_crtcs; i++)
  636. drm_crtc_vblank_off(priv->crtcs[i]);
  637. priv->fbdev = omap_fbdev_init(ddev);
  638. drm_kms_helper_poll_init(ddev);
  639. /*
  640. * Register the DRM device with the core and the connectors with
  641. * sysfs.
  642. */
  643. ret = drm_dev_register(ddev, 0);
  644. if (ret)
  645. goto err_cleanup_helpers;
  646. return 0;
  647. err_cleanup_helpers:
  648. drm_kms_helper_poll_fini(ddev);
  649. if (priv->fbdev)
  650. omap_fbdev_free(ddev);
  651. err_cleanup_modeset:
  652. drm_mode_config_cleanup(ddev);
  653. omap_drm_irq_uninstall(ddev);
  654. err_free_drm_dev:
  655. omap_gem_deinit(ddev);
  656. drm_dev_unref(ddev);
  657. err_free_priv:
  658. destroy_workqueue(priv->wq);
  659. kfree(priv);
  660. err_disconnect_dssdevs:
  661. omap_disconnect_dssdevs();
  662. err_crtc_uninit:
  663. omap_crtc_pre_uninit();
  664. return ret;
  665. }
  666. static int pdev_remove(struct platform_device *pdev)
  667. {
  668. struct drm_device *ddev = platform_get_drvdata(pdev);
  669. struct omap_drm_private *priv = ddev->dev_private;
  670. DBG("");
  671. drm_dev_unregister(ddev);
  672. drm_kms_helper_poll_fini(ddev);
  673. if (priv->fbdev)
  674. omap_fbdev_free(ddev);
  675. drm_mode_config_cleanup(ddev);
  676. omap_drm_irq_uninstall(ddev);
  677. omap_gem_deinit(ddev);
  678. drm_dev_unref(ddev);
  679. destroy_workqueue(priv->wq);
  680. kfree(priv);
  681. omap_disconnect_dssdevs();
  682. omap_crtc_pre_uninit();
  683. return 0;
  684. }
  685. #ifdef CONFIG_PM_SLEEP
  686. static int omap_drm_suspend_all_displays(void)
  687. {
  688. struct omap_dss_device *dssdev = NULL;
  689. for_each_dss_dev(dssdev) {
  690. if (!dssdev->driver)
  691. continue;
  692. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  693. dssdev->driver->disable(dssdev);
  694. dssdev->activate_after_resume = true;
  695. } else {
  696. dssdev->activate_after_resume = false;
  697. }
  698. }
  699. return 0;
  700. }
  701. static int omap_drm_resume_all_displays(void)
  702. {
  703. struct omap_dss_device *dssdev = NULL;
  704. for_each_dss_dev(dssdev) {
  705. if (!dssdev->driver)
  706. continue;
  707. if (dssdev->activate_after_resume) {
  708. dssdev->driver->enable(dssdev);
  709. dssdev->activate_after_resume = false;
  710. }
  711. }
  712. return 0;
  713. }
  714. static int omap_drm_suspend(struct device *dev)
  715. {
  716. struct drm_device *drm_dev = dev_get_drvdata(dev);
  717. drm_kms_helper_poll_disable(drm_dev);
  718. drm_modeset_lock_all(drm_dev);
  719. omap_drm_suspend_all_displays();
  720. drm_modeset_unlock_all(drm_dev);
  721. return 0;
  722. }
  723. static int omap_drm_resume(struct device *dev)
  724. {
  725. struct drm_device *drm_dev = dev_get_drvdata(dev);
  726. drm_modeset_lock_all(drm_dev);
  727. omap_drm_resume_all_displays();
  728. drm_modeset_unlock_all(drm_dev);
  729. drm_kms_helper_poll_enable(drm_dev);
  730. return omap_gem_resume(dev);
  731. }
  732. #endif
  733. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  734. static struct platform_driver pdev = {
  735. .driver = {
  736. .name = DRIVER_NAME,
  737. .pm = &omapdrm_pm_ops,
  738. },
  739. .probe = pdev_probe,
  740. .remove = pdev_remove,
  741. };
  742. static struct platform_driver * const drivers[] = {
  743. &omap_dmm_driver,
  744. &pdev,
  745. };
  746. static int __init omap_drm_init(void)
  747. {
  748. DBG("init");
  749. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  750. }
  751. static void __exit omap_drm_fini(void)
  752. {
  753. DBG("fini");
  754. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  755. }
  756. /* need late_initcall() so we load after dss_driver's are loaded */
  757. late_initcall(omap_drm_init);
  758. module_exit(omap_drm_fini);
  759. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  760. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  761. MODULE_ALIAS("platform:" DRIVER_NAME);
  762. MODULE_LICENSE("GPL v2");