dwc3-pci.c 7.8 KB

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  1. /**
  2. * dwc3-pci.c - PCI Specific glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/acpi.h>
  26. #include <linux/delay.h>
  27. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  28. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  29. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  30. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  31. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  32. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  33. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  34. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  35. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  36. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  37. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  38. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  39. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  40. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  41. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  42. { "reset-gpios", &reset_gpios, 1 },
  43. { "cs-gpios", &cs_gpios, 1 },
  44. { },
  45. };
  46. static int dwc3_pci_quirks(struct pci_dev *pdev, struct platform_device *dwc3)
  47. {
  48. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  49. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  50. struct property_entry properties[] = {
  51. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  52. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  53. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  54. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  55. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  56. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  57. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  58. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  59. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  60. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  61. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  62. /*
  63. * FIXME these quirks should be removed when AMD NL
  64. * tapes out
  65. */
  66. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  67. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  68. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  69. { },
  70. };
  71. return platform_device_add_properties(dwc3, properties);
  72. }
  73. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  74. int ret;
  75. struct property_entry properties[] = {
  76. PROPERTY_ENTRY_STRING("dr-mode", "peripheral"),
  77. { }
  78. };
  79. ret = platform_device_add_properties(dwc3, properties);
  80. if (ret < 0)
  81. return ret;
  82. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  83. struct gpio_desc *gpio;
  84. acpi_dev_add_driver_gpios(ACPI_COMPANION(&pdev->dev),
  85. acpi_dwc3_byt_gpios);
  86. /*
  87. * These GPIOs will turn on the USB2 PHY. Note that we have to
  88. * put the gpio descriptors again here because the phy driver
  89. * might want to grab them, too.
  90. */
  91. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  92. if (IS_ERR(gpio))
  93. return PTR_ERR(gpio);
  94. gpiod_set_value_cansleep(gpio, 1);
  95. gpiod_put(gpio);
  96. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  97. if (IS_ERR(gpio))
  98. return PTR_ERR(gpio);
  99. if (gpio) {
  100. gpiod_set_value_cansleep(gpio, 1);
  101. gpiod_put(gpio);
  102. usleep_range(10000, 11000);
  103. }
  104. }
  105. }
  106. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  107. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  108. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  109. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  110. struct property_entry properties[] = {
  111. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  112. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  113. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  114. { },
  115. };
  116. return platform_device_add_properties(dwc3, properties);
  117. }
  118. return 0;
  119. }
  120. static int dwc3_pci_probe(struct pci_dev *pci,
  121. const struct pci_device_id *id)
  122. {
  123. struct resource res[2];
  124. struct platform_device *dwc3;
  125. int ret;
  126. struct device *dev = &pci->dev;
  127. ret = pcim_enable_device(pci);
  128. if (ret) {
  129. dev_err(dev, "failed to enable pci device\n");
  130. return -ENODEV;
  131. }
  132. pci_set_master(pci);
  133. dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  134. if (!dwc3) {
  135. dev_err(dev, "couldn't allocate dwc3 device\n");
  136. return -ENOMEM;
  137. }
  138. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  139. res[0].start = pci_resource_start(pci, 0);
  140. res[0].end = pci_resource_end(pci, 0);
  141. res[0].name = "dwc_usb3";
  142. res[0].flags = IORESOURCE_MEM;
  143. res[1].start = pci->irq;
  144. res[1].name = "dwc_usb3";
  145. res[1].flags = IORESOURCE_IRQ;
  146. ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
  147. if (ret) {
  148. dev_err(dev, "couldn't add resources to dwc3 device\n");
  149. return ret;
  150. }
  151. dwc3->dev.parent = dev;
  152. ACPI_COMPANION_SET(&dwc3->dev, ACPI_COMPANION(dev));
  153. ret = dwc3_pci_quirks(pci, dwc3);
  154. if (ret)
  155. goto err;
  156. ret = platform_device_add(dwc3);
  157. if (ret) {
  158. dev_err(dev, "failed to register dwc3 device\n");
  159. goto err;
  160. }
  161. device_init_wakeup(dev, true);
  162. device_set_run_wake(dev, true);
  163. pci_set_drvdata(pci, dwc3);
  164. pm_runtime_put(dev);
  165. return 0;
  166. err:
  167. platform_device_put(dwc3);
  168. return ret;
  169. }
  170. static void dwc3_pci_remove(struct pci_dev *pci)
  171. {
  172. device_init_wakeup(&pci->dev, false);
  173. pm_runtime_get(&pci->dev);
  174. acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pci->dev));
  175. platform_device_unregister(pci_get_drvdata(pci));
  176. }
  177. static const struct pci_device_id dwc3_pci_id_table[] = {
  178. {
  179. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  180. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  181. },
  182. {
  183. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  184. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  185. },
  186. {
  187. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  188. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  189. },
  190. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  191. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  192. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  193. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  194. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  195. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  196. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  197. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  198. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  199. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  200. { } /* Terminating Entry */
  201. };
  202. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  203. #ifdef CONFIG_PM
  204. static int dwc3_pci_runtime_suspend(struct device *dev)
  205. {
  206. if (device_run_wake(dev))
  207. return 0;
  208. return -EBUSY;
  209. }
  210. static int dwc3_pci_pm_dummy(struct device *dev)
  211. {
  212. /*
  213. * There's nothing to do here. No, seriously. Everything is either taken
  214. * care either by PCI subsystem or dwc3/core.c, so we have nothing
  215. * missing here.
  216. *
  217. * So you'd think we didn't need this at all, but PCI subsystem will
  218. * bail out if we don't have a valid callback :-s
  219. */
  220. return 0;
  221. }
  222. #endif /* CONFIG_PM */
  223. static struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  224. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_pm_dummy, dwc3_pci_pm_dummy)
  225. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_pm_dummy,
  226. NULL)
  227. };
  228. static struct pci_driver dwc3_pci_driver = {
  229. .name = "dwc3-pci",
  230. .id_table = dwc3_pci_id_table,
  231. .probe = dwc3_pci_probe,
  232. .remove = dwc3_pci_remove,
  233. .driver = {
  234. .pm = &dwc3_pci_dev_pm_ops,
  235. }
  236. };
  237. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  238. MODULE_LICENSE("GPL v2");
  239. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  240. module_pci_driver(dwc3_pci_driver);