pci-versatile.c 6.3 KB

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  1. /*
  2. * Copyright 2004 Koninklijke Philips Electronics NV
  3. *
  4. * Conversion to platform driver and DT:
  5. * Copyright 2014 Linaro Ltd.
  6. *
  7. * This software is licensed under the terms of the GNU General Public
  8. * License version 2, as published by the Free Software Foundation, and
  9. * may be copied, distributed, and modified under those terms.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * 14/04/2005 Initial version, colin.king@philips.com
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_pci.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/pci.h>
  24. #include <linux/platform_device.h>
  25. static void __iomem *versatile_pci_base;
  26. static void __iomem *versatile_cfg_base[2];
  27. #define PCI_IMAP(m) (versatile_pci_base + ((m) * 4))
  28. #define PCI_SMAP(m) (versatile_pci_base + 0x14 + ((m) * 4))
  29. #define PCI_SELFID (versatile_pci_base + 0xc)
  30. #define VP_PCI_DEVICE_ID 0x030010ee
  31. #define VP_PCI_CLASS_ID 0x0b400000
  32. static u32 pci_slot_ignore;
  33. static int __init versatile_pci_slot_ignore(char *str)
  34. {
  35. int retval;
  36. int slot;
  37. while ((retval = get_option(&str, &slot))) {
  38. if ((slot < 0) || (slot > 31))
  39. pr_err("Illegal slot value: %d\n", slot);
  40. else
  41. pci_slot_ignore |= (1 << slot);
  42. }
  43. return 1;
  44. }
  45. __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
  46. static void __iomem *versatile_map_bus(struct pci_bus *bus,
  47. unsigned int devfn, int offset)
  48. {
  49. unsigned int busnr = bus->number;
  50. if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
  51. return NULL;
  52. return versatile_cfg_base[1] + ((busnr << 16) | (devfn << 8) | offset);
  53. }
  54. static struct pci_ops pci_versatile_ops = {
  55. .map_bus = versatile_map_bus,
  56. .read = pci_generic_config_read32,
  57. .write = pci_generic_config_write,
  58. };
  59. static int versatile_pci_parse_request_of_pci_ranges(struct device *dev,
  60. struct list_head *res)
  61. {
  62. int err, mem = 1, res_valid = 0;
  63. struct device_node *np = dev->of_node;
  64. resource_size_t iobase;
  65. struct resource_entry *win;
  66. err = of_pci_get_host_bridge_resources(np, 0, 0xff, res, &iobase);
  67. if (err)
  68. return err;
  69. err = devm_request_pci_bus_resources(dev, res);
  70. if (err)
  71. goto out_release_res;
  72. resource_list_for_each_entry(win, res) {
  73. struct resource *res = win->res;
  74. switch (resource_type(res)) {
  75. case IORESOURCE_IO:
  76. err = pci_remap_iospace(res, iobase);
  77. if (err)
  78. dev_warn(dev, "error %d: failed to map resource %pR\n",
  79. err, res);
  80. break;
  81. case IORESOURCE_MEM:
  82. res_valid |= !(res->flags & IORESOURCE_PREFETCH);
  83. writel(res->start >> 28, PCI_IMAP(mem));
  84. writel(PHYS_OFFSET >> 28, PCI_SMAP(mem));
  85. mem++;
  86. break;
  87. }
  88. }
  89. if (res_valid)
  90. return 0;
  91. dev_err(dev, "non-prefetchable memory resource required\n");
  92. err = -EINVAL;
  93. out_release_res:
  94. pci_free_resource_list(res);
  95. return err;
  96. }
  97. static int versatile_pci_probe(struct platform_device *pdev)
  98. {
  99. struct resource *res;
  100. int ret, i, myslot = -1;
  101. u32 val;
  102. void __iomem *local_pci_cfg_base;
  103. struct pci_bus *bus;
  104. LIST_HEAD(pci_res);
  105. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  106. versatile_pci_base = devm_ioremap_resource(&pdev->dev, res);
  107. if (IS_ERR(versatile_pci_base))
  108. return PTR_ERR(versatile_pci_base);
  109. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  110. versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res);
  111. if (IS_ERR(versatile_cfg_base[0]))
  112. return PTR_ERR(versatile_cfg_base[0]);
  113. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  114. versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res);
  115. if (IS_ERR(versatile_cfg_base[1]))
  116. return PTR_ERR(versatile_cfg_base[1]);
  117. ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res);
  118. if (ret)
  119. return ret;
  120. /*
  121. * We need to discover the PCI core first to configure itself
  122. * before the main PCI probing is performed
  123. */
  124. for (i = 0; i < 32; i++) {
  125. if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
  126. (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
  127. myslot = i;
  128. break;
  129. }
  130. }
  131. if (myslot == -1) {
  132. dev_err(&pdev->dev, "Cannot find PCI core!\n");
  133. return -EIO;
  134. }
  135. /*
  136. * Do not to map Versatile FPGA PCI device into memory space
  137. */
  138. pci_slot_ignore |= (1 << myslot);
  139. dev_info(&pdev->dev, "PCI core found (slot %d)\n", myslot);
  140. writel(myslot, PCI_SELFID);
  141. local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);
  142. val = readl(local_pci_cfg_base + PCI_COMMAND);
  143. val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
  144. writel(val, local_pci_cfg_base + PCI_COMMAND);
  145. /*
  146. * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
  147. */
  148. writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
  149. writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
  150. writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
  151. /*
  152. * For many years the kernel and QEMU were symbiotically buggy
  153. * in that they both assumed the same broken IRQ mapping.
  154. * QEMU therefore attempts to auto-detect old broken kernels
  155. * so that they still work on newer QEMU as they did on old
  156. * QEMU. Since we now use the correct (ie matching-hardware)
  157. * IRQ mapping we write a definitely different value to a
  158. * PCI_INTERRUPT_LINE register to tell QEMU that we expect
  159. * real hardware behaviour and it need not be backwards
  160. * compatible for us. This write is harmless on real hardware.
  161. */
  162. writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
  163. pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
  164. pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);
  165. bus = pci_scan_root_bus(&pdev->dev, 0, &pci_versatile_ops, NULL, &pci_res);
  166. if (!bus)
  167. return -ENOMEM;
  168. pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
  169. pci_assign_unassigned_bus_resources(bus);
  170. pci_bus_add_devices(bus);
  171. return 0;
  172. }
  173. static const struct of_device_id versatile_pci_of_match[] = {
  174. { .compatible = "arm,versatile-pci", },
  175. { },
  176. };
  177. MODULE_DEVICE_TABLE(of, versatile_pci_of_match);
  178. static struct platform_driver versatile_pci_driver = {
  179. .driver = {
  180. .name = "versatile-pci",
  181. .of_match_table = versatile_pci_of_match,
  182. },
  183. .probe = versatile_pci_probe,
  184. };
  185. module_platform_driver(versatile_pci_driver);
  186. MODULE_DESCRIPTION("Versatile PCI driver");
  187. MODULE_LICENSE("GPL v2");