nvm.c 25 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37. * Copyright(c) 2016 Intel Deutschland GmbH
  38. * All rights reserved.
  39. *
  40. * Redistribution and use in source and binary forms, with or without
  41. * modification, are permitted provided that the following conditions
  42. * are met:
  43. *
  44. * * Redistributions of source code must retain the above copyright
  45. * notice, this list of conditions and the following disclaimer.
  46. * * Redistributions in binary form must reproduce the above copyright
  47. * notice, this list of conditions and the following disclaimer in
  48. * the documentation and/or other materials provided with the
  49. * distribution.
  50. * * Neither the name Intel Corporation nor the names of its
  51. * contributors may be used to endorse or promote products derived
  52. * from this software without specific prior written permission.
  53. *
  54. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  59. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  60. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65. *
  66. *****************************************************************************/
  67. #include <linux/firmware.h>
  68. #include <linux/rtnetlink.h>
  69. #include <linux/acpi.h>
  70. #include "iwl-trans.h"
  71. #include "iwl-csr.h"
  72. #include "mvm.h"
  73. #include "iwl-eeprom-parse.h"
  74. #include "iwl-eeprom-read.h"
  75. #include "iwl-nvm-parse.h"
  76. #include "iwl-prph.h"
  77. /* Default NVM size to read */
  78. #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024)
  79. #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
  80. #define IWL_MAX_NVM_8000_SECTION_SIZE 0x1ffc
  81. #define NVM_WRITE_OPCODE 1
  82. #define NVM_READ_OPCODE 0
  83. /* load nvm chunk response */
  84. enum {
  85. READ_NVM_CHUNK_SUCCEED = 0,
  86. READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1
  87. };
  88. /*
  89. * prepare the NVM host command w/ the pointers to the nvm buffer
  90. * and send it to fw
  91. */
  92. static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section,
  93. u16 offset, u16 length, const u8 *data)
  94. {
  95. struct iwl_nvm_access_cmd nvm_access_cmd = {
  96. .offset = cpu_to_le16(offset),
  97. .length = cpu_to_le16(length),
  98. .type = cpu_to_le16(section),
  99. .op_code = NVM_WRITE_OPCODE,
  100. };
  101. struct iwl_host_cmd cmd = {
  102. .id = NVM_ACCESS_CMD,
  103. .len = { sizeof(struct iwl_nvm_access_cmd), length },
  104. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  105. .data = { &nvm_access_cmd, data },
  106. /* data may come from vmalloc, so use _DUP */
  107. .dataflags = { 0, IWL_HCMD_DFL_DUP },
  108. };
  109. struct iwl_rx_packet *pkt;
  110. struct iwl_nvm_access_resp *nvm_resp;
  111. int ret;
  112. ret = iwl_mvm_send_cmd(mvm, &cmd);
  113. if (ret)
  114. return ret;
  115. pkt = cmd.resp_pkt;
  116. if (!pkt) {
  117. IWL_ERR(mvm, "Error in NVM_ACCESS response\n");
  118. return -EINVAL;
  119. }
  120. /* Extract & check NVM write response */
  121. nvm_resp = (void *)pkt->data;
  122. if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) {
  123. IWL_ERR(mvm,
  124. "NVM access write command failed for section %u (status = 0x%x)\n",
  125. section, le16_to_cpu(nvm_resp->status));
  126. ret = -EIO;
  127. }
  128. iwl_free_resp(&cmd);
  129. return ret;
  130. }
  131. static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section,
  132. u16 offset, u16 length, u8 *data)
  133. {
  134. struct iwl_nvm_access_cmd nvm_access_cmd = {
  135. .offset = cpu_to_le16(offset),
  136. .length = cpu_to_le16(length),
  137. .type = cpu_to_le16(section),
  138. .op_code = NVM_READ_OPCODE,
  139. };
  140. struct iwl_nvm_access_resp *nvm_resp;
  141. struct iwl_rx_packet *pkt;
  142. struct iwl_host_cmd cmd = {
  143. .id = NVM_ACCESS_CMD,
  144. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  145. .data = { &nvm_access_cmd, },
  146. };
  147. int ret, bytes_read, offset_read;
  148. u8 *resp_data;
  149. cmd.len[0] = sizeof(struct iwl_nvm_access_cmd);
  150. ret = iwl_mvm_send_cmd(mvm, &cmd);
  151. if (ret)
  152. return ret;
  153. pkt = cmd.resp_pkt;
  154. /* Extract NVM response */
  155. nvm_resp = (void *)pkt->data;
  156. ret = le16_to_cpu(nvm_resp->status);
  157. bytes_read = le16_to_cpu(nvm_resp->length);
  158. offset_read = le16_to_cpu(nvm_resp->offset);
  159. resp_data = nvm_resp->data;
  160. if (ret) {
  161. if ((offset != 0) &&
  162. (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) {
  163. /*
  164. * meaning of NOT_VALID_ADDRESS:
  165. * driver try to read chunk from address that is
  166. * multiple of 2K and got an error since addr is empty.
  167. * meaning of (offset != 0): driver already
  168. * read valid data from another chunk so this case
  169. * is not an error.
  170. */
  171. IWL_DEBUG_EEPROM(mvm->trans->dev,
  172. "NVM access command failed on offset 0x%x since that section size is multiple 2K\n",
  173. offset);
  174. ret = 0;
  175. } else {
  176. IWL_DEBUG_EEPROM(mvm->trans->dev,
  177. "NVM access command failed with status %d (device: %s)\n",
  178. ret, mvm->cfg->name);
  179. ret = -EIO;
  180. }
  181. goto exit;
  182. }
  183. if (offset_read != offset) {
  184. IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n",
  185. offset_read);
  186. ret = -EINVAL;
  187. goto exit;
  188. }
  189. /* Write data to NVM */
  190. memcpy(data + offset, resp_data, bytes_read);
  191. ret = bytes_read;
  192. exit:
  193. iwl_free_resp(&cmd);
  194. return ret;
  195. }
  196. static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section,
  197. const u8 *data, u16 length)
  198. {
  199. int offset = 0;
  200. /* copy data in chunks of 2k (and remainder if any) */
  201. while (offset < length) {
  202. int chunk_size, ret;
  203. chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE,
  204. length - offset);
  205. ret = iwl_nvm_write_chunk(mvm, section, offset,
  206. chunk_size, data + offset);
  207. if (ret < 0)
  208. return ret;
  209. offset += chunk_size;
  210. }
  211. return 0;
  212. }
  213. static void iwl_mvm_nvm_fixups(struct iwl_mvm *mvm, unsigned int section,
  214. u8 *data, unsigned int len)
  215. {
  216. #define IWL_4165_DEVICE_ID 0x5501
  217. #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
  218. if (section == NVM_SECTION_TYPE_PHY_SKU &&
  219. mvm->trans->hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
  220. (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
  221. /* OTP 0x52 bug work around: it's a 1x1 device */
  222. data[3] = ANT_B | (ANT_B << 4);
  223. }
  224. /*
  225. * Reads an NVM section completely.
  226. * NICs prior to 7000 family doesn't have a real NVM, but just read
  227. * section 0 which is the EEPROM. Because the EEPROM reading is unlimited
  228. * by uCode, we need to manually check in this case that we don't
  229. * overflow and try to read more than the EEPROM size.
  230. * For 7000 family NICs, we supply the maximal size we can read, and
  231. * the uCode fills the response with as much data as we can,
  232. * without overflowing, so no check is needed.
  233. */
  234. static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section,
  235. u8 *data, u32 size_read)
  236. {
  237. u16 length, offset = 0;
  238. int ret;
  239. /* Set nvm section read length */
  240. length = IWL_NVM_DEFAULT_CHUNK_SIZE;
  241. ret = length;
  242. /* Read the NVM until exhausted (reading less than requested) */
  243. while (ret == length) {
  244. /* Check no memory assumptions fail and cause an overflow */
  245. if ((size_read + offset + length) >
  246. mvm->cfg->base_params->eeprom_size) {
  247. IWL_ERR(mvm, "EEPROM size is too small for NVM\n");
  248. return -ENOBUFS;
  249. }
  250. ret = iwl_nvm_read_chunk(mvm, section, offset, length, data);
  251. if (ret < 0) {
  252. IWL_DEBUG_EEPROM(mvm->trans->dev,
  253. "Cannot read NVM from section %d offset %d, length %d\n",
  254. section, offset, length);
  255. return ret;
  256. }
  257. offset += ret;
  258. }
  259. iwl_mvm_nvm_fixups(mvm, section, data, offset);
  260. IWL_DEBUG_EEPROM(mvm->trans->dev,
  261. "NVM section %d read completed\n", section);
  262. return offset;
  263. }
  264. static struct iwl_nvm_data *
  265. iwl_parse_nvm_sections(struct iwl_mvm *mvm)
  266. {
  267. struct iwl_nvm_section *sections = mvm->nvm_sections;
  268. const __le16 *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku;
  269. bool lar_enabled;
  270. /* Checking for required sections */
  271. if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  272. if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
  273. !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) {
  274. IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n");
  275. return NULL;
  276. }
  277. } else {
  278. /* SW and REGULATORY sections are mandatory */
  279. if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
  280. !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) {
  281. IWL_ERR(mvm,
  282. "Can't parse empty family 8000 OTP/NVM sections\n");
  283. return NULL;
  284. }
  285. /* MAC_OVERRIDE or at least HW section must exist */
  286. if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data &&
  287. !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) {
  288. IWL_ERR(mvm,
  289. "Can't parse mac_address, empty sections\n");
  290. return NULL;
  291. }
  292. /* PHY_SKU section is mandatory in B0 */
  293. if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) {
  294. IWL_ERR(mvm,
  295. "Can't parse phy_sku in B0, empty sections\n");
  296. return NULL;
  297. }
  298. }
  299. if (WARN_ON(!mvm->cfg))
  300. return NULL;
  301. hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data;
  302. sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data;
  303. calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data;
  304. regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data;
  305. mac_override =
  306. (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data;
  307. phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data;
  308. lar_enabled = !iwlwifi_mod_params.lar_disable &&
  309. fw_has_capa(&mvm->fw->ucode_capa,
  310. IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
  311. return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib,
  312. regulatory, mac_override, phy_sku,
  313. mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant,
  314. lar_enabled);
  315. }
  316. #define MAX_NVM_FILE_LEN 16384
  317. /*
  318. * Reads external NVM from a file into mvm->nvm_sections
  319. *
  320. * HOW TO CREATE THE NVM FILE FORMAT:
  321. * ------------------------------
  322. * 1. create hex file, format:
  323. * 3800 -> header
  324. * 0000 -> header
  325. * 5a40 -> data
  326. *
  327. * rev - 6 bit (word1)
  328. * len - 10 bit (word1)
  329. * id - 4 bit (word2)
  330. * rsv - 12 bit (word2)
  331. *
  332. * 2. flip 8bits with 8 bits per line to get the right NVM file format
  333. *
  334. * 3. create binary file from the hex file
  335. *
  336. * 4. save as "iNVM_xxx.bin" under /lib/firmware
  337. */
  338. static int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm)
  339. {
  340. int ret, section_size;
  341. u16 section_id;
  342. const struct firmware *fw_entry;
  343. const struct {
  344. __le16 word1;
  345. __le16 word2;
  346. u8 data[];
  347. } *file_sec;
  348. const u8 *eof;
  349. u8 *temp;
  350. int max_section_size;
  351. const __le32 *dword_buff;
  352. #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
  353. #define NVM_WORD2_ID(x) (x >> 12)
  354. #define NVM_WORD2_LEN_FAMILY_8000(x) (2 * ((x & 0xFF) << 8 | x >> 8))
  355. #define NVM_WORD1_ID_FAMILY_8000(x) (x >> 4)
  356. #define NVM_HEADER_0 (0x2A504C54)
  357. #define NVM_HEADER_1 (0x4E564D2A)
  358. #define NVM_HEADER_SIZE (4 * sizeof(u32))
  359. IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n");
  360. /* Maximal size depends on HW family and step */
  361. if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
  362. max_section_size = IWL_MAX_NVM_SECTION_SIZE;
  363. else
  364. max_section_size = IWL_MAX_NVM_8000_SECTION_SIZE;
  365. /*
  366. * Obtain NVM image via request_firmware. Since we already used
  367. * request_firmware_nowait() for the firmware binary load and only
  368. * get here after that we assume the NVM request can be satisfied
  369. * synchronously.
  370. */
  371. ret = request_firmware(&fw_entry, mvm->nvm_file_name,
  372. mvm->trans->dev);
  373. if (ret) {
  374. IWL_ERR(mvm, "ERROR: %s isn't available %d\n",
  375. mvm->nvm_file_name, ret);
  376. return ret;
  377. }
  378. IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n",
  379. mvm->nvm_file_name, fw_entry->size);
  380. if (fw_entry->size > MAX_NVM_FILE_LEN) {
  381. IWL_ERR(mvm, "NVM file too large\n");
  382. ret = -EINVAL;
  383. goto out;
  384. }
  385. eof = fw_entry->data + fw_entry->size;
  386. dword_buff = (__le32 *)fw_entry->data;
  387. /* some NVM file will contain a header.
  388. * The header is identified by 2 dwords header as follow:
  389. * dword[0] = 0x2A504C54
  390. * dword[1] = 0x4E564D2A
  391. *
  392. * This header must be skipped when providing the NVM data to the FW.
  393. */
  394. if (fw_entry->size > NVM_HEADER_SIZE &&
  395. dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
  396. dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
  397. file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
  398. IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
  399. IWL_INFO(mvm, "NVM Manufacturing date %08X\n",
  400. le32_to_cpu(dword_buff[3]));
  401. /* nvm file validation, dword_buff[2] holds the file version */
  402. if ((CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP &&
  403. le32_to_cpu(dword_buff[2]) < 0xE4A) ||
  404. (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP &&
  405. le32_to_cpu(dword_buff[2]) >= 0xE4A)) {
  406. ret = -EFAULT;
  407. goto out;
  408. }
  409. } else {
  410. file_sec = (void *)fw_entry->data;
  411. }
  412. while (true) {
  413. if (file_sec->data > eof) {
  414. IWL_ERR(mvm,
  415. "ERROR - NVM file too short for section header\n");
  416. ret = -EINVAL;
  417. break;
  418. }
  419. /* check for EOF marker */
  420. if (!file_sec->word1 && !file_sec->word2) {
  421. ret = 0;
  422. break;
  423. }
  424. if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  425. section_size =
  426. 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
  427. section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
  428. } else {
  429. section_size = 2 * NVM_WORD2_LEN_FAMILY_8000(
  430. le16_to_cpu(file_sec->word2));
  431. section_id = NVM_WORD1_ID_FAMILY_8000(
  432. le16_to_cpu(file_sec->word1));
  433. }
  434. if (section_size > max_section_size) {
  435. IWL_ERR(mvm, "ERROR - section too large (%d)\n",
  436. section_size);
  437. ret = -EINVAL;
  438. break;
  439. }
  440. if (!section_size) {
  441. IWL_ERR(mvm, "ERROR - section empty\n");
  442. ret = -EINVAL;
  443. break;
  444. }
  445. if (file_sec->data + section_size > eof) {
  446. IWL_ERR(mvm,
  447. "ERROR - NVM file too short for section (%d bytes)\n",
  448. section_size);
  449. ret = -EINVAL;
  450. break;
  451. }
  452. if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
  453. "Invalid NVM section ID %d\n", section_id)) {
  454. ret = -EINVAL;
  455. break;
  456. }
  457. temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
  458. if (!temp) {
  459. ret = -ENOMEM;
  460. break;
  461. }
  462. iwl_mvm_nvm_fixups(mvm, section_id, temp, section_size);
  463. kfree(mvm->nvm_sections[section_id].data);
  464. mvm->nvm_sections[section_id].data = temp;
  465. mvm->nvm_sections[section_id].length = section_size;
  466. /* advance to the next section */
  467. file_sec = (void *)(file_sec->data + section_size);
  468. }
  469. out:
  470. release_firmware(fw_entry);
  471. return ret;
  472. }
  473. /* Loads the NVM data stored in mvm->nvm_sections into the NIC */
  474. int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm)
  475. {
  476. int i, ret = 0;
  477. struct iwl_nvm_section *sections = mvm->nvm_sections;
  478. IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n");
  479. for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) {
  480. if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length)
  481. continue;
  482. ret = iwl_nvm_write_section(mvm, i, sections[i].data,
  483. sections[i].length);
  484. if (ret < 0) {
  485. IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret);
  486. break;
  487. }
  488. }
  489. return ret;
  490. }
  491. int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic)
  492. {
  493. int ret, section;
  494. u32 size_read = 0;
  495. u8 *nvm_buffer, *temp;
  496. const char *nvm_file_B = mvm->cfg->default_nvm_file_B_step;
  497. const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step;
  498. if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS))
  499. return -EINVAL;
  500. /* load NVM values from nic */
  501. if (read_nvm_from_nic) {
  502. /* Read From FW NVM */
  503. IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n");
  504. nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size,
  505. GFP_KERNEL);
  506. if (!nvm_buffer)
  507. return -ENOMEM;
  508. for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) {
  509. /* we override the constness for initial read */
  510. ret = iwl_nvm_read_section(mvm, section, nvm_buffer,
  511. size_read);
  512. if (ret < 0)
  513. continue;
  514. size_read += ret;
  515. temp = kmemdup(nvm_buffer, ret, GFP_KERNEL);
  516. if (!temp) {
  517. ret = -ENOMEM;
  518. break;
  519. }
  520. iwl_mvm_nvm_fixups(mvm, section, temp, ret);
  521. mvm->nvm_sections[section].data = temp;
  522. mvm->nvm_sections[section].length = ret;
  523. #ifdef CONFIG_IWLWIFI_DEBUGFS
  524. switch (section) {
  525. case NVM_SECTION_TYPE_SW:
  526. mvm->nvm_sw_blob.data = temp;
  527. mvm->nvm_sw_blob.size = ret;
  528. break;
  529. case NVM_SECTION_TYPE_CALIBRATION:
  530. mvm->nvm_calib_blob.data = temp;
  531. mvm->nvm_calib_blob.size = ret;
  532. break;
  533. case NVM_SECTION_TYPE_PRODUCTION:
  534. mvm->nvm_prod_blob.data = temp;
  535. mvm->nvm_prod_blob.size = ret;
  536. break;
  537. case NVM_SECTION_TYPE_PHY_SKU:
  538. mvm->nvm_phy_sku_blob.data = temp;
  539. mvm->nvm_phy_sku_blob.size = ret;
  540. break;
  541. default:
  542. if (section == mvm->cfg->nvm_hw_section_num) {
  543. mvm->nvm_hw_blob.data = temp;
  544. mvm->nvm_hw_blob.size = ret;
  545. break;
  546. }
  547. }
  548. #endif
  549. }
  550. if (!size_read)
  551. IWL_ERR(mvm, "OTP is blank\n");
  552. kfree(nvm_buffer);
  553. }
  554. /* Only if PNVM selected in the mod param - load external NVM */
  555. if (mvm->nvm_file_name) {
  556. /* read External NVM file from the mod param */
  557. ret = iwl_mvm_read_external_nvm(mvm);
  558. if (ret) {
  559. /* choose the nvm_file name according to the
  560. * HW step
  561. */
  562. if (CSR_HW_REV_STEP(mvm->trans->hw_rev) ==
  563. SILICON_B_STEP)
  564. mvm->nvm_file_name = nvm_file_B;
  565. else
  566. mvm->nvm_file_name = nvm_file_C;
  567. if ((ret == -EFAULT || ret == -ENOENT) &&
  568. mvm->nvm_file_name) {
  569. /* in case nvm file was failed try again */
  570. ret = iwl_mvm_read_external_nvm(mvm);
  571. if (ret)
  572. return ret;
  573. } else {
  574. return ret;
  575. }
  576. }
  577. }
  578. /* parse the relevant nvm sections */
  579. mvm->nvm_data = iwl_parse_nvm_sections(mvm);
  580. if (!mvm->nvm_data)
  581. return -ENODATA;
  582. IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n",
  583. mvm->nvm_data->nvm_version);
  584. return 0;
  585. }
  586. struct iwl_mcc_update_resp *
  587. iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
  588. enum iwl_mcc_source src_id)
  589. {
  590. struct iwl_mcc_update_cmd mcc_update_cmd = {
  591. .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]),
  592. .source_id = (u8)src_id,
  593. };
  594. struct iwl_mcc_update_resp *resp_cp;
  595. struct iwl_rx_packet *pkt;
  596. struct iwl_host_cmd cmd = {
  597. .id = MCC_UPDATE_CMD,
  598. .flags = CMD_WANT_SKB,
  599. .data = { &mcc_update_cmd },
  600. };
  601. int ret;
  602. u32 status;
  603. int resp_len, n_channels;
  604. u16 mcc;
  605. bool resp_v2 = fw_has_capa(&mvm->fw->ucode_capa,
  606. IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V2);
  607. if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
  608. return ERR_PTR(-EOPNOTSUPP);
  609. cmd.len[0] = sizeof(struct iwl_mcc_update_cmd);
  610. if (!resp_v2)
  611. cmd.len[0] = sizeof(struct iwl_mcc_update_cmd_v1);
  612. IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n",
  613. alpha2[0], alpha2[1], src_id);
  614. ret = iwl_mvm_send_cmd(mvm, &cmd);
  615. if (ret)
  616. return ERR_PTR(ret);
  617. pkt = cmd.resp_pkt;
  618. /* Extract MCC response */
  619. if (resp_v2) {
  620. struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data;
  621. n_channels = __le32_to_cpu(mcc_resp->n_channels);
  622. resp_len = sizeof(struct iwl_mcc_update_resp) +
  623. n_channels * sizeof(__le32);
  624. resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL);
  625. } else {
  626. struct iwl_mcc_update_resp_v1 *mcc_resp_v1 = (void *)pkt->data;
  627. n_channels = __le32_to_cpu(mcc_resp_v1->n_channels);
  628. resp_len = sizeof(struct iwl_mcc_update_resp) +
  629. n_channels * sizeof(__le32);
  630. resp_cp = kzalloc(resp_len, GFP_KERNEL);
  631. if (resp_cp) {
  632. resp_cp->status = mcc_resp_v1->status;
  633. resp_cp->mcc = mcc_resp_v1->mcc;
  634. resp_cp->cap = mcc_resp_v1->cap;
  635. resp_cp->source_id = mcc_resp_v1->source_id;
  636. resp_cp->n_channels = mcc_resp_v1->n_channels;
  637. memcpy(resp_cp->channels, mcc_resp_v1->channels,
  638. n_channels * sizeof(__le32));
  639. }
  640. }
  641. if (!resp_cp) {
  642. ret = -ENOMEM;
  643. goto exit;
  644. }
  645. status = le32_to_cpu(resp_cp->status);
  646. mcc = le16_to_cpu(resp_cp->mcc);
  647. /* W/A for a FW/NVM issue - returns 0x00 for the world domain */
  648. if (mcc == 0) {
  649. mcc = 0x3030; /* "00" - world */
  650. resp_cp->mcc = cpu_to_le16(mcc);
  651. }
  652. IWL_DEBUG_LAR(mvm,
  653. "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n",
  654. status, mcc, mcc >> 8, mcc & 0xff,
  655. !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels);
  656. exit:
  657. iwl_free_resp(&cmd);
  658. if (ret)
  659. return ERR_PTR(ret);
  660. return resp_cp;
  661. }
  662. #ifdef CONFIG_ACPI
  663. #define WRD_METHOD "WRDD"
  664. #define WRDD_WIFI (0x07)
  665. #define WRDD_WIGIG (0x10)
  666. static u32 iwl_mvm_wrdd_get_mcc(struct iwl_mvm *mvm, union acpi_object *wrdd)
  667. {
  668. union acpi_object *mcc_pkg, *domain_type, *mcc_value;
  669. u32 i;
  670. if (wrdd->type != ACPI_TYPE_PACKAGE ||
  671. wrdd->package.count < 2 ||
  672. wrdd->package.elements[0].type != ACPI_TYPE_INTEGER ||
  673. wrdd->package.elements[0].integer.value != 0) {
  674. IWL_DEBUG_LAR(mvm, "Unsupported wrdd structure\n");
  675. return 0;
  676. }
  677. for (i = 1 ; i < wrdd->package.count ; ++i) {
  678. mcc_pkg = &wrdd->package.elements[i];
  679. if (mcc_pkg->type != ACPI_TYPE_PACKAGE ||
  680. mcc_pkg->package.count < 2 ||
  681. mcc_pkg->package.elements[0].type != ACPI_TYPE_INTEGER ||
  682. mcc_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) {
  683. mcc_pkg = NULL;
  684. continue;
  685. }
  686. domain_type = &mcc_pkg->package.elements[0];
  687. if (domain_type->integer.value == WRDD_WIFI)
  688. break;
  689. mcc_pkg = NULL;
  690. }
  691. if (mcc_pkg) {
  692. mcc_value = &mcc_pkg->package.elements[1];
  693. return mcc_value->integer.value;
  694. }
  695. return 0;
  696. }
  697. static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc)
  698. {
  699. acpi_handle root_handle;
  700. acpi_handle handle;
  701. struct acpi_buffer wrdd = {ACPI_ALLOCATE_BUFFER, NULL};
  702. acpi_status status;
  703. u32 mcc_val;
  704. root_handle = ACPI_HANDLE(mvm->dev);
  705. if (!root_handle) {
  706. IWL_DEBUG_LAR(mvm,
  707. "Could not retrieve root port ACPI handle\n");
  708. return -ENOENT;
  709. }
  710. /* Get the method's handle */
  711. status = acpi_get_handle(root_handle, (acpi_string)WRD_METHOD, &handle);
  712. if (ACPI_FAILURE(status)) {
  713. IWL_DEBUG_LAR(mvm, "WRD method not found\n");
  714. return -ENOENT;
  715. }
  716. /* Call WRDD with no arguments */
  717. status = acpi_evaluate_object(handle, NULL, NULL, &wrdd);
  718. if (ACPI_FAILURE(status)) {
  719. IWL_DEBUG_LAR(mvm, "WRDC invocation failed (0x%x)\n", status);
  720. return -ENOENT;
  721. }
  722. mcc_val = iwl_mvm_wrdd_get_mcc(mvm, wrdd.pointer);
  723. kfree(wrdd.pointer);
  724. if (!mcc_val)
  725. return -ENOENT;
  726. mcc[0] = (mcc_val >> 8) & 0xff;
  727. mcc[1] = mcc_val & 0xff;
  728. mcc[2] = '\0';
  729. return 0;
  730. }
  731. #else /* CONFIG_ACPI */
  732. static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc)
  733. {
  734. return -ENOENT;
  735. }
  736. #endif
  737. int iwl_mvm_init_mcc(struct iwl_mvm *mvm)
  738. {
  739. bool tlv_lar;
  740. bool nvm_lar;
  741. int retval;
  742. struct ieee80211_regdomain *regd;
  743. char mcc[3];
  744. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
  745. tlv_lar = fw_has_capa(&mvm->fw->ucode_capa,
  746. IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
  747. nvm_lar = mvm->nvm_data->lar_enabled;
  748. if (tlv_lar != nvm_lar)
  749. IWL_INFO(mvm,
  750. "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n",
  751. tlv_lar ? "enabled" : "disabled",
  752. nvm_lar ? "enabled" : "disabled");
  753. }
  754. if (!iwl_mvm_is_lar_supported(mvm))
  755. return 0;
  756. /*
  757. * try to replay the last set MCC to FW. If it doesn't exist,
  758. * queue an update to cfg80211 to retrieve the default alpha2 from FW.
  759. */
  760. retval = iwl_mvm_init_fw_regd(mvm);
  761. if (retval != -ENOENT)
  762. return retval;
  763. /*
  764. * Driver regulatory hint for initial update, this also informs the
  765. * firmware we support wifi location updates.
  766. * Disallow scans that might crash the FW while the LAR regdomain
  767. * is not set.
  768. */
  769. mvm->lar_regdom_set = false;
  770. regd = iwl_mvm_get_current_regdomain(mvm, NULL);
  771. if (IS_ERR_OR_NULL(regd))
  772. return -EIO;
  773. if (iwl_mvm_is_wifi_mcc_supported(mvm) &&
  774. !iwl_mvm_get_bios_mcc(mvm, mcc)) {
  775. kfree(regd);
  776. regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc,
  777. MCC_SOURCE_BIOS, NULL);
  778. if (IS_ERR_OR_NULL(regd))
  779. return -EIO;
  780. }
  781. retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd);
  782. kfree(regd);
  783. return retval;
  784. }
  785. void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm,
  786. struct iwl_rx_cmd_buffer *rxb)
  787. {
  788. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  789. struct iwl_mcc_chub_notif *notif = (void *)pkt->data;
  790. enum iwl_mcc_source src;
  791. char mcc[3];
  792. struct ieee80211_regdomain *regd;
  793. lockdep_assert_held(&mvm->mutex);
  794. if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
  795. return;
  796. mcc[0] = notif->mcc >> 8;
  797. mcc[1] = notif->mcc & 0xff;
  798. mcc[2] = '\0';
  799. src = notif->source_id;
  800. IWL_DEBUG_LAR(mvm,
  801. "RX: received chub update mcc cmd (mcc '%s' src %d)\n",
  802. mcc, src);
  803. regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL);
  804. if (IS_ERR_OR_NULL(regd))
  805. return;
  806. regulatory_set_wiphy_regd(mvm->hw->wiphy, regd);
  807. kfree(regd);
  808. }