sdio.c 116 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/atomic.h>
  18. #include <linux/kernel.h>
  19. #include <linux/kthread.h>
  20. #include <linux/printk.h>
  21. #include <linux/pci_ids.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/sched.h>
  25. #include <linux/mmc/sdio.h>
  26. #include <linux/mmc/sdio_ids.h>
  27. #include <linux/mmc/sdio_func.h>
  28. #include <linux/mmc/card.h>
  29. #include <linux/semaphore.h>
  30. #include <linux/firmware.h>
  31. #include <linux/module.h>
  32. #include <linux/bcma/bcma.h>
  33. #include <linux/debugfs.h>
  34. #include <linux/vmalloc.h>
  35. #include <asm/unaligned.h>
  36. #include <defs.h>
  37. #include <brcmu_wifi.h>
  38. #include <brcmu_utils.h>
  39. #include <brcm_hw_ids.h>
  40. #include <soc.h>
  41. #include "sdio.h"
  42. #include "chip.h"
  43. #include "firmware.h"
  44. #include "core.h"
  45. #include "common.h"
  46. #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
  47. #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
  48. #ifdef DEBUG
  49. #define BRCMF_TRAP_INFO_SIZE 80
  50. #define CBUF_LEN (128)
  51. /* Device console log buffer state */
  52. #define CONSOLE_BUFFER_MAX 2024
  53. struct rte_log_le {
  54. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  55. __le32 buf_size;
  56. __le32 idx;
  57. char *_buf_compat; /* Redundant pointer for backward compat. */
  58. };
  59. struct rte_console {
  60. /* Virtual UART
  61. * When there is no UART (e.g. Quickturn),
  62. * the host should write a complete
  63. * input line directly into cbuf and then write
  64. * the length into vcons_in.
  65. * This may also be used when there is a real UART
  66. * (at risk of conflicting with
  67. * the real UART). vcons_out is currently unused.
  68. */
  69. uint vcons_in;
  70. uint vcons_out;
  71. /* Output (logging) buffer
  72. * Console output is written to a ring buffer log_buf at index log_idx.
  73. * The host may read the output when it sees log_idx advance.
  74. * Output will be lost if the output wraps around faster than the host
  75. * polls.
  76. */
  77. struct rte_log_le log_le;
  78. /* Console input line buffer
  79. * Characters are read one at a time into cbuf
  80. * until <CR> is received, then
  81. * the buffer is processed as a command line.
  82. * Also used for virtual UART.
  83. */
  84. uint cbuf_idx;
  85. char cbuf[CBUF_LEN];
  86. };
  87. #endif /* DEBUG */
  88. #include <chipcommon.h>
  89. #include "bus.h"
  90. #include "debug.h"
  91. #include "tracepoint.h"
  92. #define TXQLEN 2048 /* bulk tx queue length */
  93. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  94. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  95. #define PRIOMASK 7
  96. #define TXRETRIES 2 /* # of retries for tx frames */
  97. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  98. one scheduling */
  99. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  100. one scheduling */
  101. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  102. #define MEMBLOCK 2048 /* Block size used for downloading
  103. of dongle image */
  104. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  105. biggest possible glom */
  106. #define BRCMF_FIRSTREAD (1 << 6)
  107. #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
  108. /* SBSDIO_DEVICE_CTL */
  109. /* 1: device will assert busy signal when receiving CMD53 */
  110. #define SBSDIO_DEVCTL_SETBUSY 0x01
  111. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  112. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  113. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  114. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  115. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  116. * sdio bus power cycle to clear (rev 9) */
  117. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  118. /* Force SD->SB reset mapping (rev 11) */
  119. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  120. /* Determined by CoreControl bit */
  121. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  122. /* Force backplane reset */
  123. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  124. /* Force no backplane reset */
  125. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  126. /* direct(mapped) cis space */
  127. /* MAPPED common CIS address */
  128. #define SBSDIO_CIS_BASE_COMMON 0x1000
  129. /* maximum bytes in one CIS */
  130. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  131. /* cis offset addr is < 17 bits */
  132. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  133. /* manfid tuple length, include tuple, link bytes */
  134. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  135. #define CORE_BUS_REG(base, field) \
  136. (base + offsetof(struct sdpcmd_regs, field))
  137. /* SDIO function 1 register CHIPCLKCSR */
  138. /* Force ALP request to backplane */
  139. #define SBSDIO_FORCE_ALP 0x01
  140. /* Force HT request to backplane */
  141. #define SBSDIO_FORCE_HT 0x02
  142. /* Force ILP request to backplane */
  143. #define SBSDIO_FORCE_ILP 0x04
  144. /* Make ALP ready (power up xtal) */
  145. #define SBSDIO_ALP_AVAIL_REQ 0x08
  146. /* Make HT ready (power up PLL) */
  147. #define SBSDIO_HT_AVAIL_REQ 0x10
  148. /* Squelch clock requests from HW */
  149. #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
  150. /* Status: ALP is ready */
  151. #define SBSDIO_ALP_AVAIL 0x40
  152. /* Status: HT is ready */
  153. #define SBSDIO_HT_AVAIL 0x80
  154. #define SBSDIO_CSR_MASK 0x1F
  155. #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
  156. #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
  157. #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
  158. #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
  159. #define SBSDIO_CLKAV(regval, alponly) \
  160. (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
  161. /* intstatus */
  162. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  163. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  164. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  165. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  166. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  167. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  168. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  169. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  170. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  171. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  172. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  173. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  174. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  175. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  176. #define I_PC (1 << 10) /* descriptor error */
  177. #define I_PD (1 << 11) /* data error */
  178. #define I_DE (1 << 12) /* Descriptor protocol Error */
  179. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  180. #define I_RO (1 << 14) /* Receive fifo Overflow */
  181. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  182. #define I_RI (1 << 16) /* Receive Interrupt */
  183. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  184. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  185. #define I_XI (1 << 24) /* Transmit Interrupt */
  186. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  187. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  188. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  189. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  190. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  191. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  192. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  193. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  194. #define I_DMA (I_RI | I_XI | I_ERRORS)
  195. /* corecontrol */
  196. #define CC_CISRDY (1 << 0) /* CIS Ready */
  197. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  198. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  199. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  200. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  201. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  202. /* SDA_FRAMECTRL */
  203. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  204. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  205. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  206. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  207. /*
  208. * Software allocation of To SB Mailbox resources
  209. */
  210. /* tosbmailbox bits corresponding to intstatus bits */
  211. #define SMB_NAK (1 << 0) /* Frame NAK */
  212. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  213. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  214. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  215. /* tosbmailboxdata */
  216. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  217. /*
  218. * Software allocation of To Host Mailbox resources
  219. */
  220. /* intstatus bits */
  221. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  222. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  223. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  224. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  225. /* tohostmailboxdata */
  226. #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
  227. #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
  228. #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
  229. #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
  230. #define HMB_DATA_FCDATA_MASK 0xff000000
  231. #define HMB_DATA_FCDATA_SHIFT 24
  232. #define HMB_DATA_VERSION_MASK 0x00ff0000
  233. #define HMB_DATA_VERSION_SHIFT 16
  234. /*
  235. * Software-defined protocol header
  236. */
  237. /* Current protocol version */
  238. #define SDPCM_PROT_VERSION 4
  239. /*
  240. * Shared structure between dongle and the host.
  241. * The structure contains pointers to trap or assert information.
  242. */
  243. #define SDPCM_SHARED_VERSION 0x0003
  244. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  245. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  246. #define SDPCM_SHARED_ASSERT 0x0200
  247. #define SDPCM_SHARED_TRAP 0x0400
  248. /* Space for header read, limit for data packets */
  249. #define MAX_HDR_READ (1 << 6)
  250. #define MAX_RX_DATASZ 2048
  251. /* Bump up limit on waiting for HT to account for first startup;
  252. * if the image is doing a CRC calculation before programming the PMU
  253. * for HT availability, it could take a couple hundred ms more, so
  254. * max out at a 1 second (1000000us).
  255. */
  256. #undef PMU_MAX_TRANSITION_DLY
  257. #define PMU_MAX_TRANSITION_DLY 1000000
  258. /* Value for ChipClockCSR during initial setup */
  259. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  260. SBSDIO_ALP_AVAIL_REQ)
  261. /* Flags for SDH calls */
  262. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  263. #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
  264. * when idle
  265. */
  266. #define BRCMF_IDLE_INTERVAL 1
  267. #define KSO_WAIT_US 50
  268. #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
  269. /*
  270. * Conversion of 802.1D priority to precedence level
  271. */
  272. static uint prio2prec(u32 prio)
  273. {
  274. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  275. (prio^2) : prio;
  276. }
  277. #ifdef DEBUG
  278. /* Device console log buffer state */
  279. struct brcmf_console {
  280. uint count; /* Poll interval msec counter */
  281. uint log_addr; /* Log struct address (fixed) */
  282. struct rte_log_le log_le; /* Log struct (host copy) */
  283. uint bufsize; /* Size of log buffer */
  284. u8 *buf; /* Log buffer (host copy) */
  285. uint last; /* Last buffer read index */
  286. };
  287. struct brcmf_trap_info {
  288. __le32 type;
  289. __le32 epc;
  290. __le32 cpsr;
  291. __le32 spsr;
  292. __le32 r0; /* a1 */
  293. __le32 r1; /* a2 */
  294. __le32 r2; /* a3 */
  295. __le32 r3; /* a4 */
  296. __le32 r4; /* v1 */
  297. __le32 r5; /* v2 */
  298. __le32 r6; /* v3 */
  299. __le32 r7; /* v4 */
  300. __le32 r8; /* v5 */
  301. __le32 r9; /* sb/v6 */
  302. __le32 r10; /* sl/v7 */
  303. __le32 r11; /* fp/v8 */
  304. __le32 r12; /* ip */
  305. __le32 r13; /* sp */
  306. __le32 r14; /* lr */
  307. __le32 pc; /* r15 */
  308. };
  309. #endif /* DEBUG */
  310. struct sdpcm_shared {
  311. u32 flags;
  312. u32 trap_addr;
  313. u32 assert_exp_addr;
  314. u32 assert_file_addr;
  315. u32 assert_line;
  316. u32 console_addr; /* Address of struct rte_console */
  317. u32 msgtrace_addr;
  318. u8 tag[32];
  319. u32 brpt_addr;
  320. };
  321. struct sdpcm_shared_le {
  322. __le32 flags;
  323. __le32 trap_addr;
  324. __le32 assert_exp_addr;
  325. __le32 assert_file_addr;
  326. __le32 assert_line;
  327. __le32 console_addr; /* Address of struct rte_console */
  328. __le32 msgtrace_addr;
  329. u8 tag[32];
  330. __le32 brpt_addr;
  331. };
  332. /* dongle SDIO bus specific header info */
  333. struct brcmf_sdio_hdrinfo {
  334. u8 seq_num;
  335. u8 channel;
  336. u16 len;
  337. u16 len_left;
  338. u16 len_nxtfrm;
  339. u8 dat_offset;
  340. bool lastfrm;
  341. u16 tail_pad;
  342. };
  343. /*
  344. * hold counter variables
  345. */
  346. struct brcmf_sdio_count {
  347. uint intrcount; /* Count of device interrupt callbacks */
  348. uint lastintrs; /* Count as of last watchdog timer */
  349. uint pollcnt; /* Count of active polls */
  350. uint regfails; /* Count of R_REG failures */
  351. uint tx_sderrs; /* Count of tx attempts with sd errors */
  352. uint fcqueued; /* Tx packets that got queued */
  353. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  354. uint rx_toolong; /* Receive frames too long to receive */
  355. uint rxc_errors; /* SDIO errors when reading control frames */
  356. uint rx_hdrfail; /* SDIO errors on header reads */
  357. uint rx_badhdr; /* Bad received headers (roosync?) */
  358. uint rx_badseq; /* Mismatched rx sequence number */
  359. uint fc_rcvd; /* Number of flow-control events received */
  360. uint fc_xoff; /* Number which turned on flow-control */
  361. uint fc_xon; /* Number which turned off flow-control */
  362. uint rxglomfail; /* Failed deglom attempts */
  363. uint rxglomframes; /* Number of glom frames (superframes) */
  364. uint rxglompkts; /* Number of packets from glom frames */
  365. uint f2rxhdrs; /* Number of header reads */
  366. uint f2rxdata; /* Number of frame data reads */
  367. uint f2txdata; /* Number of f2 frame writes */
  368. uint f1regdata; /* Number of f1 register accesses */
  369. uint tickcnt; /* Number of watchdog been schedule */
  370. ulong tx_ctlerrs; /* Err of sending ctrl frames */
  371. ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
  372. ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
  373. ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
  374. ulong rx_readahead_cnt; /* packets where header read-ahead was used */
  375. };
  376. /* misc chip info needed by some of the routines */
  377. /* Private data for SDIO bus interaction */
  378. struct brcmf_sdio {
  379. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  380. struct brcmf_chip *ci; /* Chip info struct */
  381. u32 hostintmask; /* Copy of Host Interrupt Mask */
  382. atomic_t intstatus; /* Intstatus bits (events) pending */
  383. atomic_t fcstate; /* State of dongle flow-control */
  384. uint blocksize; /* Block size of SDIO transfers */
  385. uint roundup; /* Max roundup limit */
  386. struct pktq txq; /* Queue length used for flow-control */
  387. u8 flowcontrol; /* per prio flow control bitmask */
  388. u8 tx_seq; /* Transmit sequence number (next) */
  389. u8 tx_max; /* Maximum transmit sequence allowed */
  390. u8 *hdrbuf; /* buffer for handling rx frame */
  391. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  392. u8 rx_seq; /* Receive sequence number (expected) */
  393. struct brcmf_sdio_hdrinfo cur_read;
  394. /* info of current read frame */
  395. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  396. bool rxpending; /* Data frame pending in dongle */
  397. uint rxbound; /* Rx frames to read before resched */
  398. uint txbound; /* Tx frames to send before resched */
  399. uint txminmax;
  400. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  401. struct sk_buff_head glom; /* Packet list for glommed superframe */
  402. u8 *rxbuf; /* Buffer for receiving control packets */
  403. uint rxblen; /* Allocated length of rxbuf */
  404. u8 *rxctl; /* Aligned pointer into rxbuf */
  405. u8 *rxctl_orig; /* pointer for freeing rxctl */
  406. uint rxlen; /* Length of valid data in buffer */
  407. spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
  408. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  409. bool intr; /* Use interrupts */
  410. bool poll; /* Use polling */
  411. atomic_t ipend; /* Device interrupt is pending */
  412. uint spurious; /* Count of spurious interrupts */
  413. uint pollrate; /* Ticks between device polls */
  414. uint polltick; /* Tick counter */
  415. #ifdef DEBUG
  416. uint console_interval;
  417. struct brcmf_console console; /* Console output polling support */
  418. uint console_addr; /* Console address from shared struct */
  419. #endif /* DEBUG */
  420. uint clkstate; /* State of sd and backplane clock(s) */
  421. s32 idletime; /* Control for activity timeout */
  422. s32 idlecount; /* Activity timeout counter */
  423. s32 idleclock; /* How to set bus driver when idle */
  424. bool rxflow_mode; /* Rx flow control mode */
  425. bool rxflow; /* Is rx flow control on */
  426. bool alp_only; /* Don't use HT clock (ALP only) */
  427. u8 *ctrl_frame_buf;
  428. u16 ctrl_frame_len;
  429. bool ctrl_frame_stat;
  430. int ctrl_frame_err;
  431. spinlock_t txq_lock; /* protect bus->txq */
  432. wait_queue_head_t ctrl_wait;
  433. wait_queue_head_t dcmd_resp_wait;
  434. struct timer_list timer;
  435. struct completion watchdog_wait;
  436. struct task_struct *watchdog_tsk;
  437. bool wd_active;
  438. struct workqueue_struct *brcmf_wq;
  439. struct work_struct datawork;
  440. bool dpc_triggered;
  441. bool dpc_running;
  442. bool txoff; /* Transmit flow-controlled */
  443. struct brcmf_sdio_count sdcnt;
  444. bool sr_enabled; /* SaveRestore enabled */
  445. bool sleeping;
  446. u8 tx_hdrlen; /* sdio bus header length for tx packet */
  447. bool txglom; /* host tx glomming enable flag */
  448. u16 head_align; /* buffer pointer alignment */
  449. u16 sgentry_align; /* scatter-gather buffer alignment */
  450. };
  451. /* clkstate */
  452. #define CLK_NONE 0
  453. #define CLK_SDONLY 1
  454. #define CLK_PENDING 2
  455. #define CLK_AVAIL 3
  456. #ifdef DEBUG
  457. static int qcount[NUMPRIO];
  458. #endif /* DEBUG */
  459. #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  460. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  461. /* Limit on rounding up frames */
  462. static const uint max_roundup = 512;
  463. #define ALIGNMENT 4
  464. enum brcmf_sdio_frmtype {
  465. BRCMF_SDIO_FT_NORMAL,
  466. BRCMF_SDIO_FT_SUPER,
  467. BRCMF_SDIO_FT_SUB,
  468. };
  469. #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
  470. /* SDIO Pad drive strength to select value mappings */
  471. struct sdiod_drive_str {
  472. u8 strength; /* Pad Drive Strength in mA */
  473. u8 sel; /* Chip-specific select value */
  474. };
  475. /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
  476. static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
  477. {32, 0x6},
  478. {26, 0x7},
  479. {22, 0x4},
  480. {16, 0x5},
  481. {12, 0x2},
  482. {8, 0x3},
  483. {4, 0x0},
  484. {0, 0x1}
  485. };
  486. /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
  487. static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
  488. {6, 0x7},
  489. {5, 0x6},
  490. {4, 0x5},
  491. {3, 0x4},
  492. {2, 0x2},
  493. {1, 0x1},
  494. {0, 0x0}
  495. };
  496. /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
  497. static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
  498. {3, 0x3},
  499. {2, 0x2},
  500. {1, 0x1},
  501. {0, 0x0} };
  502. /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
  503. static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
  504. {16, 0x7},
  505. {12, 0x5},
  506. {8, 0x3},
  507. {4, 0x1}
  508. };
  509. BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
  510. BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
  511. "brcmfmac43241b0-sdio.txt");
  512. BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
  513. "brcmfmac43241b4-sdio.txt");
  514. BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
  515. "brcmfmac43241b5-sdio.txt");
  516. BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
  517. BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
  518. BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
  519. BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
  520. BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
  521. BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
  522. BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
  523. BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
  524. BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
  525. BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
  526. BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
  527. static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
  528. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
  529. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
  530. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
  531. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
  532. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
  533. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
  534. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
  535. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
  536. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
  537. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
  538. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
  539. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
  540. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
  541. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
  542. BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356)
  543. };
  544. static void pkt_align(struct sk_buff *p, int len, int align)
  545. {
  546. uint datalign;
  547. datalign = (unsigned long)(p->data);
  548. datalign = roundup(datalign, (align)) - datalign;
  549. if (datalign)
  550. skb_pull(p, datalign);
  551. __skb_trim(p, len);
  552. }
  553. /* To check if there's window offered */
  554. static bool data_ok(struct brcmf_sdio *bus)
  555. {
  556. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  557. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  558. }
  559. /*
  560. * Reads a register in the SDIO hardware block. This block occupies a series of
  561. * adresses on the 32 bit backplane bus.
  562. */
  563. static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
  564. {
  565. struct brcmf_core *core;
  566. int ret;
  567. core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  568. *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
  569. return ret;
  570. }
  571. static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
  572. {
  573. struct brcmf_core *core;
  574. int ret;
  575. core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  576. brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
  577. return ret;
  578. }
  579. static int
  580. brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
  581. {
  582. u8 wr_val = 0, rd_val, cmp_val, bmask;
  583. int err = 0;
  584. int try_cnt = 0;
  585. brcmf_dbg(TRACE, "Enter: on=%d\n", on);
  586. wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
  587. /* 1st KSO write goes to AOS wake up core if device is asleep */
  588. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  589. wr_val, &err);
  590. if (on) {
  591. /* device WAKEUP through KSO:
  592. * write bit 0 & read back until
  593. * both bits 0 (kso bit) & 1 (dev on status) are set
  594. */
  595. cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
  596. SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
  597. bmask = cmp_val;
  598. usleep_range(2000, 3000);
  599. } else {
  600. /* Put device to sleep, turn off KSO */
  601. cmp_val = 0;
  602. /* only check for bit0, bit1(dev on status) may not
  603. * get cleared right away
  604. */
  605. bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
  606. }
  607. do {
  608. /* reliable KSO bit set/clr:
  609. * the sdiod sleep write access is synced to PMU 32khz clk
  610. * just one write attempt may fail,
  611. * read it back until it matches written value
  612. */
  613. rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  614. &err);
  615. if (((rd_val & bmask) == cmp_val) && !err)
  616. break;
  617. udelay(KSO_WAIT_US);
  618. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  619. wr_val, &err);
  620. } while (try_cnt++ < MAX_KSO_ATTEMPTS);
  621. if (try_cnt > 2)
  622. brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
  623. rd_val, err);
  624. if (try_cnt > MAX_KSO_ATTEMPTS)
  625. brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
  626. return err;
  627. }
  628. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  629. /* Turn backplane clock on or off */
  630. static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
  631. {
  632. int err;
  633. u8 clkctl, clkreq, devctl;
  634. unsigned long timeout;
  635. brcmf_dbg(SDIO, "Enter\n");
  636. clkctl = 0;
  637. if (bus->sr_enabled) {
  638. bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
  639. return 0;
  640. }
  641. if (on) {
  642. /* Request HT Avail */
  643. clkreq =
  644. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  645. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  646. clkreq, &err);
  647. if (err) {
  648. brcmf_err("HT Avail request error: %d\n", err);
  649. return -EBADE;
  650. }
  651. /* Check current status */
  652. clkctl = brcmf_sdiod_regrb(bus->sdiodev,
  653. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  654. if (err) {
  655. brcmf_err("HT Avail read error: %d\n", err);
  656. return -EBADE;
  657. }
  658. /* Go to pending and await interrupt if appropriate */
  659. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  660. /* Allow only clock-available interrupt */
  661. devctl = brcmf_sdiod_regrb(bus->sdiodev,
  662. SBSDIO_DEVICE_CTL, &err);
  663. if (err) {
  664. brcmf_err("Devctl error setting CA: %d\n",
  665. err);
  666. return -EBADE;
  667. }
  668. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  669. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  670. devctl, &err);
  671. brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
  672. bus->clkstate = CLK_PENDING;
  673. return 0;
  674. } else if (bus->clkstate == CLK_PENDING) {
  675. /* Cancel CA-only interrupt filter */
  676. devctl = brcmf_sdiod_regrb(bus->sdiodev,
  677. SBSDIO_DEVICE_CTL, &err);
  678. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  679. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  680. devctl, &err);
  681. }
  682. /* Otherwise, wait here (polling) for HT Avail */
  683. timeout = jiffies +
  684. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  685. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  686. clkctl = brcmf_sdiod_regrb(bus->sdiodev,
  687. SBSDIO_FUNC1_CHIPCLKCSR,
  688. &err);
  689. if (time_after(jiffies, timeout))
  690. break;
  691. else
  692. usleep_range(5000, 10000);
  693. }
  694. if (err) {
  695. brcmf_err("HT Avail request error: %d\n", err);
  696. return -EBADE;
  697. }
  698. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  699. brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
  700. PMU_MAX_TRANSITION_DLY, clkctl);
  701. return -EBADE;
  702. }
  703. /* Mark clock available */
  704. bus->clkstate = CLK_AVAIL;
  705. brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
  706. #if defined(DEBUG)
  707. if (!bus->alp_only) {
  708. if (SBSDIO_ALPONLY(clkctl))
  709. brcmf_err("HT Clock should be on\n");
  710. }
  711. #endif /* defined (DEBUG) */
  712. } else {
  713. clkreq = 0;
  714. if (bus->clkstate == CLK_PENDING) {
  715. /* Cancel CA-only interrupt filter */
  716. devctl = brcmf_sdiod_regrb(bus->sdiodev,
  717. SBSDIO_DEVICE_CTL, &err);
  718. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  719. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  720. devctl, &err);
  721. }
  722. bus->clkstate = CLK_SDONLY;
  723. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  724. clkreq, &err);
  725. brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
  726. if (err) {
  727. brcmf_err("Failed access turning clock off: %d\n",
  728. err);
  729. return -EBADE;
  730. }
  731. }
  732. return 0;
  733. }
  734. /* Change idle/active SD state */
  735. static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
  736. {
  737. brcmf_dbg(SDIO, "Enter\n");
  738. if (on)
  739. bus->clkstate = CLK_SDONLY;
  740. else
  741. bus->clkstate = CLK_NONE;
  742. return 0;
  743. }
  744. /* Transition SD and backplane clock readiness */
  745. static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
  746. {
  747. #ifdef DEBUG
  748. uint oldstate = bus->clkstate;
  749. #endif /* DEBUG */
  750. brcmf_dbg(SDIO, "Enter\n");
  751. /* Early exit if we're already there */
  752. if (bus->clkstate == target)
  753. return 0;
  754. switch (target) {
  755. case CLK_AVAIL:
  756. /* Make sure SD clock is available */
  757. if (bus->clkstate == CLK_NONE)
  758. brcmf_sdio_sdclk(bus, true);
  759. /* Now request HT Avail on the backplane */
  760. brcmf_sdio_htclk(bus, true, pendok);
  761. break;
  762. case CLK_SDONLY:
  763. /* Remove HT request, or bring up SD clock */
  764. if (bus->clkstate == CLK_NONE)
  765. brcmf_sdio_sdclk(bus, true);
  766. else if (bus->clkstate == CLK_AVAIL)
  767. brcmf_sdio_htclk(bus, false, false);
  768. else
  769. brcmf_err("request for %d -> %d\n",
  770. bus->clkstate, target);
  771. break;
  772. case CLK_NONE:
  773. /* Make sure to remove HT request */
  774. if (bus->clkstate == CLK_AVAIL)
  775. brcmf_sdio_htclk(bus, false, false);
  776. /* Now remove the SD clock */
  777. brcmf_sdio_sdclk(bus, false);
  778. break;
  779. }
  780. #ifdef DEBUG
  781. brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
  782. #endif /* DEBUG */
  783. return 0;
  784. }
  785. static int
  786. brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
  787. {
  788. int err = 0;
  789. u8 clkcsr;
  790. brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
  791. (sleep ? "SLEEP" : "WAKE"),
  792. (bus->sleeping ? "SLEEP" : "WAKE"));
  793. /* If SR is enabled control bus state with KSO */
  794. if (bus->sr_enabled) {
  795. /* Done if we're already in the requested state */
  796. if (sleep == bus->sleeping)
  797. goto end;
  798. /* Going to sleep */
  799. if (sleep) {
  800. clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
  801. SBSDIO_FUNC1_CHIPCLKCSR,
  802. &err);
  803. if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
  804. brcmf_dbg(SDIO, "no clock, set ALP\n");
  805. brcmf_sdiod_regwb(bus->sdiodev,
  806. SBSDIO_FUNC1_CHIPCLKCSR,
  807. SBSDIO_ALP_AVAIL_REQ, &err);
  808. }
  809. err = brcmf_sdio_kso_control(bus, false);
  810. } else {
  811. err = brcmf_sdio_kso_control(bus, true);
  812. }
  813. if (err) {
  814. brcmf_err("error while changing bus sleep state %d\n",
  815. err);
  816. goto done;
  817. }
  818. }
  819. end:
  820. /* control clocks */
  821. if (sleep) {
  822. if (!bus->sr_enabled)
  823. brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
  824. } else {
  825. brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
  826. brcmf_sdio_wd_timer(bus, true);
  827. }
  828. bus->sleeping = sleep;
  829. brcmf_dbg(SDIO, "new state %s\n",
  830. (sleep ? "SLEEP" : "WAKE"));
  831. done:
  832. brcmf_dbg(SDIO, "Exit: err=%d\n", err);
  833. return err;
  834. }
  835. #ifdef DEBUG
  836. static inline bool brcmf_sdio_valid_shared_address(u32 addr)
  837. {
  838. return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
  839. }
  840. static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
  841. struct sdpcm_shared *sh)
  842. {
  843. u32 addr = 0;
  844. int rv;
  845. u32 shaddr = 0;
  846. struct sdpcm_shared_le sh_le;
  847. __le32 addr_le;
  848. sdio_claim_host(bus->sdiodev->func[1]);
  849. brcmf_sdio_bus_sleep(bus, false, false);
  850. /*
  851. * Read last word in socram to determine
  852. * address of sdpcm_shared structure
  853. */
  854. shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
  855. if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
  856. shaddr -= bus->ci->srsize;
  857. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
  858. (u8 *)&addr_le, 4);
  859. if (rv < 0)
  860. goto fail;
  861. /*
  862. * Check if addr is valid.
  863. * NVRAM length at the end of memory should have been overwritten.
  864. */
  865. addr = le32_to_cpu(addr_le);
  866. if (!brcmf_sdio_valid_shared_address(addr)) {
  867. brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
  868. rv = -EINVAL;
  869. goto fail;
  870. }
  871. brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
  872. /* Read hndrte_shared structure */
  873. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
  874. sizeof(struct sdpcm_shared_le));
  875. if (rv < 0)
  876. goto fail;
  877. sdio_release_host(bus->sdiodev->func[1]);
  878. /* Endianness */
  879. sh->flags = le32_to_cpu(sh_le.flags);
  880. sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
  881. sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
  882. sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
  883. sh->assert_line = le32_to_cpu(sh_le.assert_line);
  884. sh->console_addr = le32_to_cpu(sh_le.console_addr);
  885. sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
  886. if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
  887. brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
  888. SDPCM_SHARED_VERSION,
  889. sh->flags & SDPCM_SHARED_VERSION_MASK);
  890. return -EPROTO;
  891. }
  892. return 0;
  893. fail:
  894. brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
  895. rv, addr);
  896. sdio_release_host(bus->sdiodev->func[1]);
  897. return rv;
  898. }
  899. static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
  900. {
  901. struct sdpcm_shared sh;
  902. if (brcmf_sdio_readshared(bus, &sh) == 0)
  903. bus->console_addr = sh.console_addr;
  904. }
  905. #else
  906. static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
  907. {
  908. }
  909. #endif /* DEBUG */
  910. static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
  911. {
  912. u32 intstatus = 0;
  913. u32 hmb_data;
  914. u8 fcbits;
  915. int ret;
  916. brcmf_dbg(SDIO, "Enter\n");
  917. /* Read mailbox data and ack that we did so */
  918. ret = r_sdreg32(bus, &hmb_data,
  919. offsetof(struct sdpcmd_regs, tohostmailboxdata));
  920. if (ret == 0)
  921. w_sdreg32(bus, SMB_INT_ACK,
  922. offsetof(struct sdpcmd_regs, tosbmailbox));
  923. bus->sdcnt.f1regdata += 2;
  924. /* Dongle recomposed rx frames, accept them again */
  925. if (hmb_data & HMB_DATA_NAKHANDLED) {
  926. brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
  927. bus->rx_seq);
  928. if (!bus->rxskip)
  929. brcmf_err("unexpected NAKHANDLED!\n");
  930. bus->rxskip = false;
  931. intstatus |= I_HMB_FRAME_IND;
  932. }
  933. /*
  934. * DEVREADY does not occur with gSPI.
  935. */
  936. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  937. bus->sdpcm_ver =
  938. (hmb_data & HMB_DATA_VERSION_MASK) >>
  939. HMB_DATA_VERSION_SHIFT;
  940. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  941. brcmf_err("Version mismatch, dongle reports %d, "
  942. "expecting %d\n",
  943. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  944. else
  945. brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
  946. bus->sdpcm_ver);
  947. /*
  948. * Retrieve console state address now that firmware should have
  949. * updated it.
  950. */
  951. brcmf_sdio_get_console_addr(bus);
  952. }
  953. /*
  954. * Flow Control has been moved into the RX headers and this out of band
  955. * method isn't used any more.
  956. * remaining backward compatible with older dongles.
  957. */
  958. if (hmb_data & HMB_DATA_FC) {
  959. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  960. HMB_DATA_FCDATA_SHIFT;
  961. if (fcbits & ~bus->flowcontrol)
  962. bus->sdcnt.fc_xoff++;
  963. if (bus->flowcontrol & ~fcbits)
  964. bus->sdcnt.fc_xon++;
  965. bus->sdcnt.fc_rcvd++;
  966. bus->flowcontrol = fcbits;
  967. }
  968. /* Shouldn't be any others */
  969. if (hmb_data & ~(HMB_DATA_DEVREADY |
  970. HMB_DATA_NAKHANDLED |
  971. HMB_DATA_FC |
  972. HMB_DATA_FWREADY |
  973. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  974. brcmf_err("Unknown mailbox data content: 0x%02x\n",
  975. hmb_data);
  976. return intstatus;
  977. }
  978. static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
  979. {
  980. uint retries = 0;
  981. u16 lastrbc;
  982. u8 hi, lo;
  983. int err;
  984. brcmf_err("%sterminate frame%s\n",
  985. abort ? "abort command, " : "",
  986. rtx ? ", send NAK" : "");
  987. if (abort)
  988. brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
  989. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
  990. SFC_RF_TERM, &err);
  991. bus->sdcnt.f1regdata++;
  992. /* Wait until the packet has been flushed (device/FIFO stable) */
  993. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  994. hi = brcmf_sdiod_regrb(bus->sdiodev,
  995. SBSDIO_FUNC1_RFRAMEBCHI, &err);
  996. lo = brcmf_sdiod_regrb(bus->sdiodev,
  997. SBSDIO_FUNC1_RFRAMEBCLO, &err);
  998. bus->sdcnt.f1regdata += 2;
  999. if ((hi == 0) && (lo == 0))
  1000. break;
  1001. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  1002. brcmf_err("count growing: last 0x%04x now 0x%04x\n",
  1003. lastrbc, (hi << 8) + lo);
  1004. }
  1005. lastrbc = (hi << 8) + lo;
  1006. }
  1007. if (!retries)
  1008. brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
  1009. else
  1010. brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
  1011. if (rtx) {
  1012. bus->sdcnt.rxrtx++;
  1013. err = w_sdreg32(bus, SMB_NAK,
  1014. offsetof(struct sdpcmd_regs, tosbmailbox));
  1015. bus->sdcnt.f1regdata++;
  1016. if (err == 0)
  1017. bus->rxskip = true;
  1018. }
  1019. /* Clear partial in any case */
  1020. bus->cur_read.len = 0;
  1021. }
  1022. static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
  1023. {
  1024. struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
  1025. u8 i, hi, lo;
  1026. /* On failure, abort the command and terminate the frame */
  1027. brcmf_err("sdio error, abort command and terminate frame\n");
  1028. bus->sdcnt.tx_sderrs++;
  1029. brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
  1030. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
  1031. bus->sdcnt.f1regdata++;
  1032. for (i = 0; i < 3; i++) {
  1033. hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
  1034. lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
  1035. bus->sdcnt.f1regdata += 2;
  1036. if ((hi == 0) && (lo == 0))
  1037. break;
  1038. }
  1039. }
  1040. /* return total length of buffer chain */
  1041. static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
  1042. {
  1043. struct sk_buff *p;
  1044. uint total;
  1045. total = 0;
  1046. skb_queue_walk(&bus->glom, p)
  1047. total += p->len;
  1048. return total;
  1049. }
  1050. static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
  1051. {
  1052. struct sk_buff *cur, *next;
  1053. skb_queue_walk_safe(&bus->glom, cur, next) {
  1054. skb_unlink(cur, &bus->glom);
  1055. brcmu_pkt_buf_free_skb(cur);
  1056. }
  1057. }
  1058. /**
  1059. * brcmfmac sdio bus specific header
  1060. * This is the lowest layer header wrapped on the packets transmitted between
  1061. * host and WiFi dongle which contains information needed for SDIO core and
  1062. * firmware
  1063. *
  1064. * It consists of 3 parts: hardware header, hardware extension header and
  1065. * software header
  1066. * hardware header (frame tag) - 4 bytes
  1067. * Byte 0~1: Frame length
  1068. * Byte 2~3: Checksum, bit-wise inverse of frame length
  1069. * hardware extension header - 8 bytes
  1070. * Tx glom mode only, N/A for Rx or normal Tx
  1071. * Byte 0~1: Packet length excluding hw frame tag
  1072. * Byte 2: Reserved
  1073. * Byte 3: Frame flags, bit 0: last frame indication
  1074. * Byte 4~5: Reserved
  1075. * Byte 6~7: Tail padding length
  1076. * software header - 8 bytes
  1077. * Byte 0: Rx/Tx sequence number
  1078. * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
  1079. * Byte 2: Length of next data frame, reserved for Tx
  1080. * Byte 3: Data offset
  1081. * Byte 4: Flow control bits, reserved for Tx
  1082. * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
  1083. * Byte 6~7: Reserved
  1084. */
  1085. #define SDPCM_HWHDR_LEN 4
  1086. #define SDPCM_HWEXT_LEN 8
  1087. #define SDPCM_SWHDR_LEN 8
  1088. #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
  1089. /* software header */
  1090. #define SDPCM_SEQ_MASK 0x000000ff
  1091. #define SDPCM_SEQ_WRAP 256
  1092. #define SDPCM_CHANNEL_MASK 0x00000f00
  1093. #define SDPCM_CHANNEL_SHIFT 8
  1094. #define SDPCM_CONTROL_CHANNEL 0 /* Control */
  1095. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
  1096. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
  1097. #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
  1098. #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
  1099. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  1100. #define SDPCM_NEXTLEN_MASK 0x00ff0000
  1101. #define SDPCM_NEXTLEN_SHIFT 16
  1102. #define SDPCM_DOFFSET_MASK 0xff000000
  1103. #define SDPCM_DOFFSET_SHIFT 24
  1104. #define SDPCM_FCMASK_MASK 0x000000ff
  1105. #define SDPCM_WINDOW_MASK 0x0000ff00
  1106. #define SDPCM_WINDOW_SHIFT 8
  1107. static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
  1108. {
  1109. u32 hdrvalue;
  1110. hdrvalue = *(u32 *)swheader;
  1111. return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
  1112. }
  1113. static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
  1114. {
  1115. u32 hdrvalue;
  1116. u8 ret;
  1117. hdrvalue = *(u32 *)swheader;
  1118. ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
  1119. return (ret == SDPCM_EVENT_CHANNEL);
  1120. }
  1121. static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
  1122. struct brcmf_sdio_hdrinfo *rd,
  1123. enum brcmf_sdio_frmtype type)
  1124. {
  1125. u16 len, checksum;
  1126. u8 rx_seq, fc, tx_seq_max;
  1127. u32 swheader;
  1128. trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
  1129. /* hw header */
  1130. len = get_unaligned_le16(header);
  1131. checksum = get_unaligned_le16(header + sizeof(u16));
  1132. /* All zero means no more to read */
  1133. if (!(len | checksum)) {
  1134. bus->rxpending = false;
  1135. return -ENODATA;
  1136. }
  1137. if ((u16)(~(len ^ checksum))) {
  1138. brcmf_err("HW header checksum error\n");
  1139. bus->sdcnt.rx_badhdr++;
  1140. brcmf_sdio_rxfail(bus, false, false);
  1141. return -EIO;
  1142. }
  1143. if (len < SDPCM_HDRLEN) {
  1144. brcmf_err("HW header length error\n");
  1145. return -EPROTO;
  1146. }
  1147. if (type == BRCMF_SDIO_FT_SUPER &&
  1148. (roundup(len, bus->blocksize) != rd->len)) {
  1149. brcmf_err("HW superframe header length error\n");
  1150. return -EPROTO;
  1151. }
  1152. if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
  1153. brcmf_err("HW subframe header length error\n");
  1154. return -EPROTO;
  1155. }
  1156. rd->len = len;
  1157. /* software header */
  1158. header += SDPCM_HWHDR_LEN;
  1159. swheader = le32_to_cpu(*(__le32 *)header);
  1160. if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
  1161. brcmf_err("Glom descriptor found in superframe head\n");
  1162. rd->len = 0;
  1163. return -EINVAL;
  1164. }
  1165. rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
  1166. rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
  1167. if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
  1168. type != BRCMF_SDIO_FT_SUPER) {
  1169. brcmf_err("HW header length too long\n");
  1170. bus->sdcnt.rx_toolong++;
  1171. brcmf_sdio_rxfail(bus, false, false);
  1172. rd->len = 0;
  1173. return -EPROTO;
  1174. }
  1175. if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
  1176. brcmf_err("Wrong channel for superframe\n");
  1177. rd->len = 0;
  1178. return -EINVAL;
  1179. }
  1180. if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
  1181. rd->channel != SDPCM_EVENT_CHANNEL) {
  1182. brcmf_err("Wrong channel for subframe\n");
  1183. rd->len = 0;
  1184. return -EINVAL;
  1185. }
  1186. rd->dat_offset = brcmf_sdio_getdatoffset(header);
  1187. if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
  1188. brcmf_err("seq %d: bad data offset\n", rx_seq);
  1189. bus->sdcnt.rx_badhdr++;
  1190. brcmf_sdio_rxfail(bus, false, false);
  1191. rd->len = 0;
  1192. return -ENXIO;
  1193. }
  1194. if (rd->seq_num != rx_seq) {
  1195. brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
  1196. bus->sdcnt.rx_badseq++;
  1197. rd->seq_num = rx_seq;
  1198. }
  1199. /* no need to check the reset for subframe */
  1200. if (type == BRCMF_SDIO_FT_SUB)
  1201. return 0;
  1202. rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
  1203. if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
  1204. /* only warm for NON glom packet */
  1205. if (rd->channel != SDPCM_GLOM_CHANNEL)
  1206. brcmf_err("seq %d: next length error\n", rx_seq);
  1207. rd->len_nxtfrm = 0;
  1208. }
  1209. swheader = le32_to_cpu(*(__le32 *)(header + 4));
  1210. fc = swheader & SDPCM_FCMASK_MASK;
  1211. if (bus->flowcontrol != fc) {
  1212. if (~bus->flowcontrol & fc)
  1213. bus->sdcnt.fc_xoff++;
  1214. if (bus->flowcontrol & ~fc)
  1215. bus->sdcnt.fc_xon++;
  1216. bus->sdcnt.fc_rcvd++;
  1217. bus->flowcontrol = fc;
  1218. }
  1219. tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
  1220. if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
  1221. brcmf_err("seq %d: max tx seq number error\n", rx_seq);
  1222. tx_seq_max = bus->tx_seq + 2;
  1223. }
  1224. bus->tx_max = tx_seq_max;
  1225. return 0;
  1226. }
  1227. static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
  1228. {
  1229. *(__le16 *)header = cpu_to_le16(frm_length);
  1230. *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
  1231. }
  1232. static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
  1233. struct brcmf_sdio_hdrinfo *hd_info)
  1234. {
  1235. u32 hdrval;
  1236. u8 hdr_offset;
  1237. brcmf_sdio_update_hwhdr(header, hd_info->len);
  1238. hdr_offset = SDPCM_HWHDR_LEN;
  1239. if (bus->txglom) {
  1240. hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
  1241. *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
  1242. hdrval = (u16)hd_info->tail_pad << 16;
  1243. *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
  1244. hdr_offset += SDPCM_HWEXT_LEN;
  1245. }
  1246. hdrval = hd_info->seq_num;
  1247. hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
  1248. SDPCM_CHANNEL_MASK;
  1249. hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
  1250. SDPCM_DOFFSET_MASK;
  1251. *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
  1252. *(((__le32 *)(header + hdr_offset)) + 1) = 0;
  1253. trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
  1254. }
  1255. static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
  1256. {
  1257. u16 dlen, totlen;
  1258. u8 *dptr, num = 0;
  1259. u16 sublen;
  1260. struct sk_buff *pfirst, *pnext;
  1261. int errcode;
  1262. u8 doff, sfdoff;
  1263. struct brcmf_sdio_hdrinfo rd_new;
  1264. /* If packets, issue read(s) and send up packet chain */
  1265. /* Return sequence numbers consumed? */
  1266. brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
  1267. bus->glomd, skb_peek(&bus->glom));
  1268. /* If there's a descriptor, generate the packet chain */
  1269. if (bus->glomd) {
  1270. pfirst = pnext = NULL;
  1271. dlen = (u16) (bus->glomd->len);
  1272. dptr = bus->glomd->data;
  1273. if (!dlen || (dlen & 1)) {
  1274. brcmf_err("bad glomd len(%d), ignore descriptor\n",
  1275. dlen);
  1276. dlen = 0;
  1277. }
  1278. for (totlen = num = 0; dlen; num++) {
  1279. /* Get (and move past) next length */
  1280. sublen = get_unaligned_le16(dptr);
  1281. dlen -= sizeof(u16);
  1282. dptr += sizeof(u16);
  1283. if ((sublen < SDPCM_HDRLEN) ||
  1284. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  1285. brcmf_err("descriptor len %d bad: %d\n",
  1286. num, sublen);
  1287. pnext = NULL;
  1288. break;
  1289. }
  1290. if (sublen % bus->sgentry_align) {
  1291. brcmf_err("sublen %d not multiple of %d\n",
  1292. sublen, bus->sgentry_align);
  1293. }
  1294. totlen += sublen;
  1295. /* For last frame, adjust read len so total
  1296. is a block multiple */
  1297. if (!dlen) {
  1298. sublen +=
  1299. (roundup(totlen, bus->blocksize) - totlen);
  1300. totlen = roundup(totlen, bus->blocksize);
  1301. }
  1302. /* Allocate/chain packet for next subframe */
  1303. pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
  1304. if (pnext == NULL) {
  1305. brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
  1306. num, sublen);
  1307. break;
  1308. }
  1309. skb_queue_tail(&bus->glom, pnext);
  1310. /* Adhere to start alignment requirements */
  1311. pkt_align(pnext, sublen, bus->sgentry_align);
  1312. }
  1313. /* If all allocations succeeded, save packet chain
  1314. in bus structure */
  1315. if (pnext) {
  1316. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  1317. totlen, num);
  1318. if (BRCMF_GLOM_ON() && bus->cur_read.len &&
  1319. totlen != bus->cur_read.len) {
  1320. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  1321. bus->cur_read.len, totlen, rxseq);
  1322. }
  1323. pfirst = pnext = NULL;
  1324. } else {
  1325. brcmf_sdio_free_glom(bus);
  1326. num = 0;
  1327. }
  1328. /* Done with descriptor packet */
  1329. brcmu_pkt_buf_free_skb(bus->glomd);
  1330. bus->glomd = NULL;
  1331. bus->cur_read.len = 0;
  1332. }
  1333. /* Ok -- either we just generated a packet chain,
  1334. or had one from before */
  1335. if (!skb_queue_empty(&bus->glom)) {
  1336. if (BRCMF_GLOM_ON()) {
  1337. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1338. skb_queue_walk(&bus->glom, pnext) {
  1339. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1340. pnext, (u8 *) (pnext->data),
  1341. pnext->len, pnext->len);
  1342. }
  1343. }
  1344. pfirst = skb_peek(&bus->glom);
  1345. dlen = (u16) brcmf_sdio_glom_len(bus);
  1346. /* Do an SDIO read for the superframe. Configurable iovar to
  1347. * read directly into the chained packet, or allocate a large
  1348. * packet and and copy into the chain.
  1349. */
  1350. sdio_claim_host(bus->sdiodev->func[1]);
  1351. errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
  1352. &bus->glom, dlen);
  1353. sdio_release_host(bus->sdiodev->func[1]);
  1354. bus->sdcnt.f2rxdata++;
  1355. /* On failure, kill the superframe */
  1356. if (errcode < 0) {
  1357. brcmf_err("glom read of %d bytes failed: %d\n",
  1358. dlen, errcode);
  1359. sdio_claim_host(bus->sdiodev->func[1]);
  1360. brcmf_sdio_rxfail(bus, true, false);
  1361. bus->sdcnt.rxglomfail++;
  1362. brcmf_sdio_free_glom(bus);
  1363. sdio_release_host(bus->sdiodev->func[1]);
  1364. return 0;
  1365. }
  1366. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1367. pfirst->data, min_t(int, pfirst->len, 48),
  1368. "SUPERFRAME:\n");
  1369. rd_new.seq_num = rxseq;
  1370. rd_new.len = dlen;
  1371. sdio_claim_host(bus->sdiodev->func[1]);
  1372. errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
  1373. BRCMF_SDIO_FT_SUPER);
  1374. sdio_release_host(bus->sdiodev->func[1]);
  1375. bus->cur_read.len = rd_new.len_nxtfrm << 4;
  1376. /* Remove superframe header, remember offset */
  1377. skb_pull(pfirst, rd_new.dat_offset);
  1378. sfdoff = rd_new.dat_offset;
  1379. num = 0;
  1380. /* Validate all the subframe headers */
  1381. skb_queue_walk(&bus->glom, pnext) {
  1382. /* leave when invalid subframe is found */
  1383. if (errcode)
  1384. break;
  1385. rd_new.len = pnext->len;
  1386. rd_new.seq_num = rxseq++;
  1387. sdio_claim_host(bus->sdiodev->func[1]);
  1388. errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
  1389. BRCMF_SDIO_FT_SUB);
  1390. sdio_release_host(bus->sdiodev->func[1]);
  1391. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1392. pnext->data, 32, "subframe:\n");
  1393. num++;
  1394. }
  1395. if (errcode) {
  1396. /* Terminate frame on error */
  1397. sdio_claim_host(bus->sdiodev->func[1]);
  1398. brcmf_sdio_rxfail(bus, true, false);
  1399. bus->sdcnt.rxglomfail++;
  1400. brcmf_sdio_free_glom(bus);
  1401. sdio_release_host(bus->sdiodev->func[1]);
  1402. bus->cur_read.len = 0;
  1403. return 0;
  1404. }
  1405. /* Basic SD framing looks ok - process each packet (header) */
  1406. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1407. dptr = (u8 *) (pfirst->data);
  1408. sublen = get_unaligned_le16(dptr);
  1409. doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
  1410. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
  1411. dptr, pfirst->len,
  1412. "Rx Subframe Data:\n");
  1413. __skb_trim(pfirst, sublen);
  1414. skb_pull(pfirst, doff);
  1415. if (pfirst->len == 0) {
  1416. skb_unlink(pfirst, &bus->glom);
  1417. brcmu_pkt_buf_free_skb(pfirst);
  1418. continue;
  1419. }
  1420. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1421. pfirst->data,
  1422. min_t(int, pfirst->len, 32),
  1423. "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1424. bus->glom.qlen, pfirst, pfirst->data,
  1425. pfirst->len, pfirst->next,
  1426. pfirst->prev);
  1427. skb_unlink(pfirst, &bus->glom);
  1428. if (brcmf_sdio_fromevntchan(pfirst->data))
  1429. brcmf_rx_event(bus->sdiodev->dev, pfirst);
  1430. else
  1431. brcmf_rx_frame(bus->sdiodev->dev, pfirst,
  1432. false);
  1433. bus->sdcnt.rxglompkts++;
  1434. }
  1435. bus->sdcnt.rxglomframes++;
  1436. }
  1437. return num;
  1438. }
  1439. static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
  1440. bool *pending)
  1441. {
  1442. DECLARE_WAITQUEUE(wait, current);
  1443. int timeout = DCMD_RESP_TIMEOUT;
  1444. /* Wait until control frame is available */
  1445. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1446. set_current_state(TASK_INTERRUPTIBLE);
  1447. while (!(*condition) && (!signal_pending(current) && timeout))
  1448. timeout = schedule_timeout(timeout);
  1449. if (signal_pending(current))
  1450. *pending = true;
  1451. set_current_state(TASK_RUNNING);
  1452. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1453. return timeout;
  1454. }
  1455. static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
  1456. {
  1457. wake_up_interruptible(&bus->dcmd_resp_wait);
  1458. return 0;
  1459. }
  1460. static void
  1461. brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
  1462. {
  1463. uint rdlen, pad;
  1464. u8 *buf = NULL, *rbuf;
  1465. int sdret;
  1466. brcmf_dbg(TRACE, "Enter\n");
  1467. if (bus->rxblen)
  1468. buf = vzalloc(bus->rxblen);
  1469. if (!buf)
  1470. goto done;
  1471. rbuf = bus->rxbuf;
  1472. pad = ((unsigned long)rbuf % bus->head_align);
  1473. if (pad)
  1474. rbuf += (bus->head_align - pad);
  1475. /* Copy the already-read portion over */
  1476. memcpy(buf, hdr, BRCMF_FIRSTREAD);
  1477. if (len <= BRCMF_FIRSTREAD)
  1478. goto gotpkt;
  1479. /* Raise rdlen to next SDIO block to avoid tail command */
  1480. rdlen = len - BRCMF_FIRSTREAD;
  1481. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1482. pad = bus->blocksize - (rdlen % bus->blocksize);
  1483. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1484. ((len + pad) < bus->sdiodev->bus_if->maxctl))
  1485. rdlen += pad;
  1486. } else if (rdlen % bus->head_align) {
  1487. rdlen += bus->head_align - (rdlen % bus->head_align);
  1488. }
  1489. /* Drop if the read is too big or it exceeds our maximum */
  1490. if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
  1491. brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
  1492. rdlen, bus->sdiodev->bus_if->maxctl);
  1493. brcmf_sdio_rxfail(bus, false, false);
  1494. goto done;
  1495. }
  1496. if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
  1497. brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1498. len, len - doff, bus->sdiodev->bus_if->maxctl);
  1499. bus->sdcnt.rx_toolong++;
  1500. brcmf_sdio_rxfail(bus, false, false);
  1501. goto done;
  1502. }
  1503. /* Read remain of frame body */
  1504. sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
  1505. bus->sdcnt.f2rxdata++;
  1506. /* Control frame failures need retransmission */
  1507. if (sdret < 0) {
  1508. brcmf_err("read %d control bytes failed: %d\n",
  1509. rdlen, sdret);
  1510. bus->sdcnt.rxc_errors++;
  1511. brcmf_sdio_rxfail(bus, true, true);
  1512. goto done;
  1513. } else
  1514. memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
  1515. gotpkt:
  1516. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
  1517. buf, len, "RxCtrl:\n");
  1518. /* Point to valid data and indicate its length */
  1519. spin_lock_bh(&bus->rxctl_lock);
  1520. if (bus->rxctl) {
  1521. brcmf_err("last control frame is being processed.\n");
  1522. spin_unlock_bh(&bus->rxctl_lock);
  1523. vfree(buf);
  1524. goto done;
  1525. }
  1526. bus->rxctl = buf + doff;
  1527. bus->rxctl_orig = buf;
  1528. bus->rxlen = len - doff;
  1529. spin_unlock_bh(&bus->rxctl_lock);
  1530. done:
  1531. /* Awake any waiters */
  1532. brcmf_sdio_dcmd_resp_wake(bus);
  1533. }
  1534. /* Pad read to blocksize for efficiency */
  1535. static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
  1536. {
  1537. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1538. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1539. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1540. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1541. *rdlen += *pad;
  1542. } else if (*rdlen % bus->head_align) {
  1543. *rdlen += bus->head_align - (*rdlen % bus->head_align);
  1544. }
  1545. }
  1546. static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
  1547. {
  1548. struct sk_buff *pkt; /* Packet for event or data frames */
  1549. u16 pad; /* Number of pad bytes to read */
  1550. uint rxleft = 0; /* Remaining number of frames allowed */
  1551. int ret; /* Return code from calls */
  1552. uint rxcount = 0; /* Total frames read */
  1553. struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
  1554. u8 head_read = 0;
  1555. brcmf_dbg(TRACE, "Enter\n");
  1556. /* Not finished unless we encounter no more frames indication */
  1557. bus->rxpending = true;
  1558. for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
  1559. !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
  1560. rd->seq_num++, rxleft--) {
  1561. /* Handle glomming separately */
  1562. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1563. u8 cnt;
  1564. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1565. bus->glomd, skb_peek(&bus->glom));
  1566. cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
  1567. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1568. rd->seq_num += cnt - 1;
  1569. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1570. continue;
  1571. }
  1572. rd->len_left = rd->len;
  1573. /* read header first for unknow frame length */
  1574. sdio_claim_host(bus->sdiodev->func[1]);
  1575. if (!rd->len) {
  1576. ret = brcmf_sdiod_recv_buf(bus->sdiodev,
  1577. bus->rxhdr, BRCMF_FIRSTREAD);
  1578. bus->sdcnt.f2rxhdrs++;
  1579. if (ret < 0) {
  1580. brcmf_err("RXHEADER FAILED: %d\n",
  1581. ret);
  1582. bus->sdcnt.rx_hdrfail++;
  1583. brcmf_sdio_rxfail(bus, true, true);
  1584. sdio_release_host(bus->sdiodev->func[1]);
  1585. continue;
  1586. }
  1587. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
  1588. bus->rxhdr, SDPCM_HDRLEN,
  1589. "RxHdr:\n");
  1590. if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
  1591. BRCMF_SDIO_FT_NORMAL)) {
  1592. sdio_release_host(bus->sdiodev->func[1]);
  1593. if (!bus->rxpending)
  1594. break;
  1595. else
  1596. continue;
  1597. }
  1598. if (rd->channel == SDPCM_CONTROL_CHANNEL) {
  1599. brcmf_sdio_read_control(bus, bus->rxhdr,
  1600. rd->len,
  1601. rd->dat_offset);
  1602. /* prepare the descriptor for the next read */
  1603. rd->len = rd->len_nxtfrm << 4;
  1604. rd->len_nxtfrm = 0;
  1605. /* treat all packet as event if we don't know */
  1606. rd->channel = SDPCM_EVENT_CHANNEL;
  1607. sdio_release_host(bus->sdiodev->func[1]);
  1608. continue;
  1609. }
  1610. rd->len_left = rd->len > BRCMF_FIRSTREAD ?
  1611. rd->len - BRCMF_FIRSTREAD : 0;
  1612. head_read = BRCMF_FIRSTREAD;
  1613. }
  1614. brcmf_sdio_pad(bus, &pad, &rd->len_left);
  1615. pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
  1616. bus->head_align);
  1617. if (!pkt) {
  1618. /* Give up on data, request rtx of events */
  1619. brcmf_err("brcmu_pkt_buf_get_skb failed\n");
  1620. brcmf_sdio_rxfail(bus, false,
  1621. RETRYCHAN(rd->channel));
  1622. sdio_release_host(bus->sdiodev->func[1]);
  1623. continue;
  1624. }
  1625. skb_pull(pkt, head_read);
  1626. pkt_align(pkt, rd->len_left, bus->head_align);
  1627. ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
  1628. bus->sdcnt.f2rxdata++;
  1629. sdio_release_host(bus->sdiodev->func[1]);
  1630. if (ret < 0) {
  1631. brcmf_err("read %d bytes from channel %d failed: %d\n",
  1632. rd->len, rd->channel, ret);
  1633. brcmu_pkt_buf_free_skb(pkt);
  1634. sdio_claim_host(bus->sdiodev->func[1]);
  1635. brcmf_sdio_rxfail(bus, true,
  1636. RETRYCHAN(rd->channel));
  1637. sdio_release_host(bus->sdiodev->func[1]);
  1638. continue;
  1639. }
  1640. if (head_read) {
  1641. skb_push(pkt, head_read);
  1642. memcpy(pkt->data, bus->rxhdr, head_read);
  1643. head_read = 0;
  1644. } else {
  1645. memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
  1646. rd_new.seq_num = rd->seq_num;
  1647. sdio_claim_host(bus->sdiodev->func[1]);
  1648. if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
  1649. BRCMF_SDIO_FT_NORMAL)) {
  1650. rd->len = 0;
  1651. brcmu_pkt_buf_free_skb(pkt);
  1652. }
  1653. bus->sdcnt.rx_readahead_cnt++;
  1654. if (rd->len != roundup(rd_new.len, 16)) {
  1655. brcmf_err("frame length mismatch:read %d, should be %d\n",
  1656. rd->len,
  1657. roundup(rd_new.len, 16) >> 4);
  1658. rd->len = 0;
  1659. brcmf_sdio_rxfail(bus, true, true);
  1660. sdio_release_host(bus->sdiodev->func[1]);
  1661. brcmu_pkt_buf_free_skb(pkt);
  1662. continue;
  1663. }
  1664. sdio_release_host(bus->sdiodev->func[1]);
  1665. rd->len_nxtfrm = rd_new.len_nxtfrm;
  1666. rd->channel = rd_new.channel;
  1667. rd->dat_offset = rd_new.dat_offset;
  1668. brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
  1669. BRCMF_DATA_ON()) &&
  1670. BRCMF_HDRS_ON(),
  1671. bus->rxhdr, SDPCM_HDRLEN,
  1672. "RxHdr:\n");
  1673. if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
  1674. brcmf_err("readahead on control packet %d?\n",
  1675. rd_new.seq_num);
  1676. /* Force retry w/normal header read */
  1677. rd->len = 0;
  1678. sdio_claim_host(bus->sdiodev->func[1]);
  1679. brcmf_sdio_rxfail(bus, false, true);
  1680. sdio_release_host(bus->sdiodev->func[1]);
  1681. brcmu_pkt_buf_free_skb(pkt);
  1682. continue;
  1683. }
  1684. }
  1685. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
  1686. pkt->data, rd->len, "Rx Data:\n");
  1687. /* Save superframe descriptor and allocate packet frame */
  1688. if (rd->channel == SDPCM_GLOM_CHANNEL) {
  1689. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
  1690. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1691. rd->len);
  1692. brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
  1693. pkt->data, rd->len,
  1694. "Glom Data:\n");
  1695. __skb_trim(pkt, rd->len);
  1696. skb_pull(pkt, SDPCM_HDRLEN);
  1697. bus->glomd = pkt;
  1698. } else {
  1699. brcmf_err("%s: glom superframe w/o "
  1700. "descriptor!\n", __func__);
  1701. sdio_claim_host(bus->sdiodev->func[1]);
  1702. brcmf_sdio_rxfail(bus, false, false);
  1703. sdio_release_host(bus->sdiodev->func[1]);
  1704. }
  1705. /* prepare the descriptor for the next read */
  1706. rd->len = rd->len_nxtfrm << 4;
  1707. rd->len_nxtfrm = 0;
  1708. /* treat all packet as event if we don't know */
  1709. rd->channel = SDPCM_EVENT_CHANNEL;
  1710. continue;
  1711. }
  1712. /* Fill in packet len and prio, deliver upward */
  1713. __skb_trim(pkt, rd->len);
  1714. skb_pull(pkt, rd->dat_offset);
  1715. if (pkt->len == 0)
  1716. brcmu_pkt_buf_free_skb(pkt);
  1717. else if (rd->channel == SDPCM_EVENT_CHANNEL)
  1718. brcmf_rx_event(bus->sdiodev->dev, pkt);
  1719. else
  1720. brcmf_rx_frame(bus->sdiodev->dev, pkt,
  1721. false);
  1722. /* prepare the descriptor for the next read */
  1723. rd->len = rd->len_nxtfrm << 4;
  1724. rd->len_nxtfrm = 0;
  1725. /* treat all packet as event if we don't know */
  1726. rd->channel = SDPCM_EVENT_CHANNEL;
  1727. }
  1728. rxcount = maxframes - rxleft;
  1729. /* Message if we hit the limit */
  1730. if (!rxleft)
  1731. brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
  1732. else
  1733. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1734. /* Back off rxseq if awaiting rtx, update rx_seq */
  1735. if (bus->rxskip)
  1736. rd->seq_num--;
  1737. bus->rx_seq = rd->seq_num;
  1738. return rxcount;
  1739. }
  1740. static void
  1741. brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
  1742. {
  1743. wake_up_interruptible(&bus->ctrl_wait);
  1744. return;
  1745. }
  1746. static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
  1747. {
  1748. u16 head_pad;
  1749. u8 *dat_buf;
  1750. dat_buf = (u8 *)(pkt->data);
  1751. /* Check head padding */
  1752. head_pad = ((unsigned long)dat_buf % bus->head_align);
  1753. if (head_pad) {
  1754. if (skb_headroom(pkt) < head_pad) {
  1755. bus->sdiodev->bus_if->tx_realloc++;
  1756. head_pad = 0;
  1757. if (skb_cow(pkt, head_pad))
  1758. return -ENOMEM;
  1759. }
  1760. skb_push(pkt, head_pad);
  1761. dat_buf = (u8 *)(pkt->data);
  1762. memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
  1763. }
  1764. return head_pad;
  1765. }
  1766. /**
  1767. * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
  1768. * bus layer usage.
  1769. */
  1770. /* flag marking a dummy skb added for DMA alignment requirement */
  1771. #define ALIGN_SKB_FLAG 0x8000
  1772. /* bit mask of data length chopped from the previous packet */
  1773. #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
  1774. static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
  1775. struct sk_buff_head *pktq,
  1776. struct sk_buff *pkt, u16 total_len)
  1777. {
  1778. struct brcmf_sdio_dev *sdiodev;
  1779. struct sk_buff *pkt_pad;
  1780. u16 tail_pad, tail_chop, chain_pad;
  1781. unsigned int blksize;
  1782. bool lastfrm;
  1783. int ntail, ret;
  1784. sdiodev = bus->sdiodev;
  1785. blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
  1786. /* sg entry alignment should be a divisor of block size */
  1787. WARN_ON(blksize % bus->sgentry_align);
  1788. /* Check tail padding */
  1789. lastfrm = skb_queue_is_last(pktq, pkt);
  1790. tail_pad = 0;
  1791. tail_chop = pkt->len % bus->sgentry_align;
  1792. if (tail_chop)
  1793. tail_pad = bus->sgentry_align - tail_chop;
  1794. chain_pad = (total_len + tail_pad) % blksize;
  1795. if (lastfrm && chain_pad)
  1796. tail_pad += blksize - chain_pad;
  1797. if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
  1798. pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
  1799. bus->head_align);
  1800. if (pkt_pad == NULL)
  1801. return -ENOMEM;
  1802. ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
  1803. if (unlikely(ret < 0)) {
  1804. kfree_skb(pkt_pad);
  1805. return ret;
  1806. }
  1807. memcpy(pkt_pad->data,
  1808. pkt->data + pkt->len - tail_chop,
  1809. tail_chop);
  1810. *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
  1811. skb_trim(pkt, pkt->len - tail_chop);
  1812. skb_trim(pkt_pad, tail_pad + tail_chop);
  1813. __skb_queue_after(pktq, pkt, pkt_pad);
  1814. } else {
  1815. ntail = pkt->data_len + tail_pad -
  1816. (pkt->end - pkt->tail);
  1817. if (skb_cloned(pkt) || ntail > 0)
  1818. if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
  1819. return -ENOMEM;
  1820. if (skb_linearize(pkt))
  1821. return -ENOMEM;
  1822. __skb_put(pkt, tail_pad);
  1823. }
  1824. return tail_pad;
  1825. }
  1826. /**
  1827. * brcmf_sdio_txpkt_prep - packet preparation for transmit
  1828. * @bus: brcmf_sdio structure pointer
  1829. * @pktq: packet list pointer
  1830. * @chan: virtual channel to transmit the packet
  1831. *
  1832. * Processes to be applied to the packet
  1833. * - Align data buffer pointer
  1834. * - Align data buffer length
  1835. * - Prepare header
  1836. * Return: negative value if there is error
  1837. */
  1838. static int
  1839. brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
  1840. uint chan)
  1841. {
  1842. u16 head_pad, total_len;
  1843. struct sk_buff *pkt_next;
  1844. u8 txseq;
  1845. int ret;
  1846. struct brcmf_sdio_hdrinfo hd_info = {0};
  1847. txseq = bus->tx_seq;
  1848. total_len = 0;
  1849. skb_queue_walk(pktq, pkt_next) {
  1850. /* alignment packet inserted in previous
  1851. * loop cycle can be skipped as it is
  1852. * already properly aligned and does not
  1853. * need an sdpcm header.
  1854. */
  1855. if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
  1856. continue;
  1857. /* align packet data pointer */
  1858. ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
  1859. if (ret < 0)
  1860. return ret;
  1861. head_pad = (u16)ret;
  1862. if (head_pad)
  1863. memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
  1864. total_len += pkt_next->len;
  1865. hd_info.len = pkt_next->len;
  1866. hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
  1867. if (bus->txglom && pktq->qlen > 1) {
  1868. ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
  1869. pkt_next, total_len);
  1870. if (ret < 0)
  1871. return ret;
  1872. hd_info.tail_pad = (u16)ret;
  1873. total_len += (u16)ret;
  1874. }
  1875. hd_info.channel = chan;
  1876. hd_info.dat_offset = head_pad + bus->tx_hdrlen;
  1877. hd_info.seq_num = txseq++;
  1878. /* Now fill the header */
  1879. brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
  1880. if (BRCMF_BYTES_ON() &&
  1881. ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
  1882. (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
  1883. brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
  1884. "Tx Frame:\n");
  1885. else if (BRCMF_HDRS_ON())
  1886. brcmf_dbg_hex_dump(true, pkt_next->data,
  1887. head_pad + bus->tx_hdrlen,
  1888. "Tx Header:\n");
  1889. }
  1890. /* Hardware length tag of the first packet should be total
  1891. * length of the chain (including padding)
  1892. */
  1893. if (bus->txglom)
  1894. brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
  1895. return 0;
  1896. }
  1897. /**
  1898. * brcmf_sdio_txpkt_postp - packet post processing for transmit
  1899. * @bus: brcmf_sdio structure pointer
  1900. * @pktq: packet list pointer
  1901. *
  1902. * Processes to be applied to the packet
  1903. * - Remove head padding
  1904. * - Remove tail padding
  1905. */
  1906. static void
  1907. brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
  1908. {
  1909. u8 *hdr;
  1910. u32 dat_offset;
  1911. u16 tail_pad;
  1912. u16 dummy_flags, chop_len;
  1913. struct sk_buff *pkt_next, *tmp, *pkt_prev;
  1914. skb_queue_walk_safe(pktq, pkt_next, tmp) {
  1915. dummy_flags = *(u16 *)(pkt_next->cb);
  1916. if (dummy_flags & ALIGN_SKB_FLAG) {
  1917. chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
  1918. if (chop_len) {
  1919. pkt_prev = pkt_next->prev;
  1920. skb_put(pkt_prev, chop_len);
  1921. }
  1922. __skb_unlink(pkt_next, pktq);
  1923. brcmu_pkt_buf_free_skb(pkt_next);
  1924. } else {
  1925. hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
  1926. dat_offset = le32_to_cpu(*(__le32 *)hdr);
  1927. dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
  1928. SDPCM_DOFFSET_SHIFT;
  1929. skb_pull(pkt_next, dat_offset);
  1930. if (bus->txglom) {
  1931. tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
  1932. skb_trim(pkt_next, pkt_next->len - tail_pad);
  1933. }
  1934. }
  1935. }
  1936. }
  1937. /* Writes a HW/SW header into the packet and sends it. */
  1938. /* Assumes: (a) header space already there, (b) caller holds lock */
  1939. static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
  1940. uint chan)
  1941. {
  1942. int ret;
  1943. struct sk_buff *pkt_next, *tmp;
  1944. brcmf_dbg(TRACE, "Enter\n");
  1945. ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
  1946. if (ret)
  1947. goto done;
  1948. sdio_claim_host(bus->sdiodev->func[1]);
  1949. ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
  1950. bus->sdcnt.f2txdata++;
  1951. if (ret < 0)
  1952. brcmf_sdio_txfail(bus);
  1953. sdio_release_host(bus->sdiodev->func[1]);
  1954. done:
  1955. brcmf_sdio_txpkt_postp(bus, pktq);
  1956. if (ret == 0)
  1957. bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
  1958. skb_queue_walk_safe(pktq, pkt_next, tmp) {
  1959. __skb_unlink(pkt_next, pktq);
  1960. brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
  1961. }
  1962. return ret;
  1963. }
  1964. static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
  1965. {
  1966. struct sk_buff *pkt;
  1967. struct sk_buff_head pktq;
  1968. u32 intstatus = 0;
  1969. int ret = 0, prec_out, i;
  1970. uint cnt = 0;
  1971. u8 tx_prec_map, pkt_num;
  1972. brcmf_dbg(TRACE, "Enter\n");
  1973. tx_prec_map = ~bus->flowcontrol;
  1974. /* Send frames until the limit or some other event */
  1975. for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
  1976. pkt_num = 1;
  1977. if (bus->txglom)
  1978. pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
  1979. bus->sdiodev->txglomsz);
  1980. pkt_num = min_t(u32, pkt_num,
  1981. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
  1982. __skb_queue_head_init(&pktq);
  1983. spin_lock_bh(&bus->txq_lock);
  1984. for (i = 0; i < pkt_num; i++) {
  1985. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
  1986. &prec_out);
  1987. if (pkt == NULL)
  1988. break;
  1989. __skb_queue_tail(&pktq, pkt);
  1990. }
  1991. spin_unlock_bh(&bus->txq_lock);
  1992. if (i == 0)
  1993. break;
  1994. ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
  1995. cnt += i;
  1996. /* In poll mode, need to check for other events */
  1997. if (!bus->intr) {
  1998. /* Check device status, signal pending interrupt */
  1999. sdio_claim_host(bus->sdiodev->func[1]);
  2000. ret = r_sdreg32(bus, &intstatus,
  2001. offsetof(struct sdpcmd_regs,
  2002. intstatus));
  2003. sdio_release_host(bus->sdiodev->func[1]);
  2004. bus->sdcnt.f2txdata++;
  2005. if (ret != 0)
  2006. break;
  2007. if (intstatus & bus->hostintmask)
  2008. atomic_set(&bus->ipend, 1);
  2009. }
  2010. }
  2011. /* Deflow-control stack if needed */
  2012. if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
  2013. bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
  2014. bus->txoff = false;
  2015. brcmf_txflowblock(bus->sdiodev->dev, false);
  2016. }
  2017. return cnt;
  2018. }
  2019. static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
  2020. {
  2021. u8 doff;
  2022. u16 pad;
  2023. uint retries = 0;
  2024. struct brcmf_sdio_hdrinfo hd_info = {0};
  2025. int ret;
  2026. brcmf_dbg(TRACE, "Enter\n");
  2027. /* Back the pointer to make room for bus header */
  2028. frame -= bus->tx_hdrlen;
  2029. len += bus->tx_hdrlen;
  2030. /* Add alignment padding (optional for ctl frames) */
  2031. doff = ((unsigned long)frame % bus->head_align);
  2032. if (doff) {
  2033. frame -= doff;
  2034. len += doff;
  2035. memset(frame + bus->tx_hdrlen, 0, doff);
  2036. }
  2037. /* Round send length to next SDIO block */
  2038. pad = 0;
  2039. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2040. pad = bus->blocksize - (len % bus->blocksize);
  2041. if ((pad > bus->roundup) || (pad >= bus->blocksize))
  2042. pad = 0;
  2043. } else if (len % bus->head_align) {
  2044. pad = bus->head_align - (len % bus->head_align);
  2045. }
  2046. len += pad;
  2047. hd_info.len = len - pad;
  2048. hd_info.channel = SDPCM_CONTROL_CHANNEL;
  2049. hd_info.dat_offset = doff + bus->tx_hdrlen;
  2050. hd_info.seq_num = bus->tx_seq;
  2051. hd_info.lastfrm = true;
  2052. hd_info.tail_pad = pad;
  2053. brcmf_sdio_hdpack(bus, frame, &hd_info);
  2054. if (bus->txglom)
  2055. brcmf_sdio_update_hwhdr(frame, len);
  2056. brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
  2057. frame, len, "Tx Frame:\n");
  2058. brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
  2059. BRCMF_HDRS_ON(),
  2060. frame, min_t(u16, len, 16), "TxHdr:\n");
  2061. do {
  2062. ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
  2063. if (ret < 0)
  2064. brcmf_sdio_txfail(bus);
  2065. else
  2066. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
  2067. } while (ret < 0 && retries++ < TXRETRIES);
  2068. return ret;
  2069. }
  2070. static void brcmf_sdio_bus_stop(struct device *dev)
  2071. {
  2072. u32 local_hostintmask;
  2073. u8 saveclk;
  2074. int err;
  2075. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2076. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2077. struct brcmf_sdio *bus = sdiodev->bus;
  2078. brcmf_dbg(TRACE, "Enter\n");
  2079. if (bus->watchdog_tsk) {
  2080. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  2081. kthread_stop(bus->watchdog_tsk);
  2082. bus->watchdog_tsk = NULL;
  2083. }
  2084. if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
  2085. sdio_claim_host(sdiodev->func[1]);
  2086. /* Enable clock for device interrupts */
  2087. brcmf_sdio_bus_sleep(bus, false, false);
  2088. /* Disable and clear interrupts at the chip level also */
  2089. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
  2090. local_hostintmask = bus->hostintmask;
  2091. bus->hostintmask = 0;
  2092. /* Force backplane clocks to assure F2 interrupt propagates */
  2093. saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  2094. &err);
  2095. if (!err)
  2096. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  2097. (saveclk | SBSDIO_FORCE_HT), &err);
  2098. if (err)
  2099. brcmf_err("Failed to force clock for F2: err %d\n",
  2100. err);
  2101. /* Turn off the bus (F2), free any pending packets */
  2102. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  2103. sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
  2104. /* Clear any pending interrupts now that F2 is disabled */
  2105. w_sdreg32(bus, local_hostintmask,
  2106. offsetof(struct sdpcmd_regs, intstatus));
  2107. sdio_release_host(sdiodev->func[1]);
  2108. }
  2109. /* Clear the data packet queues */
  2110. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  2111. /* Clear any held glomming stuff */
  2112. brcmu_pkt_buf_free_skb(bus->glomd);
  2113. brcmf_sdio_free_glom(bus);
  2114. /* Clear rx control and wake any waiters */
  2115. spin_lock_bh(&bus->rxctl_lock);
  2116. bus->rxlen = 0;
  2117. spin_unlock_bh(&bus->rxctl_lock);
  2118. brcmf_sdio_dcmd_resp_wake(bus);
  2119. /* Reset some F2 state stuff */
  2120. bus->rxskip = false;
  2121. bus->tx_seq = bus->rx_seq = 0;
  2122. }
  2123. static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
  2124. {
  2125. struct brcmf_sdio_dev *sdiodev;
  2126. unsigned long flags;
  2127. sdiodev = bus->sdiodev;
  2128. if (sdiodev->oob_irq_requested) {
  2129. spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
  2130. if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
  2131. enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
  2132. sdiodev->irq_en = true;
  2133. }
  2134. spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
  2135. }
  2136. }
  2137. static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
  2138. {
  2139. struct brcmf_core *buscore;
  2140. u32 addr;
  2141. unsigned long val;
  2142. int ret;
  2143. buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  2144. addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
  2145. val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
  2146. bus->sdcnt.f1regdata++;
  2147. if (ret != 0)
  2148. return ret;
  2149. val &= bus->hostintmask;
  2150. atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
  2151. /* Clear interrupts */
  2152. if (val) {
  2153. brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
  2154. bus->sdcnt.f1regdata++;
  2155. atomic_or(val, &bus->intstatus);
  2156. }
  2157. return ret;
  2158. }
  2159. static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
  2160. {
  2161. u32 newstatus = 0;
  2162. unsigned long intstatus;
  2163. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  2164. uint framecnt; /* Temporary counter of tx/rx frames */
  2165. int err = 0;
  2166. brcmf_dbg(TRACE, "Enter\n");
  2167. sdio_claim_host(bus->sdiodev->func[1]);
  2168. /* If waiting for HTAVAIL, check status */
  2169. if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
  2170. u8 clkctl, devctl = 0;
  2171. #ifdef DEBUG
  2172. /* Check for inconsistent device control */
  2173. devctl = brcmf_sdiod_regrb(bus->sdiodev,
  2174. SBSDIO_DEVICE_CTL, &err);
  2175. #endif /* DEBUG */
  2176. /* Read CSR, if clock on switch to AVAIL, else ignore */
  2177. clkctl = brcmf_sdiod_regrb(bus->sdiodev,
  2178. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2179. brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  2180. devctl, clkctl);
  2181. if (SBSDIO_HTAV(clkctl)) {
  2182. devctl = brcmf_sdiod_regrb(bus->sdiodev,
  2183. SBSDIO_DEVICE_CTL, &err);
  2184. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  2185. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  2186. devctl, &err);
  2187. bus->clkstate = CLK_AVAIL;
  2188. }
  2189. }
  2190. /* Make sure backplane clock is on */
  2191. brcmf_sdio_bus_sleep(bus, false, true);
  2192. /* Pending interrupt indicates new device status */
  2193. if (atomic_read(&bus->ipend) > 0) {
  2194. atomic_set(&bus->ipend, 0);
  2195. err = brcmf_sdio_intr_rstatus(bus);
  2196. }
  2197. /* Start with leftover status bits */
  2198. intstatus = atomic_xchg(&bus->intstatus, 0);
  2199. /* Handle flow-control change: read new state in case our ack
  2200. * crossed another change interrupt. If change still set, assume
  2201. * FC ON for safety, let next loop through do the debounce.
  2202. */
  2203. if (intstatus & I_HMB_FC_CHANGE) {
  2204. intstatus &= ~I_HMB_FC_CHANGE;
  2205. err = w_sdreg32(bus, I_HMB_FC_CHANGE,
  2206. offsetof(struct sdpcmd_regs, intstatus));
  2207. err = r_sdreg32(bus, &newstatus,
  2208. offsetof(struct sdpcmd_regs, intstatus));
  2209. bus->sdcnt.f1regdata += 2;
  2210. atomic_set(&bus->fcstate,
  2211. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
  2212. intstatus |= (newstatus & bus->hostintmask);
  2213. }
  2214. /* Handle host mailbox indication */
  2215. if (intstatus & I_HMB_HOST_INT) {
  2216. intstatus &= ~I_HMB_HOST_INT;
  2217. intstatus |= brcmf_sdio_hostmail(bus);
  2218. }
  2219. sdio_release_host(bus->sdiodev->func[1]);
  2220. /* Generally don't ask for these, can get CRC errors... */
  2221. if (intstatus & I_WR_OOSYNC) {
  2222. brcmf_err("Dongle reports WR_OOSYNC\n");
  2223. intstatus &= ~I_WR_OOSYNC;
  2224. }
  2225. if (intstatus & I_RD_OOSYNC) {
  2226. brcmf_err("Dongle reports RD_OOSYNC\n");
  2227. intstatus &= ~I_RD_OOSYNC;
  2228. }
  2229. if (intstatus & I_SBINT) {
  2230. brcmf_err("Dongle reports SBINT\n");
  2231. intstatus &= ~I_SBINT;
  2232. }
  2233. /* Would be active due to wake-wlan in gSPI */
  2234. if (intstatus & I_CHIPACTIVE) {
  2235. brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
  2236. intstatus &= ~I_CHIPACTIVE;
  2237. }
  2238. /* Ignore frame indications if rxskip is set */
  2239. if (bus->rxskip)
  2240. intstatus &= ~I_HMB_FRAME_IND;
  2241. /* On frame indication, read available frames */
  2242. if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
  2243. brcmf_sdio_readframes(bus, bus->rxbound);
  2244. if (!bus->rxpending)
  2245. intstatus &= ~I_HMB_FRAME_IND;
  2246. }
  2247. /* Keep still-pending events for next scheduling */
  2248. if (intstatus)
  2249. atomic_or(intstatus, &bus->intstatus);
  2250. brcmf_sdio_clrintr(bus);
  2251. if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
  2252. data_ok(bus)) {
  2253. sdio_claim_host(bus->sdiodev->func[1]);
  2254. if (bus->ctrl_frame_stat) {
  2255. err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
  2256. bus->ctrl_frame_len);
  2257. bus->ctrl_frame_err = err;
  2258. wmb();
  2259. bus->ctrl_frame_stat = false;
  2260. }
  2261. sdio_release_host(bus->sdiodev->func[1]);
  2262. brcmf_sdio_wait_event_wakeup(bus);
  2263. }
  2264. /* Send queued frames (limit 1 if rx may still be pending) */
  2265. if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
  2266. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
  2267. data_ok(bus)) {
  2268. framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
  2269. txlimit;
  2270. brcmf_sdio_sendfromq(bus, framecnt);
  2271. }
  2272. if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
  2273. brcmf_err("failed backplane access over SDIO, halting operation\n");
  2274. atomic_set(&bus->intstatus, 0);
  2275. if (bus->ctrl_frame_stat) {
  2276. sdio_claim_host(bus->sdiodev->func[1]);
  2277. if (bus->ctrl_frame_stat) {
  2278. bus->ctrl_frame_err = -ENODEV;
  2279. wmb();
  2280. bus->ctrl_frame_stat = false;
  2281. brcmf_sdio_wait_event_wakeup(bus);
  2282. }
  2283. sdio_release_host(bus->sdiodev->func[1]);
  2284. }
  2285. } else if (atomic_read(&bus->intstatus) ||
  2286. atomic_read(&bus->ipend) > 0 ||
  2287. (!atomic_read(&bus->fcstate) &&
  2288. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
  2289. data_ok(bus))) {
  2290. bus->dpc_triggered = true;
  2291. }
  2292. }
  2293. static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
  2294. {
  2295. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2296. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2297. struct brcmf_sdio *bus = sdiodev->bus;
  2298. return &bus->txq;
  2299. }
  2300. static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
  2301. {
  2302. struct sk_buff *p;
  2303. int eprec = -1; /* precedence to evict from */
  2304. /* Fast case, precedence queue is not full and we are also not
  2305. * exceeding total queue length
  2306. */
  2307. if (!pktq_pfull(q, prec) && !pktq_full(q)) {
  2308. brcmu_pktq_penq(q, prec, pkt);
  2309. return true;
  2310. }
  2311. /* Determine precedence from which to evict packet, if any */
  2312. if (pktq_pfull(q, prec)) {
  2313. eprec = prec;
  2314. } else if (pktq_full(q)) {
  2315. p = brcmu_pktq_peek_tail(q, &eprec);
  2316. if (eprec > prec)
  2317. return false;
  2318. }
  2319. /* Evict if needed */
  2320. if (eprec >= 0) {
  2321. /* Detect queueing to unconfigured precedence */
  2322. if (eprec == prec)
  2323. return false; /* refuse newer (incoming) packet */
  2324. /* Evict packet according to discard policy */
  2325. p = brcmu_pktq_pdeq_tail(q, eprec);
  2326. if (p == NULL)
  2327. brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
  2328. brcmu_pkt_buf_free_skb(p);
  2329. }
  2330. /* Enqueue */
  2331. p = brcmu_pktq_penq(q, prec, pkt);
  2332. if (p == NULL)
  2333. brcmf_err("brcmu_pktq_penq() failed\n");
  2334. return p != NULL;
  2335. }
  2336. static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
  2337. {
  2338. int ret = -EBADE;
  2339. uint prec;
  2340. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2341. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2342. struct brcmf_sdio *bus = sdiodev->bus;
  2343. brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
  2344. if (sdiodev->state != BRCMF_SDIOD_DATA)
  2345. return -EIO;
  2346. /* Add space for the header */
  2347. skb_push(pkt, bus->tx_hdrlen);
  2348. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2349. prec = prio2prec((pkt->priority & PRIOMASK));
  2350. /* Check for existing queue, current flow-control,
  2351. pending event, or pending clock */
  2352. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2353. bus->sdcnt.fcqueued++;
  2354. /* Priority based enq */
  2355. spin_lock_bh(&bus->txq_lock);
  2356. /* reset bus_flags in packet cb */
  2357. *(u16 *)(pkt->cb) = 0;
  2358. if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
  2359. skb_pull(pkt, bus->tx_hdrlen);
  2360. brcmf_err("out of bus->txq !!!\n");
  2361. ret = -ENOSR;
  2362. } else {
  2363. ret = 0;
  2364. }
  2365. if (pktq_len(&bus->txq) >= TXHI) {
  2366. bus->txoff = true;
  2367. brcmf_txflowblock(dev, true);
  2368. }
  2369. spin_unlock_bh(&bus->txq_lock);
  2370. #ifdef DEBUG
  2371. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2372. qcount[prec] = pktq_plen(&bus->txq, prec);
  2373. #endif
  2374. brcmf_sdio_trigger_dpc(bus);
  2375. return ret;
  2376. }
  2377. #ifdef DEBUG
  2378. #define CONSOLE_LINE_MAX 192
  2379. static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
  2380. {
  2381. struct brcmf_console *c = &bus->console;
  2382. u8 line[CONSOLE_LINE_MAX], ch;
  2383. u32 n, idx, addr;
  2384. int rv;
  2385. /* Don't do anything until FWREADY updates console address */
  2386. if (bus->console_addr == 0)
  2387. return 0;
  2388. /* Read console log struct */
  2389. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2390. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
  2391. sizeof(c->log_le));
  2392. if (rv < 0)
  2393. return rv;
  2394. /* Allocate console buffer (one time only) */
  2395. if (c->buf == NULL) {
  2396. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2397. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2398. if (c->buf == NULL)
  2399. return -ENOMEM;
  2400. }
  2401. idx = le32_to_cpu(c->log_le.idx);
  2402. /* Protect against corrupt value */
  2403. if (idx > c->bufsize)
  2404. return -EBADE;
  2405. /* Skip reading the console buffer if the index pointer
  2406. has not moved */
  2407. if (idx == c->last)
  2408. return 0;
  2409. /* Read the console buffer */
  2410. addr = le32_to_cpu(c->log_le.buf);
  2411. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
  2412. if (rv < 0)
  2413. return rv;
  2414. while (c->last != idx) {
  2415. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2416. if (c->last == idx) {
  2417. /* This would output a partial line.
  2418. * Instead, back up
  2419. * the buffer pointer and output this
  2420. * line next time around.
  2421. */
  2422. if (c->last >= n)
  2423. c->last -= n;
  2424. else
  2425. c->last = c->bufsize - n;
  2426. goto break2;
  2427. }
  2428. ch = c->buf[c->last];
  2429. c->last = (c->last + 1) % c->bufsize;
  2430. if (ch == '\n')
  2431. break;
  2432. line[n] = ch;
  2433. }
  2434. if (n > 0) {
  2435. if (line[n - 1] == '\r')
  2436. n--;
  2437. line[n] = 0;
  2438. pr_debug("CONSOLE: %s\n", line);
  2439. }
  2440. }
  2441. break2:
  2442. return 0;
  2443. }
  2444. #endif /* DEBUG */
  2445. static int
  2446. brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
  2447. {
  2448. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2449. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2450. struct brcmf_sdio *bus = sdiodev->bus;
  2451. int ret;
  2452. brcmf_dbg(TRACE, "Enter\n");
  2453. if (sdiodev->state != BRCMF_SDIOD_DATA)
  2454. return -EIO;
  2455. /* Send from dpc */
  2456. bus->ctrl_frame_buf = msg;
  2457. bus->ctrl_frame_len = msglen;
  2458. wmb();
  2459. bus->ctrl_frame_stat = true;
  2460. brcmf_sdio_trigger_dpc(bus);
  2461. wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
  2462. CTL_DONE_TIMEOUT);
  2463. ret = 0;
  2464. if (bus->ctrl_frame_stat) {
  2465. sdio_claim_host(bus->sdiodev->func[1]);
  2466. if (bus->ctrl_frame_stat) {
  2467. brcmf_dbg(SDIO, "ctrl_frame timeout\n");
  2468. bus->ctrl_frame_stat = false;
  2469. ret = -ETIMEDOUT;
  2470. }
  2471. sdio_release_host(bus->sdiodev->func[1]);
  2472. }
  2473. if (!ret) {
  2474. brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
  2475. bus->ctrl_frame_err);
  2476. rmb();
  2477. ret = bus->ctrl_frame_err;
  2478. }
  2479. if (ret)
  2480. bus->sdcnt.tx_ctlerrs++;
  2481. else
  2482. bus->sdcnt.tx_ctlpkts++;
  2483. return ret;
  2484. }
  2485. #ifdef DEBUG
  2486. static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
  2487. struct sdpcm_shared *sh)
  2488. {
  2489. u32 addr, console_ptr, console_size, console_index;
  2490. char *conbuf = NULL;
  2491. __le32 sh_val;
  2492. int rv;
  2493. /* obtain console information from device memory */
  2494. addr = sh->console_addr + offsetof(struct rte_console, log_le);
  2495. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
  2496. (u8 *)&sh_val, sizeof(u32));
  2497. if (rv < 0)
  2498. return rv;
  2499. console_ptr = le32_to_cpu(sh_val);
  2500. addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
  2501. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
  2502. (u8 *)&sh_val, sizeof(u32));
  2503. if (rv < 0)
  2504. return rv;
  2505. console_size = le32_to_cpu(sh_val);
  2506. addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
  2507. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
  2508. (u8 *)&sh_val, sizeof(u32));
  2509. if (rv < 0)
  2510. return rv;
  2511. console_index = le32_to_cpu(sh_val);
  2512. /* allocate buffer for console data */
  2513. if (console_size <= CONSOLE_BUFFER_MAX)
  2514. conbuf = vzalloc(console_size+1);
  2515. if (!conbuf)
  2516. return -ENOMEM;
  2517. /* obtain the console data from device */
  2518. conbuf[console_size] = '\0';
  2519. rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
  2520. console_size);
  2521. if (rv < 0)
  2522. goto done;
  2523. rv = seq_write(seq, conbuf + console_index,
  2524. console_size - console_index);
  2525. if (rv < 0)
  2526. goto done;
  2527. if (console_index > 0)
  2528. rv = seq_write(seq, conbuf, console_index - 1);
  2529. done:
  2530. vfree(conbuf);
  2531. return rv;
  2532. }
  2533. static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
  2534. struct sdpcm_shared *sh)
  2535. {
  2536. int error;
  2537. struct brcmf_trap_info tr;
  2538. if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
  2539. brcmf_dbg(INFO, "no trap in firmware\n");
  2540. return 0;
  2541. }
  2542. error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
  2543. sizeof(struct brcmf_trap_info));
  2544. if (error < 0)
  2545. return error;
  2546. seq_printf(seq,
  2547. "dongle trap info: type 0x%x @ epc 0x%08x\n"
  2548. " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
  2549. " lr 0x%08x pc 0x%08x offset 0x%x\n"
  2550. " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
  2551. " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
  2552. le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
  2553. le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
  2554. le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
  2555. le32_to_cpu(tr.pc), sh->trap_addr,
  2556. le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
  2557. le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
  2558. le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
  2559. le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
  2560. return 0;
  2561. }
  2562. static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
  2563. struct sdpcm_shared *sh)
  2564. {
  2565. int error = 0;
  2566. char file[80] = "?";
  2567. char expr[80] = "<???>";
  2568. if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
  2569. brcmf_dbg(INFO, "firmware not built with -assert\n");
  2570. return 0;
  2571. } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
  2572. brcmf_dbg(INFO, "no assert in dongle\n");
  2573. return 0;
  2574. }
  2575. sdio_claim_host(bus->sdiodev->func[1]);
  2576. if (sh->assert_file_addr != 0) {
  2577. error = brcmf_sdiod_ramrw(bus->sdiodev, false,
  2578. sh->assert_file_addr, (u8 *)file, 80);
  2579. if (error < 0)
  2580. return error;
  2581. }
  2582. if (sh->assert_exp_addr != 0) {
  2583. error = brcmf_sdiod_ramrw(bus->sdiodev, false,
  2584. sh->assert_exp_addr, (u8 *)expr, 80);
  2585. if (error < 0)
  2586. return error;
  2587. }
  2588. sdio_release_host(bus->sdiodev->func[1]);
  2589. seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
  2590. file, sh->assert_line, expr);
  2591. return 0;
  2592. }
  2593. static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
  2594. {
  2595. int error;
  2596. struct sdpcm_shared sh;
  2597. error = brcmf_sdio_readshared(bus, &sh);
  2598. if (error < 0)
  2599. return error;
  2600. if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
  2601. brcmf_dbg(INFO, "firmware not built with -assert\n");
  2602. else if (sh.flags & SDPCM_SHARED_ASSERT)
  2603. brcmf_err("assertion in dongle\n");
  2604. if (sh.flags & SDPCM_SHARED_TRAP)
  2605. brcmf_err("firmware trap in dongle\n");
  2606. return 0;
  2607. }
  2608. static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
  2609. {
  2610. int error = 0;
  2611. struct sdpcm_shared sh;
  2612. error = brcmf_sdio_readshared(bus, &sh);
  2613. if (error < 0)
  2614. goto done;
  2615. error = brcmf_sdio_assert_info(seq, bus, &sh);
  2616. if (error < 0)
  2617. goto done;
  2618. error = brcmf_sdio_trap_info(seq, bus, &sh);
  2619. if (error < 0)
  2620. goto done;
  2621. error = brcmf_sdio_dump_console(seq, bus, &sh);
  2622. done:
  2623. return error;
  2624. }
  2625. static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
  2626. {
  2627. struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
  2628. struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
  2629. return brcmf_sdio_died_dump(seq, bus);
  2630. }
  2631. static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
  2632. {
  2633. struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
  2634. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2635. struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
  2636. seq_printf(seq,
  2637. "intrcount: %u\nlastintrs: %u\n"
  2638. "pollcnt: %u\nregfails: %u\n"
  2639. "tx_sderrs: %u\nfcqueued: %u\n"
  2640. "rxrtx: %u\nrx_toolong: %u\n"
  2641. "rxc_errors: %u\nrx_hdrfail: %u\n"
  2642. "rx_badhdr: %u\nrx_badseq: %u\n"
  2643. "fc_rcvd: %u\nfc_xoff: %u\n"
  2644. "fc_xon: %u\nrxglomfail: %u\n"
  2645. "rxglomframes: %u\nrxglompkts: %u\n"
  2646. "f2rxhdrs: %u\nf2rxdata: %u\n"
  2647. "f2txdata: %u\nf1regdata: %u\n"
  2648. "tickcnt: %u\ntx_ctlerrs: %lu\n"
  2649. "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
  2650. "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
  2651. sdcnt->intrcount, sdcnt->lastintrs,
  2652. sdcnt->pollcnt, sdcnt->regfails,
  2653. sdcnt->tx_sderrs, sdcnt->fcqueued,
  2654. sdcnt->rxrtx, sdcnt->rx_toolong,
  2655. sdcnt->rxc_errors, sdcnt->rx_hdrfail,
  2656. sdcnt->rx_badhdr, sdcnt->rx_badseq,
  2657. sdcnt->fc_rcvd, sdcnt->fc_xoff,
  2658. sdcnt->fc_xon, sdcnt->rxglomfail,
  2659. sdcnt->rxglomframes, sdcnt->rxglompkts,
  2660. sdcnt->f2rxhdrs, sdcnt->f2rxdata,
  2661. sdcnt->f2txdata, sdcnt->f1regdata,
  2662. sdcnt->tickcnt, sdcnt->tx_ctlerrs,
  2663. sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
  2664. sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
  2665. return 0;
  2666. }
  2667. static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
  2668. {
  2669. struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
  2670. struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
  2671. if (IS_ERR_OR_NULL(dentry))
  2672. return;
  2673. bus->console_interval = BRCMF_CONSOLE;
  2674. brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
  2675. brcmf_debugfs_add_entry(drvr, "counters",
  2676. brcmf_debugfs_sdio_count_read);
  2677. debugfs_create_u32("console_interval", 0644, dentry,
  2678. &bus->console_interval);
  2679. }
  2680. #else
  2681. static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
  2682. {
  2683. return 0;
  2684. }
  2685. static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
  2686. {
  2687. }
  2688. #endif /* DEBUG */
  2689. static int
  2690. brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
  2691. {
  2692. int timeleft;
  2693. uint rxlen = 0;
  2694. bool pending;
  2695. u8 *buf;
  2696. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2697. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2698. struct brcmf_sdio *bus = sdiodev->bus;
  2699. brcmf_dbg(TRACE, "Enter\n");
  2700. if (sdiodev->state != BRCMF_SDIOD_DATA)
  2701. return -EIO;
  2702. /* Wait until control frame is available */
  2703. timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2704. spin_lock_bh(&bus->rxctl_lock);
  2705. rxlen = bus->rxlen;
  2706. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2707. bus->rxctl = NULL;
  2708. buf = bus->rxctl_orig;
  2709. bus->rxctl_orig = NULL;
  2710. bus->rxlen = 0;
  2711. spin_unlock_bh(&bus->rxctl_lock);
  2712. vfree(buf);
  2713. if (rxlen) {
  2714. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2715. rxlen, msglen);
  2716. } else if (timeleft == 0) {
  2717. brcmf_err("resumed on timeout\n");
  2718. brcmf_sdio_checkdied(bus);
  2719. } else if (pending) {
  2720. brcmf_dbg(CTL, "cancelled\n");
  2721. return -ERESTARTSYS;
  2722. } else {
  2723. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2724. brcmf_sdio_checkdied(bus);
  2725. }
  2726. if (rxlen)
  2727. bus->sdcnt.rx_ctlpkts++;
  2728. else
  2729. bus->sdcnt.rx_ctlerrs++;
  2730. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2731. }
  2732. #ifdef DEBUG
  2733. static bool
  2734. brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
  2735. u8 *ram_data, uint ram_sz)
  2736. {
  2737. char *ram_cmp;
  2738. int err;
  2739. bool ret = true;
  2740. int address;
  2741. int offset;
  2742. int len;
  2743. /* read back and verify */
  2744. brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
  2745. ram_sz);
  2746. ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
  2747. /* do not proceed while no memory but */
  2748. if (!ram_cmp)
  2749. return true;
  2750. address = ram_addr;
  2751. offset = 0;
  2752. while (offset < ram_sz) {
  2753. len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
  2754. ram_sz - offset;
  2755. err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
  2756. if (err) {
  2757. brcmf_err("error %d on reading %d membytes at 0x%08x\n",
  2758. err, len, address);
  2759. ret = false;
  2760. break;
  2761. } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
  2762. brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
  2763. offset, len);
  2764. ret = false;
  2765. break;
  2766. }
  2767. offset += len;
  2768. address += len;
  2769. }
  2770. kfree(ram_cmp);
  2771. return ret;
  2772. }
  2773. #else /* DEBUG */
  2774. static bool
  2775. brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
  2776. u8 *ram_data, uint ram_sz)
  2777. {
  2778. return true;
  2779. }
  2780. #endif /* DEBUG */
  2781. static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
  2782. const struct firmware *fw)
  2783. {
  2784. int err;
  2785. brcmf_dbg(TRACE, "Enter\n");
  2786. err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
  2787. (u8 *)fw->data, fw->size);
  2788. if (err)
  2789. brcmf_err("error %d on writing %d membytes at 0x%08x\n",
  2790. err, (int)fw->size, bus->ci->rambase);
  2791. else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
  2792. (u8 *)fw->data, fw->size))
  2793. err = -EIO;
  2794. return err;
  2795. }
  2796. static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
  2797. void *vars, u32 varsz)
  2798. {
  2799. int address;
  2800. int err;
  2801. brcmf_dbg(TRACE, "Enter\n");
  2802. address = bus->ci->ramsize - varsz + bus->ci->rambase;
  2803. err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
  2804. if (err)
  2805. brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
  2806. err, varsz, address);
  2807. else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
  2808. err = -EIO;
  2809. return err;
  2810. }
  2811. static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
  2812. const struct firmware *fw,
  2813. void *nvram, u32 nvlen)
  2814. {
  2815. int bcmerror;
  2816. u32 rstvec;
  2817. sdio_claim_host(bus->sdiodev->func[1]);
  2818. brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
  2819. rstvec = get_unaligned_le32(fw->data);
  2820. brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
  2821. bcmerror = brcmf_sdio_download_code_file(bus, fw);
  2822. release_firmware(fw);
  2823. if (bcmerror) {
  2824. brcmf_err("dongle image file download failed\n");
  2825. brcmf_fw_nvram_free(nvram);
  2826. goto err;
  2827. }
  2828. bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
  2829. brcmf_fw_nvram_free(nvram);
  2830. if (bcmerror) {
  2831. brcmf_err("dongle nvram file download failed\n");
  2832. goto err;
  2833. }
  2834. /* Take arm out of reset */
  2835. if (!brcmf_chip_set_active(bus->ci, rstvec)) {
  2836. brcmf_err("error getting out of ARM core reset\n");
  2837. goto err;
  2838. }
  2839. err:
  2840. brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
  2841. sdio_release_host(bus->sdiodev->func[1]);
  2842. return bcmerror;
  2843. }
  2844. static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
  2845. {
  2846. int err = 0;
  2847. u8 val;
  2848. brcmf_dbg(TRACE, "Enter\n");
  2849. val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
  2850. if (err) {
  2851. brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
  2852. return;
  2853. }
  2854. val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
  2855. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
  2856. if (err) {
  2857. brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
  2858. return;
  2859. }
  2860. /* Add CMD14 Support */
  2861. brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
  2862. (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
  2863. SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
  2864. &err);
  2865. if (err) {
  2866. brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
  2867. return;
  2868. }
  2869. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  2870. SBSDIO_FORCE_HT, &err);
  2871. if (err) {
  2872. brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
  2873. return;
  2874. }
  2875. /* set flag */
  2876. bus->sr_enabled = true;
  2877. brcmf_dbg(INFO, "SR enabled\n");
  2878. }
  2879. /* enable KSO bit */
  2880. static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
  2881. {
  2882. u8 val;
  2883. int err = 0;
  2884. brcmf_dbg(TRACE, "Enter\n");
  2885. /* KSO bit added in SDIO core rev 12 */
  2886. if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
  2887. return 0;
  2888. val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
  2889. if (err) {
  2890. brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
  2891. return err;
  2892. }
  2893. if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
  2894. val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
  2895. SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
  2896. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  2897. val, &err);
  2898. if (err) {
  2899. brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
  2900. return err;
  2901. }
  2902. }
  2903. return 0;
  2904. }
  2905. static int brcmf_sdio_bus_preinit(struct device *dev)
  2906. {
  2907. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2908. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2909. struct brcmf_sdio *bus = sdiodev->bus;
  2910. uint pad_size;
  2911. u32 value;
  2912. int err;
  2913. /* the commands below use the terms tx and rx from
  2914. * a device perspective, ie. bus:txglom affects the
  2915. * bus transfers from device to host.
  2916. */
  2917. if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
  2918. /* for sdio core rev < 12, disable txgloming */
  2919. value = 0;
  2920. err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
  2921. sizeof(u32));
  2922. } else {
  2923. /* otherwise, set txglomalign */
  2924. value = sdiodev->settings->bus.sdio.sd_sgentry_align;
  2925. /* SDIO ADMA requires at least 32 bit alignment */
  2926. value = max_t(u32, value, 4);
  2927. err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
  2928. sizeof(u32));
  2929. }
  2930. if (err < 0)
  2931. goto done;
  2932. bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
  2933. if (sdiodev->sg_support) {
  2934. bus->txglom = false;
  2935. value = 1;
  2936. pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
  2937. err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
  2938. &value, sizeof(u32));
  2939. if (err < 0) {
  2940. /* bus:rxglom is allowed to fail */
  2941. err = 0;
  2942. } else {
  2943. bus->txglom = true;
  2944. bus->tx_hdrlen += SDPCM_HWEXT_LEN;
  2945. }
  2946. }
  2947. brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
  2948. done:
  2949. return err;
  2950. }
  2951. static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
  2952. {
  2953. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2954. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2955. struct brcmf_sdio *bus = sdiodev->bus;
  2956. return bus->ci->ramsize - bus->ci->srsize;
  2957. }
  2958. static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
  2959. size_t mem_size)
  2960. {
  2961. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2962. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  2963. struct brcmf_sdio *bus = sdiodev->bus;
  2964. int err;
  2965. int address;
  2966. int offset;
  2967. int len;
  2968. brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
  2969. mem_size);
  2970. address = bus->ci->rambase;
  2971. offset = err = 0;
  2972. sdio_claim_host(sdiodev->func[1]);
  2973. while (offset < mem_size) {
  2974. len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
  2975. mem_size - offset;
  2976. err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
  2977. if (err) {
  2978. brcmf_err("error %d on reading %d membytes at 0x%08x\n",
  2979. err, len, address);
  2980. goto done;
  2981. }
  2982. data += len;
  2983. offset += len;
  2984. address += len;
  2985. }
  2986. done:
  2987. sdio_release_host(sdiodev->func[1]);
  2988. return err;
  2989. }
  2990. void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
  2991. {
  2992. if (!bus->dpc_triggered) {
  2993. bus->dpc_triggered = true;
  2994. queue_work(bus->brcmf_wq, &bus->datawork);
  2995. }
  2996. }
  2997. void brcmf_sdio_isr(struct brcmf_sdio *bus)
  2998. {
  2999. brcmf_dbg(TRACE, "Enter\n");
  3000. if (!bus) {
  3001. brcmf_err("bus is null pointer, exiting\n");
  3002. return;
  3003. }
  3004. /* Count the interrupt call */
  3005. bus->sdcnt.intrcount++;
  3006. if (in_interrupt())
  3007. atomic_set(&bus->ipend, 1);
  3008. else
  3009. if (brcmf_sdio_intr_rstatus(bus)) {
  3010. brcmf_err("failed backplane access\n");
  3011. }
  3012. /* Disable additional interrupts (is this needed now)? */
  3013. if (!bus->intr)
  3014. brcmf_err("isr w/o interrupt configured!\n");
  3015. bus->dpc_triggered = true;
  3016. queue_work(bus->brcmf_wq, &bus->datawork);
  3017. }
  3018. static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
  3019. {
  3020. brcmf_dbg(TIMER, "Enter\n");
  3021. /* Poll period: check device if appropriate. */
  3022. if (!bus->sr_enabled &&
  3023. bus->poll && (++bus->polltick >= bus->pollrate)) {
  3024. u32 intstatus = 0;
  3025. /* Reset poll tick */
  3026. bus->polltick = 0;
  3027. /* Check device if no interrupts */
  3028. if (!bus->intr ||
  3029. (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
  3030. if (!bus->dpc_triggered) {
  3031. u8 devpend;
  3032. sdio_claim_host(bus->sdiodev->func[1]);
  3033. devpend = brcmf_sdiod_regrb(bus->sdiodev,
  3034. SDIO_CCCR_INTx,
  3035. NULL);
  3036. sdio_release_host(bus->sdiodev->func[1]);
  3037. intstatus = devpend & (INTR_STATUS_FUNC1 |
  3038. INTR_STATUS_FUNC2);
  3039. }
  3040. /* If there is something, make like the ISR and
  3041. schedule the DPC */
  3042. if (intstatus) {
  3043. bus->sdcnt.pollcnt++;
  3044. atomic_set(&bus->ipend, 1);
  3045. bus->dpc_triggered = true;
  3046. queue_work(bus->brcmf_wq, &bus->datawork);
  3047. }
  3048. }
  3049. /* Update interrupt tracking */
  3050. bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
  3051. }
  3052. #ifdef DEBUG
  3053. /* Poll for console output periodically */
  3054. if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
  3055. bus->console_interval != 0) {
  3056. bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
  3057. if (bus->console.count >= bus->console_interval) {
  3058. bus->console.count -= bus->console_interval;
  3059. sdio_claim_host(bus->sdiodev->func[1]);
  3060. /* Make sure backplane clock is on */
  3061. brcmf_sdio_bus_sleep(bus, false, false);
  3062. if (brcmf_sdio_readconsole(bus) < 0)
  3063. /* stop on error */
  3064. bus->console_interval = 0;
  3065. sdio_release_host(bus->sdiodev->func[1]);
  3066. }
  3067. }
  3068. #endif /* DEBUG */
  3069. /* On idle timeout clear activity flag and/or turn off clock */
  3070. if (!bus->dpc_triggered) {
  3071. rmb();
  3072. if ((!bus->dpc_running) && (bus->idletime > 0) &&
  3073. (bus->clkstate == CLK_AVAIL)) {
  3074. bus->idlecount++;
  3075. if (bus->idlecount > bus->idletime) {
  3076. brcmf_dbg(SDIO, "idle\n");
  3077. sdio_claim_host(bus->sdiodev->func[1]);
  3078. brcmf_sdio_wd_timer(bus, false);
  3079. bus->idlecount = 0;
  3080. brcmf_sdio_bus_sleep(bus, true, false);
  3081. sdio_release_host(bus->sdiodev->func[1]);
  3082. }
  3083. } else {
  3084. bus->idlecount = 0;
  3085. }
  3086. } else {
  3087. bus->idlecount = 0;
  3088. }
  3089. }
  3090. static void brcmf_sdio_dataworker(struct work_struct *work)
  3091. {
  3092. struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
  3093. datawork);
  3094. bus->dpc_running = true;
  3095. wmb();
  3096. while (ACCESS_ONCE(bus->dpc_triggered)) {
  3097. bus->dpc_triggered = false;
  3098. brcmf_sdio_dpc(bus);
  3099. bus->idlecount = 0;
  3100. }
  3101. bus->dpc_running = false;
  3102. if (brcmf_sdiod_freezing(bus->sdiodev)) {
  3103. brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
  3104. brcmf_sdiod_try_freeze(bus->sdiodev);
  3105. brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
  3106. }
  3107. }
  3108. static void
  3109. brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
  3110. struct brcmf_chip *ci, u32 drivestrength)
  3111. {
  3112. const struct sdiod_drive_str *str_tab = NULL;
  3113. u32 str_mask;
  3114. u32 str_shift;
  3115. u32 i;
  3116. u32 drivestrength_sel = 0;
  3117. u32 cc_data_temp;
  3118. u32 addr;
  3119. if (!(ci->cc_caps & CC_CAP_PMU))
  3120. return;
  3121. switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
  3122. case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
  3123. str_tab = sdiod_drvstr_tab1_1v8;
  3124. str_mask = 0x00003800;
  3125. str_shift = 11;
  3126. break;
  3127. case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
  3128. str_tab = sdiod_drvstr_tab6_1v8;
  3129. str_mask = 0x00001800;
  3130. str_shift = 11;
  3131. break;
  3132. case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
  3133. /* note: 43143 does not support tristate */
  3134. i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
  3135. if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
  3136. str_tab = sdiod_drvstr_tab2_3v3;
  3137. str_mask = 0x00000007;
  3138. str_shift = 0;
  3139. } else
  3140. brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
  3141. ci->name, drivestrength);
  3142. break;
  3143. case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
  3144. str_tab = sdiod_drive_strength_tab5_1v8;
  3145. str_mask = 0x00003800;
  3146. str_shift = 11;
  3147. break;
  3148. default:
  3149. brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
  3150. ci->name, ci->chiprev, ci->pmurev);
  3151. break;
  3152. }
  3153. if (str_tab != NULL) {
  3154. struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
  3155. for (i = 0; str_tab[i].strength != 0; i++) {
  3156. if (drivestrength >= str_tab[i].strength) {
  3157. drivestrength_sel = str_tab[i].sel;
  3158. break;
  3159. }
  3160. }
  3161. addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
  3162. brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
  3163. cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
  3164. cc_data_temp &= ~str_mask;
  3165. drivestrength_sel <<= str_shift;
  3166. cc_data_temp |= drivestrength_sel;
  3167. brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
  3168. brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
  3169. str_tab[i].strength, drivestrength, cc_data_temp);
  3170. }
  3171. }
  3172. static int brcmf_sdio_buscoreprep(void *ctx)
  3173. {
  3174. struct brcmf_sdio_dev *sdiodev = ctx;
  3175. int err = 0;
  3176. u8 clkval, clkset;
  3177. /* Try forcing SDIO core to do ALPAvail request only */
  3178. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
  3179. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  3180. if (err) {
  3181. brcmf_err("error writing for HT off\n");
  3182. return err;
  3183. }
  3184. /* If register supported, wait for ALPAvail and then force ALP */
  3185. /* This may take up to 15 milliseconds */
  3186. clkval = brcmf_sdiod_regrb(sdiodev,
  3187. SBSDIO_FUNC1_CHIPCLKCSR, NULL);
  3188. if ((clkval & ~SBSDIO_AVBITS) != clkset) {
  3189. brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
  3190. clkset, clkval);
  3191. return -EACCES;
  3192. }
  3193. SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
  3194. SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
  3195. !SBSDIO_ALPAV(clkval)),
  3196. PMU_MAX_TRANSITION_DLY);
  3197. if (!SBSDIO_ALPAV(clkval)) {
  3198. brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
  3199. clkval);
  3200. return -EBUSY;
  3201. }
  3202. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
  3203. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  3204. udelay(65);
  3205. /* Also, disable the extra SDIO pull-ups */
  3206. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
  3207. return 0;
  3208. }
  3209. static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
  3210. u32 rstvec)
  3211. {
  3212. struct brcmf_sdio_dev *sdiodev = ctx;
  3213. struct brcmf_core *core;
  3214. u32 reg_addr;
  3215. /* clear all interrupts */
  3216. core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
  3217. reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
  3218. brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
  3219. if (rstvec)
  3220. /* Write reset vector to address 0 */
  3221. brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
  3222. sizeof(rstvec));
  3223. }
  3224. static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
  3225. {
  3226. struct brcmf_sdio_dev *sdiodev = ctx;
  3227. u32 val, rev;
  3228. val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
  3229. if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
  3230. addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
  3231. rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
  3232. if (rev >= 2) {
  3233. val &= ~CID_ID_MASK;
  3234. val |= BRCM_CC_4339_CHIP_ID;
  3235. }
  3236. }
  3237. return val;
  3238. }
  3239. static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
  3240. {
  3241. struct brcmf_sdio_dev *sdiodev = ctx;
  3242. brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
  3243. }
  3244. static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
  3245. .prepare = brcmf_sdio_buscoreprep,
  3246. .activate = brcmf_sdio_buscore_activate,
  3247. .read32 = brcmf_sdio_buscore_read32,
  3248. .write32 = brcmf_sdio_buscore_write32,
  3249. };
  3250. static bool
  3251. brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
  3252. {
  3253. struct brcmf_sdio_dev *sdiodev;
  3254. u8 clkctl = 0;
  3255. int err = 0;
  3256. int reg_addr;
  3257. u32 reg_val;
  3258. u32 drivestrength;
  3259. sdiodev = bus->sdiodev;
  3260. sdio_claim_host(sdiodev->func[1]);
  3261. pr_debug("F1 signature read @0x18000000=0x%4x\n",
  3262. brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
  3263. /*
  3264. * Force PLL off until brcmf_chip_attach()
  3265. * programs PLL control regs
  3266. */
  3267. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  3268. BRCMF_INIT_CLKCTL1, &err);
  3269. if (!err)
  3270. clkctl = brcmf_sdiod_regrb(sdiodev,
  3271. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3272. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3273. brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3274. err, BRCMF_INIT_CLKCTL1, clkctl);
  3275. goto fail;
  3276. }
  3277. bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
  3278. if (IS_ERR(bus->ci)) {
  3279. brcmf_err("brcmf_chip_attach failed!\n");
  3280. bus->ci = NULL;
  3281. goto fail;
  3282. }
  3283. sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
  3284. BRCMF_BUSTYPE_SDIO,
  3285. bus->ci->chip,
  3286. bus->ci->chiprev);
  3287. if (!sdiodev->settings) {
  3288. brcmf_err("Failed to get device parameters\n");
  3289. goto fail;
  3290. }
  3291. /* platform specific configuration:
  3292. * alignments must be at least 4 bytes for ADMA
  3293. */
  3294. bus->head_align = ALIGNMENT;
  3295. bus->sgentry_align = ALIGNMENT;
  3296. if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
  3297. bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
  3298. if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
  3299. bus->sgentry_align =
  3300. sdiodev->settings->bus.sdio.sd_sgentry_align;
  3301. /* allocate scatter-gather table. sg support
  3302. * will be disabled upon allocation failure.
  3303. */
  3304. brcmf_sdiod_sgtable_alloc(sdiodev);
  3305. #ifdef CONFIG_PM_SLEEP
  3306. /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
  3307. * is true or when platform data OOB irq is true).
  3308. */
  3309. if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
  3310. ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
  3311. (sdiodev->settings->bus.sdio.oob_irq_supported)))
  3312. sdiodev->bus_if->wowl_supported = true;
  3313. #endif
  3314. if (brcmf_sdio_kso_init(bus)) {
  3315. brcmf_err("error enabling KSO\n");
  3316. goto fail;
  3317. }
  3318. if (sdiodev->settings->bus.sdio.drive_strength)
  3319. drivestrength = sdiodev->settings->bus.sdio.drive_strength;
  3320. else
  3321. drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
  3322. brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
  3323. /* Set card control so an SDIO card reset does a WLAN backplane reset */
  3324. reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
  3325. if (err)
  3326. goto fail;
  3327. reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
  3328. brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
  3329. if (err)
  3330. goto fail;
  3331. /* set PMUControl so a backplane reset does PMU state reload */
  3332. reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
  3333. reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
  3334. if (err)
  3335. goto fail;
  3336. reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
  3337. brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
  3338. if (err)
  3339. goto fail;
  3340. sdio_release_host(sdiodev->func[1]);
  3341. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3342. /* allocate header buffer */
  3343. bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
  3344. if (!bus->hdrbuf)
  3345. return false;
  3346. /* Locate an appropriately-aligned portion of hdrbuf */
  3347. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3348. bus->head_align);
  3349. /* Set the poll and/or interrupt flags */
  3350. bus->intr = true;
  3351. bus->poll = false;
  3352. if (bus->poll)
  3353. bus->pollrate = 1;
  3354. return true;
  3355. fail:
  3356. sdio_release_host(sdiodev->func[1]);
  3357. return false;
  3358. }
  3359. static int
  3360. brcmf_sdio_watchdog_thread(void *data)
  3361. {
  3362. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3363. int wait;
  3364. allow_signal(SIGTERM);
  3365. /* Run until signal received */
  3366. brcmf_sdiod_freezer_count(bus->sdiodev);
  3367. while (1) {
  3368. if (kthread_should_stop())
  3369. break;
  3370. brcmf_sdiod_freezer_uncount(bus->sdiodev);
  3371. wait = wait_for_completion_interruptible(&bus->watchdog_wait);
  3372. brcmf_sdiod_freezer_count(bus->sdiodev);
  3373. brcmf_sdiod_try_freeze(bus->sdiodev);
  3374. if (!wait) {
  3375. brcmf_sdio_bus_watchdog(bus);
  3376. /* Count the tick for reference */
  3377. bus->sdcnt.tickcnt++;
  3378. reinit_completion(&bus->watchdog_wait);
  3379. } else
  3380. break;
  3381. }
  3382. return 0;
  3383. }
  3384. static void
  3385. brcmf_sdio_watchdog(unsigned long data)
  3386. {
  3387. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3388. if (bus->watchdog_tsk) {
  3389. complete(&bus->watchdog_wait);
  3390. /* Reschedule the watchdog */
  3391. if (bus->wd_active)
  3392. mod_timer(&bus->timer,
  3393. jiffies + BRCMF_WD_POLL);
  3394. }
  3395. }
  3396. static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
  3397. .stop = brcmf_sdio_bus_stop,
  3398. .preinit = brcmf_sdio_bus_preinit,
  3399. .txdata = brcmf_sdio_bus_txdata,
  3400. .txctl = brcmf_sdio_bus_txctl,
  3401. .rxctl = brcmf_sdio_bus_rxctl,
  3402. .gettxq = brcmf_sdio_bus_gettxq,
  3403. .wowl_config = brcmf_sdio_wowl_config,
  3404. .get_ramsize = brcmf_sdio_bus_get_ramsize,
  3405. .get_memdump = brcmf_sdio_bus_get_memdump,
  3406. };
  3407. static void brcmf_sdio_firmware_callback(struct device *dev,
  3408. const struct firmware *code,
  3409. void *nvram, u32 nvram_len)
  3410. {
  3411. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  3412. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
  3413. struct brcmf_sdio *bus = sdiodev->bus;
  3414. int err = 0;
  3415. u8 saveclk;
  3416. brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
  3417. if (!bus_if->drvr)
  3418. return;
  3419. /* try to download image and nvram to the dongle */
  3420. bus->alp_only = true;
  3421. err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
  3422. if (err)
  3423. goto fail;
  3424. bus->alp_only = false;
  3425. /* Start the watchdog timer */
  3426. bus->sdcnt.tickcnt = 0;
  3427. brcmf_sdio_wd_timer(bus, true);
  3428. sdio_claim_host(sdiodev->func[1]);
  3429. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  3430. brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
  3431. if (bus->clkstate != CLK_AVAIL)
  3432. goto release;
  3433. /* Force clocks on backplane to be sure F2 interrupt propagates */
  3434. saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3435. if (!err) {
  3436. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  3437. (saveclk | SBSDIO_FORCE_HT), &err);
  3438. }
  3439. if (err) {
  3440. brcmf_err("Failed to force clock for F2: err %d\n", err);
  3441. goto release;
  3442. }
  3443. /* Enable function 2 (frame transfers) */
  3444. w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
  3445. offsetof(struct sdpcmd_regs, tosbmailboxdata));
  3446. err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
  3447. brcmf_dbg(INFO, "enable F2: err=%d\n", err);
  3448. /* If F2 successfully enabled, set core and enable interrupts */
  3449. if (!err) {
  3450. /* Set up the interrupt mask and enable interrupts */
  3451. bus->hostintmask = HOSTINTMASK;
  3452. w_sdreg32(bus, bus->hostintmask,
  3453. offsetof(struct sdpcmd_regs, hostintmask));
  3454. brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
  3455. } else {
  3456. /* Disable F2 again */
  3457. sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
  3458. goto release;
  3459. }
  3460. if (brcmf_chip_sr_capable(bus->ci)) {
  3461. brcmf_sdio_sr_init(bus);
  3462. } else {
  3463. /* Restore previous clock setting */
  3464. brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  3465. saveclk, &err);
  3466. }
  3467. if (err == 0) {
  3468. /* Allow full data communication using DPC from now on. */
  3469. brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
  3470. err = brcmf_sdiod_intr_register(sdiodev);
  3471. if (err != 0)
  3472. brcmf_err("intr register failed:%d\n", err);
  3473. }
  3474. /* If we didn't come up, turn off backplane clock */
  3475. if (err != 0)
  3476. brcmf_sdio_clkctl(bus, CLK_NONE, false);
  3477. sdio_release_host(sdiodev->func[1]);
  3478. err = brcmf_bus_start(dev);
  3479. if (err != 0) {
  3480. brcmf_err("dongle is not responding\n");
  3481. goto fail;
  3482. }
  3483. return;
  3484. release:
  3485. sdio_release_host(sdiodev->func[1]);
  3486. fail:
  3487. brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
  3488. device_release_driver(dev);
  3489. }
  3490. struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
  3491. {
  3492. int ret;
  3493. struct brcmf_sdio *bus;
  3494. struct workqueue_struct *wq;
  3495. brcmf_dbg(TRACE, "Enter\n");
  3496. /* Allocate private bus interface state */
  3497. bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
  3498. if (!bus)
  3499. goto fail;
  3500. bus->sdiodev = sdiodev;
  3501. sdiodev->bus = bus;
  3502. skb_queue_head_init(&bus->glom);
  3503. bus->txbound = BRCMF_TXBOUND;
  3504. bus->rxbound = BRCMF_RXBOUND;
  3505. bus->txminmax = BRCMF_TXMINMAX;
  3506. bus->tx_seq = SDPCM_SEQ_WRAP - 1;
  3507. /* single-threaded workqueue */
  3508. wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
  3509. dev_name(&sdiodev->func[1]->dev));
  3510. if (!wq) {
  3511. brcmf_err("insufficient memory to create txworkqueue\n");
  3512. goto fail;
  3513. }
  3514. brcmf_sdiod_freezer_count(sdiodev);
  3515. INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
  3516. bus->brcmf_wq = wq;
  3517. /* attempt to attach to the dongle */
  3518. if (!(brcmf_sdio_probe_attach(bus))) {
  3519. brcmf_err("brcmf_sdio_probe_attach failed\n");
  3520. goto fail;
  3521. }
  3522. spin_lock_init(&bus->rxctl_lock);
  3523. spin_lock_init(&bus->txq_lock);
  3524. init_waitqueue_head(&bus->ctrl_wait);
  3525. init_waitqueue_head(&bus->dcmd_resp_wait);
  3526. /* Set up the watchdog timer */
  3527. init_timer(&bus->timer);
  3528. bus->timer.data = (unsigned long)bus;
  3529. bus->timer.function = brcmf_sdio_watchdog;
  3530. /* Initialize watchdog thread */
  3531. init_completion(&bus->watchdog_wait);
  3532. bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
  3533. bus, "brcmf_wdog/%s",
  3534. dev_name(&sdiodev->func[1]->dev));
  3535. if (IS_ERR(bus->watchdog_tsk)) {
  3536. pr_warn("brcmf_watchdog thread failed to start\n");
  3537. bus->watchdog_tsk = NULL;
  3538. }
  3539. /* Initialize DPC thread */
  3540. bus->dpc_triggered = false;
  3541. bus->dpc_running = false;
  3542. /* Assign bus interface call back */
  3543. bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
  3544. bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
  3545. bus->sdiodev->bus_if->chip = bus->ci->chip;
  3546. bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
  3547. /* default sdio bus header length for tx packet */
  3548. bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
  3549. /* Attach to the common layer, reserve hdr space */
  3550. ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
  3551. if (ret != 0) {
  3552. brcmf_err("brcmf_attach failed\n");
  3553. goto fail;
  3554. }
  3555. /* allocate scatter-gather table. sg support
  3556. * will be disabled upon allocation failure.
  3557. */
  3558. brcmf_sdiod_sgtable_alloc(bus->sdiodev);
  3559. /* Query the F2 block size, set roundup accordingly */
  3560. bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
  3561. bus->roundup = min(max_roundup, bus->blocksize);
  3562. /* Allocate buffers */
  3563. if (bus->sdiodev->bus_if->maxctl) {
  3564. bus->sdiodev->bus_if->maxctl += bus->roundup;
  3565. bus->rxblen =
  3566. roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
  3567. ALIGNMENT) + bus->head_align;
  3568. bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
  3569. if (!(bus->rxbuf)) {
  3570. brcmf_err("rxbuf allocation failed\n");
  3571. goto fail;
  3572. }
  3573. }
  3574. sdio_claim_host(bus->sdiodev->func[1]);
  3575. /* Disable F2 to clear any intermediate frame state on the dongle */
  3576. sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
  3577. bus->rxflow = false;
  3578. /* Done with backplane-dependent accesses, can drop clock... */
  3579. brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3580. sdio_release_host(bus->sdiodev->func[1]);
  3581. /* ...and initialize clock/power states */
  3582. bus->clkstate = CLK_SDONLY;
  3583. bus->idletime = BRCMF_IDLE_INTERVAL;
  3584. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3585. /* SR state */
  3586. bus->sr_enabled = false;
  3587. brcmf_sdio_debugfs_create(bus);
  3588. brcmf_dbg(INFO, "completed!!\n");
  3589. ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
  3590. brcmf_sdio_fwnames,
  3591. ARRAY_SIZE(brcmf_sdio_fwnames),
  3592. sdiodev->fw_name, sdiodev->nvram_name);
  3593. if (ret)
  3594. goto fail;
  3595. ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
  3596. sdiodev->fw_name, sdiodev->nvram_name,
  3597. brcmf_sdio_firmware_callback);
  3598. if (ret != 0) {
  3599. brcmf_err("async firmware request failed: %d\n", ret);
  3600. goto fail;
  3601. }
  3602. return bus;
  3603. fail:
  3604. brcmf_sdio_remove(bus);
  3605. return NULL;
  3606. }
  3607. /* Detach and free everything */
  3608. void brcmf_sdio_remove(struct brcmf_sdio *bus)
  3609. {
  3610. brcmf_dbg(TRACE, "Enter\n");
  3611. if (bus) {
  3612. /* De-register interrupt handler */
  3613. brcmf_sdiod_intr_unregister(bus->sdiodev);
  3614. brcmf_detach(bus->sdiodev->dev);
  3615. cancel_work_sync(&bus->datawork);
  3616. if (bus->brcmf_wq)
  3617. destroy_workqueue(bus->brcmf_wq);
  3618. if (bus->ci) {
  3619. if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
  3620. sdio_claim_host(bus->sdiodev->func[1]);
  3621. brcmf_sdio_wd_timer(bus, false);
  3622. brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
  3623. /* Leave the device in state where it is
  3624. * 'passive'. This is done by resetting all
  3625. * necessary cores.
  3626. */
  3627. msleep(20);
  3628. brcmf_chip_set_passive(bus->ci);
  3629. brcmf_sdio_clkctl(bus, CLK_NONE, false);
  3630. sdio_release_host(bus->sdiodev->func[1]);
  3631. }
  3632. brcmf_chip_detach(bus->ci);
  3633. }
  3634. if (bus->sdiodev->settings)
  3635. brcmf_release_module_param(bus->sdiodev->settings);
  3636. kfree(bus->rxbuf);
  3637. kfree(bus->hdrbuf);
  3638. kfree(bus);
  3639. }
  3640. brcmf_dbg(TRACE, "Disconnected\n");
  3641. }
  3642. void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
  3643. {
  3644. /* Totally stop the timer */
  3645. if (!active && bus->wd_active) {
  3646. del_timer_sync(&bus->timer);
  3647. bus->wd_active = false;
  3648. return;
  3649. }
  3650. /* don't start the wd until fw is loaded */
  3651. if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
  3652. return;
  3653. if (active) {
  3654. if (!bus->wd_active) {
  3655. /* Create timer again when watchdog period is
  3656. dynamically changed or in the first instance
  3657. */
  3658. bus->timer.expires = jiffies + BRCMF_WD_POLL;
  3659. add_timer(&bus->timer);
  3660. bus->wd_active = true;
  3661. } else {
  3662. /* Re arm the timer, at last watchdog period */
  3663. mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
  3664. }
  3665. }
  3666. }
  3667. int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
  3668. {
  3669. int ret;
  3670. sdio_claim_host(bus->sdiodev->func[1]);
  3671. ret = brcmf_sdio_bus_sleep(bus, sleep, false);
  3672. sdio_release_host(bus->sdiodev->func[1]);
  3673. return ret;
  3674. }