core.c 57 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include <asm/byteorder.h>
  21. #include "core.h"
  22. #include "mac.h"
  23. #include "htc.h"
  24. #include "hif.h"
  25. #include "wmi.h"
  26. #include "bmi.h"
  27. #include "debug.h"
  28. #include "htt.h"
  29. #include "testmode.h"
  30. #include "wmi-ops.h"
  31. unsigned int ath10k_debug_mask;
  32. static unsigned int ath10k_cryptmode_param;
  33. static bool uart_print;
  34. static bool skip_otp;
  35. static bool rawmode;
  36. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  37. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  38. module_param(uart_print, bool, 0644);
  39. module_param(skip_otp, bool, 0644);
  40. module_param(rawmode, bool, 0644);
  41. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  42. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  43. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  44. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  45. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  46. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  47. {
  48. .id = QCA988X_HW_2_0_VERSION,
  49. .dev_id = QCA988X_2_0_DEVICE_ID,
  50. .name = "qca988x hw2.0",
  51. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  52. .uart_pin = 7,
  53. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  54. .otp_exe_param = 0,
  55. .channel_counters_freq_hz = 88000,
  56. .max_probe_resp_desc_thres = 0,
  57. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  58. .cal_data_len = 2116,
  59. .fw = {
  60. .dir = QCA988X_HW_2_0_FW_DIR,
  61. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  62. .board_size = QCA988X_BOARD_DATA_SZ,
  63. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  64. },
  65. },
  66. {
  67. .id = QCA9887_HW_1_0_VERSION,
  68. .dev_id = QCA9887_1_0_DEVICE_ID,
  69. .name = "qca9887 hw1.0",
  70. .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
  71. .uart_pin = 7,
  72. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  73. .otp_exe_param = 0,
  74. .channel_counters_freq_hz = 88000,
  75. .max_probe_resp_desc_thres = 0,
  76. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  77. .cal_data_len = 2116,
  78. .fw = {
  79. .dir = QCA9887_HW_1_0_FW_DIR,
  80. .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
  81. .board_size = QCA9887_BOARD_DATA_SZ,
  82. .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
  83. },
  84. },
  85. {
  86. .id = QCA6174_HW_2_1_VERSION,
  87. .dev_id = QCA6164_2_1_DEVICE_ID,
  88. .name = "qca6164 hw2.1",
  89. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  90. .uart_pin = 6,
  91. .otp_exe_param = 0,
  92. .channel_counters_freq_hz = 88000,
  93. .max_probe_resp_desc_thres = 0,
  94. .cal_data_len = 8124,
  95. .fw = {
  96. .dir = QCA6174_HW_2_1_FW_DIR,
  97. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  98. .board_size = QCA6174_BOARD_DATA_SZ,
  99. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  100. },
  101. },
  102. {
  103. .id = QCA6174_HW_2_1_VERSION,
  104. .dev_id = QCA6174_2_1_DEVICE_ID,
  105. .name = "qca6174 hw2.1",
  106. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  107. .uart_pin = 6,
  108. .otp_exe_param = 0,
  109. .channel_counters_freq_hz = 88000,
  110. .max_probe_resp_desc_thres = 0,
  111. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  112. .cal_data_len = 8124,
  113. .fw = {
  114. .dir = QCA6174_HW_2_1_FW_DIR,
  115. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  116. .board_size = QCA6174_BOARD_DATA_SZ,
  117. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  118. },
  119. },
  120. {
  121. .id = QCA6174_HW_3_0_VERSION,
  122. .dev_id = QCA6174_2_1_DEVICE_ID,
  123. .name = "qca6174 hw3.0",
  124. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  125. .uart_pin = 6,
  126. .otp_exe_param = 0,
  127. .channel_counters_freq_hz = 88000,
  128. .max_probe_resp_desc_thres = 0,
  129. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  130. .cal_data_len = 8124,
  131. .fw = {
  132. .dir = QCA6174_HW_3_0_FW_DIR,
  133. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  134. .board_size = QCA6174_BOARD_DATA_SZ,
  135. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  136. },
  137. },
  138. {
  139. .id = QCA6174_HW_3_2_VERSION,
  140. .dev_id = QCA6174_2_1_DEVICE_ID,
  141. .name = "qca6174 hw3.2",
  142. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  143. .uart_pin = 6,
  144. .otp_exe_param = 0,
  145. .channel_counters_freq_hz = 88000,
  146. .max_probe_resp_desc_thres = 0,
  147. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  148. .cal_data_len = 8124,
  149. .fw = {
  150. /* uses same binaries as hw3.0 */
  151. .dir = QCA6174_HW_3_0_FW_DIR,
  152. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  153. .board_size = QCA6174_BOARD_DATA_SZ,
  154. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  155. },
  156. },
  157. {
  158. .id = QCA99X0_HW_2_0_DEV_VERSION,
  159. .dev_id = QCA99X0_2_0_DEVICE_ID,
  160. .name = "qca99x0 hw2.0",
  161. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  162. .uart_pin = 7,
  163. .otp_exe_param = 0x00000700,
  164. .continuous_frag_desc = true,
  165. .cck_rate_map_rev2 = true,
  166. .channel_counters_freq_hz = 150000,
  167. .max_probe_resp_desc_thres = 24,
  168. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  169. .tx_chain_mask = 0xf,
  170. .rx_chain_mask = 0xf,
  171. .max_spatial_stream = 4,
  172. .cal_data_len = 12064,
  173. .fw = {
  174. .dir = QCA99X0_HW_2_0_FW_DIR,
  175. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  176. .board_size = QCA99X0_BOARD_DATA_SZ,
  177. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  178. },
  179. },
  180. {
  181. .id = QCA9984_HW_1_0_DEV_VERSION,
  182. .dev_id = QCA9984_1_0_DEVICE_ID,
  183. .name = "qca9984/qca9994 hw1.0",
  184. .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
  185. .uart_pin = 7,
  186. .otp_exe_param = 0x00000700,
  187. .continuous_frag_desc = true,
  188. .cck_rate_map_rev2 = true,
  189. .channel_counters_freq_hz = 150000,
  190. .max_probe_resp_desc_thres = 24,
  191. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  192. .tx_chain_mask = 0xf,
  193. .rx_chain_mask = 0xf,
  194. .max_spatial_stream = 4,
  195. .cal_data_len = 12064,
  196. .fw = {
  197. .dir = QCA9984_HW_1_0_FW_DIR,
  198. .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
  199. .board_size = QCA99X0_BOARD_DATA_SZ,
  200. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  201. },
  202. },
  203. {
  204. .id = QCA9888_HW_2_0_DEV_VERSION,
  205. .dev_id = QCA9888_2_0_DEVICE_ID,
  206. .name = "qca9888 hw2.0",
  207. .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
  208. .uart_pin = 7,
  209. .otp_exe_param = 0x00000700,
  210. .continuous_frag_desc = true,
  211. .channel_counters_freq_hz = 150000,
  212. .max_probe_resp_desc_thres = 24,
  213. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  214. .tx_chain_mask = 3,
  215. .rx_chain_mask = 3,
  216. .max_spatial_stream = 2,
  217. .cal_data_len = 12064,
  218. .fw = {
  219. .dir = QCA9888_HW_2_0_FW_DIR,
  220. .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
  221. .board_size = QCA99X0_BOARD_DATA_SZ,
  222. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  223. },
  224. },
  225. {
  226. .id = QCA9377_HW_1_0_DEV_VERSION,
  227. .dev_id = QCA9377_1_0_DEVICE_ID,
  228. .name = "qca9377 hw1.0",
  229. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  230. .uart_pin = 6,
  231. .otp_exe_param = 0,
  232. .channel_counters_freq_hz = 88000,
  233. .max_probe_resp_desc_thres = 0,
  234. .cal_data_len = 8124,
  235. .fw = {
  236. .dir = QCA9377_HW_1_0_FW_DIR,
  237. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  238. .board_size = QCA9377_BOARD_DATA_SZ,
  239. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  240. },
  241. },
  242. {
  243. .id = QCA9377_HW_1_1_DEV_VERSION,
  244. .dev_id = QCA9377_1_0_DEVICE_ID,
  245. .name = "qca9377 hw1.1",
  246. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  247. .uart_pin = 6,
  248. .otp_exe_param = 0,
  249. .channel_counters_freq_hz = 88000,
  250. .max_probe_resp_desc_thres = 0,
  251. .cal_data_len = 8124,
  252. .fw = {
  253. .dir = QCA9377_HW_1_0_FW_DIR,
  254. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  255. .board_size = QCA9377_BOARD_DATA_SZ,
  256. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  257. },
  258. },
  259. {
  260. .id = QCA4019_HW_1_0_DEV_VERSION,
  261. .dev_id = 0,
  262. .name = "qca4019 hw1.0",
  263. .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
  264. .uart_pin = 7,
  265. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  266. .otp_exe_param = 0x0010000,
  267. .continuous_frag_desc = true,
  268. .cck_rate_map_rev2 = true,
  269. .channel_counters_freq_hz = 125000,
  270. .max_probe_resp_desc_thres = 24,
  271. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  272. .tx_chain_mask = 0x3,
  273. .rx_chain_mask = 0x3,
  274. .max_spatial_stream = 2,
  275. .cal_data_len = 12064,
  276. .fw = {
  277. .dir = QCA4019_HW_1_0_FW_DIR,
  278. .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
  279. .board_size = QCA4019_BOARD_DATA_SZ,
  280. .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
  281. },
  282. },
  283. };
  284. static const char *const ath10k_core_fw_feature_str[] = {
  285. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  286. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  287. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  288. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  289. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  290. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  291. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  292. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  293. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  294. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  295. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  296. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  297. [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
  298. [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
  299. [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
  300. };
  301. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  302. size_t buf_len,
  303. enum ath10k_fw_features feat)
  304. {
  305. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  306. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  307. ATH10K_FW_FEATURE_COUNT);
  308. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  309. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  310. return scnprintf(buf, buf_len, "bit%d", feat);
  311. }
  312. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  313. }
  314. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  315. char *buf,
  316. size_t buf_len)
  317. {
  318. unsigned int len = 0;
  319. int i;
  320. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  321. if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
  322. if (len > 0)
  323. len += scnprintf(buf + len, buf_len - len, ",");
  324. len += ath10k_core_get_fw_feature_str(buf + len,
  325. buf_len - len,
  326. i);
  327. }
  328. }
  329. }
  330. static void ath10k_send_suspend_complete(struct ath10k *ar)
  331. {
  332. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  333. complete(&ar->target_suspend);
  334. }
  335. static int ath10k_init_configure_target(struct ath10k *ar)
  336. {
  337. u32 param_host;
  338. int ret;
  339. /* tell target which HTC version it is used*/
  340. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  341. HTC_PROTOCOL_VERSION);
  342. if (ret) {
  343. ath10k_err(ar, "settings HTC version failed\n");
  344. return ret;
  345. }
  346. /* set the firmware mode to STA/IBSS/AP */
  347. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  348. if (ret) {
  349. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  350. return ret;
  351. }
  352. /* TODO following parameters need to be re-visited. */
  353. /* num_device */
  354. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  355. /* Firmware mode */
  356. /* FIXME: Why FW_MODE_AP ??.*/
  357. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  358. /* mac_addr_method */
  359. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  360. /* firmware_bridge */
  361. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  362. /* fwsubmode */
  363. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  364. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  365. if (ret) {
  366. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  367. return ret;
  368. }
  369. /* We do all byte-swapping on the host */
  370. ret = ath10k_bmi_write32(ar, hi_be, 0);
  371. if (ret) {
  372. ath10k_err(ar, "setting host CPU BE mode failed\n");
  373. return ret;
  374. }
  375. /* FW descriptor/Data swap flags */
  376. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  377. if (ret) {
  378. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  379. return ret;
  380. }
  381. /* Some devices have a special sanity check that verifies the PCI
  382. * Device ID is written to this host interest var. It is known to be
  383. * required to boot QCA6164.
  384. */
  385. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  386. ar->dev_id);
  387. if (ret) {
  388. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  389. return ret;
  390. }
  391. return 0;
  392. }
  393. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  394. const char *dir,
  395. const char *file)
  396. {
  397. char filename[100];
  398. const struct firmware *fw;
  399. int ret;
  400. if (file == NULL)
  401. return ERR_PTR(-ENOENT);
  402. if (dir == NULL)
  403. dir = ".";
  404. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  405. ret = request_firmware(&fw, filename, ar->dev);
  406. if (ret)
  407. return ERR_PTR(ret);
  408. return fw;
  409. }
  410. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  411. size_t data_len)
  412. {
  413. u32 board_data_size = ar->hw_params.fw.board_size;
  414. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  415. u32 board_ext_data_addr;
  416. int ret;
  417. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  418. if (ret) {
  419. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  420. ret);
  421. return ret;
  422. }
  423. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  424. "boot push board extended data addr 0x%x\n",
  425. board_ext_data_addr);
  426. if (board_ext_data_addr == 0)
  427. return 0;
  428. if (data_len != (board_data_size + board_ext_data_size)) {
  429. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  430. data_len, board_data_size, board_ext_data_size);
  431. return -EINVAL;
  432. }
  433. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  434. data + board_data_size,
  435. board_ext_data_size);
  436. if (ret) {
  437. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  438. return ret;
  439. }
  440. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  441. (board_ext_data_size << 16) | 1);
  442. if (ret) {
  443. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  444. ret);
  445. return ret;
  446. }
  447. return 0;
  448. }
  449. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  450. size_t data_len)
  451. {
  452. u32 board_data_size = ar->hw_params.fw.board_size;
  453. u32 address;
  454. int ret;
  455. ret = ath10k_push_board_ext_data(ar, data, data_len);
  456. if (ret) {
  457. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  458. goto exit;
  459. }
  460. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  461. if (ret) {
  462. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  463. goto exit;
  464. }
  465. ret = ath10k_bmi_write_memory(ar, address, data,
  466. min_t(u32, board_data_size,
  467. data_len));
  468. if (ret) {
  469. ath10k_err(ar, "could not write board data (%d)\n", ret);
  470. goto exit;
  471. }
  472. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  473. if (ret) {
  474. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  475. goto exit;
  476. }
  477. exit:
  478. return ret;
  479. }
  480. static int ath10k_download_cal_file(struct ath10k *ar,
  481. const struct firmware *file)
  482. {
  483. int ret;
  484. if (!file)
  485. return -ENOENT;
  486. if (IS_ERR(file))
  487. return PTR_ERR(file);
  488. ret = ath10k_download_board_data(ar, file->data, file->size);
  489. if (ret) {
  490. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  491. return ret;
  492. }
  493. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  494. return 0;
  495. }
  496. static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
  497. {
  498. struct device_node *node;
  499. int data_len;
  500. void *data;
  501. int ret;
  502. node = ar->dev->of_node;
  503. if (!node)
  504. /* Device Tree is optional, don't print any warnings if
  505. * there's no node for ath10k.
  506. */
  507. return -ENOENT;
  508. if (!of_get_property(node, dt_name, &data_len)) {
  509. /* The calibration data node is optional */
  510. return -ENOENT;
  511. }
  512. if (data_len != ar->hw_params.cal_data_len) {
  513. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  514. data_len);
  515. ret = -EMSGSIZE;
  516. goto out;
  517. }
  518. data = kmalloc(data_len, GFP_KERNEL);
  519. if (!data) {
  520. ret = -ENOMEM;
  521. goto out;
  522. }
  523. ret = of_property_read_u8_array(node, dt_name, data, data_len);
  524. if (ret) {
  525. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  526. ret);
  527. goto out_free;
  528. }
  529. ret = ath10k_download_board_data(ar, data, data_len);
  530. if (ret) {
  531. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  532. ret);
  533. goto out_free;
  534. }
  535. ret = 0;
  536. out_free:
  537. kfree(data);
  538. out:
  539. return ret;
  540. }
  541. static int ath10k_download_cal_eeprom(struct ath10k *ar)
  542. {
  543. size_t data_len;
  544. void *data = NULL;
  545. int ret;
  546. ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
  547. if (ret) {
  548. if (ret != -EOPNOTSUPP)
  549. ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
  550. ret);
  551. goto out_free;
  552. }
  553. ret = ath10k_download_board_data(ar, data, data_len);
  554. if (ret) {
  555. ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
  556. ret);
  557. goto out_free;
  558. }
  559. ret = 0;
  560. out_free:
  561. kfree(data);
  562. return ret;
  563. }
  564. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  565. {
  566. u32 result, address;
  567. u8 board_id, chip_id;
  568. int ret;
  569. address = ar->hw_params.patch_load_addr;
  570. if (!ar->normal_mode_fw.fw_file.otp_data ||
  571. !ar->normal_mode_fw.fw_file.otp_len) {
  572. ath10k_warn(ar,
  573. "failed to retrieve board id because of invalid otp\n");
  574. return -ENODATA;
  575. }
  576. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  577. "boot upload otp to 0x%x len %zd for board id\n",
  578. address, ar->normal_mode_fw.fw_file.otp_len);
  579. ret = ath10k_bmi_fast_download(ar, address,
  580. ar->normal_mode_fw.fw_file.otp_data,
  581. ar->normal_mode_fw.fw_file.otp_len);
  582. if (ret) {
  583. ath10k_err(ar, "could not write otp for board id check: %d\n",
  584. ret);
  585. return ret;
  586. }
  587. ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
  588. &result);
  589. if (ret) {
  590. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  591. ret);
  592. return ret;
  593. }
  594. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  595. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  596. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  597. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  598. result, board_id, chip_id);
  599. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0)
  600. return -EOPNOTSUPP;
  601. ar->id.bmi_ids_valid = true;
  602. ar->id.bmi_board_id = board_id;
  603. ar->id.bmi_chip_id = chip_id;
  604. return 0;
  605. }
  606. static int ath10k_download_and_run_otp(struct ath10k *ar)
  607. {
  608. u32 result, address = ar->hw_params.patch_load_addr;
  609. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  610. int ret;
  611. ret = ath10k_download_board_data(ar,
  612. ar->running_fw->board_data,
  613. ar->running_fw->board_len);
  614. if (ret) {
  615. ath10k_err(ar, "failed to download board data: %d\n", ret);
  616. return ret;
  617. }
  618. /* OTP is optional */
  619. if (!ar->running_fw->fw_file.otp_data ||
  620. !ar->running_fw->fw_file.otp_len) {
  621. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
  622. ar->running_fw->fw_file.otp_data,
  623. ar->running_fw->fw_file.otp_len);
  624. return 0;
  625. }
  626. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  627. address, ar->running_fw->fw_file.otp_len);
  628. ret = ath10k_bmi_fast_download(ar, address,
  629. ar->running_fw->fw_file.otp_data,
  630. ar->running_fw->fw_file.otp_len);
  631. if (ret) {
  632. ath10k_err(ar, "could not write otp (%d)\n", ret);
  633. return ret;
  634. }
  635. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  636. if (ret) {
  637. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  638. return ret;
  639. }
  640. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  641. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  642. ar->running_fw->fw_file.fw_features)) &&
  643. result != 0) {
  644. ath10k_err(ar, "otp calibration failed: %d", result);
  645. return -EINVAL;
  646. }
  647. return 0;
  648. }
  649. static int ath10k_download_fw(struct ath10k *ar)
  650. {
  651. u32 address, data_len;
  652. const void *data;
  653. int ret;
  654. address = ar->hw_params.patch_load_addr;
  655. data = ar->running_fw->fw_file.firmware_data;
  656. data_len = ar->running_fw->fw_file.firmware_len;
  657. ret = ath10k_swap_code_seg_configure(ar);
  658. if (ret) {
  659. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  660. ret);
  661. return ret;
  662. }
  663. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  664. "boot uploading firmware image %p len %d\n",
  665. data, data_len);
  666. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  667. if (ret) {
  668. ath10k_err(ar, "failed to download firmware: %d\n",
  669. ret);
  670. return ret;
  671. }
  672. return ret;
  673. }
  674. static void ath10k_core_free_board_files(struct ath10k *ar)
  675. {
  676. if (!IS_ERR(ar->normal_mode_fw.board))
  677. release_firmware(ar->normal_mode_fw.board);
  678. ar->normal_mode_fw.board = NULL;
  679. ar->normal_mode_fw.board_data = NULL;
  680. ar->normal_mode_fw.board_len = 0;
  681. }
  682. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  683. {
  684. if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
  685. release_firmware(ar->normal_mode_fw.fw_file.firmware);
  686. if (!IS_ERR(ar->cal_file))
  687. release_firmware(ar->cal_file);
  688. if (!IS_ERR(ar->pre_cal_file))
  689. release_firmware(ar->pre_cal_file);
  690. ath10k_swap_code_seg_release(ar);
  691. ar->normal_mode_fw.fw_file.otp_data = NULL;
  692. ar->normal_mode_fw.fw_file.otp_len = 0;
  693. ar->normal_mode_fw.fw_file.firmware = NULL;
  694. ar->normal_mode_fw.fw_file.firmware_data = NULL;
  695. ar->normal_mode_fw.fw_file.firmware_len = 0;
  696. ar->cal_file = NULL;
  697. ar->pre_cal_file = NULL;
  698. }
  699. static int ath10k_fetch_cal_file(struct ath10k *ar)
  700. {
  701. char filename[100];
  702. /* pre-cal-<bus>-<id>.bin */
  703. scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
  704. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  705. ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  706. if (!IS_ERR(ar->pre_cal_file))
  707. goto success;
  708. /* cal-<bus>-<id>.bin */
  709. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  710. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  711. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  712. if (IS_ERR(ar->cal_file))
  713. /* calibration file is optional, don't print any warnings */
  714. return PTR_ERR(ar->cal_file);
  715. success:
  716. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  717. ATH10K_FW_DIR, filename);
  718. return 0;
  719. }
  720. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  721. {
  722. if (!ar->hw_params.fw.board) {
  723. ath10k_err(ar, "failed to find board file fw entry\n");
  724. return -EINVAL;
  725. }
  726. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  727. ar->hw_params.fw.dir,
  728. ar->hw_params.fw.board);
  729. if (IS_ERR(ar->normal_mode_fw.board))
  730. return PTR_ERR(ar->normal_mode_fw.board);
  731. ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
  732. ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
  733. return 0;
  734. }
  735. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  736. const void *buf, size_t buf_len,
  737. const char *boardname)
  738. {
  739. const struct ath10k_fw_ie *hdr;
  740. bool name_match_found;
  741. int ret, board_ie_id;
  742. size_t board_ie_len;
  743. const void *board_ie_data;
  744. name_match_found = false;
  745. /* go through ATH10K_BD_IE_BOARD_ elements */
  746. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  747. hdr = buf;
  748. board_ie_id = le32_to_cpu(hdr->id);
  749. board_ie_len = le32_to_cpu(hdr->len);
  750. board_ie_data = hdr->data;
  751. buf_len -= sizeof(*hdr);
  752. buf += sizeof(*hdr);
  753. if (buf_len < ALIGN(board_ie_len, 4)) {
  754. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  755. buf_len, ALIGN(board_ie_len, 4));
  756. ret = -EINVAL;
  757. goto out;
  758. }
  759. switch (board_ie_id) {
  760. case ATH10K_BD_IE_BOARD_NAME:
  761. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  762. board_ie_data, board_ie_len);
  763. if (board_ie_len != strlen(boardname))
  764. break;
  765. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  766. if (ret)
  767. break;
  768. name_match_found = true;
  769. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  770. "boot found match for name '%s'",
  771. boardname);
  772. break;
  773. case ATH10K_BD_IE_BOARD_DATA:
  774. if (!name_match_found)
  775. /* no match found */
  776. break;
  777. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  778. "boot found board data for '%s'",
  779. boardname);
  780. ar->normal_mode_fw.board_data = board_ie_data;
  781. ar->normal_mode_fw.board_len = board_ie_len;
  782. ret = 0;
  783. goto out;
  784. default:
  785. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  786. board_ie_id);
  787. break;
  788. }
  789. /* jump over the padding */
  790. board_ie_len = ALIGN(board_ie_len, 4);
  791. buf_len -= board_ie_len;
  792. buf += board_ie_len;
  793. }
  794. /* no match found */
  795. ret = -ENOENT;
  796. out:
  797. return ret;
  798. }
  799. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  800. const char *boardname,
  801. const char *filename)
  802. {
  803. size_t len, magic_len, ie_len;
  804. struct ath10k_fw_ie *hdr;
  805. const u8 *data;
  806. int ret, ie_id;
  807. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  808. ar->hw_params.fw.dir,
  809. filename);
  810. if (IS_ERR(ar->normal_mode_fw.board))
  811. return PTR_ERR(ar->normal_mode_fw.board);
  812. data = ar->normal_mode_fw.board->data;
  813. len = ar->normal_mode_fw.board->size;
  814. /* magic has extra null byte padded */
  815. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  816. if (len < magic_len) {
  817. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  818. ar->hw_params.fw.dir, filename, len);
  819. ret = -EINVAL;
  820. goto err;
  821. }
  822. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  823. ath10k_err(ar, "found invalid board magic\n");
  824. ret = -EINVAL;
  825. goto err;
  826. }
  827. /* magic is padded to 4 bytes */
  828. magic_len = ALIGN(magic_len, 4);
  829. if (len < magic_len) {
  830. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  831. ar->hw_params.fw.dir, filename, len);
  832. ret = -EINVAL;
  833. goto err;
  834. }
  835. data += magic_len;
  836. len -= magic_len;
  837. while (len > sizeof(struct ath10k_fw_ie)) {
  838. hdr = (struct ath10k_fw_ie *)data;
  839. ie_id = le32_to_cpu(hdr->id);
  840. ie_len = le32_to_cpu(hdr->len);
  841. len -= sizeof(*hdr);
  842. data = hdr->data;
  843. if (len < ALIGN(ie_len, 4)) {
  844. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  845. ie_id, ie_len, len);
  846. ret = -EINVAL;
  847. goto err;
  848. }
  849. switch (ie_id) {
  850. case ATH10K_BD_IE_BOARD:
  851. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  852. boardname);
  853. if (ret == -ENOENT)
  854. /* no match found, continue */
  855. break;
  856. else if (ret)
  857. /* there was an error, bail out */
  858. goto err;
  859. /* board data found */
  860. goto out;
  861. }
  862. /* jump over the padding */
  863. ie_len = ALIGN(ie_len, 4);
  864. len -= ie_len;
  865. data += ie_len;
  866. }
  867. out:
  868. if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) {
  869. ath10k_err(ar,
  870. "failed to fetch board data for %s from %s/%s\n",
  871. boardname, ar->hw_params.fw.dir, filename);
  872. ret = -ENODATA;
  873. goto err;
  874. }
  875. return 0;
  876. err:
  877. ath10k_core_free_board_files(ar);
  878. return ret;
  879. }
  880. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  881. size_t name_len)
  882. {
  883. if (ar->id.bmi_ids_valid) {
  884. scnprintf(name, name_len,
  885. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  886. ath10k_bus_str(ar->hif.bus),
  887. ar->id.bmi_chip_id,
  888. ar->id.bmi_board_id);
  889. goto out;
  890. }
  891. scnprintf(name, name_len,
  892. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
  893. ath10k_bus_str(ar->hif.bus),
  894. ar->id.vendor, ar->id.device,
  895. ar->id.subsystem_vendor, ar->id.subsystem_device);
  896. out:
  897. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  898. return 0;
  899. }
  900. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  901. {
  902. char boardname[100];
  903. int ret;
  904. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  905. if (ret) {
  906. ath10k_err(ar, "failed to create board name: %d", ret);
  907. return ret;
  908. }
  909. ar->bd_api = 2;
  910. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  911. ATH10K_BOARD_API2_FILE);
  912. if (!ret)
  913. goto success;
  914. ar->bd_api = 1;
  915. ret = ath10k_core_fetch_board_data_api_1(ar);
  916. if (ret) {
  917. ath10k_err(ar, "failed to fetch board data\n");
  918. return ret;
  919. }
  920. success:
  921. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  922. return 0;
  923. }
  924. int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
  925. struct ath10k_fw_file *fw_file)
  926. {
  927. size_t magic_len, len, ie_len;
  928. int ie_id, i, index, bit, ret;
  929. struct ath10k_fw_ie *hdr;
  930. const u8 *data;
  931. __le32 *timestamp, *version;
  932. /* first fetch the firmware file (firmware-*.bin) */
  933. fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
  934. name);
  935. if (IS_ERR(fw_file->firmware)) {
  936. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  937. ar->hw_params.fw.dir, name,
  938. PTR_ERR(fw_file->firmware));
  939. return PTR_ERR(fw_file->firmware);
  940. }
  941. data = fw_file->firmware->data;
  942. len = fw_file->firmware->size;
  943. /* magic also includes the null byte, check that as well */
  944. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  945. if (len < magic_len) {
  946. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  947. ar->hw_params.fw.dir, name, len);
  948. ret = -EINVAL;
  949. goto err;
  950. }
  951. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  952. ath10k_err(ar, "invalid firmware magic\n");
  953. ret = -EINVAL;
  954. goto err;
  955. }
  956. /* jump over the padding */
  957. magic_len = ALIGN(magic_len, 4);
  958. len -= magic_len;
  959. data += magic_len;
  960. /* loop elements */
  961. while (len > sizeof(struct ath10k_fw_ie)) {
  962. hdr = (struct ath10k_fw_ie *)data;
  963. ie_id = le32_to_cpu(hdr->id);
  964. ie_len = le32_to_cpu(hdr->len);
  965. len -= sizeof(*hdr);
  966. data += sizeof(*hdr);
  967. if (len < ie_len) {
  968. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  969. ie_id, len, ie_len);
  970. ret = -EINVAL;
  971. goto err;
  972. }
  973. switch (ie_id) {
  974. case ATH10K_FW_IE_FW_VERSION:
  975. if (ie_len > sizeof(fw_file->fw_version) - 1)
  976. break;
  977. memcpy(fw_file->fw_version, data, ie_len);
  978. fw_file->fw_version[ie_len] = '\0';
  979. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  980. "found fw version %s\n",
  981. fw_file->fw_version);
  982. break;
  983. case ATH10K_FW_IE_TIMESTAMP:
  984. if (ie_len != sizeof(u32))
  985. break;
  986. timestamp = (__le32 *)data;
  987. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  988. le32_to_cpup(timestamp));
  989. break;
  990. case ATH10K_FW_IE_FEATURES:
  991. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  992. "found firmware features ie (%zd B)\n",
  993. ie_len);
  994. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  995. index = i / 8;
  996. bit = i % 8;
  997. if (index == ie_len)
  998. break;
  999. if (data[index] & (1 << bit)) {
  1000. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1001. "Enabling feature bit: %i\n",
  1002. i);
  1003. __set_bit(i, fw_file->fw_features);
  1004. }
  1005. }
  1006. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  1007. fw_file->fw_features,
  1008. sizeof(fw_file->fw_features));
  1009. break;
  1010. case ATH10K_FW_IE_FW_IMAGE:
  1011. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1012. "found fw image ie (%zd B)\n",
  1013. ie_len);
  1014. fw_file->firmware_data = data;
  1015. fw_file->firmware_len = ie_len;
  1016. break;
  1017. case ATH10K_FW_IE_OTP_IMAGE:
  1018. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1019. "found otp image ie (%zd B)\n",
  1020. ie_len);
  1021. fw_file->otp_data = data;
  1022. fw_file->otp_len = ie_len;
  1023. break;
  1024. case ATH10K_FW_IE_WMI_OP_VERSION:
  1025. if (ie_len != sizeof(u32))
  1026. break;
  1027. version = (__le32 *)data;
  1028. fw_file->wmi_op_version = le32_to_cpup(version);
  1029. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  1030. fw_file->wmi_op_version);
  1031. break;
  1032. case ATH10K_FW_IE_HTT_OP_VERSION:
  1033. if (ie_len != sizeof(u32))
  1034. break;
  1035. version = (__le32 *)data;
  1036. fw_file->htt_op_version = le32_to_cpup(version);
  1037. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  1038. fw_file->htt_op_version);
  1039. break;
  1040. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  1041. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1042. "found fw code swap image ie (%zd B)\n",
  1043. ie_len);
  1044. fw_file->codeswap_data = data;
  1045. fw_file->codeswap_len = ie_len;
  1046. break;
  1047. default:
  1048. ath10k_warn(ar, "Unknown FW IE: %u\n",
  1049. le32_to_cpu(hdr->id));
  1050. break;
  1051. }
  1052. /* jump over the padding */
  1053. ie_len = ALIGN(ie_len, 4);
  1054. len -= ie_len;
  1055. data += ie_len;
  1056. }
  1057. if (!fw_file->firmware_data ||
  1058. !fw_file->firmware_len) {
  1059. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  1060. ar->hw_params.fw.dir, name);
  1061. ret = -ENOMEDIUM;
  1062. goto err;
  1063. }
  1064. return 0;
  1065. err:
  1066. ath10k_core_free_firmware_files(ar);
  1067. return ret;
  1068. }
  1069. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  1070. {
  1071. int ret;
  1072. /* calibration file is optional, don't check for any errors */
  1073. ath10k_fetch_cal_file(ar);
  1074. ar->fw_api = 5;
  1075. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1076. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE,
  1077. &ar->normal_mode_fw.fw_file);
  1078. if (ret == 0)
  1079. goto success;
  1080. ar->fw_api = 4;
  1081. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1082. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE,
  1083. &ar->normal_mode_fw.fw_file);
  1084. if (ret == 0)
  1085. goto success;
  1086. ar->fw_api = 3;
  1087. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1088. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE,
  1089. &ar->normal_mode_fw.fw_file);
  1090. if (ret == 0)
  1091. goto success;
  1092. ar->fw_api = 2;
  1093. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1094. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE,
  1095. &ar->normal_mode_fw.fw_file);
  1096. if (ret)
  1097. return ret;
  1098. success:
  1099. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1100. return 0;
  1101. }
  1102. static int ath10k_core_pre_cal_download(struct ath10k *ar)
  1103. {
  1104. int ret;
  1105. ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
  1106. if (ret == 0) {
  1107. ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
  1108. goto success;
  1109. }
  1110. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1111. "boot did not find a pre calibration file, try DT next: %d\n",
  1112. ret);
  1113. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
  1114. if (ret) {
  1115. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1116. "unable to load pre cal data from DT: %d\n", ret);
  1117. return ret;
  1118. }
  1119. ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
  1120. success:
  1121. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1122. ath10k_cal_mode_str(ar->cal_mode));
  1123. return 0;
  1124. }
  1125. static int ath10k_core_pre_cal_config(struct ath10k *ar)
  1126. {
  1127. int ret;
  1128. ret = ath10k_core_pre_cal_download(ar);
  1129. if (ret) {
  1130. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1131. "failed to load pre cal data: %d\n", ret);
  1132. return ret;
  1133. }
  1134. ret = ath10k_core_get_board_id_from_otp(ar);
  1135. if (ret) {
  1136. ath10k_err(ar, "failed to get board id: %d\n", ret);
  1137. return ret;
  1138. }
  1139. ret = ath10k_download_and_run_otp(ar);
  1140. if (ret) {
  1141. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1142. return ret;
  1143. }
  1144. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1145. "pre cal configuration done successfully\n");
  1146. return 0;
  1147. }
  1148. static int ath10k_download_cal_data(struct ath10k *ar)
  1149. {
  1150. int ret;
  1151. ret = ath10k_core_pre_cal_config(ar);
  1152. if (ret == 0)
  1153. return 0;
  1154. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1155. "pre cal download procedure failed, try cal file: %d\n",
  1156. ret);
  1157. ret = ath10k_download_cal_file(ar, ar->cal_file);
  1158. if (ret == 0) {
  1159. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1160. goto done;
  1161. }
  1162. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1163. "boot did not find a calibration file, try DT next: %d\n",
  1164. ret);
  1165. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
  1166. if (ret == 0) {
  1167. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1168. goto done;
  1169. }
  1170. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1171. "boot did not find DT entry, try target EEPROM next: %d\n",
  1172. ret);
  1173. ret = ath10k_download_cal_eeprom(ar);
  1174. if (ret == 0) {
  1175. ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
  1176. goto done;
  1177. }
  1178. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1179. "boot did not find target EEPROM entry, try OTP next: %d\n",
  1180. ret);
  1181. ret = ath10k_download_and_run_otp(ar);
  1182. if (ret) {
  1183. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1184. return ret;
  1185. }
  1186. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1187. done:
  1188. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1189. ath10k_cal_mode_str(ar->cal_mode));
  1190. return 0;
  1191. }
  1192. static int ath10k_init_uart(struct ath10k *ar)
  1193. {
  1194. int ret;
  1195. /*
  1196. * Explicitly setting UART prints to zero as target turns it on
  1197. * based on scratch registers.
  1198. */
  1199. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1200. if (ret) {
  1201. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1202. return ret;
  1203. }
  1204. if (!uart_print)
  1205. return 0;
  1206. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1207. if (ret) {
  1208. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1209. return ret;
  1210. }
  1211. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1212. if (ret) {
  1213. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1214. return ret;
  1215. }
  1216. /* Set the UART baud rate to 19200. */
  1217. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1218. if (ret) {
  1219. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1220. return ret;
  1221. }
  1222. ath10k_info(ar, "UART prints enabled\n");
  1223. return 0;
  1224. }
  1225. static int ath10k_init_hw_params(struct ath10k *ar)
  1226. {
  1227. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1228. int i;
  1229. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1230. hw_params = &ath10k_hw_params_list[i];
  1231. if (hw_params->id == ar->target_version &&
  1232. hw_params->dev_id == ar->dev_id)
  1233. break;
  1234. }
  1235. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1236. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1237. ar->target_version);
  1238. return -EINVAL;
  1239. }
  1240. ar->hw_params = *hw_params;
  1241. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1242. ar->hw_params.name, ar->target_version);
  1243. return 0;
  1244. }
  1245. static void ath10k_core_restart(struct work_struct *work)
  1246. {
  1247. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1248. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1249. /* Place a barrier to make sure the compiler doesn't reorder
  1250. * CRASH_FLUSH and calling other functions.
  1251. */
  1252. barrier();
  1253. ieee80211_stop_queues(ar->hw);
  1254. ath10k_drain_tx(ar);
  1255. complete_all(&ar->scan.started);
  1256. complete_all(&ar->scan.completed);
  1257. complete_all(&ar->scan.on_channel);
  1258. complete_all(&ar->offchan_tx_completed);
  1259. complete_all(&ar->install_key_done);
  1260. complete_all(&ar->vdev_setup_done);
  1261. complete_all(&ar->thermal.wmi_sync);
  1262. complete_all(&ar->bss_survey_done);
  1263. wake_up(&ar->htt.empty_tx_wq);
  1264. wake_up(&ar->wmi.tx_credits_wq);
  1265. wake_up(&ar->peer_mapping_wq);
  1266. mutex_lock(&ar->conf_mutex);
  1267. switch (ar->state) {
  1268. case ATH10K_STATE_ON:
  1269. ar->state = ATH10K_STATE_RESTARTING;
  1270. ath10k_hif_stop(ar);
  1271. ath10k_scan_finish(ar);
  1272. ieee80211_restart_hw(ar->hw);
  1273. break;
  1274. case ATH10K_STATE_OFF:
  1275. /* this can happen if driver is being unloaded
  1276. * or if the crash happens during FW probing */
  1277. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1278. break;
  1279. case ATH10K_STATE_RESTARTING:
  1280. /* hw restart might be requested from multiple places */
  1281. break;
  1282. case ATH10K_STATE_RESTARTED:
  1283. ar->state = ATH10K_STATE_WEDGED;
  1284. /* fall through */
  1285. case ATH10K_STATE_WEDGED:
  1286. ath10k_warn(ar, "device is wedged, will not restart\n");
  1287. break;
  1288. case ATH10K_STATE_UTF:
  1289. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1290. break;
  1291. }
  1292. mutex_unlock(&ar->conf_mutex);
  1293. }
  1294. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1295. {
  1296. struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
  1297. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
  1298. !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1299. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1300. return -EINVAL;
  1301. }
  1302. if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1303. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1304. ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
  1305. return -EINVAL;
  1306. }
  1307. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1308. switch (ath10k_cryptmode_param) {
  1309. case ATH10K_CRYPT_MODE_HW:
  1310. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1311. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1312. break;
  1313. case ATH10K_CRYPT_MODE_SW:
  1314. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1315. fw_file->fw_features)) {
  1316. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1317. return -EINVAL;
  1318. }
  1319. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1320. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1321. break;
  1322. default:
  1323. ath10k_info(ar, "invalid cryptmode: %d\n",
  1324. ath10k_cryptmode_param);
  1325. return -EINVAL;
  1326. }
  1327. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1328. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1329. if (rawmode) {
  1330. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1331. fw_file->fw_features)) {
  1332. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1333. return -EINVAL;
  1334. }
  1335. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1336. }
  1337. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1338. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1339. /* Workaround:
  1340. *
  1341. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1342. * and causes enormous performance issues (malformed frames,
  1343. * etc).
  1344. *
  1345. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1346. * albeit a bit slower compared to regular operation.
  1347. */
  1348. ar->htt.max_num_amsdu = 1;
  1349. }
  1350. /* Backwards compatibility for firmwares without
  1351. * ATH10K_FW_IE_WMI_OP_VERSION.
  1352. */
  1353. if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1354. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1355. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1356. fw_file->fw_features))
  1357. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1358. else
  1359. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1360. } else {
  1361. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1362. }
  1363. }
  1364. switch (fw_file->wmi_op_version) {
  1365. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1366. ar->max_num_peers = TARGET_NUM_PEERS;
  1367. ar->max_num_stations = TARGET_NUM_STATIONS;
  1368. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1369. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1370. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1371. WMI_STAT_PEER;
  1372. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1373. break;
  1374. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1375. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1376. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1377. if (ath10k_peer_stats_enabled(ar)) {
  1378. ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
  1379. ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
  1380. } else {
  1381. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1382. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1383. }
  1384. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1385. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1386. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1387. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1388. break;
  1389. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1390. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1391. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1392. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1393. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1394. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1395. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1396. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1397. WMI_STAT_PEER;
  1398. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1399. break;
  1400. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1401. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1402. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1403. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1404. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1405. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1406. ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
  1407. WMI_10_4_STAT_PEER_EXTD;
  1408. ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
  1409. if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
  1410. fw_file->fw_features))
  1411. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
  1412. else
  1413. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  1414. break;
  1415. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1416. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1417. WARN_ON(1);
  1418. return -EINVAL;
  1419. }
  1420. /* Backwards compatibility for firmwares without
  1421. * ATH10K_FW_IE_HTT_OP_VERSION.
  1422. */
  1423. if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1424. switch (fw_file->wmi_op_version) {
  1425. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1426. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1427. break;
  1428. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1429. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1430. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1431. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1432. break;
  1433. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1434. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1435. break;
  1436. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1437. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1438. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1439. ath10k_err(ar, "htt op version not found from fw meta data");
  1440. return -EINVAL;
  1441. }
  1442. }
  1443. return 0;
  1444. }
  1445. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
  1446. const struct ath10k_fw_components *fw)
  1447. {
  1448. int status;
  1449. u32 val;
  1450. lockdep_assert_held(&ar->conf_mutex);
  1451. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1452. ar->running_fw = fw;
  1453. ath10k_bmi_start(ar);
  1454. if (ath10k_init_configure_target(ar)) {
  1455. status = -EINVAL;
  1456. goto err;
  1457. }
  1458. status = ath10k_download_cal_data(ar);
  1459. if (status)
  1460. goto err;
  1461. /* Some of of qca988x solutions are having global reset issue
  1462. * during target initialization. Bypassing PLL setting before
  1463. * downloading firmware and letting the SoC run on REF_CLK is
  1464. * fixing the problem. Corresponding firmware change is also needed
  1465. * to set the clock source once the target is initialized.
  1466. */
  1467. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1468. ar->running_fw->fw_file.fw_features)) {
  1469. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1470. if (status) {
  1471. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1472. status);
  1473. goto err;
  1474. }
  1475. }
  1476. status = ath10k_download_fw(ar);
  1477. if (status)
  1478. goto err;
  1479. status = ath10k_init_uart(ar);
  1480. if (status)
  1481. goto err;
  1482. ar->htc.htc_ops.target_send_suspend_complete =
  1483. ath10k_send_suspend_complete;
  1484. status = ath10k_htc_init(ar);
  1485. if (status) {
  1486. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1487. goto err;
  1488. }
  1489. status = ath10k_bmi_done(ar);
  1490. if (status)
  1491. goto err;
  1492. status = ath10k_wmi_attach(ar);
  1493. if (status) {
  1494. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1495. goto err;
  1496. }
  1497. status = ath10k_htt_init(ar);
  1498. if (status) {
  1499. ath10k_err(ar, "failed to init htt: %d\n", status);
  1500. goto err_wmi_detach;
  1501. }
  1502. status = ath10k_htt_tx_alloc(&ar->htt);
  1503. if (status) {
  1504. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1505. goto err_wmi_detach;
  1506. }
  1507. status = ath10k_htt_rx_alloc(&ar->htt);
  1508. if (status) {
  1509. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1510. goto err_htt_tx_detach;
  1511. }
  1512. status = ath10k_hif_start(ar);
  1513. if (status) {
  1514. ath10k_err(ar, "could not start HIF: %d\n", status);
  1515. goto err_htt_rx_detach;
  1516. }
  1517. status = ath10k_htc_wait_target(&ar->htc);
  1518. if (status) {
  1519. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1520. goto err_hif_stop;
  1521. }
  1522. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1523. status = ath10k_htt_connect(&ar->htt);
  1524. if (status) {
  1525. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1526. goto err_hif_stop;
  1527. }
  1528. }
  1529. status = ath10k_wmi_connect(ar);
  1530. if (status) {
  1531. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1532. goto err_hif_stop;
  1533. }
  1534. status = ath10k_htc_start(&ar->htc);
  1535. if (status) {
  1536. ath10k_err(ar, "failed to start htc: %d\n", status);
  1537. goto err_hif_stop;
  1538. }
  1539. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1540. status = ath10k_wmi_wait_for_service_ready(ar);
  1541. if (status) {
  1542. ath10k_warn(ar, "wmi service ready event not received");
  1543. goto err_hif_stop;
  1544. }
  1545. }
  1546. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1547. ar->hw->wiphy->fw_version);
  1548. if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map)) {
  1549. val = 0;
  1550. if (ath10k_peer_stats_enabled(ar))
  1551. val = WMI_10_4_PEER_STATS;
  1552. if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
  1553. val |= WMI_10_4_BSS_CHANNEL_INFO_64;
  1554. /* 10.4 firmware supports BT-Coex without reloading firmware
  1555. * via pdev param. To support Bluetooth coexistence pdev param,
  1556. * WMI_COEX_GPIO_SUPPORT of extended resource config should be
  1557. * enabled always.
  1558. */
  1559. if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
  1560. test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
  1561. ar->running_fw->fw_file.fw_features))
  1562. val |= WMI_10_4_COEX_GPIO_SUPPORT;
  1563. status = ath10k_mac_ext_resource_config(ar, val);
  1564. if (status) {
  1565. ath10k_err(ar,
  1566. "failed to send ext resource cfg command : %d\n",
  1567. status);
  1568. goto err_hif_stop;
  1569. }
  1570. }
  1571. status = ath10k_wmi_cmd_init(ar);
  1572. if (status) {
  1573. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1574. status);
  1575. goto err_hif_stop;
  1576. }
  1577. status = ath10k_wmi_wait_for_unified_ready(ar);
  1578. if (status) {
  1579. ath10k_err(ar, "wmi unified ready event not received\n");
  1580. goto err_hif_stop;
  1581. }
  1582. /* If firmware indicates Full Rx Reorder support it must be used in a
  1583. * slightly different manner. Let HTT code know.
  1584. */
  1585. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1586. ar->wmi.svc_map));
  1587. status = ath10k_htt_rx_ring_refill(ar);
  1588. if (status) {
  1589. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1590. goto err_hif_stop;
  1591. }
  1592. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1593. INIT_LIST_HEAD(&ar->arvifs);
  1594. /* we don't care about HTT in UTF mode */
  1595. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1596. status = ath10k_htt_setup(&ar->htt);
  1597. if (status) {
  1598. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1599. goto err_hif_stop;
  1600. }
  1601. }
  1602. status = ath10k_debug_start(ar);
  1603. if (status)
  1604. goto err_hif_stop;
  1605. return 0;
  1606. err_hif_stop:
  1607. ath10k_hif_stop(ar);
  1608. err_htt_rx_detach:
  1609. ath10k_htt_rx_free(&ar->htt);
  1610. err_htt_tx_detach:
  1611. ath10k_htt_tx_free(&ar->htt);
  1612. err_wmi_detach:
  1613. ath10k_wmi_detach(ar);
  1614. err:
  1615. return status;
  1616. }
  1617. EXPORT_SYMBOL(ath10k_core_start);
  1618. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1619. {
  1620. int ret;
  1621. unsigned long time_left;
  1622. reinit_completion(&ar->target_suspend);
  1623. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1624. if (ret) {
  1625. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1626. return ret;
  1627. }
  1628. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1629. if (!time_left) {
  1630. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1631. return -ETIMEDOUT;
  1632. }
  1633. return 0;
  1634. }
  1635. void ath10k_core_stop(struct ath10k *ar)
  1636. {
  1637. lockdep_assert_held(&ar->conf_mutex);
  1638. ath10k_debug_stop(ar);
  1639. /* try to suspend target */
  1640. if (ar->state != ATH10K_STATE_RESTARTING &&
  1641. ar->state != ATH10K_STATE_UTF)
  1642. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1643. ath10k_hif_stop(ar);
  1644. ath10k_htt_tx_free(&ar->htt);
  1645. ath10k_htt_rx_free(&ar->htt);
  1646. ath10k_wmi_detach(ar);
  1647. }
  1648. EXPORT_SYMBOL(ath10k_core_stop);
  1649. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1650. * order to know what hw capabilities should be advertised to mac80211 it is
  1651. * necessary to load the firmware (and tear it down immediately since start
  1652. * hook will try to init it again) before registering */
  1653. static int ath10k_core_probe_fw(struct ath10k *ar)
  1654. {
  1655. struct bmi_target_info target_info;
  1656. int ret = 0;
  1657. ret = ath10k_hif_power_up(ar);
  1658. if (ret) {
  1659. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1660. return ret;
  1661. }
  1662. memset(&target_info, 0, sizeof(target_info));
  1663. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1664. if (ret) {
  1665. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1666. goto err_power_down;
  1667. }
  1668. ar->target_version = target_info.version;
  1669. ar->hw->wiphy->hw_version = target_info.version;
  1670. ret = ath10k_init_hw_params(ar);
  1671. if (ret) {
  1672. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1673. goto err_power_down;
  1674. }
  1675. ret = ath10k_core_fetch_firmware_files(ar);
  1676. if (ret) {
  1677. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1678. goto err_power_down;
  1679. }
  1680. BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
  1681. sizeof(ar->normal_mode_fw.fw_file.fw_version));
  1682. memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
  1683. sizeof(ar->hw->wiphy->fw_version));
  1684. ath10k_debug_print_hwfw_info(ar);
  1685. ret = ath10k_core_pre_cal_download(ar);
  1686. if (ret) {
  1687. /* pre calibration data download is not necessary
  1688. * for all the chipsets. Ignore failures and continue.
  1689. */
  1690. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1691. "could not load pre cal data: %d\n", ret);
  1692. }
  1693. ret = ath10k_core_get_board_id_from_otp(ar);
  1694. if (ret && ret != -EOPNOTSUPP) {
  1695. ath10k_err(ar, "failed to get board id from otp: %d\n",
  1696. ret);
  1697. goto err_free_firmware_files;
  1698. }
  1699. ret = ath10k_core_fetch_board_file(ar);
  1700. if (ret) {
  1701. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1702. goto err_free_firmware_files;
  1703. }
  1704. ath10k_debug_print_board_info(ar);
  1705. ret = ath10k_core_init_firmware_features(ar);
  1706. if (ret) {
  1707. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1708. ret);
  1709. goto err_free_firmware_files;
  1710. }
  1711. ret = ath10k_swap_code_seg_init(ar);
  1712. if (ret) {
  1713. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1714. ret);
  1715. goto err_free_firmware_files;
  1716. }
  1717. mutex_lock(&ar->conf_mutex);
  1718. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
  1719. &ar->normal_mode_fw);
  1720. if (ret) {
  1721. ath10k_err(ar, "could not init core (%d)\n", ret);
  1722. goto err_unlock;
  1723. }
  1724. ath10k_debug_print_boot_info(ar);
  1725. ath10k_core_stop(ar);
  1726. mutex_unlock(&ar->conf_mutex);
  1727. ath10k_hif_power_down(ar);
  1728. return 0;
  1729. err_unlock:
  1730. mutex_unlock(&ar->conf_mutex);
  1731. err_free_firmware_files:
  1732. ath10k_core_free_firmware_files(ar);
  1733. err_power_down:
  1734. ath10k_hif_power_down(ar);
  1735. return ret;
  1736. }
  1737. static void ath10k_core_register_work(struct work_struct *work)
  1738. {
  1739. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1740. int status;
  1741. status = ath10k_core_probe_fw(ar);
  1742. if (status) {
  1743. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1744. goto err;
  1745. }
  1746. status = ath10k_mac_register(ar);
  1747. if (status) {
  1748. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1749. goto err_release_fw;
  1750. }
  1751. status = ath10k_debug_register(ar);
  1752. if (status) {
  1753. ath10k_err(ar, "unable to initialize debugfs\n");
  1754. goto err_unregister_mac;
  1755. }
  1756. status = ath10k_spectral_create(ar);
  1757. if (status) {
  1758. ath10k_err(ar, "failed to initialize spectral\n");
  1759. goto err_debug_destroy;
  1760. }
  1761. status = ath10k_thermal_register(ar);
  1762. if (status) {
  1763. ath10k_err(ar, "could not register thermal device: %d\n",
  1764. status);
  1765. goto err_spectral_destroy;
  1766. }
  1767. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1768. return;
  1769. err_spectral_destroy:
  1770. ath10k_spectral_destroy(ar);
  1771. err_debug_destroy:
  1772. ath10k_debug_destroy(ar);
  1773. err_unregister_mac:
  1774. ath10k_mac_unregister(ar);
  1775. err_release_fw:
  1776. ath10k_core_free_firmware_files(ar);
  1777. err:
  1778. /* TODO: It's probably a good idea to release device from the driver
  1779. * but calling device_release_driver() here will cause a deadlock.
  1780. */
  1781. return;
  1782. }
  1783. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1784. {
  1785. ar->chip_id = chip_id;
  1786. queue_work(ar->workqueue, &ar->register_work);
  1787. return 0;
  1788. }
  1789. EXPORT_SYMBOL(ath10k_core_register);
  1790. void ath10k_core_unregister(struct ath10k *ar)
  1791. {
  1792. cancel_work_sync(&ar->register_work);
  1793. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1794. return;
  1795. ath10k_thermal_unregister(ar);
  1796. /* Stop spectral before unregistering from mac80211 to remove the
  1797. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1798. * would be already be free'd recursively, leading to a double free.
  1799. */
  1800. ath10k_spectral_destroy(ar);
  1801. /* We must unregister from mac80211 before we stop HTC and HIF.
  1802. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1803. * unhappy about callback failures. */
  1804. ath10k_mac_unregister(ar);
  1805. ath10k_testmode_destroy(ar);
  1806. ath10k_core_free_firmware_files(ar);
  1807. ath10k_core_free_board_files(ar);
  1808. ath10k_debug_unregister(ar);
  1809. }
  1810. EXPORT_SYMBOL(ath10k_core_unregister);
  1811. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1812. enum ath10k_bus bus,
  1813. enum ath10k_hw_rev hw_rev,
  1814. const struct ath10k_hif_ops *hif_ops)
  1815. {
  1816. struct ath10k *ar;
  1817. int ret;
  1818. ar = ath10k_mac_create(priv_size);
  1819. if (!ar)
  1820. return NULL;
  1821. ar->ath_common.priv = ar;
  1822. ar->ath_common.hw = ar->hw;
  1823. ar->dev = dev;
  1824. ar->hw_rev = hw_rev;
  1825. ar->hif.ops = hif_ops;
  1826. ar->hif.bus = bus;
  1827. switch (hw_rev) {
  1828. case ATH10K_HW_QCA988X:
  1829. case ATH10K_HW_QCA9887:
  1830. ar->regs = &qca988x_regs;
  1831. ar->hw_values = &qca988x_values;
  1832. break;
  1833. case ATH10K_HW_QCA6174:
  1834. case ATH10K_HW_QCA9377:
  1835. ar->regs = &qca6174_regs;
  1836. ar->hw_values = &qca6174_values;
  1837. break;
  1838. case ATH10K_HW_QCA99X0:
  1839. case ATH10K_HW_QCA9984:
  1840. ar->regs = &qca99x0_regs;
  1841. ar->hw_values = &qca99x0_values;
  1842. break;
  1843. case ATH10K_HW_QCA9888:
  1844. ar->regs = &qca99x0_regs;
  1845. ar->hw_values = &qca9888_values;
  1846. break;
  1847. case ATH10K_HW_QCA4019:
  1848. ar->regs = &qca4019_regs;
  1849. ar->hw_values = &qca4019_values;
  1850. break;
  1851. default:
  1852. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1853. hw_rev);
  1854. ret = -ENOTSUPP;
  1855. goto err_free_mac;
  1856. }
  1857. init_completion(&ar->scan.started);
  1858. init_completion(&ar->scan.completed);
  1859. init_completion(&ar->scan.on_channel);
  1860. init_completion(&ar->target_suspend);
  1861. init_completion(&ar->wow.wakeup_completed);
  1862. init_completion(&ar->install_key_done);
  1863. init_completion(&ar->vdev_setup_done);
  1864. init_completion(&ar->thermal.wmi_sync);
  1865. init_completion(&ar->bss_survey_done);
  1866. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1867. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1868. if (!ar->workqueue)
  1869. goto err_free_mac;
  1870. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1871. if (!ar->workqueue_aux)
  1872. goto err_free_wq;
  1873. mutex_init(&ar->conf_mutex);
  1874. spin_lock_init(&ar->data_lock);
  1875. spin_lock_init(&ar->txqs_lock);
  1876. INIT_LIST_HEAD(&ar->txqs);
  1877. INIT_LIST_HEAD(&ar->peers);
  1878. init_waitqueue_head(&ar->peer_mapping_wq);
  1879. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1880. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1881. init_completion(&ar->offchan_tx_completed);
  1882. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1883. skb_queue_head_init(&ar->offchan_tx_queue);
  1884. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1885. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1886. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1887. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1888. ret = ath10k_debug_create(ar);
  1889. if (ret)
  1890. goto err_free_aux_wq;
  1891. return ar;
  1892. err_free_aux_wq:
  1893. destroy_workqueue(ar->workqueue_aux);
  1894. err_free_wq:
  1895. destroy_workqueue(ar->workqueue);
  1896. err_free_mac:
  1897. ath10k_mac_destroy(ar);
  1898. return NULL;
  1899. }
  1900. EXPORT_SYMBOL(ath10k_core_create);
  1901. void ath10k_core_destroy(struct ath10k *ar)
  1902. {
  1903. flush_workqueue(ar->workqueue);
  1904. destroy_workqueue(ar->workqueue);
  1905. flush_workqueue(ar->workqueue_aux);
  1906. destroy_workqueue(ar->workqueue_aux);
  1907. ath10k_debug_destroy(ar);
  1908. ath10k_wmi_free_host_mem(ar);
  1909. ath10k_mac_destroy(ar);
  1910. }
  1911. EXPORT_SYMBOL(ath10k_core_destroy);
  1912. MODULE_AUTHOR("Qualcomm Atheros");
  1913. MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
  1914. MODULE_LICENSE("Dual BSD/GPL");