r8152.c 101 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. #include <linux/suspend.h>
  28. #include <linux/acpi.h>
  29. /* Information for net-next */
  30. #define NETNEXT_VERSION "08"
  31. /* Information for net */
  32. #define NET_VERSION "5"
  33. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  34. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  35. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  36. #define MODULENAME "r8152"
  37. #define R8152_PHY_ID 32
  38. #define PLA_IDR 0xc000
  39. #define PLA_RCR 0xc010
  40. #define PLA_RMS 0xc016
  41. #define PLA_RXFIFO_CTRL0 0xc0a0
  42. #define PLA_RXFIFO_CTRL1 0xc0a4
  43. #define PLA_RXFIFO_CTRL2 0xc0a8
  44. #define PLA_DMY_REG0 0xc0b0
  45. #define PLA_FMC 0xc0b4
  46. #define PLA_CFG_WOL 0xc0b6
  47. #define PLA_TEREDO_CFG 0xc0bc
  48. #define PLA_MAR 0xcd00
  49. #define PLA_BACKUP 0xd000
  50. #define PAL_BDC_CR 0xd1a0
  51. #define PLA_TEREDO_TIMER 0xd2cc
  52. #define PLA_REALWOW_TIMER 0xd2e8
  53. #define PLA_LEDSEL 0xdd90
  54. #define PLA_LED_FEATURE 0xdd92
  55. #define PLA_PHYAR 0xde00
  56. #define PLA_BOOT_CTRL 0xe004
  57. #define PLA_GPHY_INTR_IMR 0xe022
  58. #define PLA_EEE_CR 0xe040
  59. #define PLA_EEEP_CR 0xe080
  60. #define PLA_MAC_PWR_CTRL 0xe0c0
  61. #define PLA_MAC_PWR_CTRL2 0xe0ca
  62. #define PLA_MAC_PWR_CTRL3 0xe0cc
  63. #define PLA_MAC_PWR_CTRL4 0xe0ce
  64. #define PLA_WDT6_CTRL 0xe428
  65. #define PLA_TCR0 0xe610
  66. #define PLA_TCR1 0xe612
  67. #define PLA_MTPS 0xe615
  68. #define PLA_TXFIFO_CTRL 0xe618
  69. #define PLA_RSTTALLY 0xe800
  70. #define PLA_CR 0xe813
  71. #define PLA_CRWECR 0xe81c
  72. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  73. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  74. #define PLA_CONFIG5 0xe822
  75. #define PLA_PHY_PWR 0xe84c
  76. #define PLA_OOB_CTRL 0xe84f
  77. #define PLA_CPCR 0xe854
  78. #define PLA_MISC_0 0xe858
  79. #define PLA_MISC_1 0xe85a
  80. #define PLA_OCP_GPHY_BASE 0xe86c
  81. #define PLA_TALLYCNT 0xe890
  82. #define PLA_SFF_STS_7 0xe8de
  83. #define PLA_PHYSTATUS 0xe908
  84. #define PLA_BP_BA 0xfc26
  85. #define PLA_BP_0 0xfc28
  86. #define PLA_BP_1 0xfc2a
  87. #define PLA_BP_2 0xfc2c
  88. #define PLA_BP_3 0xfc2e
  89. #define PLA_BP_4 0xfc30
  90. #define PLA_BP_5 0xfc32
  91. #define PLA_BP_6 0xfc34
  92. #define PLA_BP_7 0xfc36
  93. #define PLA_BP_EN 0xfc38
  94. #define USB_USB2PHY 0xb41e
  95. #define USB_SSPHYLINK2 0xb428
  96. #define USB_U2P3_CTRL 0xb460
  97. #define USB_CSR_DUMMY1 0xb464
  98. #define USB_CSR_DUMMY2 0xb466
  99. #define USB_DEV_STAT 0xb808
  100. #define USB_CONNECT_TIMER 0xcbf8
  101. #define USB_BURST_SIZE 0xcfc0
  102. #define USB_USB_CTRL 0xd406
  103. #define USB_PHY_CTRL 0xd408
  104. #define USB_TX_AGG 0xd40a
  105. #define USB_RX_BUF_TH 0xd40c
  106. #define USB_USB_TIMER 0xd428
  107. #define USB_RX_EARLY_TIMEOUT 0xd42c
  108. #define USB_RX_EARLY_SIZE 0xd42e
  109. #define USB_PM_CTRL_STATUS 0xd432
  110. #define USB_TX_DMA 0xd434
  111. #define USB_TOLERANCE 0xd490
  112. #define USB_LPM_CTRL 0xd41a
  113. #define USB_BMU_RESET 0xd4b0
  114. #define USB_UPS_CTRL 0xd800
  115. #define USB_MISC_0 0xd81a
  116. #define USB_POWER_CUT 0xd80a
  117. #define USB_AFE_CTRL2 0xd824
  118. #define USB_WDT11_CTRL 0xe43c
  119. #define USB_BP_BA 0xfc26
  120. #define USB_BP_0 0xfc28
  121. #define USB_BP_1 0xfc2a
  122. #define USB_BP_2 0xfc2c
  123. #define USB_BP_3 0xfc2e
  124. #define USB_BP_4 0xfc30
  125. #define USB_BP_5 0xfc32
  126. #define USB_BP_6 0xfc34
  127. #define USB_BP_7 0xfc36
  128. #define USB_BP_EN 0xfc38
  129. /* OCP Registers */
  130. #define OCP_ALDPS_CONFIG 0x2010
  131. #define OCP_EEE_CONFIG1 0x2080
  132. #define OCP_EEE_CONFIG2 0x2092
  133. #define OCP_EEE_CONFIG3 0x2094
  134. #define OCP_BASE_MII 0xa400
  135. #define OCP_EEE_AR 0xa41a
  136. #define OCP_EEE_DATA 0xa41c
  137. #define OCP_PHY_STATUS 0xa420
  138. #define OCP_POWER_CFG 0xa430
  139. #define OCP_EEE_CFG 0xa432
  140. #define OCP_SRAM_ADDR 0xa436
  141. #define OCP_SRAM_DATA 0xa438
  142. #define OCP_DOWN_SPEED 0xa442
  143. #define OCP_EEE_ABLE 0xa5c4
  144. #define OCP_EEE_ADV 0xa5d0
  145. #define OCP_EEE_LPABLE 0xa5d2
  146. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  147. #define OCP_ADC_CFG 0xbc06
  148. /* SRAM Register */
  149. #define SRAM_LPF_CFG 0x8012
  150. #define SRAM_10M_AMP1 0x8080
  151. #define SRAM_10M_AMP2 0x8082
  152. #define SRAM_IMPEDANCE 0x8084
  153. /* PLA_RCR */
  154. #define RCR_AAP 0x00000001
  155. #define RCR_APM 0x00000002
  156. #define RCR_AM 0x00000004
  157. #define RCR_AB 0x00000008
  158. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  159. /* PLA_RXFIFO_CTRL0 */
  160. #define RXFIFO_THR1_NORMAL 0x00080002
  161. #define RXFIFO_THR1_OOB 0x01800003
  162. /* PLA_RXFIFO_CTRL1 */
  163. #define RXFIFO_THR2_FULL 0x00000060
  164. #define RXFIFO_THR2_HIGH 0x00000038
  165. #define RXFIFO_THR2_OOB 0x0000004a
  166. #define RXFIFO_THR2_NORMAL 0x00a0
  167. /* PLA_RXFIFO_CTRL2 */
  168. #define RXFIFO_THR3_FULL 0x00000078
  169. #define RXFIFO_THR3_HIGH 0x00000048
  170. #define RXFIFO_THR3_OOB 0x0000005a
  171. #define RXFIFO_THR3_NORMAL 0x0110
  172. /* PLA_TXFIFO_CTRL */
  173. #define TXFIFO_THR_NORMAL 0x00400008
  174. #define TXFIFO_THR_NORMAL2 0x01000008
  175. /* PLA_DMY_REG0 */
  176. #define ECM_ALDPS 0x0002
  177. /* PLA_FMC */
  178. #define FMC_FCR_MCU_EN 0x0001
  179. /* PLA_EEEP_CR */
  180. #define EEEP_CR_EEEP_TX 0x0002
  181. /* PLA_WDT6_CTRL */
  182. #define WDT6_SET_MODE 0x0010
  183. /* PLA_TCR0 */
  184. #define TCR0_TX_EMPTY 0x0800
  185. #define TCR0_AUTO_FIFO 0x0080
  186. /* PLA_TCR1 */
  187. #define VERSION_MASK 0x7cf0
  188. /* PLA_MTPS */
  189. #define MTPS_JUMBO (12 * 1024 / 64)
  190. #define MTPS_DEFAULT (6 * 1024 / 64)
  191. /* PLA_RSTTALLY */
  192. #define TALLY_RESET 0x0001
  193. /* PLA_CR */
  194. #define CR_RST 0x10
  195. #define CR_RE 0x08
  196. #define CR_TE 0x04
  197. /* PLA_CRWECR */
  198. #define CRWECR_NORAML 0x00
  199. #define CRWECR_CONFIG 0xc0
  200. /* PLA_OOB_CTRL */
  201. #define NOW_IS_OOB 0x80
  202. #define TXFIFO_EMPTY 0x20
  203. #define RXFIFO_EMPTY 0x10
  204. #define LINK_LIST_READY 0x02
  205. #define DIS_MCU_CLROOB 0x01
  206. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  207. /* PLA_MISC_1 */
  208. #define RXDY_GATED_EN 0x0008
  209. /* PLA_SFF_STS_7 */
  210. #define RE_INIT_LL 0x8000
  211. #define MCU_BORW_EN 0x4000
  212. /* PLA_CPCR */
  213. #define CPCR_RX_VLAN 0x0040
  214. /* PLA_CFG_WOL */
  215. #define MAGIC_EN 0x0001
  216. /* PLA_TEREDO_CFG */
  217. #define TEREDO_SEL 0x8000
  218. #define TEREDO_WAKE_MASK 0x7f00
  219. #define TEREDO_RS_EVENT_MASK 0x00fe
  220. #define OOB_TEREDO_EN 0x0001
  221. /* PAL_BDC_CR */
  222. #define ALDPS_PROXY_MODE 0x0001
  223. /* PLA_CONFIG34 */
  224. #define LINK_ON_WAKE_EN 0x0010
  225. #define LINK_OFF_WAKE_EN 0x0008
  226. /* PLA_CONFIG5 */
  227. #define BWF_EN 0x0040
  228. #define MWF_EN 0x0020
  229. #define UWF_EN 0x0010
  230. #define LAN_WAKE_EN 0x0002
  231. /* PLA_LED_FEATURE */
  232. #define LED_MODE_MASK 0x0700
  233. /* PLA_PHY_PWR */
  234. #define TX_10M_IDLE_EN 0x0080
  235. #define PFM_PWM_SWITCH 0x0040
  236. /* PLA_MAC_PWR_CTRL */
  237. #define D3_CLK_GATED_EN 0x00004000
  238. #define MCU_CLK_RATIO 0x07010f07
  239. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  240. #define ALDPS_SPDWN_RATIO 0x0f87
  241. /* PLA_MAC_PWR_CTRL2 */
  242. #define EEE_SPDWN_RATIO 0x8007
  243. /* PLA_MAC_PWR_CTRL3 */
  244. #define PKT_AVAIL_SPDWN_EN 0x0100
  245. #define SUSPEND_SPDWN_EN 0x0004
  246. #define U1U2_SPDWN_EN 0x0002
  247. #define L1_SPDWN_EN 0x0001
  248. /* PLA_MAC_PWR_CTRL4 */
  249. #define PWRSAVE_SPDWN_EN 0x1000
  250. #define RXDV_SPDWN_EN 0x0800
  251. #define TX10MIDLE_EN 0x0100
  252. #define TP100_SPDWN_EN 0x0020
  253. #define TP500_SPDWN_EN 0x0010
  254. #define TP1000_SPDWN_EN 0x0008
  255. #define EEE_SPDWN_EN 0x0001
  256. /* PLA_GPHY_INTR_IMR */
  257. #define GPHY_STS_MSK 0x0001
  258. #define SPEED_DOWN_MSK 0x0002
  259. #define SPDWN_RXDV_MSK 0x0004
  260. #define SPDWN_LINKCHG_MSK 0x0008
  261. /* PLA_PHYAR */
  262. #define PHYAR_FLAG 0x80000000
  263. /* PLA_EEE_CR */
  264. #define EEE_RX_EN 0x0001
  265. #define EEE_TX_EN 0x0002
  266. /* PLA_BOOT_CTRL */
  267. #define AUTOLOAD_DONE 0x0002
  268. /* USB_USB2PHY */
  269. #define USB2PHY_SUSPEND 0x0001
  270. #define USB2PHY_L1 0x0002
  271. /* USB_SSPHYLINK2 */
  272. #define pwd_dn_scale_mask 0x3ffe
  273. #define pwd_dn_scale(x) ((x) << 1)
  274. /* USB_CSR_DUMMY1 */
  275. #define DYNAMIC_BURST 0x0001
  276. /* USB_CSR_DUMMY2 */
  277. #define EP4_FULL_FC 0x0001
  278. /* USB_DEV_STAT */
  279. #define STAT_SPEED_MASK 0x0006
  280. #define STAT_SPEED_HIGH 0x0000
  281. #define STAT_SPEED_FULL 0x0002
  282. /* USB_TX_AGG */
  283. #define TX_AGG_MAX_THRESHOLD 0x03
  284. /* USB_RX_BUF_TH */
  285. #define RX_THR_SUPPER 0x0c350180
  286. #define RX_THR_HIGH 0x7a120180
  287. #define RX_THR_SLOW 0xffff0180
  288. /* USB_TX_DMA */
  289. #define TEST_MODE_DISABLE 0x00000001
  290. #define TX_SIZE_ADJUST1 0x00000100
  291. /* USB_BMU_RESET */
  292. #define BMU_RESET_EP_IN 0x01
  293. #define BMU_RESET_EP_OUT 0x02
  294. /* USB_UPS_CTRL */
  295. #define POWER_CUT 0x0100
  296. /* USB_PM_CTRL_STATUS */
  297. #define RESUME_INDICATE 0x0001
  298. /* USB_USB_CTRL */
  299. #define RX_AGG_DISABLE 0x0010
  300. #define RX_ZERO_EN 0x0080
  301. /* USB_U2P3_CTRL */
  302. #define U2P3_ENABLE 0x0001
  303. /* USB_POWER_CUT */
  304. #define PWR_EN 0x0001
  305. #define PHASE2_EN 0x0008
  306. /* USB_MISC_0 */
  307. #define PCUT_STATUS 0x0001
  308. /* USB_RX_EARLY_TIMEOUT */
  309. #define COALESCE_SUPER 85000U
  310. #define COALESCE_HIGH 250000U
  311. #define COALESCE_SLOW 524280U
  312. /* USB_WDT11_CTRL */
  313. #define TIMER11_EN 0x0001
  314. /* USB_LPM_CTRL */
  315. /* bit 4 ~ 5: fifo empty boundary */
  316. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  317. /* bit 2 ~ 3: LMP timer */
  318. #define LPM_TIMER_MASK 0x0c
  319. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  320. #define LPM_TIMER_500US 0x0c /* 500 us */
  321. #define ROK_EXIT_LPM 0x02
  322. /* USB_AFE_CTRL2 */
  323. #define SEN_VAL_MASK 0xf800
  324. #define SEN_VAL_NORMAL 0xa000
  325. #define SEL_RXIDLE 0x0100
  326. /* OCP_ALDPS_CONFIG */
  327. #define ENPWRSAVE 0x8000
  328. #define ENPDNPS 0x0200
  329. #define LINKENA 0x0100
  330. #define DIS_SDSAVE 0x0010
  331. /* OCP_PHY_STATUS */
  332. #define PHY_STAT_MASK 0x0007
  333. #define PHY_STAT_LAN_ON 3
  334. #define PHY_STAT_PWRDN 5
  335. /* OCP_POWER_CFG */
  336. #define EEE_CLKDIV_EN 0x8000
  337. #define EN_ALDPS 0x0004
  338. #define EN_10M_PLLOFF 0x0001
  339. /* OCP_EEE_CONFIG1 */
  340. #define RG_TXLPI_MSK_HFDUP 0x8000
  341. #define RG_MATCLR_EN 0x4000
  342. #define EEE_10_CAP 0x2000
  343. #define EEE_NWAY_EN 0x1000
  344. #define TX_QUIET_EN 0x0200
  345. #define RX_QUIET_EN 0x0100
  346. #define sd_rise_time_mask 0x0070
  347. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  348. #define RG_RXLPI_MSK_HFDUP 0x0008
  349. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  350. /* OCP_EEE_CONFIG2 */
  351. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  352. #define RG_DACQUIET_EN 0x0400
  353. #define RG_LDVQUIET_EN 0x0200
  354. #define RG_CKRSEL 0x0020
  355. #define RG_EEEPRG_EN 0x0010
  356. /* OCP_EEE_CONFIG3 */
  357. #define fast_snr_mask 0xff80
  358. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  359. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  360. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  361. /* OCP_EEE_AR */
  362. /* bit[15:14] function */
  363. #define FUN_ADDR 0x0000
  364. #define FUN_DATA 0x4000
  365. /* bit[4:0] device addr */
  366. /* OCP_EEE_CFG */
  367. #define CTAP_SHORT_EN 0x0040
  368. #define EEE10_EN 0x0010
  369. /* OCP_DOWN_SPEED */
  370. #define EN_10M_BGOFF 0x0080
  371. /* OCP_PHY_STATE */
  372. #define TXDIS_STATE 0x01
  373. #define ABD_STATE 0x02
  374. /* OCP_ADC_CFG */
  375. #define CKADSEL_L 0x0100
  376. #define ADC_EN 0x0080
  377. #define EN_EMI_L 0x0040
  378. /* SRAM_LPF_CFG */
  379. #define LPF_AUTO_TUNE 0x8000
  380. /* SRAM_10M_AMP1 */
  381. #define GDAC_IB_UPALL 0x0008
  382. /* SRAM_10M_AMP2 */
  383. #define AMP_DN 0x0200
  384. /* SRAM_IMPEDANCE */
  385. #define RX_DRIVING_MASK 0x6000
  386. /* MAC PASSTHRU */
  387. #define AD_MASK 0xfee0
  388. #define EFUSE 0xcfdb
  389. #define PASS_THRU_MASK 0x1
  390. enum rtl_register_content {
  391. _1000bps = 0x10,
  392. _100bps = 0x08,
  393. _10bps = 0x04,
  394. LINK_STATUS = 0x02,
  395. FULL_DUP = 0x01,
  396. };
  397. #define RTL8152_MAX_TX 4
  398. #define RTL8152_MAX_RX 10
  399. #define INTBUFSIZE 2
  400. #define CRC_SIZE 4
  401. #define TX_ALIGN 4
  402. #define RX_ALIGN 8
  403. #define INTR_LINK 0x0004
  404. #define RTL8152_REQT_READ 0xc0
  405. #define RTL8152_REQT_WRITE 0x40
  406. #define RTL8152_REQ_GET_REGS 0x05
  407. #define RTL8152_REQ_SET_REGS 0x05
  408. #define BYTE_EN_DWORD 0xff
  409. #define BYTE_EN_WORD 0x33
  410. #define BYTE_EN_BYTE 0x11
  411. #define BYTE_EN_SIX_BYTES 0x3f
  412. #define BYTE_EN_START_MASK 0x0f
  413. #define BYTE_EN_END_MASK 0xf0
  414. #define RTL8153_MAX_PACKET 9216 /* 9K */
  415. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  416. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  417. #define RTL8153_RMS RTL8153_MAX_PACKET
  418. #define RTL8152_TX_TIMEOUT (5 * HZ)
  419. #define RTL8152_NAPI_WEIGHT 64
  420. /* rtl8152 flags */
  421. enum rtl8152_flags {
  422. RTL8152_UNPLUG = 0,
  423. RTL8152_SET_RX_MODE,
  424. WORK_ENABLE,
  425. RTL8152_LINK_CHG,
  426. SELECTIVE_SUSPEND,
  427. PHY_RESET,
  428. SCHEDULE_NAPI,
  429. };
  430. /* Define these values to match your device */
  431. #define VENDOR_ID_REALTEK 0x0bda
  432. #define VENDOR_ID_SAMSUNG 0x04e8
  433. #define VENDOR_ID_LENOVO 0x17ef
  434. #define VENDOR_ID_NVIDIA 0x0955
  435. #define MCU_TYPE_PLA 0x0100
  436. #define MCU_TYPE_USB 0x0000
  437. struct tally_counter {
  438. __le64 tx_packets;
  439. __le64 rx_packets;
  440. __le64 tx_errors;
  441. __le32 rx_errors;
  442. __le16 rx_missed;
  443. __le16 align_errors;
  444. __le32 tx_one_collision;
  445. __le32 tx_multi_collision;
  446. __le64 rx_unicast;
  447. __le64 rx_broadcast;
  448. __le32 rx_multicast;
  449. __le16 tx_aborted;
  450. __le16 tx_underrun;
  451. };
  452. struct rx_desc {
  453. __le32 opts1;
  454. #define RX_LEN_MASK 0x7fff
  455. __le32 opts2;
  456. #define RD_UDP_CS BIT(23)
  457. #define RD_TCP_CS BIT(22)
  458. #define RD_IPV6_CS BIT(20)
  459. #define RD_IPV4_CS BIT(19)
  460. __le32 opts3;
  461. #define IPF BIT(23) /* IP checksum fail */
  462. #define UDPF BIT(22) /* UDP checksum fail */
  463. #define TCPF BIT(21) /* TCP checksum fail */
  464. #define RX_VLAN_TAG BIT(16)
  465. __le32 opts4;
  466. __le32 opts5;
  467. __le32 opts6;
  468. };
  469. struct tx_desc {
  470. __le32 opts1;
  471. #define TX_FS BIT(31) /* First segment of a packet */
  472. #define TX_LS BIT(30) /* Final segment of a packet */
  473. #define GTSENDV4 BIT(28)
  474. #define GTSENDV6 BIT(27)
  475. #define GTTCPHO_SHIFT 18
  476. #define GTTCPHO_MAX 0x7fU
  477. #define TX_LEN_MAX 0x3ffffU
  478. __le32 opts2;
  479. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  480. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  481. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  482. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  483. #define MSS_SHIFT 17
  484. #define MSS_MAX 0x7ffU
  485. #define TCPHO_SHIFT 17
  486. #define TCPHO_MAX 0x7ffU
  487. #define TX_VLAN_TAG BIT(16)
  488. };
  489. struct r8152;
  490. struct rx_agg {
  491. struct list_head list;
  492. struct urb *urb;
  493. struct r8152 *context;
  494. void *buffer;
  495. void *head;
  496. };
  497. struct tx_agg {
  498. struct list_head list;
  499. struct urb *urb;
  500. struct r8152 *context;
  501. void *buffer;
  502. void *head;
  503. u32 skb_num;
  504. u32 skb_len;
  505. };
  506. struct r8152 {
  507. unsigned long flags;
  508. struct usb_device *udev;
  509. struct napi_struct napi;
  510. struct usb_interface *intf;
  511. struct net_device *netdev;
  512. struct urb *intr_urb;
  513. struct tx_agg tx_info[RTL8152_MAX_TX];
  514. struct rx_agg rx_info[RTL8152_MAX_RX];
  515. struct list_head rx_done, tx_free;
  516. struct sk_buff_head tx_queue, rx_queue;
  517. spinlock_t rx_lock, tx_lock;
  518. struct delayed_work schedule, hw_phy_work;
  519. struct mii_if_info mii;
  520. struct mutex control; /* use for hw setting */
  521. #ifdef CONFIG_PM_SLEEP
  522. struct notifier_block pm_notifier;
  523. #endif
  524. struct rtl_ops {
  525. void (*init)(struct r8152 *);
  526. int (*enable)(struct r8152 *);
  527. void (*disable)(struct r8152 *);
  528. void (*up)(struct r8152 *);
  529. void (*down)(struct r8152 *);
  530. void (*unload)(struct r8152 *);
  531. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  532. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  533. bool (*in_nway)(struct r8152 *);
  534. void (*hw_phy_cfg)(struct r8152 *);
  535. void (*autosuspend_en)(struct r8152 *tp, bool enable);
  536. } rtl_ops;
  537. int intr_interval;
  538. u32 saved_wolopts;
  539. u32 msg_enable;
  540. u32 tx_qlen;
  541. u32 coalesce;
  542. u16 ocp_base;
  543. u16 speed;
  544. u8 *intr_buff;
  545. u8 version;
  546. u8 duplex;
  547. u8 autoneg;
  548. };
  549. enum rtl_version {
  550. RTL_VER_UNKNOWN = 0,
  551. RTL_VER_01,
  552. RTL_VER_02,
  553. RTL_VER_03,
  554. RTL_VER_04,
  555. RTL_VER_05,
  556. RTL_VER_06,
  557. RTL_VER_MAX
  558. };
  559. enum tx_csum_stat {
  560. TX_CSUM_SUCCESS = 0,
  561. TX_CSUM_TSO,
  562. TX_CSUM_NONE
  563. };
  564. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  565. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  566. */
  567. static const int multicast_filter_limit = 32;
  568. static unsigned int agg_buf_sz = 16384;
  569. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  570. VLAN_ETH_HLEN - VLAN_HLEN)
  571. static
  572. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  573. {
  574. int ret;
  575. void *tmp;
  576. tmp = kmalloc(size, GFP_KERNEL);
  577. if (!tmp)
  578. return -ENOMEM;
  579. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  580. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  581. value, index, tmp, size, 500);
  582. memcpy(data, tmp, size);
  583. kfree(tmp);
  584. return ret;
  585. }
  586. static
  587. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  588. {
  589. int ret;
  590. void *tmp;
  591. tmp = kmemdup(data, size, GFP_KERNEL);
  592. if (!tmp)
  593. return -ENOMEM;
  594. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  595. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  596. value, index, tmp, size, 500);
  597. kfree(tmp);
  598. return ret;
  599. }
  600. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  601. void *data, u16 type)
  602. {
  603. u16 limit = 64;
  604. int ret = 0;
  605. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  606. return -ENODEV;
  607. /* both size and indix must be 4 bytes align */
  608. if ((size & 3) || !size || (index & 3) || !data)
  609. return -EPERM;
  610. if ((u32)index + (u32)size > 0xffff)
  611. return -EPERM;
  612. while (size) {
  613. if (size > limit) {
  614. ret = get_registers(tp, index, type, limit, data);
  615. if (ret < 0)
  616. break;
  617. index += limit;
  618. data += limit;
  619. size -= limit;
  620. } else {
  621. ret = get_registers(tp, index, type, size, data);
  622. if (ret < 0)
  623. break;
  624. index += size;
  625. data += size;
  626. size = 0;
  627. break;
  628. }
  629. }
  630. if (ret == -ENODEV)
  631. set_bit(RTL8152_UNPLUG, &tp->flags);
  632. return ret;
  633. }
  634. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  635. u16 size, void *data, u16 type)
  636. {
  637. int ret;
  638. u16 byteen_start, byteen_end, byen;
  639. u16 limit = 512;
  640. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  641. return -ENODEV;
  642. /* both size and indix must be 4 bytes align */
  643. if ((size & 3) || !size || (index & 3) || !data)
  644. return -EPERM;
  645. if ((u32)index + (u32)size > 0xffff)
  646. return -EPERM;
  647. byteen_start = byteen & BYTE_EN_START_MASK;
  648. byteen_end = byteen & BYTE_EN_END_MASK;
  649. byen = byteen_start | (byteen_start << 4);
  650. ret = set_registers(tp, index, type | byen, 4, data);
  651. if (ret < 0)
  652. goto error1;
  653. index += 4;
  654. data += 4;
  655. size -= 4;
  656. if (size) {
  657. size -= 4;
  658. while (size) {
  659. if (size > limit) {
  660. ret = set_registers(tp, index,
  661. type | BYTE_EN_DWORD,
  662. limit, data);
  663. if (ret < 0)
  664. goto error1;
  665. index += limit;
  666. data += limit;
  667. size -= limit;
  668. } else {
  669. ret = set_registers(tp, index,
  670. type | BYTE_EN_DWORD,
  671. size, data);
  672. if (ret < 0)
  673. goto error1;
  674. index += size;
  675. data += size;
  676. size = 0;
  677. break;
  678. }
  679. }
  680. byen = byteen_end | (byteen_end >> 4);
  681. ret = set_registers(tp, index, type | byen, 4, data);
  682. if (ret < 0)
  683. goto error1;
  684. }
  685. error1:
  686. if (ret == -ENODEV)
  687. set_bit(RTL8152_UNPLUG, &tp->flags);
  688. return ret;
  689. }
  690. static inline
  691. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  692. {
  693. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  694. }
  695. static inline
  696. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  697. {
  698. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  699. }
  700. static inline
  701. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  702. {
  703. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  704. }
  705. static inline
  706. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  707. {
  708. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  709. }
  710. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  711. {
  712. __le32 data;
  713. generic_ocp_read(tp, index, sizeof(data), &data, type);
  714. return __le32_to_cpu(data);
  715. }
  716. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  717. {
  718. __le32 tmp = __cpu_to_le32(data);
  719. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  720. }
  721. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  722. {
  723. u32 data;
  724. __le32 tmp;
  725. u8 shift = index & 2;
  726. index &= ~3;
  727. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  728. data = __le32_to_cpu(tmp);
  729. data >>= (shift * 8);
  730. data &= 0xffff;
  731. return (u16)data;
  732. }
  733. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  734. {
  735. u32 mask = 0xffff;
  736. __le32 tmp;
  737. u16 byen = BYTE_EN_WORD;
  738. u8 shift = index & 2;
  739. data &= mask;
  740. if (index & 2) {
  741. byen <<= shift;
  742. mask <<= (shift * 8);
  743. data <<= (shift * 8);
  744. index &= ~3;
  745. }
  746. tmp = __cpu_to_le32(data);
  747. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  748. }
  749. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  750. {
  751. u32 data;
  752. __le32 tmp;
  753. u8 shift = index & 3;
  754. index &= ~3;
  755. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  756. data = __le32_to_cpu(tmp);
  757. data >>= (shift * 8);
  758. data &= 0xff;
  759. return (u8)data;
  760. }
  761. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  762. {
  763. u32 mask = 0xff;
  764. __le32 tmp;
  765. u16 byen = BYTE_EN_BYTE;
  766. u8 shift = index & 3;
  767. data &= mask;
  768. if (index & 3) {
  769. byen <<= shift;
  770. mask <<= (shift * 8);
  771. data <<= (shift * 8);
  772. index &= ~3;
  773. }
  774. tmp = __cpu_to_le32(data);
  775. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  776. }
  777. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  778. {
  779. u16 ocp_base, ocp_index;
  780. ocp_base = addr & 0xf000;
  781. if (ocp_base != tp->ocp_base) {
  782. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  783. tp->ocp_base = ocp_base;
  784. }
  785. ocp_index = (addr & 0x0fff) | 0xb000;
  786. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  787. }
  788. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  789. {
  790. u16 ocp_base, ocp_index;
  791. ocp_base = addr & 0xf000;
  792. if (ocp_base != tp->ocp_base) {
  793. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  794. tp->ocp_base = ocp_base;
  795. }
  796. ocp_index = (addr & 0x0fff) | 0xb000;
  797. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  798. }
  799. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  800. {
  801. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  802. }
  803. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  804. {
  805. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  806. }
  807. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  808. {
  809. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  810. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  811. }
  812. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  813. {
  814. struct r8152 *tp = netdev_priv(netdev);
  815. int ret;
  816. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  817. return -ENODEV;
  818. if (phy_id != R8152_PHY_ID)
  819. return -EINVAL;
  820. ret = r8152_mdio_read(tp, reg);
  821. return ret;
  822. }
  823. static
  824. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  825. {
  826. struct r8152 *tp = netdev_priv(netdev);
  827. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  828. return;
  829. if (phy_id != R8152_PHY_ID)
  830. return;
  831. r8152_mdio_write(tp, reg, val);
  832. }
  833. static int
  834. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  835. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  836. {
  837. struct r8152 *tp = netdev_priv(netdev);
  838. struct sockaddr *addr = p;
  839. int ret = -EADDRNOTAVAIL;
  840. if (!is_valid_ether_addr(addr->sa_data))
  841. goto out1;
  842. ret = usb_autopm_get_interface(tp->intf);
  843. if (ret < 0)
  844. goto out1;
  845. mutex_lock(&tp->control);
  846. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  847. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  848. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  849. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  850. mutex_unlock(&tp->control);
  851. usb_autopm_put_interface(tp->intf);
  852. out1:
  853. return ret;
  854. }
  855. /* Devices containing RTL8153-AD can support a persistent
  856. * host system provided MAC address.
  857. * Examples of this are Dell TB15 and Dell WD15 docks
  858. */
  859. static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
  860. {
  861. acpi_status status;
  862. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  863. union acpi_object *obj;
  864. int ret = -EINVAL;
  865. u32 ocp_data;
  866. unsigned char buf[6];
  867. /* test for -AD variant of RTL8153 */
  868. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  869. if ((ocp_data & AD_MASK) != 0x1000)
  870. return -ENODEV;
  871. /* test for MAC address pass-through bit */
  872. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
  873. if ((ocp_data & PASS_THRU_MASK) != 1)
  874. return -ENODEV;
  875. /* returns _AUXMAC_#AABBCCDDEEFF# */
  876. status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
  877. obj = (union acpi_object *)buffer.pointer;
  878. if (!ACPI_SUCCESS(status))
  879. return -ENODEV;
  880. if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
  881. netif_warn(tp, probe, tp->netdev,
  882. "Invalid buffer when reading pass-thru MAC addr: "
  883. "(%d, %d)\n",
  884. obj->type, obj->string.length);
  885. goto amacout;
  886. }
  887. if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
  888. strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
  889. netif_warn(tp, probe, tp->netdev,
  890. "Invalid header when reading pass-thru MAC addr\n");
  891. goto amacout;
  892. }
  893. ret = hex2bin(buf, obj->string.pointer + 9, 6);
  894. if (!(ret == 0 && is_valid_ether_addr(buf))) {
  895. netif_warn(tp, probe, tp->netdev,
  896. "Invalid MAC when reading pass-thru MAC addr: "
  897. "%d, %pM\n", ret, buf);
  898. ret = -EINVAL;
  899. goto amacout;
  900. }
  901. memcpy(sa->sa_data, buf, 6);
  902. ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
  903. netif_info(tp, probe, tp->netdev,
  904. "Using pass-thru MAC addr %pM\n", sa->sa_data);
  905. amacout:
  906. kfree(obj);
  907. return ret;
  908. }
  909. static int set_ethernet_addr(struct r8152 *tp)
  910. {
  911. struct net_device *dev = tp->netdev;
  912. struct sockaddr sa;
  913. int ret;
  914. if (tp->version == RTL_VER_01)
  915. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  916. else {
  917. /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
  918. * or system doesn't provide valid _SB.AMAC this will be
  919. * be expected to non-zero
  920. */
  921. ret = vendor_mac_passthru_addr_read(tp, &sa);
  922. if (ret < 0)
  923. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  924. }
  925. if (ret < 0) {
  926. netif_err(tp, probe, dev, "Get ether addr fail\n");
  927. } else if (!is_valid_ether_addr(sa.sa_data)) {
  928. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  929. sa.sa_data);
  930. eth_hw_addr_random(dev);
  931. ether_addr_copy(sa.sa_data, dev->dev_addr);
  932. ret = rtl8152_set_mac_address(dev, &sa);
  933. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  934. sa.sa_data);
  935. } else {
  936. if (tp->version == RTL_VER_01)
  937. ether_addr_copy(dev->dev_addr, sa.sa_data);
  938. else
  939. ret = rtl8152_set_mac_address(dev, &sa);
  940. }
  941. return ret;
  942. }
  943. static void read_bulk_callback(struct urb *urb)
  944. {
  945. struct net_device *netdev;
  946. int status = urb->status;
  947. struct rx_agg *agg;
  948. struct r8152 *tp;
  949. agg = urb->context;
  950. if (!agg)
  951. return;
  952. tp = agg->context;
  953. if (!tp)
  954. return;
  955. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  956. return;
  957. if (!test_bit(WORK_ENABLE, &tp->flags))
  958. return;
  959. netdev = tp->netdev;
  960. /* When link down, the driver would cancel all bulks. */
  961. /* This avoid the re-submitting bulk */
  962. if (!netif_carrier_ok(netdev))
  963. return;
  964. usb_mark_last_busy(tp->udev);
  965. switch (status) {
  966. case 0:
  967. if (urb->actual_length < ETH_ZLEN)
  968. break;
  969. spin_lock(&tp->rx_lock);
  970. list_add_tail(&agg->list, &tp->rx_done);
  971. spin_unlock(&tp->rx_lock);
  972. napi_schedule(&tp->napi);
  973. return;
  974. case -ESHUTDOWN:
  975. set_bit(RTL8152_UNPLUG, &tp->flags);
  976. netif_device_detach(tp->netdev);
  977. return;
  978. case -ENOENT:
  979. return; /* the urb is in unlink state */
  980. case -ETIME:
  981. if (net_ratelimit())
  982. netdev_warn(netdev, "maybe reset is needed?\n");
  983. break;
  984. default:
  985. if (net_ratelimit())
  986. netdev_warn(netdev, "Rx status %d\n", status);
  987. break;
  988. }
  989. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  990. }
  991. static void write_bulk_callback(struct urb *urb)
  992. {
  993. struct net_device_stats *stats;
  994. struct net_device *netdev;
  995. struct tx_agg *agg;
  996. struct r8152 *tp;
  997. int status = urb->status;
  998. agg = urb->context;
  999. if (!agg)
  1000. return;
  1001. tp = agg->context;
  1002. if (!tp)
  1003. return;
  1004. netdev = tp->netdev;
  1005. stats = &netdev->stats;
  1006. if (status) {
  1007. if (net_ratelimit())
  1008. netdev_warn(netdev, "Tx status %d\n", status);
  1009. stats->tx_errors += agg->skb_num;
  1010. } else {
  1011. stats->tx_packets += agg->skb_num;
  1012. stats->tx_bytes += agg->skb_len;
  1013. }
  1014. spin_lock(&tp->tx_lock);
  1015. list_add_tail(&agg->list, &tp->tx_free);
  1016. spin_unlock(&tp->tx_lock);
  1017. usb_autopm_put_interface_async(tp->intf);
  1018. if (!netif_carrier_ok(netdev))
  1019. return;
  1020. if (!test_bit(WORK_ENABLE, &tp->flags))
  1021. return;
  1022. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1023. return;
  1024. if (!skb_queue_empty(&tp->tx_queue))
  1025. napi_schedule(&tp->napi);
  1026. }
  1027. static void intr_callback(struct urb *urb)
  1028. {
  1029. struct r8152 *tp;
  1030. __le16 *d;
  1031. int status = urb->status;
  1032. int res;
  1033. tp = urb->context;
  1034. if (!tp)
  1035. return;
  1036. if (!test_bit(WORK_ENABLE, &tp->flags))
  1037. return;
  1038. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1039. return;
  1040. switch (status) {
  1041. case 0: /* success */
  1042. break;
  1043. case -ECONNRESET: /* unlink */
  1044. case -ESHUTDOWN:
  1045. netif_device_detach(tp->netdev);
  1046. case -ENOENT:
  1047. case -EPROTO:
  1048. netif_info(tp, intr, tp->netdev,
  1049. "Stop submitting intr, status %d\n", status);
  1050. return;
  1051. case -EOVERFLOW:
  1052. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  1053. goto resubmit;
  1054. /* -EPIPE: should clear the halt */
  1055. default:
  1056. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  1057. goto resubmit;
  1058. }
  1059. d = urb->transfer_buffer;
  1060. if (INTR_LINK & __le16_to_cpu(d[0])) {
  1061. if (!netif_carrier_ok(tp->netdev)) {
  1062. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1063. schedule_delayed_work(&tp->schedule, 0);
  1064. }
  1065. } else {
  1066. if (netif_carrier_ok(tp->netdev)) {
  1067. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1068. schedule_delayed_work(&tp->schedule, 0);
  1069. }
  1070. }
  1071. resubmit:
  1072. res = usb_submit_urb(urb, GFP_ATOMIC);
  1073. if (res == -ENODEV) {
  1074. set_bit(RTL8152_UNPLUG, &tp->flags);
  1075. netif_device_detach(tp->netdev);
  1076. } else if (res) {
  1077. netif_err(tp, intr, tp->netdev,
  1078. "can't resubmit intr, status %d\n", res);
  1079. }
  1080. }
  1081. static inline void *rx_agg_align(void *data)
  1082. {
  1083. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1084. }
  1085. static inline void *tx_agg_align(void *data)
  1086. {
  1087. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1088. }
  1089. static void free_all_mem(struct r8152 *tp)
  1090. {
  1091. int i;
  1092. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1093. usb_free_urb(tp->rx_info[i].urb);
  1094. tp->rx_info[i].urb = NULL;
  1095. kfree(tp->rx_info[i].buffer);
  1096. tp->rx_info[i].buffer = NULL;
  1097. tp->rx_info[i].head = NULL;
  1098. }
  1099. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1100. usb_free_urb(tp->tx_info[i].urb);
  1101. tp->tx_info[i].urb = NULL;
  1102. kfree(tp->tx_info[i].buffer);
  1103. tp->tx_info[i].buffer = NULL;
  1104. tp->tx_info[i].head = NULL;
  1105. }
  1106. usb_free_urb(tp->intr_urb);
  1107. tp->intr_urb = NULL;
  1108. kfree(tp->intr_buff);
  1109. tp->intr_buff = NULL;
  1110. }
  1111. static int alloc_all_mem(struct r8152 *tp)
  1112. {
  1113. struct net_device *netdev = tp->netdev;
  1114. struct usb_interface *intf = tp->intf;
  1115. struct usb_host_interface *alt = intf->cur_altsetting;
  1116. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1117. struct urb *urb;
  1118. int node, i;
  1119. u8 *buf;
  1120. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1121. spin_lock_init(&tp->rx_lock);
  1122. spin_lock_init(&tp->tx_lock);
  1123. INIT_LIST_HEAD(&tp->tx_free);
  1124. skb_queue_head_init(&tp->tx_queue);
  1125. skb_queue_head_init(&tp->rx_queue);
  1126. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1127. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1128. if (!buf)
  1129. goto err1;
  1130. if (buf != rx_agg_align(buf)) {
  1131. kfree(buf);
  1132. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1133. node);
  1134. if (!buf)
  1135. goto err1;
  1136. }
  1137. urb = usb_alloc_urb(0, GFP_KERNEL);
  1138. if (!urb) {
  1139. kfree(buf);
  1140. goto err1;
  1141. }
  1142. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1143. tp->rx_info[i].context = tp;
  1144. tp->rx_info[i].urb = urb;
  1145. tp->rx_info[i].buffer = buf;
  1146. tp->rx_info[i].head = rx_agg_align(buf);
  1147. }
  1148. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1149. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1150. if (!buf)
  1151. goto err1;
  1152. if (buf != tx_agg_align(buf)) {
  1153. kfree(buf);
  1154. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1155. node);
  1156. if (!buf)
  1157. goto err1;
  1158. }
  1159. urb = usb_alloc_urb(0, GFP_KERNEL);
  1160. if (!urb) {
  1161. kfree(buf);
  1162. goto err1;
  1163. }
  1164. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1165. tp->tx_info[i].context = tp;
  1166. tp->tx_info[i].urb = urb;
  1167. tp->tx_info[i].buffer = buf;
  1168. tp->tx_info[i].head = tx_agg_align(buf);
  1169. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1170. }
  1171. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1172. if (!tp->intr_urb)
  1173. goto err1;
  1174. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1175. if (!tp->intr_buff)
  1176. goto err1;
  1177. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1178. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1179. tp->intr_buff, INTBUFSIZE, intr_callback,
  1180. tp, tp->intr_interval);
  1181. return 0;
  1182. err1:
  1183. free_all_mem(tp);
  1184. return -ENOMEM;
  1185. }
  1186. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1187. {
  1188. struct tx_agg *agg = NULL;
  1189. unsigned long flags;
  1190. if (list_empty(&tp->tx_free))
  1191. return NULL;
  1192. spin_lock_irqsave(&tp->tx_lock, flags);
  1193. if (!list_empty(&tp->tx_free)) {
  1194. struct list_head *cursor;
  1195. cursor = tp->tx_free.next;
  1196. list_del_init(cursor);
  1197. agg = list_entry(cursor, struct tx_agg, list);
  1198. }
  1199. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1200. return agg;
  1201. }
  1202. /* r8152_csum_workaround()
  1203. * The hw limites the value the transport offset. When the offset is out of the
  1204. * range, calculate the checksum by sw.
  1205. */
  1206. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1207. struct sk_buff_head *list)
  1208. {
  1209. if (skb_shinfo(skb)->gso_size) {
  1210. netdev_features_t features = tp->netdev->features;
  1211. struct sk_buff_head seg_list;
  1212. struct sk_buff *segs, *nskb;
  1213. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1214. segs = skb_gso_segment(skb, features);
  1215. if (IS_ERR(segs) || !segs)
  1216. goto drop;
  1217. __skb_queue_head_init(&seg_list);
  1218. do {
  1219. nskb = segs;
  1220. segs = segs->next;
  1221. nskb->next = NULL;
  1222. __skb_queue_tail(&seg_list, nskb);
  1223. } while (segs);
  1224. skb_queue_splice(&seg_list, list);
  1225. dev_kfree_skb(skb);
  1226. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1227. if (skb_checksum_help(skb) < 0)
  1228. goto drop;
  1229. __skb_queue_head(list, skb);
  1230. } else {
  1231. struct net_device_stats *stats;
  1232. drop:
  1233. stats = &tp->netdev->stats;
  1234. stats->tx_dropped++;
  1235. dev_kfree_skb(skb);
  1236. }
  1237. }
  1238. /* msdn_giant_send_check()
  1239. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1240. * packet length for IPv6 TCP large packets.
  1241. */
  1242. static int msdn_giant_send_check(struct sk_buff *skb)
  1243. {
  1244. const struct ipv6hdr *ipv6h;
  1245. struct tcphdr *th;
  1246. int ret;
  1247. ret = skb_cow_head(skb, 0);
  1248. if (ret)
  1249. return ret;
  1250. ipv6h = ipv6_hdr(skb);
  1251. th = tcp_hdr(skb);
  1252. th->check = 0;
  1253. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1254. return ret;
  1255. }
  1256. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1257. {
  1258. if (skb_vlan_tag_present(skb)) {
  1259. u32 opts2;
  1260. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1261. desc->opts2 |= cpu_to_le32(opts2);
  1262. }
  1263. }
  1264. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1265. {
  1266. u32 opts2 = le32_to_cpu(desc->opts2);
  1267. if (opts2 & RX_VLAN_TAG)
  1268. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1269. swab16(opts2 & 0xffff));
  1270. }
  1271. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1272. struct sk_buff *skb, u32 len, u32 transport_offset)
  1273. {
  1274. u32 mss = skb_shinfo(skb)->gso_size;
  1275. u32 opts1, opts2 = 0;
  1276. int ret = TX_CSUM_SUCCESS;
  1277. WARN_ON_ONCE(len > TX_LEN_MAX);
  1278. opts1 = len | TX_FS | TX_LS;
  1279. if (mss) {
  1280. if (transport_offset > GTTCPHO_MAX) {
  1281. netif_warn(tp, tx_err, tp->netdev,
  1282. "Invalid transport offset 0x%x for TSO\n",
  1283. transport_offset);
  1284. ret = TX_CSUM_TSO;
  1285. goto unavailable;
  1286. }
  1287. switch (vlan_get_protocol(skb)) {
  1288. case htons(ETH_P_IP):
  1289. opts1 |= GTSENDV4;
  1290. break;
  1291. case htons(ETH_P_IPV6):
  1292. if (msdn_giant_send_check(skb)) {
  1293. ret = TX_CSUM_TSO;
  1294. goto unavailable;
  1295. }
  1296. opts1 |= GTSENDV6;
  1297. break;
  1298. default:
  1299. WARN_ON_ONCE(1);
  1300. break;
  1301. }
  1302. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1303. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1304. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1305. u8 ip_protocol;
  1306. if (transport_offset > TCPHO_MAX) {
  1307. netif_warn(tp, tx_err, tp->netdev,
  1308. "Invalid transport offset 0x%x\n",
  1309. transport_offset);
  1310. ret = TX_CSUM_NONE;
  1311. goto unavailable;
  1312. }
  1313. switch (vlan_get_protocol(skb)) {
  1314. case htons(ETH_P_IP):
  1315. opts2 |= IPV4_CS;
  1316. ip_protocol = ip_hdr(skb)->protocol;
  1317. break;
  1318. case htons(ETH_P_IPV6):
  1319. opts2 |= IPV6_CS;
  1320. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1321. break;
  1322. default:
  1323. ip_protocol = IPPROTO_RAW;
  1324. break;
  1325. }
  1326. if (ip_protocol == IPPROTO_TCP)
  1327. opts2 |= TCP_CS;
  1328. else if (ip_protocol == IPPROTO_UDP)
  1329. opts2 |= UDP_CS;
  1330. else
  1331. WARN_ON_ONCE(1);
  1332. opts2 |= transport_offset << TCPHO_SHIFT;
  1333. }
  1334. desc->opts2 = cpu_to_le32(opts2);
  1335. desc->opts1 = cpu_to_le32(opts1);
  1336. unavailable:
  1337. return ret;
  1338. }
  1339. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1340. {
  1341. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1342. int remain, ret;
  1343. u8 *tx_data;
  1344. __skb_queue_head_init(&skb_head);
  1345. spin_lock(&tx_queue->lock);
  1346. skb_queue_splice_init(tx_queue, &skb_head);
  1347. spin_unlock(&tx_queue->lock);
  1348. tx_data = agg->head;
  1349. agg->skb_num = 0;
  1350. agg->skb_len = 0;
  1351. remain = agg_buf_sz;
  1352. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1353. struct tx_desc *tx_desc;
  1354. struct sk_buff *skb;
  1355. unsigned int len;
  1356. u32 offset;
  1357. skb = __skb_dequeue(&skb_head);
  1358. if (!skb)
  1359. break;
  1360. len = skb->len + sizeof(*tx_desc);
  1361. if (len > remain) {
  1362. __skb_queue_head(&skb_head, skb);
  1363. break;
  1364. }
  1365. tx_data = tx_agg_align(tx_data);
  1366. tx_desc = (struct tx_desc *)tx_data;
  1367. offset = (u32)skb_transport_offset(skb);
  1368. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1369. r8152_csum_workaround(tp, skb, &skb_head);
  1370. continue;
  1371. }
  1372. rtl_tx_vlan_tag(tx_desc, skb);
  1373. tx_data += sizeof(*tx_desc);
  1374. len = skb->len;
  1375. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1376. struct net_device_stats *stats = &tp->netdev->stats;
  1377. stats->tx_dropped++;
  1378. dev_kfree_skb_any(skb);
  1379. tx_data -= sizeof(*tx_desc);
  1380. continue;
  1381. }
  1382. tx_data += len;
  1383. agg->skb_len += len;
  1384. agg->skb_num++;
  1385. dev_kfree_skb_any(skb);
  1386. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1387. }
  1388. if (!skb_queue_empty(&skb_head)) {
  1389. spin_lock(&tx_queue->lock);
  1390. skb_queue_splice(&skb_head, tx_queue);
  1391. spin_unlock(&tx_queue->lock);
  1392. }
  1393. netif_tx_lock(tp->netdev);
  1394. if (netif_queue_stopped(tp->netdev) &&
  1395. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1396. netif_wake_queue(tp->netdev);
  1397. netif_tx_unlock(tp->netdev);
  1398. ret = usb_autopm_get_interface_async(tp->intf);
  1399. if (ret < 0)
  1400. goto out_tx_fill;
  1401. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1402. agg->head, (int)(tx_data - (u8 *)agg->head),
  1403. (usb_complete_t)write_bulk_callback, agg);
  1404. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1405. if (ret < 0)
  1406. usb_autopm_put_interface_async(tp->intf);
  1407. out_tx_fill:
  1408. return ret;
  1409. }
  1410. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1411. {
  1412. u8 checksum = CHECKSUM_NONE;
  1413. u32 opts2, opts3;
  1414. if (tp->version == RTL_VER_01)
  1415. goto return_result;
  1416. opts2 = le32_to_cpu(rx_desc->opts2);
  1417. opts3 = le32_to_cpu(rx_desc->opts3);
  1418. if (opts2 & RD_IPV4_CS) {
  1419. if (opts3 & IPF)
  1420. checksum = CHECKSUM_NONE;
  1421. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1422. checksum = CHECKSUM_NONE;
  1423. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1424. checksum = CHECKSUM_NONE;
  1425. else
  1426. checksum = CHECKSUM_UNNECESSARY;
  1427. } else if (RD_IPV6_CS) {
  1428. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1429. checksum = CHECKSUM_UNNECESSARY;
  1430. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1431. checksum = CHECKSUM_UNNECESSARY;
  1432. }
  1433. return_result:
  1434. return checksum;
  1435. }
  1436. static int rx_bottom(struct r8152 *tp, int budget)
  1437. {
  1438. unsigned long flags;
  1439. struct list_head *cursor, *next, rx_queue;
  1440. int ret = 0, work_done = 0;
  1441. if (!skb_queue_empty(&tp->rx_queue)) {
  1442. while (work_done < budget) {
  1443. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1444. struct net_device *netdev = tp->netdev;
  1445. struct net_device_stats *stats = &netdev->stats;
  1446. unsigned int pkt_len;
  1447. if (!skb)
  1448. break;
  1449. pkt_len = skb->len;
  1450. napi_gro_receive(&tp->napi, skb);
  1451. work_done++;
  1452. stats->rx_packets++;
  1453. stats->rx_bytes += pkt_len;
  1454. }
  1455. }
  1456. if (list_empty(&tp->rx_done))
  1457. goto out1;
  1458. INIT_LIST_HEAD(&rx_queue);
  1459. spin_lock_irqsave(&tp->rx_lock, flags);
  1460. list_splice_init(&tp->rx_done, &rx_queue);
  1461. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1462. list_for_each_safe(cursor, next, &rx_queue) {
  1463. struct rx_desc *rx_desc;
  1464. struct rx_agg *agg;
  1465. int len_used = 0;
  1466. struct urb *urb;
  1467. u8 *rx_data;
  1468. list_del_init(cursor);
  1469. agg = list_entry(cursor, struct rx_agg, list);
  1470. urb = agg->urb;
  1471. if (urb->actual_length < ETH_ZLEN)
  1472. goto submit;
  1473. rx_desc = agg->head;
  1474. rx_data = agg->head;
  1475. len_used += sizeof(struct rx_desc);
  1476. while (urb->actual_length > len_used) {
  1477. struct net_device *netdev = tp->netdev;
  1478. struct net_device_stats *stats = &netdev->stats;
  1479. unsigned int pkt_len;
  1480. struct sk_buff *skb;
  1481. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1482. if (pkt_len < ETH_ZLEN)
  1483. break;
  1484. len_used += pkt_len;
  1485. if (urb->actual_length < len_used)
  1486. break;
  1487. pkt_len -= CRC_SIZE;
  1488. rx_data += sizeof(struct rx_desc);
  1489. skb = napi_alloc_skb(&tp->napi, pkt_len);
  1490. if (!skb) {
  1491. stats->rx_dropped++;
  1492. goto find_next_rx;
  1493. }
  1494. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1495. memcpy(skb->data, rx_data, pkt_len);
  1496. skb_put(skb, pkt_len);
  1497. skb->protocol = eth_type_trans(skb, netdev);
  1498. rtl_rx_vlan_tag(rx_desc, skb);
  1499. if (work_done < budget) {
  1500. napi_gro_receive(&tp->napi, skb);
  1501. work_done++;
  1502. stats->rx_packets++;
  1503. stats->rx_bytes += pkt_len;
  1504. } else {
  1505. __skb_queue_tail(&tp->rx_queue, skb);
  1506. }
  1507. find_next_rx:
  1508. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1509. rx_desc = (struct rx_desc *)rx_data;
  1510. len_used = (int)(rx_data - (u8 *)agg->head);
  1511. len_used += sizeof(struct rx_desc);
  1512. }
  1513. submit:
  1514. if (!ret) {
  1515. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1516. } else {
  1517. urb->actual_length = 0;
  1518. list_add_tail(&agg->list, next);
  1519. }
  1520. }
  1521. if (!list_empty(&rx_queue)) {
  1522. spin_lock_irqsave(&tp->rx_lock, flags);
  1523. list_splice_tail(&rx_queue, &tp->rx_done);
  1524. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1525. }
  1526. out1:
  1527. return work_done;
  1528. }
  1529. static void tx_bottom(struct r8152 *tp)
  1530. {
  1531. int res;
  1532. do {
  1533. struct tx_agg *agg;
  1534. if (skb_queue_empty(&tp->tx_queue))
  1535. break;
  1536. agg = r8152_get_tx_agg(tp);
  1537. if (!agg)
  1538. break;
  1539. res = r8152_tx_agg_fill(tp, agg);
  1540. if (res) {
  1541. struct net_device *netdev = tp->netdev;
  1542. if (res == -ENODEV) {
  1543. set_bit(RTL8152_UNPLUG, &tp->flags);
  1544. netif_device_detach(netdev);
  1545. } else {
  1546. struct net_device_stats *stats = &netdev->stats;
  1547. unsigned long flags;
  1548. netif_warn(tp, tx_err, netdev,
  1549. "failed tx_urb %d\n", res);
  1550. stats->tx_dropped += agg->skb_num;
  1551. spin_lock_irqsave(&tp->tx_lock, flags);
  1552. list_add_tail(&agg->list, &tp->tx_free);
  1553. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1554. }
  1555. }
  1556. } while (res == 0);
  1557. }
  1558. static void bottom_half(struct r8152 *tp)
  1559. {
  1560. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1561. return;
  1562. if (!test_bit(WORK_ENABLE, &tp->flags))
  1563. return;
  1564. /* When link down, the driver would cancel all bulks. */
  1565. /* This avoid the re-submitting bulk */
  1566. if (!netif_carrier_ok(tp->netdev))
  1567. return;
  1568. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1569. tx_bottom(tp);
  1570. }
  1571. static int r8152_poll(struct napi_struct *napi, int budget)
  1572. {
  1573. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1574. int work_done;
  1575. work_done = rx_bottom(tp, budget);
  1576. bottom_half(tp);
  1577. if (work_done < budget) {
  1578. napi_complete(napi);
  1579. if (!list_empty(&tp->rx_done))
  1580. napi_schedule(napi);
  1581. }
  1582. return work_done;
  1583. }
  1584. static
  1585. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1586. {
  1587. int ret;
  1588. /* The rx would be stopped, so skip submitting */
  1589. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1590. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1591. return 0;
  1592. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1593. agg->head, agg_buf_sz,
  1594. (usb_complete_t)read_bulk_callback, agg);
  1595. ret = usb_submit_urb(agg->urb, mem_flags);
  1596. if (ret == -ENODEV) {
  1597. set_bit(RTL8152_UNPLUG, &tp->flags);
  1598. netif_device_detach(tp->netdev);
  1599. } else if (ret) {
  1600. struct urb *urb = agg->urb;
  1601. unsigned long flags;
  1602. urb->actual_length = 0;
  1603. spin_lock_irqsave(&tp->rx_lock, flags);
  1604. list_add_tail(&agg->list, &tp->rx_done);
  1605. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1606. netif_err(tp, rx_err, tp->netdev,
  1607. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1608. napi_schedule(&tp->napi);
  1609. }
  1610. return ret;
  1611. }
  1612. static void rtl_drop_queued_tx(struct r8152 *tp)
  1613. {
  1614. struct net_device_stats *stats = &tp->netdev->stats;
  1615. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1616. struct sk_buff *skb;
  1617. if (skb_queue_empty(tx_queue))
  1618. return;
  1619. __skb_queue_head_init(&skb_head);
  1620. spin_lock_bh(&tx_queue->lock);
  1621. skb_queue_splice_init(tx_queue, &skb_head);
  1622. spin_unlock_bh(&tx_queue->lock);
  1623. while ((skb = __skb_dequeue(&skb_head))) {
  1624. dev_kfree_skb(skb);
  1625. stats->tx_dropped++;
  1626. }
  1627. }
  1628. static void rtl8152_tx_timeout(struct net_device *netdev)
  1629. {
  1630. struct r8152 *tp = netdev_priv(netdev);
  1631. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1632. usb_queue_reset_device(tp->intf);
  1633. }
  1634. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1635. {
  1636. struct r8152 *tp = netdev_priv(netdev);
  1637. if (netif_carrier_ok(netdev)) {
  1638. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1639. schedule_delayed_work(&tp->schedule, 0);
  1640. }
  1641. }
  1642. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1643. {
  1644. struct r8152 *tp = netdev_priv(netdev);
  1645. u32 mc_filter[2]; /* Multicast hash filter */
  1646. __le32 tmp[2];
  1647. u32 ocp_data;
  1648. netif_stop_queue(netdev);
  1649. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1650. ocp_data &= ~RCR_ACPT_ALL;
  1651. ocp_data |= RCR_AB | RCR_APM;
  1652. if (netdev->flags & IFF_PROMISC) {
  1653. /* Unconditionally log net taps. */
  1654. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1655. ocp_data |= RCR_AM | RCR_AAP;
  1656. mc_filter[1] = 0xffffffff;
  1657. mc_filter[0] = 0xffffffff;
  1658. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1659. (netdev->flags & IFF_ALLMULTI)) {
  1660. /* Too many to filter perfectly -- accept all multicasts. */
  1661. ocp_data |= RCR_AM;
  1662. mc_filter[1] = 0xffffffff;
  1663. mc_filter[0] = 0xffffffff;
  1664. } else {
  1665. struct netdev_hw_addr *ha;
  1666. mc_filter[1] = 0;
  1667. mc_filter[0] = 0;
  1668. netdev_for_each_mc_addr(ha, netdev) {
  1669. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1670. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1671. ocp_data |= RCR_AM;
  1672. }
  1673. }
  1674. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1675. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1676. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1677. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1678. netif_wake_queue(netdev);
  1679. }
  1680. static netdev_features_t
  1681. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1682. netdev_features_t features)
  1683. {
  1684. u32 mss = skb_shinfo(skb)->gso_size;
  1685. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1686. int offset = skb_transport_offset(skb);
  1687. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1688. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  1689. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1690. features &= ~NETIF_F_GSO_MASK;
  1691. return features;
  1692. }
  1693. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1694. struct net_device *netdev)
  1695. {
  1696. struct r8152 *tp = netdev_priv(netdev);
  1697. skb_tx_timestamp(skb);
  1698. skb_queue_tail(&tp->tx_queue, skb);
  1699. if (!list_empty(&tp->tx_free)) {
  1700. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1701. set_bit(SCHEDULE_NAPI, &tp->flags);
  1702. schedule_delayed_work(&tp->schedule, 0);
  1703. } else {
  1704. usb_mark_last_busy(tp->udev);
  1705. napi_schedule(&tp->napi);
  1706. }
  1707. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1708. netif_stop_queue(netdev);
  1709. }
  1710. return NETDEV_TX_OK;
  1711. }
  1712. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1713. {
  1714. u32 ocp_data;
  1715. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1716. ocp_data &= ~FMC_FCR_MCU_EN;
  1717. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1718. ocp_data |= FMC_FCR_MCU_EN;
  1719. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1720. }
  1721. static void rtl8152_nic_reset(struct r8152 *tp)
  1722. {
  1723. int i;
  1724. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1725. for (i = 0; i < 1000; i++) {
  1726. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1727. break;
  1728. usleep_range(100, 400);
  1729. }
  1730. }
  1731. static void set_tx_qlen(struct r8152 *tp)
  1732. {
  1733. struct net_device *netdev = tp->netdev;
  1734. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1735. sizeof(struct tx_desc));
  1736. }
  1737. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1738. {
  1739. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1740. }
  1741. static void rtl_set_eee_plus(struct r8152 *tp)
  1742. {
  1743. u32 ocp_data;
  1744. u8 speed;
  1745. speed = rtl8152_get_speed(tp);
  1746. if (speed & _10bps) {
  1747. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1748. ocp_data |= EEEP_CR_EEEP_TX;
  1749. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1750. } else {
  1751. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1752. ocp_data &= ~EEEP_CR_EEEP_TX;
  1753. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1754. }
  1755. }
  1756. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1757. {
  1758. u32 ocp_data;
  1759. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1760. if (enable)
  1761. ocp_data |= RXDY_GATED_EN;
  1762. else
  1763. ocp_data &= ~RXDY_GATED_EN;
  1764. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1765. }
  1766. static int rtl_start_rx(struct r8152 *tp)
  1767. {
  1768. int i, ret = 0;
  1769. INIT_LIST_HEAD(&tp->rx_done);
  1770. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1771. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1772. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1773. if (ret)
  1774. break;
  1775. }
  1776. if (ret && ++i < RTL8152_MAX_RX) {
  1777. struct list_head rx_queue;
  1778. unsigned long flags;
  1779. INIT_LIST_HEAD(&rx_queue);
  1780. do {
  1781. struct rx_agg *agg = &tp->rx_info[i++];
  1782. struct urb *urb = agg->urb;
  1783. urb->actual_length = 0;
  1784. list_add_tail(&agg->list, &rx_queue);
  1785. } while (i < RTL8152_MAX_RX);
  1786. spin_lock_irqsave(&tp->rx_lock, flags);
  1787. list_splice_tail(&rx_queue, &tp->rx_done);
  1788. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1789. }
  1790. return ret;
  1791. }
  1792. static int rtl_stop_rx(struct r8152 *tp)
  1793. {
  1794. int i;
  1795. for (i = 0; i < RTL8152_MAX_RX; i++)
  1796. usb_kill_urb(tp->rx_info[i].urb);
  1797. while (!skb_queue_empty(&tp->rx_queue))
  1798. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1799. return 0;
  1800. }
  1801. static int rtl_enable(struct r8152 *tp)
  1802. {
  1803. u32 ocp_data;
  1804. r8152b_reset_packet_filter(tp);
  1805. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1806. ocp_data |= CR_RE | CR_TE;
  1807. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1808. rxdy_gated_en(tp, false);
  1809. return 0;
  1810. }
  1811. static int rtl8152_enable(struct r8152 *tp)
  1812. {
  1813. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1814. return -ENODEV;
  1815. set_tx_qlen(tp);
  1816. rtl_set_eee_plus(tp);
  1817. return rtl_enable(tp);
  1818. }
  1819. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1820. {
  1821. u32 ocp_data = tp->coalesce / 8;
  1822. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1823. }
  1824. static void r8153_set_rx_early_size(struct r8152 *tp)
  1825. {
  1826. u32 mtu = tp->netdev->mtu;
  1827. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8;
  1828. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1829. }
  1830. static int rtl8153_enable(struct r8152 *tp)
  1831. {
  1832. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1833. return -ENODEV;
  1834. usb_disable_lpm(tp->udev);
  1835. set_tx_qlen(tp);
  1836. rtl_set_eee_plus(tp);
  1837. r8153_set_rx_early_timeout(tp);
  1838. r8153_set_rx_early_size(tp);
  1839. return rtl_enable(tp);
  1840. }
  1841. static void rtl_disable(struct r8152 *tp)
  1842. {
  1843. u32 ocp_data;
  1844. int i;
  1845. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1846. rtl_drop_queued_tx(tp);
  1847. return;
  1848. }
  1849. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1850. ocp_data &= ~RCR_ACPT_ALL;
  1851. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1852. rtl_drop_queued_tx(tp);
  1853. for (i = 0; i < RTL8152_MAX_TX; i++)
  1854. usb_kill_urb(tp->tx_info[i].urb);
  1855. rxdy_gated_en(tp, true);
  1856. for (i = 0; i < 1000; i++) {
  1857. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1858. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1859. break;
  1860. usleep_range(1000, 2000);
  1861. }
  1862. for (i = 0; i < 1000; i++) {
  1863. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1864. break;
  1865. usleep_range(1000, 2000);
  1866. }
  1867. rtl_stop_rx(tp);
  1868. rtl8152_nic_reset(tp);
  1869. }
  1870. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1871. {
  1872. u32 ocp_data;
  1873. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1874. if (enable)
  1875. ocp_data |= POWER_CUT;
  1876. else
  1877. ocp_data &= ~POWER_CUT;
  1878. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1879. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1880. ocp_data &= ~RESUME_INDICATE;
  1881. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1882. }
  1883. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1884. {
  1885. u32 ocp_data;
  1886. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1887. if (enable)
  1888. ocp_data |= CPCR_RX_VLAN;
  1889. else
  1890. ocp_data &= ~CPCR_RX_VLAN;
  1891. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1892. }
  1893. static int rtl8152_set_features(struct net_device *dev,
  1894. netdev_features_t features)
  1895. {
  1896. netdev_features_t changed = features ^ dev->features;
  1897. struct r8152 *tp = netdev_priv(dev);
  1898. int ret;
  1899. ret = usb_autopm_get_interface(tp->intf);
  1900. if (ret < 0)
  1901. goto out;
  1902. mutex_lock(&tp->control);
  1903. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1904. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1905. rtl_rx_vlan_en(tp, true);
  1906. else
  1907. rtl_rx_vlan_en(tp, false);
  1908. }
  1909. mutex_unlock(&tp->control);
  1910. usb_autopm_put_interface(tp->intf);
  1911. out:
  1912. return ret;
  1913. }
  1914. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1915. static u32 __rtl_get_wol(struct r8152 *tp)
  1916. {
  1917. u32 ocp_data;
  1918. u32 wolopts = 0;
  1919. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1920. if (ocp_data & LINK_ON_WAKE_EN)
  1921. wolopts |= WAKE_PHY;
  1922. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1923. if (ocp_data & UWF_EN)
  1924. wolopts |= WAKE_UCAST;
  1925. if (ocp_data & BWF_EN)
  1926. wolopts |= WAKE_BCAST;
  1927. if (ocp_data & MWF_EN)
  1928. wolopts |= WAKE_MCAST;
  1929. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1930. if (ocp_data & MAGIC_EN)
  1931. wolopts |= WAKE_MAGIC;
  1932. return wolopts;
  1933. }
  1934. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1935. {
  1936. u32 ocp_data;
  1937. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1938. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1939. ocp_data &= ~LINK_ON_WAKE_EN;
  1940. if (wolopts & WAKE_PHY)
  1941. ocp_data |= LINK_ON_WAKE_EN;
  1942. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1943. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1944. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
  1945. if (wolopts & WAKE_UCAST)
  1946. ocp_data |= UWF_EN;
  1947. if (wolopts & WAKE_BCAST)
  1948. ocp_data |= BWF_EN;
  1949. if (wolopts & WAKE_MCAST)
  1950. ocp_data |= MWF_EN;
  1951. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1952. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1953. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1954. ocp_data &= ~MAGIC_EN;
  1955. if (wolopts & WAKE_MAGIC)
  1956. ocp_data |= MAGIC_EN;
  1957. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1958. if (wolopts & WAKE_ANY)
  1959. device_set_wakeup_enable(&tp->udev->dev, true);
  1960. else
  1961. device_set_wakeup_enable(&tp->udev->dev, false);
  1962. }
  1963. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  1964. {
  1965. u8 u1u2[8];
  1966. if (enable)
  1967. memset(u1u2, 0xff, sizeof(u1u2));
  1968. else
  1969. memset(u1u2, 0x00, sizeof(u1u2));
  1970. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  1971. }
  1972. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  1973. {
  1974. u32 ocp_data;
  1975. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  1976. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  1977. ocp_data |= U2P3_ENABLE;
  1978. else
  1979. ocp_data &= ~U2P3_ENABLE;
  1980. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  1981. }
  1982. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  1983. {
  1984. u32 ocp_data;
  1985. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  1986. if (enable)
  1987. ocp_data |= PWR_EN | PHASE2_EN;
  1988. else
  1989. ocp_data &= ~(PWR_EN | PHASE2_EN);
  1990. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  1991. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1992. ocp_data &= ~PCUT_STATUS;
  1993. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  1994. }
  1995. static bool rtl_can_wakeup(struct r8152 *tp)
  1996. {
  1997. struct usb_device *udev = tp->udev;
  1998. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  1999. }
  2000. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  2001. {
  2002. if (enable) {
  2003. u32 ocp_data;
  2004. __rtl_set_wol(tp, WAKE_ANY);
  2005. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2006. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2007. ocp_data |= LINK_OFF_WAKE_EN;
  2008. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2009. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2010. } else {
  2011. u32 ocp_data;
  2012. __rtl_set_wol(tp, tp->saved_wolopts);
  2013. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2014. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2015. ocp_data &= ~LINK_OFF_WAKE_EN;
  2016. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2017. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2018. }
  2019. }
  2020. static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
  2021. {
  2022. rtl_runtime_suspend_enable(tp, enable);
  2023. if (enable) {
  2024. r8153_u1u2en(tp, false);
  2025. r8153_u2p3en(tp, false);
  2026. } else {
  2027. r8153_u2p3en(tp, true);
  2028. r8153_u1u2en(tp, true);
  2029. }
  2030. }
  2031. static void r8153_teredo_off(struct r8152 *tp)
  2032. {
  2033. u32 ocp_data;
  2034. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2035. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  2036. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2037. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  2038. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  2039. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  2040. }
  2041. static void rtl_reset_bmu(struct r8152 *tp)
  2042. {
  2043. u32 ocp_data;
  2044. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
  2045. ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
  2046. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2047. ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
  2048. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2049. }
  2050. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  2051. {
  2052. if (enable) {
  2053. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  2054. LINKENA | DIS_SDSAVE);
  2055. } else {
  2056. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  2057. DIS_SDSAVE);
  2058. msleep(20);
  2059. }
  2060. }
  2061. static void rtl8152_disable(struct r8152 *tp)
  2062. {
  2063. r8152_aldps_en(tp, false);
  2064. rtl_disable(tp);
  2065. r8152_aldps_en(tp, true);
  2066. }
  2067. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  2068. {
  2069. u16 data;
  2070. data = r8152_mdio_read(tp, MII_BMCR);
  2071. if (data & BMCR_PDOWN) {
  2072. data &= ~BMCR_PDOWN;
  2073. r8152_mdio_write(tp, MII_BMCR, data);
  2074. }
  2075. set_bit(PHY_RESET, &tp->flags);
  2076. }
  2077. static void r8152b_exit_oob(struct r8152 *tp)
  2078. {
  2079. u32 ocp_data;
  2080. int i;
  2081. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2082. ocp_data &= ~RCR_ACPT_ALL;
  2083. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2084. rxdy_gated_en(tp, true);
  2085. r8153_teredo_off(tp);
  2086. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2087. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2088. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2089. ocp_data &= ~NOW_IS_OOB;
  2090. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2091. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2092. ocp_data &= ~MCU_BORW_EN;
  2093. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2094. for (i = 0; i < 1000; i++) {
  2095. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2096. if (ocp_data & LINK_LIST_READY)
  2097. break;
  2098. usleep_range(1000, 2000);
  2099. }
  2100. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2101. ocp_data |= RE_INIT_LL;
  2102. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2103. for (i = 0; i < 1000; i++) {
  2104. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2105. if (ocp_data & LINK_LIST_READY)
  2106. break;
  2107. usleep_range(1000, 2000);
  2108. }
  2109. rtl8152_nic_reset(tp);
  2110. /* rx share fifo credit full threshold */
  2111. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2112. if (tp->udev->speed == USB_SPEED_FULL ||
  2113. tp->udev->speed == USB_SPEED_LOW) {
  2114. /* rx share fifo credit near full threshold */
  2115. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2116. RXFIFO_THR2_FULL);
  2117. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2118. RXFIFO_THR3_FULL);
  2119. } else {
  2120. /* rx share fifo credit near full threshold */
  2121. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2122. RXFIFO_THR2_HIGH);
  2123. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2124. RXFIFO_THR3_HIGH);
  2125. }
  2126. /* TX share fifo free credit full threshold */
  2127. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2128. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2129. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2130. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2131. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2132. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2133. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2134. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2135. ocp_data |= TCR0_AUTO_FIFO;
  2136. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2137. }
  2138. static void r8152b_enter_oob(struct r8152 *tp)
  2139. {
  2140. u32 ocp_data;
  2141. int i;
  2142. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2143. ocp_data &= ~NOW_IS_OOB;
  2144. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2145. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2146. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2147. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2148. rtl_disable(tp);
  2149. for (i = 0; i < 1000; i++) {
  2150. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2151. if (ocp_data & LINK_LIST_READY)
  2152. break;
  2153. usleep_range(1000, 2000);
  2154. }
  2155. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2156. ocp_data |= RE_INIT_LL;
  2157. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2158. for (i = 0; i < 1000; i++) {
  2159. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2160. if (ocp_data & LINK_LIST_READY)
  2161. break;
  2162. usleep_range(1000, 2000);
  2163. }
  2164. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2165. rtl_rx_vlan_en(tp, true);
  2166. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2167. ocp_data |= ALDPS_PROXY_MODE;
  2168. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2169. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2170. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2171. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2172. rxdy_gated_en(tp, false);
  2173. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2174. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2175. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2176. }
  2177. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2178. {
  2179. u32 ocp_data;
  2180. u16 data;
  2181. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  2182. tp->version == RTL_VER_05)
  2183. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2184. data = r8152_mdio_read(tp, MII_BMCR);
  2185. if (data & BMCR_PDOWN) {
  2186. data &= ~BMCR_PDOWN;
  2187. r8152_mdio_write(tp, MII_BMCR, data);
  2188. }
  2189. if (tp->version == RTL_VER_03) {
  2190. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2191. data &= ~CTAP_SHORT_EN;
  2192. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2193. }
  2194. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2195. data |= EEE_CLKDIV_EN;
  2196. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2197. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2198. data |= EN_10M_BGOFF;
  2199. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2200. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2201. data |= EN_10M_PLLOFF;
  2202. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2203. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2204. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2205. ocp_data |= PFM_PWM_SWITCH;
  2206. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2207. /* Enable LPF corner auto tune */
  2208. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2209. /* Adjust 10M Amplitude */
  2210. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2211. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2212. set_bit(PHY_RESET, &tp->flags);
  2213. }
  2214. static void r8153_first_init(struct r8152 *tp)
  2215. {
  2216. u32 ocp_data;
  2217. int i;
  2218. rxdy_gated_en(tp, true);
  2219. r8153_teredo_off(tp);
  2220. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2221. ocp_data &= ~RCR_ACPT_ALL;
  2222. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2223. rtl8152_nic_reset(tp);
  2224. rtl_reset_bmu(tp);
  2225. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2226. ocp_data &= ~NOW_IS_OOB;
  2227. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2228. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2229. ocp_data &= ~MCU_BORW_EN;
  2230. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2231. for (i = 0; i < 1000; i++) {
  2232. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2233. if (ocp_data & LINK_LIST_READY)
  2234. break;
  2235. usleep_range(1000, 2000);
  2236. }
  2237. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2238. ocp_data |= RE_INIT_LL;
  2239. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2240. for (i = 0; i < 1000; i++) {
  2241. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2242. if (ocp_data & LINK_LIST_READY)
  2243. break;
  2244. usleep_range(1000, 2000);
  2245. }
  2246. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2247. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2248. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2249. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2250. ocp_data |= TCR0_AUTO_FIFO;
  2251. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2252. rtl8152_nic_reset(tp);
  2253. /* rx share fifo credit full threshold */
  2254. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2255. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2256. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2257. /* TX share fifo free credit full threshold */
  2258. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2259. /* rx aggregation */
  2260. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2261. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2262. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2263. }
  2264. static void r8153_enter_oob(struct r8152 *tp)
  2265. {
  2266. u32 ocp_data;
  2267. int i;
  2268. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2269. ocp_data &= ~NOW_IS_OOB;
  2270. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2271. rtl_disable(tp);
  2272. rtl_reset_bmu(tp);
  2273. for (i = 0; i < 1000; i++) {
  2274. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2275. if (ocp_data & LINK_LIST_READY)
  2276. break;
  2277. usleep_range(1000, 2000);
  2278. }
  2279. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2280. ocp_data |= RE_INIT_LL;
  2281. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2282. for (i = 0; i < 1000; i++) {
  2283. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2284. if (ocp_data & LINK_LIST_READY)
  2285. break;
  2286. usleep_range(1000, 2000);
  2287. }
  2288. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2289. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2290. ocp_data &= ~TEREDO_WAKE_MASK;
  2291. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2292. rtl_rx_vlan_en(tp, true);
  2293. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2294. ocp_data |= ALDPS_PROXY_MODE;
  2295. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2296. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2297. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2298. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2299. rxdy_gated_en(tp, false);
  2300. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2301. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2302. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2303. }
  2304. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  2305. {
  2306. u16 data;
  2307. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2308. if (enable) {
  2309. data |= EN_ALDPS;
  2310. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2311. } else {
  2312. data &= ~EN_ALDPS;
  2313. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2314. msleep(20);
  2315. }
  2316. }
  2317. static void rtl8153_disable(struct r8152 *tp)
  2318. {
  2319. r8153_aldps_en(tp, false);
  2320. rtl_disable(tp);
  2321. rtl_reset_bmu(tp);
  2322. r8153_aldps_en(tp, true);
  2323. usb_enable_lpm(tp->udev);
  2324. }
  2325. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2326. {
  2327. u16 bmcr, anar, gbcr;
  2328. int ret = 0;
  2329. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2330. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2331. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2332. if (tp->mii.supports_gmii) {
  2333. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2334. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2335. } else {
  2336. gbcr = 0;
  2337. }
  2338. if (autoneg == AUTONEG_DISABLE) {
  2339. if (speed == SPEED_10) {
  2340. bmcr = 0;
  2341. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2342. } else if (speed == SPEED_100) {
  2343. bmcr = BMCR_SPEED100;
  2344. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2345. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2346. bmcr = BMCR_SPEED1000;
  2347. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2348. } else {
  2349. ret = -EINVAL;
  2350. goto out;
  2351. }
  2352. if (duplex == DUPLEX_FULL)
  2353. bmcr |= BMCR_FULLDPLX;
  2354. } else {
  2355. if (speed == SPEED_10) {
  2356. if (duplex == DUPLEX_FULL)
  2357. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2358. else
  2359. anar |= ADVERTISE_10HALF;
  2360. } else if (speed == SPEED_100) {
  2361. if (duplex == DUPLEX_FULL) {
  2362. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2363. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2364. } else {
  2365. anar |= ADVERTISE_10HALF;
  2366. anar |= ADVERTISE_100HALF;
  2367. }
  2368. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2369. if (duplex == DUPLEX_FULL) {
  2370. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2371. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2372. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2373. } else {
  2374. anar |= ADVERTISE_10HALF;
  2375. anar |= ADVERTISE_100HALF;
  2376. gbcr |= ADVERTISE_1000HALF;
  2377. }
  2378. } else {
  2379. ret = -EINVAL;
  2380. goto out;
  2381. }
  2382. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2383. }
  2384. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  2385. bmcr |= BMCR_RESET;
  2386. if (tp->mii.supports_gmii)
  2387. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2388. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2389. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2390. if (bmcr & BMCR_RESET) {
  2391. int i;
  2392. for (i = 0; i < 50; i++) {
  2393. msleep(20);
  2394. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2395. break;
  2396. }
  2397. }
  2398. out:
  2399. return ret;
  2400. }
  2401. static void rtl8152_up(struct r8152 *tp)
  2402. {
  2403. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2404. return;
  2405. r8152_aldps_en(tp, false);
  2406. r8152b_exit_oob(tp);
  2407. r8152_aldps_en(tp, true);
  2408. }
  2409. static void rtl8152_down(struct r8152 *tp)
  2410. {
  2411. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2412. rtl_drop_queued_tx(tp);
  2413. return;
  2414. }
  2415. r8152_power_cut_en(tp, false);
  2416. r8152_aldps_en(tp, false);
  2417. r8152b_enter_oob(tp);
  2418. r8152_aldps_en(tp, true);
  2419. }
  2420. static void rtl8153_up(struct r8152 *tp)
  2421. {
  2422. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2423. return;
  2424. r8153_u1u2en(tp, false);
  2425. r8153_aldps_en(tp, false);
  2426. r8153_first_init(tp);
  2427. r8153_aldps_en(tp, true);
  2428. r8153_u2p3en(tp, true);
  2429. r8153_u1u2en(tp, true);
  2430. usb_enable_lpm(tp->udev);
  2431. }
  2432. static void rtl8153_down(struct r8152 *tp)
  2433. {
  2434. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2435. rtl_drop_queued_tx(tp);
  2436. return;
  2437. }
  2438. r8153_u1u2en(tp, false);
  2439. r8153_u2p3en(tp, false);
  2440. r8153_power_cut_en(tp, false);
  2441. r8153_aldps_en(tp, false);
  2442. r8153_enter_oob(tp);
  2443. r8153_aldps_en(tp, true);
  2444. }
  2445. static bool rtl8152_in_nway(struct r8152 *tp)
  2446. {
  2447. u16 nway_state;
  2448. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  2449. tp->ocp_base = 0x2000;
  2450. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  2451. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  2452. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  2453. if (nway_state & 0xc000)
  2454. return false;
  2455. else
  2456. return true;
  2457. }
  2458. static bool rtl8153_in_nway(struct r8152 *tp)
  2459. {
  2460. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  2461. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  2462. return false;
  2463. else
  2464. return true;
  2465. }
  2466. static void set_carrier(struct r8152 *tp)
  2467. {
  2468. struct net_device *netdev = tp->netdev;
  2469. u8 speed;
  2470. speed = rtl8152_get_speed(tp);
  2471. if (speed & LINK_STATUS) {
  2472. if (!netif_carrier_ok(netdev)) {
  2473. tp->rtl_ops.enable(tp);
  2474. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2475. napi_disable(&tp->napi);
  2476. netif_carrier_on(netdev);
  2477. rtl_start_rx(tp);
  2478. napi_enable(&tp->napi);
  2479. }
  2480. } else {
  2481. if (netif_carrier_ok(netdev)) {
  2482. netif_carrier_off(netdev);
  2483. napi_disable(&tp->napi);
  2484. tp->rtl_ops.disable(tp);
  2485. napi_enable(&tp->napi);
  2486. }
  2487. }
  2488. }
  2489. static void rtl_work_func_t(struct work_struct *work)
  2490. {
  2491. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2492. /* If the device is unplugged or !netif_running(), the workqueue
  2493. * doesn't need to wake the device, and could return directly.
  2494. */
  2495. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2496. return;
  2497. if (usb_autopm_get_interface(tp->intf) < 0)
  2498. return;
  2499. if (!test_bit(WORK_ENABLE, &tp->flags))
  2500. goto out1;
  2501. if (!mutex_trylock(&tp->control)) {
  2502. schedule_delayed_work(&tp->schedule, 0);
  2503. goto out1;
  2504. }
  2505. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  2506. set_carrier(tp);
  2507. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2508. _rtl8152_set_rx_mode(tp->netdev);
  2509. /* don't schedule napi before linking */
  2510. if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
  2511. netif_carrier_ok(tp->netdev))
  2512. napi_schedule(&tp->napi);
  2513. mutex_unlock(&tp->control);
  2514. out1:
  2515. usb_autopm_put_interface(tp->intf);
  2516. }
  2517. static void rtl_hw_phy_work_func_t(struct work_struct *work)
  2518. {
  2519. struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
  2520. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2521. return;
  2522. if (usb_autopm_get_interface(tp->intf) < 0)
  2523. return;
  2524. mutex_lock(&tp->control);
  2525. tp->rtl_ops.hw_phy_cfg(tp);
  2526. rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
  2527. mutex_unlock(&tp->control);
  2528. usb_autopm_put_interface(tp->intf);
  2529. }
  2530. #ifdef CONFIG_PM_SLEEP
  2531. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  2532. void *data)
  2533. {
  2534. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  2535. switch (action) {
  2536. case PM_HIBERNATION_PREPARE:
  2537. case PM_SUSPEND_PREPARE:
  2538. usb_autopm_get_interface(tp->intf);
  2539. break;
  2540. case PM_POST_HIBERNATION:
  2541. case PM_POST_SUSPEND:
  2542. usb_autopm_put_interface(tp->intf);
  2543. break;
  2544. case PM_POST_RESTORE:
  2545. case PM_RESTORE_PREPARE:
  2546. default:
  2547. break;
  2548. }
  2549. return NOTIFY_DONE;
  2550. }
  2551. #endif
  2552. static int rtl8152_open(struct net_device *netdev)
  2553. {
  2554. struct r8152 *tp = netdev_priv(netdev);
  2555. int res = 0;
  2556. res = alloc_all_mem(tp);
  2557. if (res)
  2558. goto out;
  2559. res = usb_autopm_get_interface(tp->intf);
  2560. if (res < 0) {
  2561. free_all_mem(tp);
  2562. goto out;
  2563. }
  2564. mutex_lock(&tp->control);
  2565. tp->rtl_ops.up(tp);
  2566. netif_carrier_off(netdev);
  2567. netif_start_queue(netdev);
  2568. set_bit(WORK_ENABLE, &tp->flags);
  2569. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2570. if (res) {
  2571. if (res == -ENODEV)
  2572. netif_device_detach(tp->netdev);
  2573. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2574. res);
  2575. free_all_mem(tp);
  2576. } else {
  2577. napi_enable(&tp->napi);
  2578. }
  2579. mutex_unlock(&tp->control);
  2580. usb_autopm_put_interface(tp->intf);
  2581. #ifdef CONFIG_PM_SLEEP
  2582. tp->pm_notifier.notifier_call = rtl_notifier;
  2583. register_pm_notifier(&tp->pm_notifier);
  2584. #endif
  2585. out:
  2586. return res;
  2587. }
  2588. static int rtl8152_close(struct net_device *netdev)
  2589. {
  2590. struct r8152 *tp = netdev_priv(netdev);
  2591. int res = 0;
  2592. #ifdef CONFIG_PM_SLEEP
  2593. unregister_pm_notifier(&tp->pm_notifier);
  2594. #endif
  2595. napi_disable(&tp->napi);
  2596. clear_bit(WORK_ENABLE, &tp->flags);
  2597. usb_kill_urb(tp->intr_urb);
  2598. cancel_delayed_work_sync(&tp->schedule);
  2599. netif_stop_queue(netdev);
  2600. res = usb_autopm_get_interface(tp->intf);
  2601. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2602. rtl_drop_queued_tx(tp);
  2603. rtl_stop_rx(tp);
  2604. } else {
  2605. mutex_lock(&tp->control);
  2606. tp->rtl_ops.down(tp);
  2607. mutex_unlock(&tp->control);
  2608. usb_autopm_put_interface(tp->intf);
  2609. }
  2610. free_all_mem(tp);
  2611. return res;
  2612. }
  2613. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2614. {
  2615. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2616. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2617. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2618. }
  2619. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2620. {
  2621. u16 data;
  2622. r8152_mmd_indirect(tp, dev, reg);
  2623. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2624. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2625. return data;
  2626. }
  2627. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2628. {
  2629. r8152_mmd_indirect(tp, dev, reg);
  2630. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2631. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2632. }
  2633. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2634. {
  2635. u16 config1, config2, config3;
  2636. u32 ocp_data;
  2637. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2638. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2639. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2640. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2641. if (enable) {
  2642. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2643. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2644. config1 |= sd_rise_time(1);
  2645. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2646. config3 |= fast_snr(42);
  2647. } else {
  2648. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2649. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2650. RX_QUIET_EN);
  2651. config1 |= sd_rise_time(7);
  2652. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2653. config3 |= fast_snr(511);
  2654. }
  2655. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2656. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2657. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2658. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2659. }
  2660. static void r8152b_enable_eee(struct r8152 *tp)
  2661. {
  2662. r8152_eee_en(tp, true);
  2663. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2664. }
  2665. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2666. {
  2667. u32 ocp_data;
  2668. u16 config;
  2669. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2670. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2671. if (enable) {
  2672. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2673. config |= EEE10_EN;
  2674. } else {
  2675. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2676. config &= ~EEE10_EN;
  2677. }
  2678. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2679. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2680. }
  2681. static void r8153_enable_eee(struct r8152 *tp)
  2682. {
  2683. r8153_eee_en(tp, true);
  2684. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2685. }
  2686. static void r8152b_enable_fc(struct r8152 *tp)
  2687. {
  2688. u16 anar;
  2689. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2690. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2691. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2692. }
  2693. static void rtl_tally_reset(struct r8152 *tp)
  2694. {
  2695. u32 ocp_data;
  2696. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2697. ocp_data |= TALLY_RESET;
  2698. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2699. }
  2700. static void r8152b_init(struct r8152 *tp)
  2701. {
  2702. u32 ocp_data;
  2703. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2704. return;
  2705. r8152_aldps_en(tp, false);
  2706. if (tp->version == RTL_VER_01) {
  2707. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2708. ocp_data &= ~LED_MODE_MASK;
  2709. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2710. }
  2711. r8152_power_cut_en(tp, false);
  2712. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2713. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2714. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2715. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2716. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2717. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2718. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2719. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2720. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2721. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2722. r8152b_enable_eee(tp);
  2723. r8152_aldps_en(tp, true);
  2724. r8152b_enable_fc(tp);
  2725. rtl_tally_reset(tp);
  2726. /* enable rx aggregation */
  2727. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2728. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2729. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2730. }
  2731. static void r8153_init(struct r8152 *tp)
  2732. {
  2733. u32 ocp_data;
  2734. int i;
  2735. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2736. return;
  2737. r8153_aldps_en(tp, false);
  2738. r8153_u1u2en(tp, false);
  2739. for (i = 0; i < 500; i++) {
  2740. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2741. AUTOLOAD_DONE)
  2742. break;
  2743. msleep(20);
  2744. }
  2745. for (i = 0; i < 500; i++) {
  2746. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2747. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2748. break;
  2749. msleep(20);
  2750. }
  2751. usb_disable_lpm(tp->udev);
  2752. r8153_u2p3en(tp, false);
  2753. if (tp->version == RTL_VER_04) {
  2754. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2755. ocp_data &= ~pwd_dn_scale_mask;
  2756. ocp_data |= pwd_dn_scale(96);
  2757. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2758. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2759. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2760. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2761. } else if (tp->version == RTL_VER_05) {
  2762. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2763. ocp_data &= ~ECM_ALDPS;
  2764. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2765. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2766. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2767. ocp_data &= ~DYNAMIC_BURST;
  2768. else
  2769. ocp_data |= DYNAMIC_BURST;
  2770. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2771. } else if (tp->version == RTL_VER_06) {
  2772. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2773. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2774. ocp_data &= ~DYNAMIC_BURST;
  2775. else
  2776. ocp_data |= DYNAMIC_BURST;
  2777. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2778. }
  2779. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2780. ocp_data |= EP4_FULL_FC;
  2781. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2782. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2783. ocp_data &= ~TIMER11_EN;
  2784. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2785. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2786. ocp_data &= ~LED_MODE_MASK;
  2787. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2788. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2789. if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
  2790. ocp_data |= LPM_TIMER_500MS;
  2791. else
  2792. ocp_data |= LPM_TIMER_500US;
  2793. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2794. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2795. ocp_data &= ~SEN_VAL_MASK;
  2796. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2797. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2798. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2799. r8153_power_cut_en(tp, false);
  2800. r8153_u1u2en(tp, true);
  2801. /* MAC clock speed down */
  2802. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
  2803. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
  2804. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
  2805. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
  2806. r8153_enable_eee(tp);
  2807. r8153_aldps_en(tp, true);
  2808. r8152b_enable_fc(tp);
  2809. rtl_tally_reset(tp);
  2810. r8153_u2p3en(tp, true);
  2811. }
  2812. static int rtl8152_pre_reset(struct usb_interface *intf)
  2813. {
  2814. struct r8152 *tp = usb_get_intfdata(intf);
  2815. struct net_device *netdev;
  2816. if (!tp)
  2817. return 0;
  2818. netdev = tp->netdev;
  2819. if (!netif_running(netdev))
  2820. return 0;
  2821. napi_disable(&tp->napi);
  2822. clear_bit(WORK_ENABLE, &tp->flags);
  2823. usb_kill_urb(tp->intr_urb);
  2824. cancel_delayed_work_sync(&tp->schedule);
  2825. if (netif_carrier_ok(netdev)) {
  2826. netif_stop_queue(netdev);
  2827. mutex_lock(&tp->control);
  2828. tp->rtl_ops.disable(tp);
  2829. mutex_unlock(&tp->control);
  2830. }
  2831. return 0;
  2832. }
  2833. static int rtl8152_post_reset(struct usb_interface *intf)
  2834. {
  2835. struct r8152 *tp = usb_get_intfdata(intf);
  2836. struct net_device *netdev;
  2837. if (!tp)
  2838. return 0;
  2839. netdev = tp->netdev;
  2840. if (!netif_running(netdev))
  2841. return 0;
  2842. set_bit(WORK_ENABLE, &tp->flags);
  2843. if (netif_carrier_ok(netdev)) {
  2844. mutex_lock(&tp->control);
  2845. tp->rtl_ops.enable(tp);
  2846. rtl8152_set_rx_mode(netdev);
  2847. mutex_unlock(&tp->control);
  2848. netif_wake_queue(netdev);
  2849. }
  2850. napi_enable(&tp->napi);
  2851. return 0;
  2852. }
  2853. static bool delay_autosuspend(struct r8152 *tp)
  2854. {
  2855. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  2856. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  2857. /* This means a linking change occurs and the driver doesn't detect it,
  2858. * yet. If the driver has disabled tx/rx and hw is linking on, the
  2859. * device wouldn't wake up by receiving any packet.
  2860. */
  2861. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  2862. return true;
  2863. /* If the linking down is occurred by nway, the device may miss the
  2864. * linking change event. And it wouldn't wake when linking on.
  2865. */
  2866. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  2867. return true;
  2868. else
  2869. return false;
  2870. }
  2871. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2872. {
  2873. struct r8152 *tp = usb_get_intfdata(intf);
  2874. struct net_device *netdev = tp->netdev;
  2875. int ret = 0;
  2876. mutex_lock(&tp->control);
  2877. if (PMSG_IS_AUTO(message)) {
  2878. if (netif_running(netdev) && delay_autosuspend(tp)) {
  2879. ret = -EBUSY;
  2880. goto out1;
  2881. }
  2882. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2883. } else {
  2884. netif_device_detach(netdev);
  2885. }
  2886. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2887. clear_bit(WORK_ENABLE, &tp->flags);
  2888. usb_kill_urb(tp->intr_urb);
  2889. napi_disable(&tp->napi);
  2890. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2891. rtl_stop_rx(tp);
  2892. tp->rtl_ops.autosuspend_en(tp, true);
  2893. } else {
  2894. cancel_delayed_work_sync(&tp->schedule);
  2895. tp->rtl_ops.down(tp);
  2896. }
  2897. napi_enable(&tp->napi);
  2898. }
  2899. out1:
  2900. mutex_unlock(&tp->control);
  2901. return ret;
  2902. }
  2903. static int rtl8152_resume(struct usb_interface *intf)
  2904. {
  2905. struct r8152 *tp = usb_get_intfdata(intf);
  2906. mutex_lock(&tp->control);
  2907. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2908. tp->rtl_ops.init(tp);
  2909. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  2910. netif_device_attach(tp->netdev);
  2911. }
  2912. if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
  2913. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2914. tp->rtl_ops.autosuspend_en(tp, false);
  2915. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2916. napi_disable(&tp->napi);
  2917. set_bit(WORK_ENABLE, &tp->flags);
  2918. if (netif_carrier_ok(tp->netdev))
  2919. rtl_start_rx(tp);
  2920. napi_enable(&tp->napi);
  2921. } else {
  2922. tp->rtl_ops.up(tp);
  2923. netif_carrier_off(tp->netdev);
  2924. set_bit(WORK_ENABLE, &tp->flags);
  2925. }
  2926. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2927. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2928. if (tp->netdev->flags & IFF_UP)
  2929. tp->rtl_ops.autosuspend_en(tp, false);
  2930. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2931. }
  2932. mutex_unlock(&tp->control);
  2933. return 0;
  2934. }
  2935. static int rtl8152_reset_resume(struct usb_interface *intf)
  2936. {
  2937. struct r8152 *tp = usb_get_intfdata(intf);
  2938. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2939. return rtl8152_resume(intf);
  2940. }
  2941. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2942. {
  2943. struct r8152 *tp = netdev_priv(dev);
  2944. if (usb_autopm_get_interface(tp->intf) < 0)
  2945. return;
  2946. if (!rtl_can_wakeup(tp)) {
  2947. wol->supported = 0;
  2948. wol->wolopts = 0;
  2949. } else {
  2950. mutex_lock(&tp->control);
  2951. wol->supported = WAKE_ANY;
  2952. wol->wolopts = __rtl_get_wol(tp);
  2953. mutex_unlock(&tp->control);
  2954. }
  2955. usb_autopm_put_interface(tp->intf);
  2956. }
  2957. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2958. {
  2959. struct r8152 *tp = netdev_priv(dev);
  2960. int ret;
  2961. if (!rtl_can_wakeup(tp))
  2962. return -EOPNOTSUPP;
  2963. ret = usb_autopm_get_interface(tp->intf);
  2964. if (ret < 0)
  2965. goto out_set_wol;
  2966. mutex_lock(&tp->control);
  2967. __rtl_set_wol(tp, wol->wolopts);
  2968. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2969. mutex_unlock(&tp->control);
  2970. usb_autopm_put_interface(tp->intf);
  2971. out_set_wol:
  2972. return ret;
  2973. }
  2974. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2975. {
  2976. struct r8152 *tp = netdev_priv(dev);
  2977. return tp->msg_enable;
  2978. }
  2979. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2980. {
  2981. struct r8152 *tp = netdev_priv(dev);
  2982. tp->msg_enable = value;
  2983. }
  2984. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2985. struct ethtool_drvinfo *info)
  2986. {
  2987. struct r8152 *tp = netdev_priv(netdev);
  2988. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2989. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2990. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2991. }
  2992. static
  2993. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2994. {
  2995. struct r8152 *tp = netdev_priv(netdev);
  2996. int ret;
  2997. if (!tp->mii.mdio_read)
  2998. return -EOPNOTSUPP;
  2999. ret = usb_autopm_get_interface(tp->intf);
  3000. if (ret < 0)
  3001. goto out;
  3002. mutex_lock(&tp->control);
  3003. ret = mii_ethtool_gset(&tp->mii, cmd);
  3004. mutex_unlock(&tp->control);
  3005. usb_autopm_put_interface(tp->intf);
  3006. out:
  3007. return ret;
  3008. }
  3009. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3010. {
  3011. struct r8152 *tp = netdev_priv(dev);
  3012. int ret;
  3013. ret = usb_autopm_get_interface(tp->intf);
  3014. if (ret < 0)
  3015. goto out;
  3016. mutex_lock(&tp->control);
  3017. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  3018. if (!ret) {
  3019. tp->autoneg = cmd->autoneg;
  3020. tp->speed = cmd->speed;
  3021. tp->duplex = cmd->duplex;
  3022. }
  3023. mutex_unlock(&tp->control);
  3024. usb_autopm_put_interface(tp->intf);
  3025. out:
  3026. return ret;
  3027. }
  3028. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  3029. "tx_packets",
  3030. "rx_packets",
  3031. "tx_errors",
  3032. "rx_errors",
  3033. "rx_missed",
  3034. "align_errors",
  3035. "tx_single_collisions",
  3036. "tx_multi_collisions",
  3037. "rx_unicast",
  3038. "rx_broadcast",
  3039. "rx_multicast",
  3040. "tx_aborted",
  3041. "tx_underrun",
  3042. };
  3043. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  3044. {
  3045. switch (sset) {
  3046. case ETH_SS_STATS:
  3047. return ARRAY_SIZE(rtl8152_gstrings);
  3048. default:
  3049. return -EOPNOTSUPP;
  3050. }
  3051. }
  3052. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  3053. struct ethtool_stats *stats, u64 *data)
  3054. {
  3055. struct r8152 *tp = netdev_priv(dev);
  3056. struct tally_counter tally;
  3057. if (usb_autopm_get_interface(tp->intf) < 0)
  3058. return;
  3059. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  3060. usb_autopm_put_interface(tp->intf);
  3061. data[0] = le64_to_cpu(tally.tx_packets);
  3062. data[1] = le64_to_cpu(tally.rx_packets);
  3063. data[2] = le64_to_cpu(tally.tx_errors);
  3064. data[3] = le32_to_cpu(tally.rx_errors);
  3065. data[4] = le16_to_cpu(tally.rx_missed);
  3066. data[5] = le16_to_cpu(tally.align_errors);
  3067. data[6] = le32_to_cpu(tally.tx_one_collision);
  3068. data[7] = le32_to_cpu(tally.tx_multi_collision);
  3069. data[8] = le64_to_cpu(tally.rx_unicast);
  3070. data[9] = le64_to_cpu(tally.rx_broadcast);
  3071. data[10] = le32_to_cpu(tally.rx_multicast);
  3072. data[11] = le16_to_cpu(tally.tx_aborted);
  3073. data[12] = le16_to_cpu(tally.tx_underrun);
  3074. }
  3075. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3076. {
  3077. switch (stringset) {
  3078. case ETH_SS_STATS:
  3079. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  3080. break;
  3081. }
  3082. }
  3083. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3084. {
  3085. u32 ocp_data, lp, adv, supported = 0;
  3086. u16 val;
  3087. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  3088. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3089. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  3090. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3091. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  3092. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3093. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3094. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3095. eee->eee_enabled = !!ocp_data;
  3096. eee->eee_active = !!(supported & adv & lp);
  3097. eee->supported = supported;
  3098. eee->advertised = adv;
  3099. eee->lp_advertised = lp;
  3100. return 0;
  3101. }
  3102. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3103. {
  3104. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3105. r8152_eee_en(tp, eee->eee_enabled);
  3106. if (!eee->eee_enabled)
  3107. val = 0;
  3108. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3109. return 0;
  3110. }
  3111. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3112. {
  3113. u32 ocp_data, lp, adv, supported = 0;
  3114. u16 val;
  3115. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  3116. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3117. val = ocp_reg_read(tp, OCP_EEE_ADV);
  3118. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3119. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  3120. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3121. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3122. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3123. eee->eee_enabled = !!ocp_data;
  3124. eee->eee_active = !!(supported & adv & lp);
  3125. eee->supported = supported;
  3126. eee->advertised = adv;
  3127. eee->lp_advertised = lp;
  3128. return 0;
  3129. }
  3130. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3131. {
  3132. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3133. r8153_eee_en(tp, eee->eee_enabled);
  3134. if (!eee->eee_enabled)
  3135. val = 0;
  3136. ocp_reg_write(tp, OCP_EEE_ADV, val);
  3137. return 0;
  3138. }
  3139. static int
  3140. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  3141. {
  3142. struct r8152 *tp = netdev_priv(net);
  3143. int ret;
  3144. ret = usb_autopm_get_interface(tp->intf);
  3145. if (ret < 0)
  3146. goto out;
  3147. mutex_lock(&tp->control);
  3148. ret = tp->rtl_ops.eee_get(tp, edata);
  3149. mutex_unlock(&tp->control);
  3150. usb_autopm_put_interface(tp->intf);
  3151. out:
  3152. return ret;
  3153. }
  3154. static int
  3155. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  3156. {
  3157. struct r8152 *tp = netdev_priv(net);
  3158. int ret;
  3159. ret = usb_autopm_get_interface(tp->intf);
  3160. if (ret < 0)
  3161. goto out;
  3162. mutex_lock(&tp->control);
  3163. ret = tp->rtl_ops.eee_set(tp, edata);
  3164. if (!ret)
  3165. ret = mii_nway_restart(&tp->mii);
  3166. mutex_unlock(&tp->control);
  3167. usb_autopm_put_interface(tp->intf);
  3168. out:
  3169. return ret;
  3170. }
  3171. static int rtl8152_nway_reset(struct net_device *dev)
  3172. {
  3173. struct r8152 *tp = netdev_priv(dev);
  3174. int ret;
  3175. ret = usb_autopm_get_interface(tp->intf);
  3176. if (ret < 0)
  3177. goto out;
  3178. mutex_lock(&tp->control);
  3179. ret = mii_nway_restart(&tp->mii);
  3180. mutex_unlock(&tp->control);
  3181. usb_autopm_put_interface(tp->intf);
  3182. out:
  3183. return ret;
  3184. }
  3185. static int rtl8152_get_coalesce(struct net_device *netdev,
  3186. struct ethtool_coalesce *coalesce)
  3187. {
  3188. struct r8152 *tp = netdev_priv(netdev);
  3189. switch (tp->version) {
  3190. case RTL_VER_01:
  3191. case RTL_VER_02:
  3192. return -EOPNOTSUPP;
  3193. default:
  3194. break;
  3195. }
  3196. coalesce->rx_coalesce_usecs = tp->coalesce;
  3197. return 0;
  3198. }
  3199. static int rtl8152_set_coalesce(struct net_device *netdev,
  3200. struct ethtool_coalesce *coalesce)
  3201. {
  3202. struct r8152 *tp = netdev_priv(netdev);
  3203. int ret;
  3204. switch (tp->version) {
  3205. case RTL_VER_01:
  3206. case RTL_VER_02:
  3207. return -EOPNOTSUPP;
  3208. default:
  3209. break;
  3210. }
  3211. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  3212. return -EINVAL;
  3213. ret = usb_autopm_get_interface(tp->intf);
  3214. if (ret < 0)
  3215. return ret;
  3216. mutex_lock(&tp->control);
  3217. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  3218. tp->coalesce = coalesce->rx_coalesce_usecs;
  3219. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  3220. r8153_set_rx_early_timeout(tp);
  3221. }
  3222. mutex_unlock(&tp->control);
  3223. usb_autopm_put_interface(tp->intf);
  3224. return ret;
  3225. }
  3226. static struct ethtool_ops ops = {
  3227. .get_drvinfo = rtl8152_get_drvinfo,
  3228. .get_settings = rtl8152_get_settings,
  3229. .set_settings = rtl8152_set_settings,
  3230. .get_link = ethtool_op_get_link,
  3231. .nway_reset = rtl8152_nway_reset,
  3232. .get_msglevel = rtl8152_get_msglevel,
  3233. .set_msglevel = rtl8152_set_msglevel,
  3234. .get_wol = rtl8152_get_wol,
  3235. .set_wol = rtl8152_set_wol,
  3236. .get_strings = rtl8152_get_strings,
  3237. .get_sset_count = rtl8152_get_sset_count,
  3238. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3239. .get_coalesce = rtl8152_get_coalesce,
  3240. .set_coalesce = rtl8152_set_coalesce,
  3241. .get_eee = rtl_ethtool_get_eee,
  3242. .set_eee = rtl_ethtool_set_eee,
  3243. };
  3244. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3245. {
  3246. struct r8152 *tp = netdev_priv(netdev);
  3247. struct mii_ioctl_data *data = if_mii(rq);
  3248. int res;
  3249. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3250. return -ENODEV;
  3251. res = usb_autopm_get_interface(tp->intf);
  3252. if (res < 0)
  3253. goto out;
  3254. switch (cmd) {
  3255. case SIOCGMIIPHY:
  3256. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3257. break;
  3258. case SIOCGMIIREG:
  3259. mutex_lock(&tp->control);
  3260. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3261. mutex_unlock(&tp->control);
  3262. break;
  3263. case SIOCSMIIREG:
  3264. if (!capable(CAP_NET_ADMIN)) {
  3265. res = -EPERM;
  3266. break;
  3267. }
  3268. mutex_lock(&tp->control);
  3269. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3270. mutex_unlock(&tp->control);
  3271. break;
  3272. default:
  3273. res = -EOPNOTSUPP;
  3274. }
  3275. usb_autopm_put_interface(tp->intf);
  3276. out:
  3277. return res;
  3278. }
  3279. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3280. {
  3281. struct r8152 *tp = netdev_priv(dev);
  3282. int ret;
  3283. switch (tp->version) {
  3284. case RTL_VER_01:
  3285. case RTL_VER_02:
  3286. return eth_change_mtu(dev, new_mtu);
  3287. default:
  3288. break;
  3289. }
  3290. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3291. return -EINVAL;
  3292. ret = usb_autopm_get_interface(tp->intf);
  3293. if (ret < 0)
  3294. return ret;
  3295. mutex_lock(&tp->control);
  3296. dev->mtu = new_mtu;
  3297. if (netif_running(dev) && netif_carrier_ok(dev))
  3298. r8153_set_rx_early_size(tp);
  3299. mutex_unlock(&tp->control);
  3300. usb_autopm_put_interface(tp->intf);
  3301. return ret;
  3302. }
  3303. static const struct net_device_ops rtl8152_netdev_ops = {
  3304. .ndo_open = rtl8152_open,
  3305. .ndo_stop = rtl8152_close,
  3306. .ndo_do_ioctl = rtl8152_ioctl,
  3307. .ndo_start_xmit = rtl8152_start_xmit,
  3308. .ndo_tx_timeout = rtl8152_tx_timeout,
  3309. .ndo_set_features = rtl8152_set_features,
  3310. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3311. .ndo_set_mac_address = rtl8152_set_mac_address,
  3312. .ndo_change_mtu = rtl8152_change_mtu,
  3313. .ndo_validate_addr = eth_validate_addr,
  3314. .ndo_features_check = rtl8152_features_check,
  3315. };
  3316. static void r8152b_get_version(struct r8152 *tp)
  3317. {
  3318. u32 ocp_data;
  3319. u16 version;
  3320. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3321. version = (u16)(ocp_data & VERSION_MASK);
  3322. switch (version) {
  3323. case 0x4c00:
  3324. tp->version = RTL_VER_01;
  3325. break;
  3326. case 0x4c10:
  3327. tp->version = RTL_VER_02;
  3328. break;
  3329. case 0x5c00:
  3330. tp->version = RTL_VER_03;
  3331. tp->mii.supports_gmii = 1;
  3332. break;
  3333. case 0x5c10:
  3334. tp->version = RTL_VER_04;
  3335. tp->mii.supports_gmii = 1;
  3336. break;
  3337. case 0x5c20:
  3338. tp->version = RTL_VER_05;
  3339. tp->mii.supports_gmii = 1;
  3340. break;
  3341. case 0x5c30:
  3342. tp->version = RTL_VER_06;
  3343. tp->mii.supports_gmii = 1;
  3344. break;
  3345. default:
  3346. netif_info(tp, probe, tp->netdev,
  3347. "Unknown version 0x%04x\n", version);
  3348. break;
  3349. }
  3350. }
  3351. static void rtl8152_unload(struct r8152 *tp)
  3352. {
  3353. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3354. return;
  3355. if (tp->version != RTL_VER_01)
  3356. r8152_power_cut_en(tp, true);
  3357. }
  3358. static void rtl8153_unload(struct r8152 *tp)
  3359. {
  3360. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3361. return;
  3362. r8153_power_cut_en(tp, false);
  3363. }
  3364. static int rtl_ops_init(struct r8152 *tp)
  3365. {
  3366. struct rtl_ops *ops = &tp->rtl_ops;
  3367. int ret = 0;
  3368. switch (tp->version) {
  3369. case RTL_VER_01:
  3370. case RTL_VER_02:
  3371. ops->init = r8152b_init;
  3372. ops->enable = rtl8152_enable;
  3373. ops->disable = rtl8152_disable;
  3374. ops->up = rtl8152_up;
  3375. ops->down = rtl8152_down;
  3376. ops->unload = rtl8152_unload;
  3377. ops->eee_get = r8152_get_eee;
  3378. ops->eee_set = r8152_set_eee;
  3379. ops->in_nway = rtl8152_in_nway;
  3380. ops->hw_phy_cfg = r8152b_hw_phy_cfg;
  3381. ops->autosuspend_en = rtl_runtime_suspend_enable;
  3382. break;
  3383. case RTL_VER_03:
  3384. case RTL_VER_04:
  3385. case RTL_VER_05:
  3386. case RTL_VER_06:
  3387. ops->init = r8153_init;
  3388. ops->enable = rtl8153_enable;
  3389. ops->disable = rtl8153_disable;
  3390. ops->up = rtl8153_up;
  3391. ops->down = rtl8153_down;
  3392. ops->unload = rtl8153_unload;
  3393. ops->eee_get = r8153_get_eee;
  3394. ops->eee_set = r8153_set_eee;
  3395. ops->in_nway = rtl8153_in_nway;
  3396. ops->hw_phy_cfg = r8153_hw_phy_cfg;
  3397. ops->autosuspend_en = rtl8153_runtime_enable;
  3398. break;
  3399. default:
  3400. ret = -ENODEV;
  3401. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3402. break;
  3403. }
  3404. return ret;
  3405. }
  3406. static int rtl8152_probe(struct usb_interface *intf,
  3407. const struct usb_device_id *id)
  3408. {
  3409. struct usb_device *udev = interface_to_usbdev(intf);
  3410. struct r8152 *tp;
  3411. struct net_device *netdev;
  3412. int ret;
  3413. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3414. usb_driver_set_configuration(udev, 1);
  3415. return -ENODEV;
  3416. }
  3417. usb_reset_device(udev);
  3418. netdev = alloc_etherdev(sizeof(struct r8152));
  3419. if (!netdev) {
  3420. dev_err(&intf->dev, "Out of memory\n");
  3421. return -ENOMEM;
  3422. }
  3423. SET_NETDEV_DEV(netdev, &intf->dev);
  3424. tp = netdev_priv(netdev);
  3425. tp->msg_enable = 0x7FFF;
  3426. tp->udev = udev;
  3427. tp->netdev = netdev;
  3428. tp->intf = intf;
  3429. r8152b_get_version(tp);
  3430. ret = rtl_ops_init(tp);
  3431. if (ret)
  3432. goto out;
  3433. mutex_init(&tp->control);
  3434. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3435. INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
  3436. netdev->netdev_ops = &rtl8152_netdev_ops;
  3437. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3438. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3439. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3440. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3441. NETIF_F_HW_VLAN_CTAG_TX;
  3442. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3443. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3444. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3445. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3446. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3447. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3448. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3449. netdev->ethtool_ops = &ops;
  3450. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3451. tp->mii.dev = netdev;
  3452. tp->mii.mdio_read = read_mii_word;
  3453. tp->mii.mdio_write = write_mii_word;
  3454. tp->mii.phy_id_mask = 0x3f;
  3455. tp->mii.reg_num_mask = 0x1f;
  3456. tp->mii.phy_id = R8152_PHY_ID;
  3457. switch (udev->speed) {
  3458. case USB_SPEED_SUPER:
  3459. case USB_SPEED_SUPER_PLUS:
  3460. tp->coalesce = COALESCE_SUPER;
  3461. break;
  3462. case USB_SPEED_HIGH:
  3463. tp->coalesce = COALESCE_HIGH;
  3464. break;
  3465. default:
  3466. tp->coalesce = COALESCE_SLOW;
  3467. break;
  3468. }
  3469. tp->autoneg = AUTONEG_ENABLE;
  3470. tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
  3471. tp->duplex = DUPLEX_FULL;
  3472. intf->needs_remote_wakeup = 1;
  3473. tp->rtl_ops.init(tp);
  3474. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  3475. set_ethernet_addr(tp);
  3476. usb_set_intfdata(intf, tp);
  3477. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3478. ret = register_netdev(netdev);
  3479. if (ret != 0) {
  3480. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3481. goto out1;
  3482. }
  3483. if (!rtl_can_wakeup(tp))
  3484. __rtl_set_wol(tp, 0);
  3485. tp->saved_wolopts = __rtl_get_wol(tp);
  3486. if (tp->saved_wolopts)
  3487. device_set_wakeup_enable(&udev->dev, true);
  3488. else
  3489. device_set_wakeup_enable(&udev->dev, false);
  3490. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3491. return 0;
  3492. out1:
  3493. netif_napi_del(&tp->napi);
  3494. usb_set_intfdata(intf, NULL);
  3495. out:
  3496. free_netdev(netdev);
  3497. return ret;
  3498. }
  3499. static void rtl8152_disconnect(struct usb_interface *intf)
  3500. {
  3501. struct r8152 *tp = usb_get_intfdata(intf);
  3502. usb_set_intfdata(intf, NULL);
  3503. if (tp) {
  3504. struct usb_device *udev = tp->udev;
  3505. if (udev->state == USB_STATE_NOTATTACHED)
  3506. set_bit(RTL8152_UNPLUG, &tp->flags);
  3507. netif_napi_del(&tp->napi);
  3508. unregister_netdev(tp->netdev);
  3509. cancel_delayed_work_sync(&tp->hw_phy_work);
  3510. tp->rtl_ops.unload(tp);
  3511. free_netdev(tp->netdev);
  3512. }
  3513. }
  3514. #define REALTEK_USB_DEVICE(vend, prod) \
  3515. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3516. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3517. .idVendor = (vend), \
  3518. .idProduct = (prod), \
  3519. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3520. }, \
  3521. { \
  3522. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3523. USB_DEVICE_ID_MATCH_DEVICE, \
  3524. .idVendor = (vend), \
  3525. .idProduct = (prod), \
  3526. .bInterfaceClass = USB_CLASS_COMM, \
  3527. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3528. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3529. /* table of devices that work with this driver */
  3530. static struct usb_device_id rtl8152_table[] = {
  3531. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3532. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3533. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3534. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3535. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3536. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3537. {}
  3538. };
  3539. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3540. static struct usb_driver rtl8152_driver = {
  3541. .name = MODULENAME,
  3542. .id_table = rtl8152_table,
  3543. .probe = rtl8152_probe,
  3544. .disconnect = rtl8152_disconnect,
  3545. .suspend = rtl8152_suspend,
  3546. .resume = rtl8152_resume,
  3547. .reset_resume = rtl8152_reset_resume,
  3548. .pre_reset = rtl8152_pre_reset,
  3549. .post_reset = rtl8152_post_reset,
  3550. .supports_autosuspend = 1,
  3551. .disable_hub_initiated_lpm = 1,
  3552. };
  3553. module_usb_driver(rtl8152_driver);
  3554. MODULE_AUTHOR(DRIVER_AUTHOR);
  3555. MODULE_DESCRIPTION(DRIVER_DESC);
  3556. MODULE_LICENSE("GPL");
  3557. MODULE_VERSION(DRIVER_VERSION);