efx.c 92 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2013 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/pci.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/delay.h>
  15. #include <linux/notifier.h>
  16. #include <linux/ip.h>
  17. #include <linux/tcp.h>
  18. #include <linux/in.h>
  19. #include <linux/ethtool.h>
  20. #include <linux/topology.h>
  21. #include <linux/gfp.h>
  22. #include <linux/aer.h>
  23. #include <linux/interrupt.h>
  24. #include "net_driver.h"
  25. #include "efx.h"
  26. #include "nic.h"
  27. #include "selftest.h"
  28. #include "sriov.h"
  29. #include "mcdi.h"
  30. #include "workarounds.h"
  31. /**************************************************************************
  32. *
  33. * Type name strings
  34. *
  35. **************************************************************************
  36. */
  37. /* Loopback mode names (see LOOPBACK_MODE()) */
  38. const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
  39. const char *const efx_loopback_mode_names[] = {
  40. [LOOPBACK_NONE] = "NONE",
  41. [LOOPBACK_DATA] = "DATAPATH",
  42. [LOOPBACK_GMAC] = "GMAC",
  43. [LOOPBACK_XGMII] = "XGMII",
  44. [LOOPBACK_XGXS] = "XGXS",
  45. [LOOPBACK_XAUI] = "XAUI",
  46. [LOOPBACK_GMII] = "GMII",
  47. [LOOPBACK_SGMII] = "SGMII",
  48. [LOOPBACK_XGBR] = "XGBR",
  49. [LOOPBACK_XFI] = "XFI",
  50. [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
  51. [LOOPBACK_GMII_FAR] = "GMII_FAR",
  52. [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
  53. [LOOPBACK_XFI_FAR] = "XFI_FAR",
  54. [LOOPBACK_GPHY] = "GPHY",
  55. [LOOPBACK_PHYXS] = "PHYXS",
  56. [LOOPBACK_PCS] = "PCS",
  57. [LOOPBACK_PMAPMD] = "PMA/PMD",
  58. [LOOPBACK_XPORT] = "XPORT",
  59. [LOOPBACK_XGMII_WS] = "XGMII_WS",
  60. [LOOPBACK_XAUI_WS] = "XAUI_WS",
  61. [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
  62. [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
  63. [LOOPBACK_GMII_WS] = "GMII_WS",
  64. [LOOPBACK_XFI_WS] = "XFI_WS",
  65. [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
  66. [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
  67. };
  68. const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
  69. const char *const efx_reset_type_names[] = {
  70. [RESET_TYPE_INVISIBLE] = "INVISIBLE",
  71. [RESET_TYPE_ALL] = "ALL",
  72. [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
  73. [RESET_TYPE_WORLD] = "WORLD",
  74. [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
  75. [RESET_TYPE_DATAPATH] = "DATAPATH",
  76. [RESET_TYPE_MC_BIST] = "MC_BIST",
  77. [RESET_TYPE_DISABLE] = "DISABLE",
  78. [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
  79. [RESET_TYPE_INT_ERROR] = "INT_ERROR",
  80. [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
  81. [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
  82. [RESET_TYPE_TX_SKIP] = "TX_SKIP",
  83. [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
  84. [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)",
  85. };
  86. /* Reset workqueue. If any NIC has a hardware failure then a reset will be
  87. * queued onto this work queue. This is not a per-nic work queue, because
  88. * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
  89. */
  90. static struct workqueue_struct *reset_workqueue;
  91. /* How often and how many times to poll for a reset while waiting for a
  92. * BIST that another function started to complete.
  93. */
  94. #define BIST_WAIT_DELAY_MS 100
  95. #define BIST_WAIT_DELAY_COUNT 100
  96. /**************************************************************************
  97. *
  98. * Configurable values
  99. *
  100. *************************************************************************/
  101. /*
  102. * Use separate channels for TX and RX events
  103. *
  104. * Set this to 1 to use separate channels for TX and RX. It allows us
  105. * to control interrupt affinity separately for TX and RX.
  106. *
  107. * This is only used in MSI-X interrupt mode
  108. */
  109. bool efx_separate_tx_channels;
  110. module_param(efx_separate_tx_channels, bool, 0444);
  111. MODULE_PARM_DESC(efx_separate_tx_channels,
  112. "Use separate channels for TX and RX");
  113. /* This is the weight assigned to each of the (per-channel) virtual
  114. * NAPI devices.
  115. */
  116. static int napi_weight = 64;
  117. /* This is the time (in jiffies) between invocations of the hardware
  118. * monitor.
  119. * On Falcon-based NICs, this will:
  120. * - Check the on-board hardware monitor;
  121. * - Poll the link state and reconfigure the hardware as necessary.
  122. * On Siena-based NICs for power systems with EEH support, this will give EEH a
  123. * chance to start.
  124. */
  125. static unsigned int efx_monitor_interval = 1 * HZ;
  126. /* Initial interrupt moderation settings. They can be modified after
  127. * module load with ethtool.
  128. *
  129. * The default for RX should strike a balance between increasing the
  130. * round-trip latency and reducing overhead.
  131. */
  132. static unsigned int rx_irq_mod_usec = 60;
  133. /* Initial interrupt moderation settings. They can be modified after
  134. * module load with ethtool.
  135. *
  136. * This default is chosen to ensure that a 10G link does not go idle
  137. * while a TX queue is stopped after it has become full. A queue is
  138. * restarted when it drops below half full. The time this takes (assuming
  139. * worst case 3 descriptors per packet and 1024 descriptors) is
  140. * 512 / 3 * 1.2 = 205 usec.
  141. */
  142. static unsigned int tx_irq_mod_usec = 150;
  143. /* This is the first interrupt mode to try out of:
  144. * 0 => MSI-X
  145. * 1 => MSI
  146. * 2 => legacy
  147. */
  148. static unsigned int interrupt_mode;
  149. /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
  150. * i.e. the number of CPUs among which we may distribute simultaneous
  151. * interrupt handling.
  152. *
  153. * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
  154. * The default (0) means to assign an interrupt to each core.
  155. */
  156. static unsigned int rss_cpus;
  157. module_param(rss_cpus, uint, 0444);
  158. MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
  159. static bool phy_flash_cfg;
  160. module_param(phy_flash_cfg, bool, 0644);
  161. MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
  162. static unsigned irq_adapt_low_thresh = 8000;
  163. module_param(irq_adapt_low_thresh, uint, 0644);
  164. MODULE_PARM_DESC(irq_adapt_low_thresh,
  165. "Threshold score for reducing IRQ moderation");
  166. static unsigned irq_adapt_high_thresh = 16000;
  167. module_param(irq_adapt_high_thresh, uint, 0644);
  168. MODULE_PARM_DESC(irq_adapt_high_thresh,
  169. "Threshold score for increasing IRQ moderation");
  170. static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  171. NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
  172. NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
  173. NETIF_MSG_TX_ERR | NETIF_MSG_HW);
  174. module_param(debug, uint, 0);
  175. MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
  176. /**************************************************************************
  177. *
  178. * Utility functions and prototypes
  179. *
  180. *************************************************************************/
  181. static int efx_soft_enable_interrupts(struct efx_nic *efx);
  182. static void efx_soft_disable_interrupts(struct efx_nic *efx);
  183. static void efx_remove_channel(struct efx_channel *channel);
  184. static void efx_remove_channels(struct efx_nic *efx);
  185. static const struct efx_channel_type efx_default_channel_type;
  186. static void efx_remove_port(struct efx_nic *efx);
  187. static void efx_init_napi_channel(struct efx_channel *channel);
  188. static void efx_fini_napi(struct efx_nic *efx);
  189. static void efx_fini_napi_channel(struct efx_channel *channel);
  190. static void efx_fini_struct(struct efx_nic *efx);
  191. static void efx_start_all(struct efx_nic *efx);
  192. static void efx_stop_all(struct efx_nic *efx);
  193. #define EFX_ASSERT_RESET_SERIALISED(efx) \
  194. do { \
  195. if ((efx->state == STATE_READY) || \
  196. (efx->state == STATE_RECOVERY) || \
  197. (efx->state == STATE_DISABLED)) \
  198. ASSERT_RTNL(); \
  199. } while (0)
  200. static int efx_check_disabled(struct efx_nic *efx)
  201. {
  202. if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
  203. netif_err(efx, drv, efx->net_dev,
  204. "device is disabled due to earlier errors\n");
  205. return -EIO;
  206. }
  207. return 0;
  208. }
  209. /**************************************************************************
  210. *
  211. * Event queue processing
  212. *
  213. *************************************************************************/
  214. /* Process channel's event queue
  215. *
  216. * This function is responsible for processing the event queue of a
  217. * single channel. The caller must guarantee that this function will
  218. * never be concurrently called more than once on the same channel,
  219. * though different channels may be being processed concurrently.
  220. */
  221. static int efx_process_channel(struct efx_channel *channel, int budget)
  222. {
  223. struct efx_tx_queue *tx_queue;
  224. int spent;
  225. if (unlikely(!channel->enabled))
  226. return 0;
  227. efx_for_each_channel_tx_queue(tx_queue, channel) {
  228. tx_queue->pkts_compl = 0;
  229. tx_queue->bytes_compl = 0;
  230. }
  231. spent = efx_nic_process_eventq(channel, budget);
  232. if (spent && efx_channel_has_rx_queue(channel)) {
  233. struct efx_rx_queue *rx_queue =
  234. efx_channel_get_rx_queue(channel);
  235. efx_rx_flush_packet(channel);
  236. efx_fast_push_rx_descriptors(rx_queue, true);
  237. }
  238. /* Update BQL */
  239. efx_for_each_channel_tx_queue(tx_queue, channel) {
  240. if (tx_queue->bytes_compl) {
  241. netdev_tx_completed_queue(tx_queue->core_txq,
  242. tx_queue->pkts_compl, tx_queue->bytes_compl);
  243. }
  244. }
  245. return spent;
  246. }
  247. /* NAPI poll handler
  248. *
  249. * NAPI guarantees serialisation of polls of the same device, which
  250. * provides the guarantee required by efx_process_channel().
  251. */
  252. static int efx_poll(struct napi_struct *napi, int budget)
  253. {
  254. struct efx_channel *channel =
  255. container_of(napi, struct efx_channel, napi_str);
  256. struct efx_nic *efx = channel->efx;
  257. int spent;
  258. if (!efx_channel_lock_napi(channel))
  259. return budget;
  260. netif_vdbg(efx, intr, efx->net_dev,
  261. "channel %d NAPI poll executing on CPU %d\n",
  262. channel->channel, raw_smp_processor_id());
  263. spent = efx_process_channel(channel, budget);
  264. if (spent < budget) {
  265. if (efx_channel_has_rx_queue(channel) &&
  266. efx->irq_rx_adaptive &&
  267. unlikely(++channel->irq_count == 1000)) {
  268. if (unlikely(channel->irq_mod_score <
  269. irq_adapt_low_thresh)) {
  270. if (channel->irq_moderation > 1) {
  271. channel->irq_moderation -= 1;
  272. efx->type->push_irq_moderation(channel);
  273. }
  274. } else if (unlikely(channel->irq_mod_score >
  275. irq_adapt_high_thresh)) {
  276. if (channel->irq_moderation <
  277. efx->irq_rx_moderation) {
  278. channel->irq_moderation += 1;
  279. efx->type->push_irq_moderation(channel);
  280. }
  281. }
  282. channel->irq_count = 0;
  283. channel->irq_mod_score = 0;
  284. }
  285. efx_filter_rfs_expire(channel);
  286. /* There is no race here; although napi_disable() will
  287. * only wait for napi_complete(), this isn't a problem
  288. * since efx_nic_eventq_read_ack() will have no effect if
  289. * interrupts have already been disabled.
  290. */
  291. napi_complete(napi);
  292. efx_nic_eventq_read_ack(channel);
  293. }
  294. efx_channel_unlock_napi(channel);
  295. return spent;
  296. }
  297. /* Create event queue
  298. * Event queue memory allocations are done only once. If the channel
  299. * is reset, the memory buffer will be reused; this guards against
  300. * errors during channel reset and also simplifies interrupt handling.
  301. */
  302. static int efx_probe_eventq(struct efx_channel *channel)
  303. {
  304. struct efx_nic *efx = channel->efx;
  305. unsigned long entries;
  306. netif_dbg(efx, probe, efx->net_dev,
  307. "chan %d create event queue\n", channel->channel);
  308. /* Build an event queue with room for one event per tx and rx buffer,
  309. * plus some extra for link state events and MCDI completions. */
  310. entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
  311. EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
  312. channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
  313. return efx_nic_probe_eventq(channel);
  314. }
  315. /* Prepare channel's event queue */
  316. static int efx_init_eventq(struct efx_channel *channel)
  317. {
  318. struct efx_nic *efx = channel->efx;
  319. int rc;
  320. EFX_WARN_ON_PARANOID(channel->eventq_init);
  321. netif_dbg(efx, drv, efx->net_dev,
  322. "chan %d init event queue\n", channel->channel);
  323. rc = efx_nic_init_eventq(channel);
  324. if (rc == 0) {
  325. efx->type->push_irq_moderation(channel);
  326. channel->eventq_read_ptr = 0;
  327. channel->eventq_init = true;
  328. }
  329. return rc;
  330. }
  331. /* Enable event queue processing and NAPI */
  332. void efx_start_eventq(struct efx_channel *channel)
  333. {
  334. netif_dbg(channel->efx, ifup, channel->efx->net_dev,
  335. "chan %d start event queue\n", channel->channel);
  336. /* Make sure the NAPI handler sees the enabled flag set */
  337. channel->enabled = true;
  338. smp_wmb();
  339. efx_channel_enable(channel);
  340. napi_enable(&channel->napi_str);
  341. efx_nic_eventq_read_ack(channel);
  342. }
  343. /* Disable event queue processing and NAPI */
  344. void efx_stop_eventq(struct efx_channel *channel)
  345. {
  346. if (!channel->enabled)
  347. return;
  348. napi_disable(&channel->napi_str);
  349. while (!efx_channel_disable(channel))
  350. usleep_range(1000, 20000);
  351. channel->enabled = false;
  352. }
  353. static void efx_fini_eventq(struct efx_channel *channel)
  354. {
  355. if (!channel->eventq_init)
  356. return;
  357. netif_dbg(channel->efx, drv, channel->efx->net_dev,
  358. "chan %d fini event queue\n", channel->channel);
  359. efx_nic_fini_eventq(channel);
  360. channel->eventq_init = false;
  361. }
  362. static void efx_remove_eventq(struct efx_channel *channel)
  363. {
  364. netif_dbg(channel->efx, drv, channel->efx->net_dev,
  365. "chan %d remove event queue\n", channel->channel);
  366. efx_nic_remove_eventq(channel);
  367. }
  368. /**************************************************************************
  369. *
  370. * Channel handling
  371. *
  372. *************************************************************************/
  373. /* Allocate and initialise a channel structure. */
  374. static struct efx_channel *
  375. efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
  376. {
  377. struct efx_channel *channel;
  378. struct efx_rx_queue *rx_queue;
  379. struct efx_tx_queue *tx_queue;
  380. int j;
  381. channel = kzalloc(sizeof(*channel), GFP_KERNEL);
  382. if (!channel)
  383. return NULL;
  384. channel->efx = efx;
  385. channel->channel = i;
  386. channel->type = &efx_default_channel_type;
  387. for (j = 0; j < EFX_TXQ_TYPES; j++) {
  388. tx_queue = &channel->tx_queue[j];
  389. tx_queue->efx = efx;
  390. tx_queue->queue = i * EFX_TXQ_TYPES + j;
  391. tx_queue->channel = channel;
  392. }
  393. rx_queue = &channel->rx_queue;
  394. rx_queue->efx = efx;
  395. setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
  396. (unsigned long)rx_queue);
  397. return channel;
  398. }
  399. /* Allocate and initialise a channel structure, copying parameters
  400. * (but not resources) from an old channel structure.
  401. */
  402. static struct efx_channel *
  403. efx_copy_channel(const struct efx_channel *old_channel)
  404. {
  405. struct efx_channel *channel;
  406. struct efx_rx_queue *rx_queue;
  407. struct efx_tx_queue *tx_queue;
  408. int j;
  409. channel = kmalloc(sizeof(*channel), GFP_KERNEL);
  410. if (!channel)
  411. return NULL;
  412. *channel = *old_channel;
  413. channel->napi_dev = NULL;
  414. memset(&channel->eventq, 0, sizeof(channel->eventq));
  415. for (j = 0; j < EFX_TXQ_TYPES; j++) {
  416. tx_queue = &channel->tx_queue[j];
  417. if (tx_queue->channel)
  418. tx_queue->channel = channel;
  419. tx_queue->buffer = NULL;
  420. memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
  421. }
  422. rx_queue = &channel->rx_queue;
  423. rx_queue->buffer = NULL;
  424. memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
  425. setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
  426. (unsigned long)rx_queue);
  427. return channel;
  428. }
  429. static int efx_probe_channel(struct efx_channel *channel)
  430. {
  431. struct efx_tx_queue *tx_queue;
  432. struct efx_rx_queue *rx_queue;
  433. int rc;
  434. netif_dbg(channel->efx, probe, channel->efx->net_dev,
  435. "creating channel %d\n", channel->channel);
  436. rc = channel->type->pre_probe(channel);
  437. if (rc)
  438. goto fail;
  439. rc = efx_probe_eventq(channel);
  440. if (rc)
  441. goto fail;
  442. efx_for_each_channel_tx_queue(tx_queue, channel) {
  443. rc = efx_probe_tx_queue(tx_queue);
  444. if (rc)
  445. goto fail;
  446. }
  447. efx_for_each_channel_rx_queue(rx_queue, channel) {
  448. rc = efx_probe_rx_queue(rx_queue);
  449. if (rc)
  450. goto fail;
  451. }
  452. return 0;
  453. fail:
  454. efx_remove_channel(channel);
  455. return rc;
  456. }
  457. static void
  458. efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
  459. {
  460. struct efx_nic *efx = channel->efx;
  461. const char *type;
  462. int number;
  463. number = channel->channel;
  464. if (efx->tx_channel_offset == 0) {
  465. type = "";
  466. } else if (channel->channel < efx->tx_channel_offset) {
  467. type = "-rx";
  468. } else {
  469. type = "-tx";
  470. number -= efx->tx_channel_offset;
  471. }
  472. snprintf(buf, len, "%s%s-%d", efx->name, type, number);
  473. }
  474. static void efx_set_channel_names(struct efx_nic *efx)
  475. {
  476. struct efx_channel *channel;
  477. efx_for_each_channel(channel, efx)
  478. channel->type->get_name(channel,
  479. efx->msi_context[channel->channel].name,
  480. sizeof(efx->msi_context[0].name));
  481. }
  482. static int efx_probe_channels(struct efx_nic *efx)
  483. {
  484. struct efx_channel *channel;
  485. int rc;
  486. /* Restart special buffer allocation */
  487. efx->next_buffer_table = 0;
  488. /* Probe channels in reverse, so that any 'extra' channels
  489. * use the start of the buffer table. This allows the traffic
  490. * channels to be resized without moving them or wasting the
  491. * entries before them.
  492. */
  493. efx_for_each_channel_rev(channel, efx) {
  494. rc = efx_probe_channel(channel);
  495. if (rc) {
  496. netif_err(efx, probe, efx->net_dev,
  497. "failed to create channel %d\n",
  498. channel->channel);
  499. goto fail;
  500. }
  501. }
  502. efx_set_channel_names(efx);
  503. return 0;
  504. fail:
  505. efx_remove_channels(efx);
  506. return rc;
  507. }
  508. /* Channels are shutdown and reinitialised whilst the NIC is running
  509. * to propagate configuration changes (mtu, checksum offload), or
  510. * to clear hardware error conditions
  511. */
  512. static void efx_start_datapath(struct efx_nic *efx)
  513. {
  514. netdev_features_t old_features = efx->net_dev->features;
  515. bool old_rx_scatter = efx->rx_scatter;
  516. struct efx_tx_queue *tx_queue;
  517. struct efx_rx_queue *rx_queue;
  518. struct efx_channel *channel;
  519. size_t rx_buf_len;
  520. /* Calculate the rx buffer allocation parameters required to
  521. * support the current MTU, including padding for header
  522. * alignment and overruns.
  523. */
  524. efx->rx_dma_len = (efx->rx_prefix_size +
  525. EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
  526. efx->type->rx_buffer_padding);
  527. rx_buf_len = (sizeof(struct efx_rx_page_state) +
  528. efx->rx_ip_align + efx->rx_dma_len);
  529. if (rx_buf_len <= PAGE_SIZE) {
  530. efx->rx_scatter = efx->type->always_rx_scatter;
  531. efx->rx_buffer_order = 0;
  532. } else if (efx->type->can_rx_scatter) {
  533. BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
  534. BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
  535. 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
  536. EFX_RX_BUF_ALIGNMENT) >
  537. PAGE_SIZE);
  538. efx->rx_scatter = true;
  539. efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
  540. efx->rx_buffer_order = 0;
  541. } else {
  542. efx->rx_scatter = false;
  543. efx->rx_buffer_order = get_order(rx_buf_len);
  544. }
  545. efx_rx_config_page_split(efx);
  546. if (efx->rx_buffer_order)
  547. netif_dbg(efx, drv, efx->net_dev,
  548. "RX buf len=%u; page order=%u batch=%u\n",
  549. efx->rx_dma_len, efx->rx_buffer_order,
  550. efx->rx_pages_per_batch);
  551. else
  552. netif_dbg(efx, drv, efx->net_dev,
  553. "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
  554. efx->rx_dma_len, efx->rx_page_buf_step,
  555. efx->rx_bufs_per_page, efx->rx_pages_per_batch);
  556. /* Restore previously fixed features in hw_features and remove
  557. * features which are fixed now
  558. */
  559. efx->net_dev->hw_features |= efx->net_dev->features;
  560. efx->net_dev->hw_features &= ~efx->fixed_features;
  561. efx->net_dev->features |= efx->fixed_features;
  562. if (efx->net_dev->features != old_features)
  563. netdev_features_change(efx->net_dev);
  564. /* RX filters may also have scatter-enabled flags */
  565. if (efx->rx_scatter != old_rx_scatter)
  566. efx->type->filter_update_rx_scatter(efx);
  567. /* We must keep at least one descriptor in a TX ring empty.
  568. * We could avoid this when the queue size does not exactly
  569. * match the hardware ring size, but it's not that important.
  570. * Therefore we stop the queue when one more skb might fill
  571. * the ring completely. We wake it when half way back to
  572. * empty.
  573. */
  574. efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
  575. efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
  576. /* Initialise the channels */
  577. efx_for_each_channel(channel, efx) {
  578. efx_for_each_channel_tx_queue(tx_queue, channel) {
  579. efx_init_tx_queue(tx_queue);
  580. atomic_inc(&efx->active_queues);
  581. }
  582. efx_for_each_channel_rx_queue(rx_queue, channel) {
  583. efx_init_rx_queue(rx_queue);
  584. atomic_inc(&efx->active_queues);
  585. efx_stop_eventq(channel);
  586. efx_fast_push_rx_descriptors(rx_queue, false);
  587. efx_start_eventq(channel);
  588. }
  589. WARN_ON(channel->rx_pkt_n_frags);
  590. }
  591. efx_ptp_start_datapath(efx);
  592. if (netif_device_present(efx->net_dev))
  593. netif_tx_wake_all_queues(efx->net_dev);
  594. }
  595. static void efx_stop_datapath(struct efx_nic *efx)
  596. {
  597. struct efx_channel *channel;
  598. struct efx_tx_queue *tx_queue;
  599. struct efx_rx_queue *rx_queue;
  600. int rc;
  601. EFX_ASSERT_RESET_SERIALISED(efx);
  602. BUG_ON(efx->port_enabled);
  603. efx_ptp_stop_datapath(efx);
  604. /* Stop RX refill */
  605. efx_for_each_channel(channel, efx) {
  606. efx_for_each_channel_rx_queue(rx_queue, channel)
  607. rx_queue->refill_enabled = false;
  608. }
  609. efx_for_each_channel(channel, efx) {
  610. /* RX packet processing is pipelined, so wait for the
  611. * NAPI handler to complete. At least event queue 0
  612. * might be kept active by non-data events, so don't
  613. * use napi_synchronize() but actually disable NAPI
  614. * temporarily.
  615. */
  616. if (efx_channel_has_rx_queue(channel)) {
  617. efx_stop_eventq(channel);
  618. efx_start_eventq(channel);
  619. }
  620. }
  621. rc = efx->type->fini_dmaq(efx);
  622. if (rc && EFX_WORKAROUND_7803(efx)) {
  623. /* Schedule a reset to recover from the flush failure. The
  624. * descriptor caches reference memory we're about to free,
  625. * but falcon_reconfigure_mac_wrapper() won't reconnect
  626. * the MACs because of the pending reset.
  627. */
  628. netif_err(efx, drv, efx->net_dev,
  629. "Resetting to recover from flush failure\n");
  630. efx_schedule_reset(efx, RESET_TYPE_ALL);
  631. } else if (rc) {
  632. netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
  633. } else {
  634. netif_dbg(efx, drv, efx->net_dev,
  635. "successfully flushed all queues\n");
  636. }
  637. efx_for_each_channel(channel, efx) {
  638. efx_for_each_channel_rx_queue(rx_queue, channel)
  639. efx_fini_rx_queue(rx_queue);
  640. efx_for_each_possible_channel_tx_queue(tx_queue, channel)
  641. efx_fini_tx_queue(tx_queue);
  642. }
  643. }
  644. static void efx_remove_channel(struct efx_channel *channel)
  645. {
  646. struct efx_tx_queue *tx_queue;
  647. struct efx_rx_queue *rx_queue;
  648. netif_dbg(channel->efx, drv, channel->efx->net_dev,
  649. "destroy chan %d\n", channel->channel);
  650. efx_for_each_channel_rx_queue(rx_queue, channel)
  651. efx_remove_rx_queue(rx_queue);
  652. efx_for_each_possible_channel_tx_queue(tx_queue, channel)
  653. efx_remove_tx_queue(tx_queue);
  654. efx_remove_eventq(channel);
  655. channel->type->post_remove(channel);
  656. }
  657. static void efx_remove_channels(struct efx_nic *efx)
  658. {
  659. struct efx_channel *channel;
  660. efx_for_each_channel(channel, efx)
  661. efx_remove_channel(channel);
  662. }
  663. int
  664. efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
  665. {
  666. struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
  667. u32 old_rxq_entries, old_txq_entries;
  668. unsigned i, next_buffer_table = 0;
  669. int rc, rc2;
  670. rc = efx_check_disabled(efx);
  671. if (rc)
  672. return rc;
  673. /* Not all channels should be reallocated. We must avoid
  674. * reallocating their buffer table entries.
  675. */
  676. efx_for_each_channel(channel, efx) {
  677. struct efx_rx_queue *rx_queue;
  678. struct efx_tx_queue *tx_queue;
  679. if (channel->type->copy)
  680. continue;
  681. next_buffer_table = max(next_buffer_table,
  682. channel->eventq.index +
  683. channel->eventq.entries);
  684. efx_for_each_channel_rx_queue(rx_queue, channel)
  685. next_buffer_table = max(next_buffer_table,
  686. rx_queue->rxd.index +
  687. rx_queue->rxd.entries);
  688. efx_for_each_channel_tx_queue(tx_queue, channel)
  689. next_buffer_table = max(next_buffer_table,
  690. tx_queue->txd.index +
  691. tx_queue->txd.entries);
  692. }
  693. efx_device_detach_sync(efx);
  694. efx_stop_all(efx);
  695. efx_soft_disable_interrupts(efx);
  696. /* Clone channels (where possible) */
  697. memset(other_channel, 0, sizeof(other_channel));
  698. for (i = 0; i < efx->n_channels; i++) {
  699. channel = efx->channel[i];
  700. if (channel->type->copy)
  701. channel = channel->type->copy(channel);
  702. if (!channel) {
  703. rc = -ENOMEM;
  704. goto out;
  705. }
  706. other_channel[i] = channel;
  707. }
  708. /* Swap entry counts and channel pointers */
  709. old_rxq_entries = efx->rxq_entries;
  710. old_txq_entries = efx->txq_entries;
  711. efx->rxq_entries = rxq_entries;
  712. efx->txq_entries = txq_entries;
  713. for (i = 0; i < efx->n_channels; i++) {
  714. channel = efx->channel[i];
  715. efx->channel[i] = other_channel[i];
  716. other_channel[i] = channel;
  717. }
  718. /* Restart buffer table allocation */
  719. efx->next_buffer_table = next_buffer_table;
  720. for (i = 0; i < efx->n_channels; i++) {
  721. channel = efx->channel[i];
  722. if (!channel->type->copy)
  723. continue;
  724. rc = efx_probe_channel(channel);
  725. if (rc)
  726. goto rollback;
  727. efx_init_napi_channel(efx->channel[i]);
  728. }
  729. out:
  730. /* Destroy unused channel structures */
  731. for (i = 0; i < efx->n_channels; i++) {
  732. channel = other_channel[i];
  733. if (channel && channel->type->copy) {
  734. efx_fini_napi_channel(channel);
  735. efx_remove_channel(channel);
  736. kfree(channel);
  737. }
  738. }
  739. rc2 = efx_soft_enable_interrupts(efx);
  740. if (rc2) {
  741. rc = rc ? rc : rc2;
  742. netif_err(efx, drv, efx->net_dev,
  743. "unable to restart interrupts on channel reallocation\n");
  744. efx_schedule_reset(efx, RESET_TYPE_DISABLE);
  745. } else {
  746. efx_start_all(efx);
  747. netif_device_attach(efx->net_dev);
  748. }
  749. return rc;
  750. rollback:
  751. /* Swap back */
  752. efx->rxq_entries = old_rxq_entries;
  753. efx->txq_entries = old_txq_entries;
  754. for (i = 0; i < efx->n_channels; i++) {
  755. channel = efx->channel[i];
  756. efx->channel[i] = other_channel[i];
  757. other_channel[i] = channel;
  758. }
  759. goto out;
  760. }
  761. void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
  762. {
  763. mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
  764. }
  765. static const struct efx_channel_type efx_default_channel_type = {
  766. .pre_probe = efx_channel_dummy_op_int,
  767. .post_remove = efx_channel_dummy_op_void,
  768. .get_name = efx_get_channel_name,
  769. .copy = efx_copy_channel,
  770. .keep_eventq = false,
  771. };
  772. int efx_channel_dummy_op_int(struct efx_channel *channel)
  773. {
  774. return 0;
  775. }
  776. void efx_channel_dummy_op_void(struct efx_channel *channel)
  777. {
  778. }
  779. /**************************************************************************
  780. *
  781. * Port handling
  782. *
  783. **************************************************************************/
  784. /* This ensures that the kernel is kept informed (via
  785. * netif_carrier_on/off) of the link status, and also maintains the
  786. * link status's stop on the port's TX queue.
  787. */
  788. void efx_link_status_changed(struct efx_nic *efx)
  789. {
  790. struct efx_link_state *link_state = &efx->link_state;
  791. /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
  792. * that no events are triggered between unregister_netdev() and the
  793. * driver unloading. A more general condition is that NETDEV_CHANGE
  794. * can only be generated between NETDEV_UP and NETDEV_DOWN */
  795. if (!netif_running(efx->net_dev))
  796. return;
  797. if (link_state->up != netif_carrier_ok(efx->net_dev)) {
  798. efx->n_link_state_changes++;
  799. if (link_state->up)
  800. netif_carrier_on(efx->net_dev);
  801. else
  802. netif_carrier_off(efx->net_dev);
  803. }
  804. /* Status message for kernel log */
  805. if (link_state->up)
  806. netif_info(efx, link, efx->net_dev,
  807. "link up at %uMbps %s-duplex (MTU %d)\n",
  808. link_state->speed, link_state->fd ? "full" : "half",
  809. efx->net_dev->mtu);
  810. else
  811. netif_info(efx, link, efx->net_dev, "link down\n");
  812. }
  813. void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
  814. {
  815. efx->link_advertising = advertising;
  816. if (advertising) {
  817. if (advertising & ADVERTISED_Pause)
  818. efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
  819. else
  820. efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
  821. if (advertising & ADVERTISED_Asym_Pause)
  822. efx->wanted_fc ^= EFX_FC_TX;
  823. }
  824. }
  825. void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
  826. {
  827. efx->wanted_fc = wanted_fc;
  828. if (efx->link_advertising) {
  829. if (wanted_fc & EFX_FC_RX)
  830. efx->link_advertising |= (ADVERTISED_Pause |
  831. ADVERTISED_Asym_Pause);
  832. else
  833. efx->link_advertising &= ~(ADVERTISED_Pause |
  834. ADVERTISED_Asym_Pause);
  835. if (wanted_fc & EFX_FC_TX)
  836. efx->link_advertising ^= ADVERTISED_Asym_Pause;
  837. }
  838. }
  839. static void efx_fini_port(struct efx_nic *efx);
  840. /* We assume that efx->type->reconfigure_mac will always try to sync RX
  841. * filters and therefore needs to read-lock the filter table against freeing
  842. */
  843. void efx_mac_reconfigure(struct efx_nic *efx)
  844. {
  845. down_read(&efx->filter_sem);
  846. efx->type->reconfigure_mac(efx);
  847. up_read(&efx->filter_sem);
  848. }
  849. /* Push loopback/power/transmit disable settings to the PHY, and reconfigure
  850. * the MAC appropriately. All other PHY configuration changes are pushed
  851. * through phy_op->set_settings(), and pushed asynchronously to the MAC
  852. * through efx_monitor().
  853. *
  854. * Callers must hold the mac_lock
  855. */
  856. int __efx_reconfigure_port(struct efx_nic *efx)
  857. {
  858. enum efx_phy_mode phy_mode;
  859. int rc;
  860. WARN_ON(!mutex_is_locked(&efx->mac_lock));
  861. /* Disable PHY transmit in mac level loopbacks */
  862. phy_mode = efx->phy_mode;
  863. if (LOOPBACK_INTERNAL(efx))
  864. efx->phy_mode |= PHY_MODE_TX_DISABLED;
  865. else
  866. efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
  867. rc = efx->type->reconfigure_port(efx);
  868. if (rc)
  869. efx->phy_mode = phy_mode;
  870. return rc;
  871. }
  872. /* Reinitialise the MAC to pick up new PHY settings, even if the port is
  873. * disabled. */
  874. int efx_reconfigure_port(struct efx_nic *efx)
  875. {
  876. int rc;
  877. EFX_ASSERT_RESET_SERIALISED(efx);
  878. mutex_lock(&efx->mac_lock);
  879. rc = __efx_reconfigure_port(efx);
  880. mutex_unlock(&efx->mac_lock);
  881. return rc;
  882. }
  883. /* Asynchronous work item for changing MAC promiscuity and multicast
  884. * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
  885. * MAC directly. */
  886. static void efx_mac_work(struct work_struct *data)
  887. {
  888. struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
  889. mutex_lock(&efx->mac_lock);
  890. if (efx->port_enabled)
  891. efx_mac_reconfigure(efx);
  892. mutex_unlock(&efx->mac_lock);
  893. }
  894. static int efx_probe_port(struct efx_nic *efx)
  895. {
  896. int rc;
  897. netif_dbg(efx, probe, efx->net_dev, "create port\n");
  898. if (phy_flash_cfg)
  899. efx->phy_mode = PHY_MODE_SPECIAL;
  900. /* Connect up MAC/PHY operations table */
  901. rc = efx->type->probe_port(efx);
  902. if (rc)
  903. return rc;
  904. /* Initialise MAC address to permanent address */
  905. ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr);
  906. return 0;
  907. }
  908. static int efx_init_port(struct efx_nic *efx)
  909. {
  910. int rc;
  911. netif_dbg(efx, drv, efx->net_dev, "init port\n");
  912. mutex_lock(&efx->mac_lock);
  913. rc = efx->phy_op->init(efx);
  914. if (rc)
  915. goto fail1;
  916. efx->port_initialized = true;
  917. /* Reconfigure the MAC before creating dma queues (required for
  918. * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
  919. efx_mac_reconfigure(efx);
  920. /* Ensure the PHY advertises the correct flow control settings */
  921. rc = efx->phy_op->reconfigure(efx);
  922. if (rc && rc != -EPERM)
  923. goto fail2;
  924. mutex_unlock(&efx->mac_lock);
  925. return 0;
  926. fail2:
  927. efx->phy_op->fini(efx);
  928. fail1:
  929. mutex_unlock(&efx->mac_lock);
  930. return rc;
  931. }
  932. static void efx_start_port(struct efx_nic *efx)
  933. {
  934. netif_dbg(efx, ifup, efx->net_dev, "start port\n");
  935. BUG_ON(efx->port_enabled);
  936. mutex_lock(&efx->mac_lock);
  937. efx->port_enabled = true;
  938. /* Ensure MAC ingress/egress is enabled */
  939. efx_mac_reconfigure(efx);
  940. mutex_unlock(&efx->mac_lock);
  941. }
  942. /* Cancel work for MAC reconfiguration, periodic hardware monitoring
  943. * and the async self-test, wait for them to finish and prevent them
  944. * being scheduled again. This doesn't cover online resets, which
  945. * should only be cancelled when removing the device.
  946. */
  947. static void efx_stop_port(struct efx_nic *efx)
  948. {
  949. netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
  950. EFX_ASSERT_RESET_SERIALISED(efx);
  951. mutex_lock(&efx->mac_lock);
  952. efx->port_enabled = false;
  953. mutex_unlock(&efx->mac_lock);
  954. /* Serialise against efx_set_multicast_list() */
  955. netif_addr_lock_bh(efx->net_dev);
  956. netif_addr_unlock_bh(efx->net_dev);
  957. cancel_delayed_work_sync(&efx->monitor_work);
  958. efx_selftest_async_cancel(efx);
  959. cancel_work_sync(&efx->mac_work);
  960. }
  961. static void efx_fini_port(struct efx_nic *efx)
  962. {
  963. netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
  964. if (!efx->port_initialized)
  965. return;
  966. efx->phy_op->fini(efx);
  967. efx->port_initialized = false;
  968. efx->link_state.up = false;
  969. efx_link_status_changed(efx);
  970. }
  971. static void efx_remove_port(struct efx_nic *efx)
  972. {
  973. netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
  974. efx->type->remove_port(efx);
  975. }
  976. /**************************************************************************
  977. *
  978. * NIC handling
  979. *
  980. **************************************************************************/
  981. static LIST_HEAD(efx_primary_list);
  982. static LIST_HEAD(efx_unassociated_list);
  983. static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right)
  984. {
  985. return left->type == right->type &&
  986. left->vpd_sn && right->vpd_sn &&
  987. !strcmp(left->vpd_sn, right->vpd_sn);
  988. }
  989. static void efx_associate(struct efx_nic *efx)
  990. {
  991. struct efx_nic *other, *next;
  992. if (efx->primary == efx) {
  993. /* Adding primary function; look for secondaries */
  994. netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n");
  995. list_add_tail(&efx->node, &efx_primary_list);
  996. list_for_each_entry_safe(other, next, &efx_unassociated_list,
  997. node) {
  998. if (efx_same_controller(efx, other)) {
  999. list_del(&other->node);
  1000. netif_dbg(other, probe, other->net_dev,
  1001. "moving to secondary list of %s %s\n",
  1002. pci_name(efx->pci_dev),
  1003. efx->net_dev->name);
  1004. list_add_tail(&other->node,
  1005. &efx->secondary_list);
  1006. other->primary = efx;
  1007. }
  1008. }
  1009. } else {
  1010. /* Adding secondary function; look for primary */
  1011. list_for_each_entry(other, &efx_primary_list, node) {
  1012. if (efx_same_controller(efx, other)) {
  1013. netif_dbg(efx, probe, efx->net_dev,
  1014. "adding to secondary list of %s %s\n",
  1015. pci_name(other->pci_dev),
  1016. other->net_dev->name);
  1017. list_add_tail(&efx->node,
  1018. &other->secondary_list);
  1019. efx->primary = other;
  1020. return;
  1021. }
  1022. }
  1023. netif_dbg(efx, probe, efx->net_dev,
  1024. "adding to unassociated list\n");
  1025. list_add_tail(&efx->node, &efx_unassociated_list);
  1026. }
  1027. }
  1028. static void efx_dissociate(struct efx_nic *efx)
  1029. {
  1030. struct efx_nic *other, *next;
  1031. list_del(&efx->node);
  1032. efx->primary = NULL;
  1033. list_for_each_entry_safe(other, next, &efx->secondary_list, node) {
  1034. list_del(&other->node);
  1035. netif_dbg(other, probe, other->net_dev,
  1036. "moving to unassociated list\n");
  1037. list_add_tail(&other->node, &efx_unassociated_list);
  1038. other->primary = NULL;
  1039. }
  1040. }
  1041. /* This configures the PCI device to enable I/O and DMA. */
  1042. static int efx_init_io(struct efx_nic *efx)
  1043. {
  1044. struct pci_dev *pci_dev = efx->pci_dev;
  1045. dma_addr_t dma_mask = efx->type->max_dma_mask;
  1046. unsigned int mem_map_size = efx->type->mem_map_size(efx);
  1047. int rc, bar;
  1048. netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
  1049. bar = efx->type->mem_bar;
  1050. rc = pci_enable_device(pci_dev);
  1051. if (rc) {
  1052. netif_err(efx, probe, efx->net_dev,
  1053. "failed to enable PCI device\n");
  1054. goto fail1;
  1055. }
  1056. pci_set_master(pci_dev);
  1057. /* Set the PCI DMA mask. Try all possibilities from our
  1058. * genuine mask down to 32 bits, because some architectures
  1059. * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
  1060. * masks event though they reject 46 bit masks.
  1061. */
  1062. while (dma_mask > 0x7fffffffUL) {
  1063. rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
  1064. if (rc == 0)
  1065. break;
  1066. dma_mask >>= 1;
  1067. }
  1068. if (rc) {
  1069. netif_err(efx, probe, efx->net_dev,
  1070. "could not find a suitable DMA mask\n");
  1071. goto fail2;
  1072. }
  1073. netif_dbg(efx, probe, efx->net_dev,
  1074. "using DMA mask %llx\n", (unsigned long long) dma_mask);
  1075. efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
  1076. rc = pci_request_region(pci_dev, bar, "sfc");
  1077. if (rc) {
  1078. netif_err(efx, probe, efx->net_dev,
  1079. "request for memory BAR failed\n");
  1080. rc = -EIO;
  1081. goto fail3;
  1082. }
  1083. efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
  1084. if (!efx->membase) {
  1085. netif_err(efx, probe, efx->net_dev,
  1086. "could not map memory BAR at %llx+%x\n",
  1087. (unsigned long long)efx->membase_phys, mem_map_size);
  1088. rc = -ENOMEM;
  1089. goto fail4;
  1090. }
  1091. netif_dbg(efx, probe, efx->net_dev,
  1092. "memory BAR at %llx+%x (virtual %p)\n",
  1093. (unsigned long long)efx->membase_phys, mem_map_size,
  1094. efx->membase);
  1095. return 0;
  1096. fail4:
  1097. pci_release_region(efx->pci_dev, bar);
  1098. fail3:
  1099. efx->membase_phys = 0;
  1100. fail2:
  1101. pci_disable_device(efx->pci_dev);
  1102. fail1:
  1103. return rc;
  1104. }
  1105. static void efx_fini_io(struct efx_nic *efx)
  1106. {
  1107. int bar;
  1108. netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
  1109. if (efx->membase) {
  1110. iounmap(efx->membase);
  1111. efx->membase = NULL;
  1112. }
  1113. if (efx->membase_phys) {
  1114. bar = efx->type->mem_bar;
  1115. pci_release_region(efx->pci_dev, bar);
  1116. efx->membase_phys = 0;
  1117. }
  1118. /* Don't disable bus-mastering if VFs are assigned */
  1119. if (!pci_vfs_assigned(efx->pci_dev))
  1120. pci_disable_device(efx->pci_dev);
  1121. }
  1122. void efx_set_default_rx_indir_table(struct efx_nic *efx)
  1123. {
  1124. size_t i;
  1125. for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
  1126. efx->rx_indir_table[i] =
  1127. ethtool_rxfh_indir_default(i, efx->rss_spread);
  1128. }
  1129. static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
  1130. {
  1131. cpumask_var_t thread_mask;
  1132. unsigned int count;
  1133. int cpu;
  1134. if (rss_cpus) {
  1135. count = rss_cpus;
  1136. } else {
  1137. if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
  1138. netif_warn(efx, probe, efx->net_dev,
  1139. "RSS disabled due to allocation failure\n");
  1140. return 1;
  1141. }
  1142. count = 0;
  1143. for_each_online_cpu(cpu) {
  1144. if (!cpumask_test_cpu(cpu, thread_mask)) {
  1145. ++count;
  1146. cpumask_or(thread_mask, thread_mask,
  1147. topology_sibling_cpumask(cpu));
  1148. }
  1149. }
  1150. free_cpumask_var(thread_mask);
  1151. }
  1152. /* If RSS is requested for the PF *and* VFs then we can't write RSS
  1153. * table entries that are inaccessible to VFs
  1154. */
  1155. #ifdef CONFIG_SFC_SRIOV
  1156. if (efx->type->sriov_wanted) {
  1157. if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
  1158. count > efx_vf_size(efx)) {
  1159. netif_warn(efx, probe, efx->net_dev,
  1160. "Reducing number of RSS channels from %u to %u for "
  1161. "VF support. Increase vf-msix-limit to use more "
  1162. "channels on the PF.\n",
  1163. count, efx_vf_size(efx));
  1164. count = efx_vf_size(efx);
  1165. }
  1166. }
  1167. #endif
  1168. return count;
  1169. }
  1170. /* Probe the number and type of interrupts we are able to obtain, and
  1171. * the resulting numbers of channels and RX queues.
  1172. */
  1173. static int efx_probe_interrupts(struct efx_nic *efx)
  1174. {
  1175. unsigned int extra_channels = 0;
  1176. unsigned int i, j;
  1177. int rc;
  1178. for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
  1179. if (efx->extra_channel_type[i])
  1180. ++extra_channels;
  1181. if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
  1182. struct msix_entry xentries[EFX_MAX_CHANNELS];
  1183. unsigned int n_channels;
  1184. n_channels = efx_wanted_parallelism(efx);
  1185. if (efx_separate_tx_channels)
  1186. n_channels *= 2;
  1187. n_channels += extra_channels;
  1188. n_channels = min(n_channels, efx->max_channels);
  1189. for (i = 0; i < n_channels; i++)
  1190. xentries[i].entry = i;
  1191. rc = pci_enable_msix_range(efx->pci_dev,
  1192. xentries, 1, n_channels);
  1193. if (rc < 0) {
  1194. /* Fall back to single channel MSI */
  1195. efx->interrupt_mode = EFX_INT_MODE_MSI;
  1196. netif_err(efx, drv, efx->net_dev,
  1197. "could not enable MSI-X\n");
  1198. } else if (rc < n_channels) {
  1199. netif_err(efx, drv, efx->net_dev,
  1200. "WARNING: Insufficient MSI-X vectors"
  1201. " available (%d < %u).\n", rc, n_channels);
  1202. netif_err(efx, drv, efx->net_dev,
  1203. "WARNING: Performance may be reduced.\n");
  1204. n_channels = rc;
  1205. }
  1206. if (rc > 0) {
  1207. efx->n_channels = n_channels;
  1208. if (n_channels > extra_channels)
  1209. n_channels -= extra_channels;
  1210. if (efx_separate_tx_channels) {
  1211. efx->n_tx_channels = min(max(n_channels / 2,
  1212. 1U),
  1213. efx->max_tx_channels);
  1214. efx->n_rx_channels = max(n_channels -
  1215. efx->n_tx_channels,
  1216. 1U);
  1217. } else {
  1218. efx->n_tx_channels = min(n_channels,
  1219. efx->max_tx_channels);
  1220. efx->n_rx_channels = n_channels;
  1221. }
  1222. for (i = 0; i < efx->n_channels; i++)
  1223. efx_get_channel(efx, i)->irq =
  1224. xentries[i].vector;
  1225. }
  1226. }
  1227. /* Try single interrupt MSI */
  1228. if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
  1229. efx->n_channels = 1;
  1230. efx->n_rx_channels = 1;
  1231. efx->n_tx_channels = 1;
  1232. rc = pci_enable_msi(efx->pci_dev);
  1233. if (rc == 0) {
  1234. efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
  1235. } else {
  1236. netif_err(efx, drv, efx->net_dev,
  1237. "could not enable MSI\n");
  1238. efx->interrupt_mode = EFX_INT_MODE_LEGACY;
  1239. }
  1240. }
  1241. /* Assume legacy interrupts */
  1242. if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
  1243. efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
  1244. efx->n_rx_channels = 1;
  1245. efx->n_tx_channels = 1;
  1246. efx->legacy_irq = efx->pci_dev->irq;
  1247. }
  1248. /* Assign extra channels if possible */
  1249. j = efx->n_channels;
  1250. for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
  1251. if (!efx->extra_channel_type[i])
  1252. continue;
  1253. if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
  1254. efx->n_channels <= extra_channels) {
  1255. efx->extra_channel_type[i]->handle_no_channel(efx);
  1256. } else {
  1257. --j;
  1258. efx_get_channel(efx, j)->type =
  1259. efx->extra_channel_type[i];
  1260. }
  1261. }
  1262. /* RSS might be usable on VFs even if it is disabled on the PF */
  1263. #ifdef CONFIG_SFC_SRIOV
  1264. if (efx->type->sriov_wanted) {
  1265. efx->rss_spread = ((efx->n_rx_channels > 1 ||
  1266. !efx->type->sriov_wanted(efx)) ?
  1267. efx->n_rx_channels : efx_vf_size(efx));
  1268. return 0;
  1269. }
  1270. #endif
  1271. efx->rss_spread = efx->n_rx_channels;
  1272. return 0;
  1273. }
  1274. static int efx_soft_enable_interrupts(struct efx_nic *efx)
  1275. {
  1276. struct efx_channel *channel, *end_channel;
  1277. int rc;
  1278. BUG_ON(efx->state == STATE_DISABLED);
  1279. efx->irq_soft_enabled = true;
  1280. smp_wmb();
  1281. efx_for_each_channel(channel, efx) {
  1282. if (!channel->type->keep_eventq) {
  1283. rc = efx_init_eventq(channel);
  1284. if (rc)
  1285. goto fail;
  1286. }
  1287. efx_start_eventq(channel);
  1288. }
  1289. efx_mcdi_mode_event(efx);
  1290. return 0;
  1291. fail:
  1292. end_channel = channel;
  1293. efx_for_each_channel(channel, efx) {
  1294. if (channel == end_channel)
  1295. break;
  1296. efx_stop_eventq(channel);
  1297. if (!channel->type->keep_eventq)
  1298. efx_fini_eventq(channel);
  1299. }
  1300. return rc;
  1301. }
  1302. static void efx_soft_disable_interrupts(struct efx_nic *efx)
  1303. {
  1304. struct efx_channel *channel;
  1305. if (efx->state == STATE_DISABLED)
  1306. return;
  1307. efx_mcdi_mode_poll(efx);
  1308. efx->irq_soft_enabled = false;
  1309. smp_wmb();
  1310. if (efx->legacy_irq)
  1311. synchronize_irq(efx->legacy_irq);
  1312. efx_for_each_channel(channel, efx) {
  1313. if (channel->irq)
  1314. synchronize_irq(channel->irq);
  1315. efx_stop_eventq(channel);
  1316. if (!channel->type->keep_eventq)
  1317. efx_fini_eventq(channel);
  1318. }
  1319. /* Flush the asynchronous MCDI request queue */
  1320. efx_mcdi_flush_async(efx);
  1321. }
  1322. static int efx_enable_interrupts(struct efx_nic *efx)
  1323. {
  1324. struct efx_channel *channel, *end_channel;
  1325. int rc;
  1326. BUG_ON(efx->state == STATE_DISABLED);
  1327. if (efx->eeh_disabled_legacy_irq) {
  1328. enable_irq(efx->legacy_irq);
  1329. efx->eeh_disabled_legacy_irq = false;
  1330. }
  1331. efx->type->irq_enable_master(efx);
  1332. efx_for_each_channel(channel, efx) {
  1333. if (channel->type->keep_eventq) {
  1334. rc = efx_init_eventq(channel);
  1335. if (rc)
  1336. goto fail;
  1337. }
  1338. }
  1339. rc = efx_soft_enable_interrupts(efx);
  1340. if (rc)
  1341. goto fail;
  1342. return 0;
  1343. fail:
  1344. end_channel = channel;
  1345. efx_for_each_channel(channel, efx) {
  1346. if (channel == end_channel)
  1347. break;
  1348. if (channel->type->keep_eventq)
  1349. efx_fini_eventq(channel);
  1350. }
  1351. efx->type->irq_disable_non_ev(efx);
  1352. return rc;
  1353. }
  1354. static void efx_disable_interrupts(struct efx_nic *efx)
  1355. {
  1356. struct efx_channel *channel;
  1357. efx_soft_disable_interrupts(efx);
  1358. efx_for_each_channel(channel, efx) {
  1359. if (channel->type->keep_eventq)
  1360. efx_fini_eventq(channel);
  1361. }
  1362. efx->type->irq_disable_non_ev(efx);
  1363. }
  1364. static void efx_remove_interrupts(struct efx_nic *efx)
  1365. {
  1366. struct efx_channel *channel;
  1367. /* Remove MSI/MSI-X interrupts */
  1368. efx_for_each_channel(channel, efx)
  1369. channel->irq = 0;
  1370. pci_disable_msi(efx->pci_dev);
  1371. pci_disable_msix(efx->pci_dev);
  1372. /* Remove legacy interrupt */
  1373. efx->legacy_irq = 0;
  1374. }
  1375. static void efx_set_channels(struct efx_nic *efx)
  1376. {
  1377. struct efx_channel *channel;
  1378. struct efx_tx_queue *tx_queue;
  1379. efx->tx_channel_offset =
  1380. efx_separate_tx_channels ?
  1381. efx->n_channels - efx->n_tx_channels : 0;
  1382. /* We need to mark which channels really have RX and TX
  1383. * queues, and adjust the TX queue numbers if we have separate
  1384. * RX-only and TX-only channels.
  1385. */
  1386. efx_for_each_channel(channel, efx) {
  1387. if (channel->channel < efx->n_rx_channels)
  1388. channel->rx_queue.core_index = channel->channel;
  1389. else
  1390. channel->rx_queue.core_index = -1;
  1391. efx_for_each_channel_tx_queue(tx_queue, channel)
  1392. tx_queue->queue -= (efx->tx_channel_offset *
  1393. EFX_TXQ_TYPES);
  1394. }
  1395. }
  1396. static int efx_probe_nic(struct efx_nic *efx)
  1397. {
  1398. int rc;
  1399. netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
  1400. /* Carry out hardware-type specific initialisation */
  1401. rc = efx->type->probe(efx);
  1402. if (rc)
  1403. return rc;
  1404. do {
  1405. if (!efx->max_channels || !efx->max_tx_channels) {
  1406. netif_err(efx, drv, efx->net_dev,
  1407. "Insufficient resources to allocate"
  1408. " any channels\n");
  1409. rc = -ENOSPC;
  1410. goto fail1;
  1411. }
  1412. /* Determine the number of channels and queues by trying
  1413. * to hook in MSI-X interrupts.
  1414. */
  1415. rc = efx_probe_interrupts(efx);
  1416. if (rc)
  1417. goto fail1;
  1418. efx_set_channels(efx);
  1419. /* dimension_resources can fail with EAGAIN */
  1420. rc = efx->type->dimension_resources(efx);
  1421. if (rc != 0 && rc != -EAGAIN)
  1422. goto fail2;
  1423. if (rc == -EAGAIN)
  1424. /* try again with new max_channels */
  1425. efx_remove_interrupts(efx);
  1426. } while (rc == -EAGAIN);
  1427. if (efx->n_channels > 1)
  1428. netdev_rss_key_fill(&efx->rx_hash_key,
  1429. sizeof(efx->rx_hash_key));
  1430. efx_set_default_rx_indir_table(efx);
  1431. netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
  1432. netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
  1433. /* Initialise the interrupt moderation settings */
  1434. efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
  1435. true);
  1436. return 0;
  1437. fail2:
  1438. efx_remove_interrupts(efx);
  1439. fail1:
  1440. efx->type->remove(efx);
  1441. return rc;
  1442. }
  1443. static void efx_remove_nic(struct efx_nic *efx)
  1444. {
  1445. netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
  1446. efx_remove_interrupts(efx);
  1447. efx->type->remove(efx);
  1448. }
  1449. static int efx_probe_filters(struct efx_nic *efx)
  1450. {
  1451. int rc;
  1452. spin_lock_init(&efx->filter_lock);
  1453. init_rwsem(&efx->filter_sem);
  1454. mutex_lock(&efx->mac_lock);
  1455. down_write(&efx->filter_sem);
  1456. rc = efx->type->filter_table_probe(efx);
  1457. if (rc)
  1458. goto out_unlock;
  1459. #ifdef CONFIG_RFS_ACCEL
  1460. if (efx->type->offload_features & NETIF_F_NTUPLE) {
  1461. struct efx_channel *channel;
  1462. int i, success = 1;
  1463. efx_for_each_channel(channel, efx) {
  1464. channel->rps_flow_id =
  1465. kcalloc(efx->type->max_rx_ip_filters,
  1466. sizeof(*channel->rps_flow_id),
  1467. GFP_KERNEL);
  1468. if (!channel->rps_flow_id)
  1469. success = 0;
  1470. else
  1471. for (i = 0;
  1472. i < efx->type->max_rx_ip_filters;
  1473. ++i)
  1474. channel->rps_flow_id[i] =
  1475. RPS_FLOW_ID_INVALID;
  1476. }
  1477. if (!success) {
  1478. efx_for_each_channel(channel, efx)
  1479. kfree(channel->rps_flow_id);
  1480. efx->type->filter_table_remove(efx);
  1481. rc = -ENOMEM;
  1482. goto out_unlock;
  1483. }
  1484. efx->rps_expire_index = efx->rps_expire_channel = 0;
  1485. }
  1486. #endif
  1487. out_unlock:
  1488. up_write(&efx->filter_sem);
  1489. mutex_unlock(&efx->mac_lock);
  1490. return rc;
  1491. }
  1492. static void efx_remove_filters(struct efx_nic *efx)
  1493. {
  1494. #ifdef CONFIG_RFS_ACCEL
  1495. struct efx_channel *channel;
  1496. efx_for_each_channel(channel, efx)
  1497. kfree(channel->rps_flow_id);
  1498. #endif
  1499. down_write(&efx->filter_sem);
  1500. efx->type->filter_table_remove(efx);
  1501. up_write(&efx->filter_sem);
  1502. }
  1503. static void efx_restore_filters(struct efx_nic *efx)
  1504. {
  1505. down_read(&efx->filter_sem);
  1506. efx->type->filter_table_restore(efx);
  1507. up_read(&efx->filter_sem);
  1508. }
  1509. /**************************************************************************
  1510. *
  1511. * NIC startup/shutdown
  1512. *
  1513. *************************************************************************/
  1514. static int efx_probe_all(struct efx_nic *efx)
  1515. {
  1516. int rc;
  1517. rc = efx_probe_nic(efx);
  1518. if (rc) {
  1519. netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
  1520. goto fail1;
  1521. }
  1522. rc = efx_probe_port(efx);
  1523. if (rc) {
  1524. netif_err(efx, probe, efx->net_dev, "failed to create port\n");
  1525. goto fail2;
  1526. }
  1527. BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
  1528. if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
  1529. rc = -EINVAL;
  1530. goto fail3;
  1531. }
  1532. efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
  1533. #ifdef CONFIG_SFC_SRIOV
  1534. rc = efx->type->vswitching_probe(efx);
  1535. if (rc) /* not fatal; the PF will still work fine */
  1536. netif_warn(efx, probe, efx->net_dev,
  1537. "failed to setup vswitching rc=%d;"
  1538. " VFs may not function\n", rc);
  1539. #endif
  1540. rc = efx_probe_filters(efx);
  1541. if (rc) {
  1542. netif_err(efx, probe, efx->net_dev,
  1543. "failed to create filter tables\n");
  1544. goto fail4;
  1545. }
  1546. rc = efx_probe_channels(efx);
  1547. if (rc)
  1548. goto fail5;
  1549. return 0;
  1550. fail5:
  1551. efx_remove_filters(efx);
  1552. fail4:
  1553. #ifdef CONFIG_SFC_SRIOV
  1554. efx->type->vswitching_remove(efx);
  1555. #endif
  1556. fail3:
  1557. efx_remove_port(efx);
  1558. fail2:
  1559. efx_remove_nic(efx);
  1560. fail1:
  1561. return rc;
  1562. }
  1563. /* If the interface is supposed to be running but is not, start
  1564. * the hardware and software data path, regular activity for the port
  1565. * (MAC statistics, link polling, etc.) and schedule the port to be
  1566. * reconfigured. Interrupts must already be enabled. This function
  1567. * is safe to call multiple times, so long as the NIC is not disabled.
  1568. * Requires the RTNL lock.
  1569. */
  1570. static void efx_start_all(struct efx_nic *efx)
  1571. {
  1572. EFX_ASSERT_RESET_SERIALISED(efx);
  1573. BUG_ON(efx->state == STATE_DISABLED);
  1574. /* Check that it is appropriate to restart the interface. All
  1575. * of these flags are safe to read under just the rtnl lock */
  1576. if (efx->port_enabled || !netif_running(efx->net_dev) ||
  1577. efx->reset_pending)
  1578. return;
  1579. efx_start_port(efx);
  1580. efx_start_datapath(efx);
  1581. /* Start the hardware monitor if there is one */
  1582. if (efx->type->monitor != NULL)
  1583. queue_delayed_work(efx->workqueue, &efx->monitor_work,
  1584. efx_monitor_interval);
  1585. /* If link state detection is normally event-driven, we have
  1586. * to poll now because we could have missed a change
  1587. */
  1588. if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
  1589. mutex_lock(&efx->mac_lock);
  1590. if (efx->phy_op->poll(efx))
  1591. efx_link_status_changed(efx);
  1592. mutex_unlock(&efx->mac_lock);
  1593. }
  1594. efx->type->start_stats(efx);
  1595. efx->type->pull_stats(efx);
  1596. spin_lock_bh(&efx->stats_lock);
  1597. efx->type->update_stats(efx, NULL, NULL);
  1598. spin_unlock_bh(&efx->stats_lock);
  1599. }
  1600. /* Quiesce the hardware and software data path, and regular activity
  1601. * for the port without bringing the link down. Safe to call multiple
  1602. * times with the NIC in almost any state, but interrupts should be
  1603. * enabled. Requires the RTNL lock.
  1604. */
  1605. static void efx_stop_all(struct efx_nic *efx)
  1606. {
  1607. EFX_ASSERT_RESET_SERIALISED(efx);
  1608. /* port_enabled can be read safely under the rtnl lock */
  1609. if (!efx->port_enabled)
  1610. return;
  1611. /* update stats before we go down so we can accurately count
  1612. * rx_nodesc_drops
  1613. */
  1614. efx->type->pull_stats(efx);
  1615. spin_lock_bh(&efx->stats_lock);
  1616. efx->type->update_stats(efx, NULL, NULL);
  1617. spin_unlock_bh(&efx->stats_lock);
  1618. efx->type->stop_stats(efx);
  1619. efx_stop_port(efx);
  1620. /* Stop the kernel transmit interface. This is only valid if
  1621. * the device is stopped or detached; otherwise the watchdog
  1622. * may fire immediately.
  1623. */
  1624. WARN_ON(netif_running(efx->net_dev) &&
  1625. netif_device_present(efx->net_dev));
  1626. netif_tx_disable(efx->net_dev);
  1627. efx_stop_datapath(efx);
  1628. }
  1629. static void efx_remove_all(struct efx_nic *efx)
  1630. {
  1631. efx_remove_channels(efx);
  1632. efx_remove_filters(efx);
  1633. #ifdef CONFIG_SFC_SRIOV
  1634. efx->type->vswitching_remove(efx);
  1635. #endif
  1636. efx_remove_port(efx);
  1637. efx_remove_nic(efx);
  1638. }
  1639. /**************************************************************************
  1640. *
  1641. * Interrupt moderation
  1642. *
  1643. **************************************************************************/
  1644. static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
  1645. {
  1646. if (usecs == 0)
  1647. return 0;
  1648. if (usecs * 1000 < quantum_ns)
  1649. return 1; /* never round down to 0 */
  1650. return usecs * 1000 / quantum_ns;
  1651. }
  1652. /* Set interrupt moderation parameters */
  1653. int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
  1654. unsigned int rx_usecs, bool rx_adaptive,
  1655. bool rx_may_override_tx)
  1656. {
  1657. struct efx_channel *channel;
  1658. unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
  1659. efx->timer_quantum_ns,
  1660. 1000);
  1661. unsigned int tx_ticks;
  1662. unsigned int rx_ticks;
  1663. EFX_ASSERT_RESET_SERIALISED(efx);
  1664. if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
  1665. return -EINVAL;
  1666. tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
  1667. rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
  1668. if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
  1669. !rx_may_override_tx) {
  1670. netif_err(efx, drv, efx->net_dev, "Channels are shared. "
  1671. "RX and TX IRQ moderation must be equal\n");
  1672. return -EINVAL;
  1673. }
  1674. efx->irq_rx_adaptive = rx_adaptive;
  1675. efx->irq_rx_moderation = rx_ticks;
  1676. efx_for_each_channel(channel, efx) {
  1677. if (efx_channel_has_rx_queue(channel))
  1678. channel->irq_moderation = rx_ticks;
  1679. else if (efx_channel_has_tx_queues(channel))
  1680. channel->irq_moderation = tx_ticks;
  1681. }
  1682. return 0;
  1683. }
  1684. void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
  1685. unsigned int *rx_usecs, bool *rx_adaptive)
  1686. {
  1687. /* We must round up when converting ticks to microseconds
  1688. * because we round down when converting the other way.
  1689. */
  1690. *rx_adaptive = efx->irq_rx_adaptive;
  1691. *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
  1692. efx->timer_quantum_ns,
  1693. 1000);
  1694. /* If channels are shared between RX and TX, so is IRQ
  1695. * moderation. Otherwise, IRQ moderation is the same for all
  1696. * TX channels and is not adaptive.
  1697. */
  1698. if (efx->tx_channel_offset == 0)
  1699. *tx_usecs = *rx_usecs;
  1700. else
  1701. *tx_usecs = DIV_ROUND_UP(
  1702. efx->channel[efx->tx_channel_offset]->irq_moderation *
  1703. efx->timer_quantum_ns,
  1704. 1000);
  1705. }
  1706. /**************************************************************************
  1707. *
  1708. * Hardware monitor
  1709. *
  1710. **************************************************************************/
  1711. /* Run periodically off the general workqueue */
  1712. static void efx_monitor(struct work_struct *data)
  1713. {
  1714. struct efx_nic *efx = container_of(data, struct efx_nic,
  1715. monitor_work.work);
  1716. netif_vdbg(efx, timer, efx->net_dev,
  1717. "hardware monitor executing on CPU %d\n",
  1718. raw_smp_processor_id());
  1719. BUG_ON(efx->type->monitor == NULL);
  1720. /* If the mac_lock is already held then it is likely a port
  1721. * reconfiguration is already in place, which will likely do
  1722. * most of the work of monitor() anyway. */
  1723. if (mutex_trylock(&efx->mac_lock)) {
  1724. if (efx->port_enabled)
  1725. efx->type->monitor(efx);
  1726. mutex_unlock(&efx->mac_lock);
  1727. }
  1728. queue_delayed_work(efx->workqueue, &efx->monitor_work,
  1729. efx_monitor_interval);
  1730. }
  1731. /**************************************************************************
  1732. *
  1733. * ioctls
  1734. *
  1735. *************************************************************************/
  1736. /* Net device ioctl
  1737. * Context: process, rtnl_lock() held.
  1738. */
  1739. static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
  1740. {
  1741. struct efx_nic *efx = netdev_priv(net_dev);
  1742. struct mii_ioctl_data *data = if_mii(ifr);
  1743. if (cmd == SIOCSHWTSTAMP)
  1744. return efx_ptp_set_ts_config(efx, ifr);
  1745. if (cmd == SIOCGHWTSTAMP)
  1746. return efx_ptp_get_ts_config(efx, ifr);
  1747. /* Convert phy_id from older PRTAD/DEVAD format */
  1748. if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
  1749. (data->phy_id & 0xfc00) == 0x0400)
  1750. data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
  1751. return mdio_mii_ioctl(&efx->mdio, data, cmd);
  1752. }
  1753. /**************************************************************************
  1754. *
  1755. * NAPI interface
  1756. *
  1757. **************************************************************************/
  1758. static void efx_init_napi_channel(struct efx_channel *channel)
  1759. {
  1760. struct efx_nic *efx = channel->efx;
  1761. channel->napi_dev = efx->net_dev;
  1762. netif_napi_add(channel->napi_dev, &channel->napi_str,
  1763. efx_poll, napi_weight);
  1764. efx_channel_busy_poll_init(channel);
  1765. }
  1766. static void efx_init_napi(struct efx_nic *efx)
  1767. {
  1768. struct efx_channel *channel;
  1769. efx_for_each_channel(channel, efx)
  1770. efx_init_napi_channel(channel);
  1771. }
  1772. static void efx_fini_napi_channel(struct efx_channel *channel)
  1773. {
  1774. if (channel->napi_dev) {
  1775. netif_napi_del(&channel->napi_str);
  1776. napi_hash_del(&channel->napi_str);
  1777. }
  1778. channel->napi_dev = NULL;
  1779. }
  1780. static void efx_fini_napi(struct efx_nic *efx)
  1781. {
  1782. struct efx_channel *channel;
  1783. efx_for_each_channel(channel, efx)
  1784. efx_fini_napi_channel(channel);
  1785. }
  1786. /**************************************************************************
  1787. *
  1788. * Kernel netpoll interface
  1789. *
  1790. *************************************************************************/
  1791. #ifdef CONFIG_NET_POLL_CONTROLLER
  1792. /* Although in the common case interrupts will be disabled, this is not
  1793. * guaranteed. However, all our work happens inside the NAPI callback,
  1794. * so no locking is required.
  1795. */
  1796. static void efx_netpoll(struct net_device *net_dev)
  1797. {
  1798. struct efx_nic *efx = netdev_priv(net_dev);
  1799. struct efx_channel *channel;
  1800. efx_for_each_channel(channel, efx)
  1801. efx_schedule_channel(channel);
  1802. }
  1803. #endif
  1804. #ifdef CONFIG_NET_RX_BUSY_POLL
  1805. static int efx_busy_poll(struct napi_struct *napi)
  1806. {
  1807. struct efx_channel *channel =
  1808. container_of(napi, struct efx_channel, napi_str);
  1809. struct efx_nic *efx = channel->efx;
  1810. int budget = 4;
  1811. int old_rx_packets, rx_packets;
  1812. if (!netif_running(efx->net_dev))
  1813. return LL_FLUSH_FAILED;
  1814. if (!efx_channel_try_lock_poll(channel))
  1815. return LL_FLUSH_BUSY;
  1816. old_rx_packets = channel->rx_queue.rx_packets;
  1817. efx_process_channel(channel, budget);
  1818. rx_packets = channel->rx_queue.rx_packets - old_rx_packets;
  1819. /* There is no race condition with NAPI here.
  1820. * NAPI will automatically be rescheduled if it yielded during busy
  1821. * polling, because it was not able to take the lock and thus returned
  1822. * the full budget.
  1823. */
  1824. efx_channel_unlock_poll(channel);
  1825. return rx_packets;
  1826. }
  1827. #endif
  1828. /**************************************************************************
  1829. *
  1830. * Kernel net device interface
  1831. *
  1832. *************************************************************************/
  1833. /* Context: process, rtnl_lock() held. */
  1834. int efx_net_open(struct net_device *net_dev)
  1835. {
  1836. struct efx_nic *efx = netdev_priv(net_dev);
  1837. int rc;
  1838. netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
  1839. raw_smp_processor_id());
  1840. rc = efx_check_disabled(efx);
  1841. if (rc)
  1842. return rc;
  1843. if (efx->phy_mode & PHY_MODE_SPECIAL)
  1844. return -EBUSY;
  1845. if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
  1846. return -EIO;
  1847. /* Notify the kernel of the link state polled during driver load,
  1848. * before the monitor starts running */
  1849. efx_link_status_changed(efx);
  1850. efx_start_all(efx);
  1851. efx_selftest_async_start(efx);
  1852. return 0;
  1853. }
  1854. /* Context: process, rtnl_lock() held.
  1855. * Note that the kernel will ignore our return code; this method
  1856. * should really be a void.
  1857. */
  1858. int efx_net_stop(struct net_device *net_dev)
  1859. {
  1860. struct efx_nic *efx = netdev_priv(net_dev);
  1861. netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
  1862. raw_smp_processor_id());
  1863. /* Stop the device and flush all the channels */
  1864. efx_stop_all(efx);
  1865. return 0;
  1866. }
  1867. /* Context: process, dev_base_lock or RTNL held, non-blocking. */
  1868. static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
  1869. struct rtnl_link_stats64 *stats)
  1870. {
  1871. struct efx_nic *efx = netdev_priv(net_dev);
  1872. spin_lock_bh(&efx->stats_lock);
  1873. efx->type->update_stats(efx, NULL, stats);
  1874. spin_unlock_bh(&efx->stats_lock);
  1875. return stats;
  1876. }
  1877. /* Context: netif_tx_lock held, BHs disabled. */
  1878. static void efx_watchdog(struct net_device *net_dev)
  1879. {
  1880. struct efx_nic *efx = netdev_priv(net_dev);
  1881. netif_err(efx, tx_err, efx->net_dev,
  1882. "TX stuck with port_enabled=%d: resetting channels\n",
  1883. efx->port_enabled);
  1884. efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
  1885. }
  1886. /* Context: process, rtnl_lock() held. */
  1887. static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
  1888. {
  1889. struct efx_nic *efx = netdev_priv(net_dev);
  1890. int rc;
  1891. rc = efx_check_disabled(efx);
  1892. if (rc)
  1893. return rc;
  1894. if (new_mtu > EFX_MAX_MTU)
  1895. return -EINVAL;
  1896. netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
  1897. efx_device_detach_sync(efx);
  1898. efx_stop_all(efx);
  1899. mutex_lock(&efx->mac_lock);
  1900. net_dev->mtu = new_mtu;
  1901. efx_mac_reconfigure(efx);
  1902. mutex_unlock(&efx->mac_lock);
  1903. efx_start_all(efx);
  1904. netif_device_attach(efx->net_dev);
  1905. return 0;
  1906. }
  1907. static int efx_set_mac_address(struct net_device *net_dev, void *data)
  1908. {
  1909. struct efx_nic *efx = netdev_priv(net_dev);
  1910. struct sockaddr *addr = data;
  1911. u8 *new_addr = addr->sa_data;
  1912. u8 old_addr[6];
  1913. int rc;
  1914. if (!is_valid_ether_addr(new_addr)) {
  1915. netif_err(efx, drv, efx->net_dev,
  1916. "invalid ethernet MAC address requested: %pM\n",
  1917. new_addr);
  1918. return -EADDRNOTAVAIL;
  1919. }
  1920. /* save old address */
  1921. ether_addr_copy(old_addr, net_dev->dev_addr);
  1922. ether_addr_copy(net_dev->dev_addr, new_addr);
  1923. if (efx->type->set_mac_address) {
  1924. rc = efx->type->set_mac_address(efx);
  1925. if (rc) {
  1926. ether_addr_copy(net_dev->dev_addr, old_addr);
  1927. return rc;
  1928. }
  1929. }
  1930. /* Reconfigure the MAC */
  1931. mutex_lock(&efx->mac_lock);
  1932. efx_mac_reconfigure(efx);
  1933. mutex_unlock(&efx->mac_lock);
  1934. return 0;
  1935. }
  1936. /* Context: netif_addr_lock held, BHs disabled. */
  1937. static void efx_set_rx_mode(struct net_device *net_dev)
  1938. {
  1939. struct efx_nic *efx = netdev_priv(net_dev);
  1940. if (efx->port_enabled)
  1941. queue_work(efx->workqueue, &efx->mac_work);
  1942. /* Otherwise efx_start_port() will do this */
  1943. }
  1944. static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
  1945. {
  1946. struct efx_nic *efx = netdev_priv(net_dev);
  1947. int rc;
  1948. /* If disabling RX n-tuple filtering, clear existing filters */
  1949. if (net_dev->features & ~data & NETIF_F_NTUPLE) {
  1950. rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
  1951. if (rc)
  1952. return rc;
  1953. }
  1954. /* If Rx VLAN filter is changed, update filters via mac_reconfigure */
  1955. if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) {
  1956. /* efx_set_rx_mode() will schedule MAC work to update filters
  1957. * when a new features are finally set in net_dev.
  1958. */
  1959. efx_set_rx_mode(net_dev);
  1960. }
  1961. return 0;
  1962. }
  1963. static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid)
  1964. {
  1965. struct efx_nic *efx = netdev_priv(net_dev);
  1966. if (efx->type->vlan_rx_add_vid)
  1967. return efx->type->vlan_rx_add_vid(efx, proto, vid);
  1968. else
  1969. return -EOPNOTSUPP;
  1970. }
  1971. static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid)
  1972. {
  1973. struct efx_nic *efx = netdev_priv(net_dev);
  1974. if (efx->type->vlan_rx_kill_vid)
  1975. return efx->type->vlan_rx_kill_vid(efx, proto, vid);
  1976. else
  1977. return -EOPNOTSUPP;
  1978. }
  1979. static const struct net_device_ops efx_netdev_ops = {
  1980. .ndo_open = efx_net_open,
  1981. .ndo_stop = efx_net_stop,
  1982. .ndo_get_stats64 = efx_net_stats,
  1983. .ndo_tx_timeout = efx_watchdog,
  1984. .ndo_start_xmit = efx_hard_start_xmit,
  1985. .ndo_validate_addr = eth_validate_addr,
  1986. .ndo_do_ioctl = efx_ioctl,
  1987. .ndo_change_mtu = efx_change_mtu,
  1988. .ndo_set_mac_address = efx_set_mac_address,
  1989. .ndo_set_rx_mode = efx_set_rx_mode,
  1990. .ndo_set_features = efx_set_features,
  1991. .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid,
  1992. .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid,
  1993. #ifdef CONFIG_SFC_SRIOV
  1994. .ndo_set_vf_mac = efx_sriov_set_vf_mac,
  1995. .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
  1996. .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
  1997. .ndo_get_vf_config = efx_sriov_get_vf_config,
  1998. .ndo_set_vf_link_state = efx_sriov_set_vf_link_state,
  1999. .ndo_get_phys_port_id = efx_sriov_get_phys_port_id,
  2000. #endif
  2001. #ifdef CONFIG_NET_POLL_CONTROLLER
  2002. .ndo_poll_controller = efx_netpoll,
  2003. #endif
  2004. .ndo_setup_tc = efx_setup_tc,
  2005. #ifdef CONFIG_NET_RX_BUSY_POLL
  2006. .ndo_busy_poll = efx_busy_poll,
  2007. #endif
  2008. #ifdef CONFIG_RFS_ACCEL
  2009. .ndo_rx_flow_steer = efx_filter_rfs,
  2010. #endif
  2011. };
  2012. static void efx_update_name(struct efx_nic *efx)
  2013. {
  2014. strcpy(efx->name, efx->net_dev->name);
  2015. efx_mtd_rename(efx);
  2016. efx_set_channel_names(efx);
  2017. }
  2018. static int efx_netdev_event(struct notifier_block *this,
  2019. unsigned long event, void *ptr)
  2020. {
  2021. struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
  2022. if ((net_dev->netdev_ops == &efx_netdev_ops) &&
  2023. event == NETDEV_CHANGENAME)
  2024. efx_update_name(netdev_priv(net_dev));
  2025. return NOTIFY_DONE;
  2026. }
  2027. static struct notifier_block efx_netdev_notifier = {
  2028. .notifier_call = efx_netdev_event,
  2029. };
  2030. static ssize_t
  2031. show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
  2032. {
  2033. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  2034. return sprintf(buf, "%d\n", efx->phy_type);
  2035. }
  2036. static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
  2037. #ifdef CONFIG_SFC_MCDI_LOGGING
  2038. static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr,
  2039. char *buf)
  2040. {
  2041. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  2042. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  2043. return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled);
  2044. }
  2045. static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr,
  2046. const char *buf, size_t count)
  2047. {
  2048. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  2049. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  2050. bool enable = count > 0 && *buf != '0';
  2051. mcdi->logging_enabled = enable;
  2052. return count;
  2053. }
  2054. static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log);
  2055. #endif
  2056. static int efx_register_netdev(struct efx_nic *efx)
  2057. {
  2058. struct net_device *net_dev = efx->net_dev;
  2059. struct efx_channel *channel;
  2060. int rc;
  2061. net_dev->watchdog_timeo = 5 * HZ;
  2062. net_dev->irq = efx->pci_dev->irq;
  2063. net_dev->netdev_ops = &efx_netdev_ops;
  2064. if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
  2065. net_dev->priv_flags |= IFF_UNICAST_FLT;
  2066. net_dev->ethtool_ops = &efx_ethtool_ops;
  2067. net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
  2068. rtnl_lock();
  2069. /* Enable resets to be scheduled and check whether any were
  2070. * already requested. If so, the NIC is probably hosed so we
  2071. * abort.
  2072. */
  2073. efx->state = STATE_READY;
  2074. smp_mb(); /* ensure we change state before checking reset_pending */
  2075. if (efx->reset_pending) {
  2076. netif_err(efx, probe, efx->net_dev,
  2077. "aborting probe due to scheduled reset\n");
  2078. rc = -EIO;
  2079. goto fail_locked;
  2080. }
  2081. rc = dev_alloc_name(net_dev, net_dev->name);
  2082. if (rc < 0)
  2083. goto fail_locked;
  2084. efx_update_name(efx);
  2085. /* Always start with carrier off; PHY events will detect the link */
  2086. netif_carrier_off(net_dev);
  2087. rc = register_netdevice(net_dev);
  2088. if (rc)
  2089. goto fail_locked;
  2090. efx_for_each_channel(channel, efx) {
  2091. struct efx_tx_queue *tx_queue;
  2092. efx_for_each_channel_tx_queue(tx_queue, channel)
  2093. efx_init_tx_queue_core_txq(tx_queue);
  2094. }
  2095. efx_associate(efx);
  2096. rtnl_unlock();
  2097. rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
  2098. if (rc) {
  2099. netif_err(efx, drv, efx->net_dev,
  2100. "failed to init net dev attributes\n");
  2101. goto fail_registered;
  2102. }
  2103. #ifdef CONFIG_SFC_MCDI_LOGGING
  2104. rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
  2105. if (rc) {
  2106. netif_err(efx, drv, efx->net_dev,
  2107. "failed to init net dev attributes\n");
  2108. goto fail_attr_mcdi_logging;
  2109. }
  2110. #endif
  2111. return 0;
  2112. #ifdef CONFIG_SFC_MCDI_LOGGING
  2113. fail_attr_mcdi_logging:
  2114. device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
  2115. #endif
  2116. fail_registered:
  2117. rtnl_lock();
  2118. efx_dissociate(efx);
  2119. unregister_netdevice(net_dev);
  2120. fail_locked:
  2121. efx->state = STATE_UNINIT;
  2122. rtnl_unlock();
  2123. netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
  2124. return rc;
  2125. }
  2126. static void efx_unregister_netdev(struct efx_nic *efx)
  2127. {
  2128. if (!efx->net_dev)
  2129. return;
  2130. BUG_ON(netdev_priv(efx->net_dev) != efx);
  2131. if (efx_dev_registered(efx)) {
  2132. strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
  2133. #ifdef CONFIG_SFC_MCDI_LOGGING
  2134. device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
  2135. #endif
  2136. device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
  2137. unregister_netdev(efx->net_dev);
  2138. }
  2139. }
  2140. /**************************************************************************
  2141. *
  2142. * Device reset and suspend
  2143. *
  2144. **************************************************************************/
  2145. /* Tears down the entire software state and most of the hardware state
  2146. * before reset. */
  2147. void efx_reset_down(struct efx_nic *efx, enum reset_type method)
  2148. {
  2149. EFX_ASSERT_RESET_SERIALISED(efx);
  2150. if (method == RESET_TYPE_MCDI_TIMEOUT)
  2151. efx->type->prepare_flr(efx);
  2152. efx_stop_all(efx);
  2153. efx_disable_interrupts(efx);
  2154. mutex_lock(&efx->mac_lock);
  2155. if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
  2156. method != RESET_TYPE_DATAPATH)
  2157. efx->phy_op->fini(efx);
  2158. efx->type->fini(efx);
  2159. }
  2160. /* This function will always ensure that the locks acquired in
  2161. * efx_reset_down() are released. A failure return code indicates
  2162. * that we were unable to reinitialise the hardware, and the
  2163. * driver should be disabled. If ok is false, then the rx and tx
  2164. * engines are not restarted, pending a RESET_DISABLE. */
  2165. int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
  2166. {
  2167. int rc;
  2168. EFX_ASSERT_RESET_SERIALISED(efx);
  2169. if (method == RESET_TYPE_MCDI_TIMEOUT)
  2170. efx->type->finish_flr(efx);
  2171. /* Ensure that SRAM is initialised even if we're disabling the device */
  2172. rc = efx->type->init(efx);
  2173. if (rc) {
  2174. netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
  2175. goto fail;
  2176. }
  2177. if (!ok)
  2178. goto fail;
  2179. if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
  2180. method != RESET_TYPE_DATAPATH) {
  2181. rc = efx->phy_op->init(efx);
  2182. if (rc)
  2183. goto fail;
  2184. rc = efx->phy_op->reconfigure(efx);
  2185. if (rc && rc != -EPERM)
  2186. netif_err(efx, drv, efx->net_dev,
  2187. "could not restore PHY settings\n");
  2188. }
  2189. rc = efx_enable_interrupts(efx);
  2190. if (rc)
  2191. goto fail;
  2192. #ifdef CONFIG_SFC_SRIOV
  2193. rc = efx->type->vswitching_restore(efx);
  2194. if (rc) /* not fatal; the PF will still work fine */
  2195. netif_warn(efx, probe, efx->net_dev,
  2196. "failed to restore vswitching rc=%d;"
  2197. " VFs may not function\n", rc);
  2198. #endif
  2199. down_read(&efx->filter_sem);
  2200. efx_restore_filters(efx);
  2201. up_read(&efx->filter_sem);
  2202. if (efx->type->sriov_reset)
  2203. efx->type->sriov_reset(efx);
  2204. mutex_unlock(&efx->mac_lock);
  2205. efx_start_all(efx);
  2206. return 0;
  2207. fail:
  2208. efx->port_initialized = false;
  2209. mutex_unlock(&efx->mac_lock);
  2210. return rc;
  2211. }
  2212. /* Reset the NIC using the specified method. Note that the reset may
  2213. * fail, in which case the card will be left in an unusable state.
  2214. *
  2215. * Caller must hold the rtnl_lock.
  2216. */
  2217. int efx_reset(struct efx_nic *efx, enum reset_type method)
  2218. {
  2219. int rc, rc2;
  2220. bool disabled;
  2221. netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
  2222. RESET_TYPE(method));
  2223. efx_device_detach_sync(efx);
  2224. efx_reset_down(efx, method);
  2225. rc = efx->type->reset(efx, method);
  2226. if (rc) {
  2227. netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
  2228. goto out;
  2229. }
  2230. /* Clear flags for the scopes we covered. We assume the NIC and
  2231. * driver are now quiescent so that there is no race here.
  2232. */
  2233. if (method < RESET_TYPE_MAX_METHOD)
  2234. efx->reset_pending &= -(1 << (method + 1));
  2235. else /* it doesn't fit into the well-ordered scope hierarchy */
  2236. __clear_bit(method, &efx->reset_pending);
  2237. /* Reinitialise bus-mastering, which may have been turned off before
  2238. * the reset was scheduled. This is still appropriate, even in the
  2239. * RESET_TYPE_DISABLE since this driver generally assumes the hardware
  2240. * can respond to requests. */
  2241. pci_set_master(efx->pci_dev);
  2242. out:
  2243. /* Leave device stopped if necessary */
  2244. disabled = rc ||
  2245. method == RESET_TYPE_DISABLE ||
  2246. method == RESET_TYPE_RECOVER_OR_DISABLE;
  2247. rc2 = efx_reset_up(efx, method, !disabled);
  2248. if (rc2) {
  2249. disabled = true;
  2250. if (!rc)
  2251. rc = rc2;
  2252. }
  2253. if (disabled) {
  2254. dev_close(efx->net_dev);
  2255. netif_err(efx, drv, efx->net_dev, "has been disabled\n");
  2256. efx->state = STATE_DISABLED;
  2257. } else {
  2258. netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
  2259. netif_device_attach(efx->net_dev);
  2260. }
  2261. return rc;
  2262. }
  2263. /* Try recovery mechanisms.
  2264. * For now only EEH is supported.
  2265. * Returns 0 if the recovery mechanisms are unsuccessful.
  2266. * Returns a non-zero value otherwise.
  2267. */
  2268. int efx_try_recovery(struct efx_nic *efx)
  2269. {
  2270. #ifdef CONFIG_EEH
  2271. /* A PCI error can occur and not be seen by EEH because nothing
  2272. * happens on the PCI bus. In this case the driver may fail and
  2273. * schedule a 'recover or reset', leading to this recovery handler.
  2274. * Manually call the eeh failure check function.
  2275. */
  2276. struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
  2277. if (eeh_dev_check_failure(eehdev)) {
  2278. /* The EEH mechanisms will handle the error and reset the
  2279. * device if necessary.
  2280. */
  2281. return 1;
  2282. }
  2283. #endif
  2284. return 0;
  2285. }
  2286. static void efx_wait_for_bist_end(struct efx_nic *efx)
  2287. {
  2288. int i;
  2289. for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
  2290. if (efx_mcdi_poll_reboot(efx))
  2291. goto out;
  2292. msleep(BIST_WAIT_DELAY_MS);
  2293. }
  2294. netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
  2295. out:
  2296. /* Either way unset the BIST flag. If we found no reboot we probably
  2297. * won't recover, but we should try.
  2298. */
  2299. efx->mc_bist_for_other_fn = false;
  2300. }
  2301. /* The worker thread exists so that code that cannot sleep can
  2302. * schedule a reset for later.
  2303. */
  2304. static void efx_reset_work(struct work_struct *data)
  2305. {
  2306. struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
  2307. unsigned long pending;
  2308. enum reset_type method;
  2309. pending = ACCESS_ONCE(efx->reset_pending);
  2310. method = fls(pending) - 1;
  2311. if (method == RESET_TYPE_MC_BIST)
  2312. efx_wait_for_bist_end(efx);
  2313. if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
  2314. method == RESET_TYPE_RECOVER_OR_ALL) &&
  2315. efx_try_recovery(efx))
  2316. return;
  2317. if (!pending)
  2318. return;
  2319. rtnl_lock();
  2320. /* We checked the state in efx_schedule_reset() but it may
  2321. * have changed by now. Now that we have the RTNL lock,
  2322. * it cannot change again.
  2323. */
  2324. if (efx->state == STATE_READY)
  2325. (void)efx_reset(efx, method);
  2326. rtnl_unlock();
  2327. }
  2328. void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
  2329. {
  2330. enum reset_type method;
  2331. if (efx->state == STATE_RECOVERY) {
  2332. netif_dbg(efx, drv, efx->net_dev,
  2333. "recovering: skip scheduling %s reset\n",
  2334. RESET_TYPE(type));
  2335. return;
  2336. }
  2337. switch (type) {
  2338. case RESET_TYPE_INVISIBLE:
  2339. case RESET_TYPE_ALL:
  2340. case RESET_TYPE_RECOVER_OR_ALL:
  2341. case RESET_TYPE_WORLD:
  2342. case RESET_TYPE_DISABLE:
  2343. case RESET_TYPE_RECOVER_OR_DISABLE:
  2344. case RESET_TYPE_DATAPATH:
  2345. case RESET_TYPE_MC_BIST:
  2346. case RESET_TYPE_MCDI_TIMEOUT:
  2347. method = type;
  2348. netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
  2349. RESET_TYPE(method));
  2350. break;
  2351. default:
  2352. method = efx->type->map_reset_reason(type);
  2353. netif_dbg(efx, drv, efx->net_dev,
  2354. "scheduling %s reset for %s\n",
  2355. RESET_TYPE(method), RESET_TYPE(type));
  2356. break;
  2357. }
  2358. set_bit(method, &efx->reset_pending);
  2359. smp_mb(); /* ensure we change reset_pending before checking state */
  2360. /* If we're not READY then just leave the flags set as the cue
  2361. * to abort probing or reschedule the reset later.
  2362. */
  2363. if (ACCESS_ONCE(efx->state) != STATE_READY)
  2364. return;
  2365. /* efx_process_channel() will no longer read events once a
  2366. * reset is scheduled. So switch back to poll'd MCDI completions. */
  2367. efx_mcdi_mode_poll(efx);
  2368. queue_work(reset_workqueue, &efx->reset_work);
  2369. }
  2370. /**************************************************************************
  2371. *
  2372. * List of NICs we support
  2373. *
  2374. **************************************************************************/
  2375. /* PCI device ID table */
  2376. static const struct pci_device_id efx_pci_table[] = {
  2377. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
  2378. PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
  2379. .driver_data = (unsigned long) &falcon_a1_nic_type},
  2380. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
  2381. PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
  2382. .driver_data = (unsigned long) &falcon_b0_nic_type},
  2383. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
  2384. .driver_data = (unsigned long) &siena_a0_nic_type},
  2385. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
  2386. .driver_data = (unsigned long) &siena_a0_nic_type},
  2387. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
  2388. .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
  2389. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */
  2390. .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
  2391. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */
  2392. .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
  2393. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */
  2394. .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
  2395. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */
  2396. .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
  2397. {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */
  2398. .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
  2399. {0} /* end of list */
  2400. };
  2401. /**************************************************************************
  2402. *
  2403. * Dummy PHY/MAC operations
  2404. *
  2405. * Can be used for some unimplemented operations
  2406. * Needed so all function pointers are valid and do not have to be tested
  2407. * before use
  2408. *
  2409. **************************************************************************/
  2410. int efx_port_dummy_op_int(struct efx_nic *efx)
  2411. {
  2412. return 0;
  2413. }
  2414. void efx_port_dummy_op_void(struct efx_nic *efx) {}
  2415. static bool efx_port_dummy_op_poll(struct efx_nic *efx)
  2416. {
  2417. return false;
  2418. }
  2419. static const struct efx_phy_operations efx_dummy_phy_operations = {
  2420. .init = efx_port_dummy_op_int,
  2421. .reconfigure = efx_port_dummy_op_int,
  2422. .poll = efx_port_dummy_op_poll,
  2423. .fini = efx_port_dummy_op_void,
  2424. };
  2425. /**************************************************************************
  2426. *
  2427. * Data housekeeping
  2428. *
  2429. **************************************************************************/
  2430. /* This zeroes out and then fills in the invariants in a struct
  2431. * efx_nic (including all sub-structures).
  2432. */
  2433. static int efx_init_struct(struct efx_nic *efx,
  2434. struct pci_dev *pci_dev, struct net_device *net_dev)
  2435. {
  2436. int i;
  2437. /* Initialise common structures */
  2438. INIT_LIST_HEAD(&efx->node);
  2439. INIT_LIST_HEAD(&efx->secondary_list);
  2440. spin_lock_init(&efx->biu_lock);
  2441. #ifdef CONFIG_SFC_MTD
  2442. INIT_LIST_HEAD(&efx->mtd_list);
  2443. #endif
  2444. INIT_WORK(&efx->reset_work, efx_reset_work);
  2445. INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
  2446. INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
  2447. efx->pci_dev = pci_dev;
  2448. efx->msg_enable = debug;
  2449. efx->state = STATE_UNINIT;
  2450. strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
  2451. efx->net_dev = net_dev;
  2452. efx->rx_prefix_size = efx->type->rx_prefix_size;
  2453. efx->rx_ip_align =
  2454. NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
  2455. efx->rx_packet_hash_offset =
  2456. efx->type->rx_hash_offset - efx->type->rx_prefix_size;
  2457. efx->rx_packet_ts_offset =
  2458. efx->type->rx_ts_offset - efx->type->rx_prefix_size;
  2459. spin_lock_init(&efx->stats_lock);
  2460. mutex_init(&efx->mac_lock);
  2461. efx->phy_op = &efx_dummy_phy_operations;
  2462. efx->mdio.dev = net_dev;
  2463. INIT_WORK(&efx->mac_work, efx_mac_work);
  2464. init_waitqueue_head(&efx->flush_wq);
  2465. for (i = 0; i < EFX_MAX_CHANNELS; i++) {
  2466. efx->channel[i] = efx_alloc_channel(efx, i, NULL);
  2467. if (!efx->channel[i])
  2468. goto fail;
  2469. efx->msi_context[i].efx = efx;
  2470. efx->msi_context[i].index = i;
  2471. }
  2472. /* Higher numbered interrupt modes are less capable! */
  2473. efx->interrupt_mode = max(efx->type->max_interrupt_mode,
  2474. interrupt_mode);
  2475. /* Would be good to use the net_dev name, but we're too early */
  2476. snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
  2477. pci_name(pci_dev));
  2478. efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
  2479. if (!efx->workqueue)
  2480. goto fail;
  2481. return 0;
  2482. fail:
  2483. efx_fini_struct(efx);
  2484. return -ENOMEM;
  2485. }
  2486. static void efx_fini_struct(struct efx_nic *efx)
  2487. {
  2488. int i;
  2489. for (i = 0; i < EFX_MAX_CHANNELS; i++)
  2490. kfree(efx->channel[i]);
  2491. kfree(efx->vpd_sn);
  2492. if (efx->workqueue) {
  2493. destroy_workqueue(efx->workqueue);
  2494. efx->workqueue = NULL;
  2495. }
  2496. }
  2497. void efx_update_sw_stats(struct efx_nic *efx, u64 *stats)
  2498. {
  2499. u64 n_rx_nodesc_trunc = 0;
  2500. struct efx_channel *channel;
  2501. efx_for_each_channel(channel, efx)
  2502. n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc;
  2503. stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc;
  2504. stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops);
  2505. }
  2506. /**************************************************************************
  2507. *
  2508. * PCI interface
  2509. *
  2510. **************************************************************************/
  2511. /* Main body of final NIC shutdown code
  2512. * This is called only at module unload (or hotplug removal).
  2513. */
  2514. static void efx_pci_remove_main(struct efx_nic *efx)
  2515. {
  2516. /* Flush reset_work. It can no longer be scheduled since we
  2517. * are not READY.
  2518. */
  2519. BUG_ON(efx->state == STATE_READY);
  2520. cancel_work_sync(&efx->reset_work);
  2521. efx_disable_interrupts(efx);
  2522. efx_nic_fini_interrupt(efx);
  2523. efx_fini_port(efx);
  2524. efx->type->fini(efx);
  2525. efx_fini_napi(efx);
  2526. efx_remove_all(efx);
  2527. }
  2528. /* Final NIC shutdown
  2529. * This is called only at module unload (or hotplug removal). A PF can call
  2530. * this on its VFs to ensure they are unbound first.
  2531. */
  2532. static void efx_pci_remove(struct pci_dev *pci_dev)
  2533. {
  2534. struct efx_nic *efx;
  2535. efx = pci_get_drvdata(pci_dev);
  2536. if (!efx)
  2537. return;
  2538. /* Mark the NIC as fini, then stop the interface */
  2539. rtnl_lock();
  2540. efx_dissociate(efx);
  2541. dev_close(efx->net_dev);
  2542. efx_disable_interrupts(efx);
  2543. efx->state = STATE_UNINIT;
  2544. rtnl_unlock();
  2545. if (efx->type->sriov_fini)
  2546. efx->type->sriov_fini(efx);
  2547. efx_unregister_netdev(efx);
  2548. efx_mtd_remove(efx);
  2549. efx_pci_remove_main(efx);
  2550. efx_fini_io(efx);
  2551. netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
  2552. efx_fini_struct(efx);
  2553. free_netdev(efx->net_dev);
  2554. pci_disable_pcie_error_reporting(pci_dev);
  2555. };
  2556. /* NIC VPD information
  2557. * Called during probe to display the part number of the
  2558. * installed NIC. VPD is potentially very large but this should
  2559. * always appear within the first 512 bytes.
  2560. */
  2561. #define SFC_VPD_LEN 512
  2562. static void efx_probe_vpd_strings(struct efx_nic *efx)
  2563. {
  2564. struct pci_dev *dev = efx->pci_dev;
  2565. char vpd_data[SFC_VPD_LEN];
  2566. ssize_t vpd_size;
  2567. int ro_start, ro_size, i, j;
  2568. /* Get the vpd data from the device */
  2569. vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
  2570. if (vpd_size <= 0) {
  2571. netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
  2572. return;
  2573. }
  2574. /* Get the Read only section */
  2575. ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
  2576. if (ro_start < 0) {
  2577. netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
  2578. return;
  2579. }
  2580. ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
  2581. j = ro_size;
  2582. i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
  2583. if (i + j > vpd_size)
  2584. j = vpd_size - i;
  2585. /* Get the Part number */
  2586. i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
  2587. if (i < 0) {
  2588. netif_err(efx, drv, efx->net_dev, "Part number not found\n");
  2589. return;
  2590. }
  2591. j = pci_vpd_info_field_size(&vpd_data[i]);
  2592. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  2593. if (i + j > vpd_size) {
  2594. netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
  2595. return;
  2596. }
  2597. netif_info(efx, drv, efx->net_dev,
  2598. "Part Number : %.*s\n", j, &vpd_data[i]);
  2599. i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
  2600. j = ro_size;
  2601. i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN");
  2602. if (i < 0) {
  2603. netif_err(efx, drv, efx->net_dev, "Serial number not found\n");
  2604. return;
  2605. }
  2606. j = pci_vpd_info_field_size(&vpd_data[i]);
  2607. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  2608. if (i + j > vpd_size) {
  2609. netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n");
  2610. return;
  2611. }
  2612. efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL);
  2613. if (!efx->vpd_sn)
  2614. return;
  2615. snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]);
  2616. }
  2617. /* Main body of NIC initialisation
  2618. * This is called at module load (or hotplug insertion, theoretically).
  2619. */
  2620. static int efx_pci_probe_main(struct efx_nic *efx)
  2621. {
  2622. int rc;
  2623. /* Do start-of-day initialisation */
  2624. rc = efx_probe_all(efx);
  2625. if (rc)
  2626. goto fail1;
  2627. efx_init_napi(efx);
  2628. rc = efx->type->init(efx);
  2629. if (rc) {
  2630. netif_err(efx, probe, efx->net_dev,
  2631. "failed to initialise NIC\n");
  2632. goto fail3;
  2633. }
  2634. rc = efx_init_port(efx);
  2635. if (rc) {
  2636. netif_err(efx, probe, efx->net_dev,
  2637. "failed to initialise port\n");
  2638. goto fail4;
  2639. }
  2640. rc = efx_nic_init_interrupt(efx);
  2641. if (rc)
  2642. goto fail5;
  2643. rc = efx_enable_interrupts(efx);
  2644. if (rc)
  2645. goto fail6;
  2646. return 0;
  2647. fail6:
  2648. efx_nic_fini_interrupt(efx);
  2649. fail5:
  2650. efx_fini_port(efx);
  2651. fail4:
  2652. efx->type->fini(efx);
  2653. fail3:
  2654. efx_fini_napi(efx);
  2655. efx_remove_all(efx);
  2656. fail1:
  2657. return rc;
  2658. }
  2659. /* NIC initialisation
  2660. *
  2661. * This is called at module load (or hotplug insertion,
  2662. * theoretically). It sets up PCI mappings, resets the NIC,
  2663. * sets up and registers the network devices with the kernel and hooks
  2664. * the interrupt service routine. It does not prepare the device for
  2665. * transmission; this is left to the first time one of the network
  2666. * interfaces is brought up (i.e. efx_net_open).
  2667. */
  2668. static int efx_pci_probe(struct pci_dev *pci_dev,
  2669. const struct pci_device_id *entry)
  2670. {
  2671. struct net_device *net_dev;
  2672. struct efx_nic *efx;
  2673. int rc;
  2674. /* Allocate and initialise a struct net_device and struct efx_nic */
  2675. net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
  2676. EFX_MAX_RX_QUEUES);
  2677. if (!net_dev)
  2678. return -ENOMEM;
  2679. efx = netdev_priv(net_dev);
  2680. efx->type = (const struct efx_nic_type *) entry->driver_data;
  2681. efx->fixed_features |= NETIF_F_HIGHDMA;
  2682. net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
  2683. NETIF_F_TSO | NETIF_F_RXCSUM);
  2684. if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM))
  2685. net_dev->features |= NETIF_F_TSO6;
  2686. /* Mask for features that also apply to VLAN devices */
  2687. net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG |
  2688. NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
  2689. NETIF_F_RXCSUM);
  2690. net_dev->hw_features = net_dev->features & ~efx->fixed_features;
  2691. /* Disable VLAN filtering by default. It may be enforced if
  2692. * the feature is fixed (i.e. VLAN filters are required to
  2693. * receive VLAN tagged packets due to vPort restrictions).
  2694. */
  2695. net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
  2696. net_dev->features |= efx->fixed_features;
  2697. pci_set_drvdata(pci_dev, efx);
  2698. SET_NETDEV_DEV(net_dev, &pci_dev->dev);
  2699. rc = efx_init_struct(efx, pci_dev, net_dev);
  2700. if (rc)
  2701. goto fail1;
  2702. netif_info(efx, probe, efx->net_dev,
  2703. "Solarflare NIC detected\n");
  2704. if (!efx->type->is_vf)
  2705. efx_probe_vpd_strings(efx);
  2706. /* Set up basic I/O (BAR mappings etc) */
  2707. rc = efx_init_io(efx);
  2708. if (rc)
  2709. goto fail2;
  2710. rc = efx_pci_probe_main(efx);
  2711. if (rc)
  2712. goto fail3;
  2713. rc = efx_register_netdev(efx);
  2714. if (rc)
  2715. goto fail4;
  2716. if (efx->type->sriov_init) {
  2717. rc = efx->type->sriov_init(efx);
  2718. if (rc)
  2719. netif_err(efx, probe, efx->net_dev,
  2720. "SR-IOV can't be enabled rc %d\n", rc);
  2721. }
  2722. netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
  2723. /* Try to create MTDs, but allow this to fail */
  2724. rtnl_lock();
  2725. rc = efx_mtd_probe(efx);
  2726. rtnl_unlock();
  2727. if (rc && rc != -EPERM)
  2728. netif_warn(efx, probe, efx->net_dev,
  2729. "failed to create MTDs (%d)\n", rc);
  2730. rc = pci_enable_pcie_error_reporting(pci_dev);
  2731. if (rc && rc != -EINVAL)
  2732. netif_notice(efx, probe, efx->net_dev,
  2733. "PCIE error reporting unavailable (%d).\n",
  2734. rc);
  2735. return 0;
  2736. fail4:
  2737. efx_pci_remove_main(efx);
  2738. fail3:
  2739. efx_fini_io(efx);
  2740. fail2:
  2741. efx_fini_struct(efx);
  2742. fail1:
  2743. WARN_ON(rc > 0);
  2744. netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
  2745. free_netdev(net_dev);
  2746. return rc;
  2747. }
  2748. /* efx_pci_sriov_configure returns the actual number of Virtual Functions
  2749. * enabled on success
  2750. */
  2751. #ifdef CONFIG_SFC_SRIOV
  2752. static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
  2753. {
  2754. int rc;
  2755. struct efx_nic *efx = pci_get_drvdata(dev);
  2756. if (efx->type->sriov_configure) {
  2757. rc = efx->type->sriov_configure(efx, num_vfs);
  2758. if (rc)
  2759. return rc;
  2760. else
  2761. return num_vfs;
  2762. } else
  2763. return -EOPNOTSUPP;
  2764. }
  2765. #endif
  2766. static int efx_pm_freeze(struct device *dev)
  2767. {
  2768. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  2769. rtnl_lock();
  2770. if (efx->state != STATE_DISABLED) {
  2771. efx->state = STATE_UNINIT;
  2772. efx_device_detach_sync(efx);
  2773. efx_stop_all(efx);
  2774. efx_disable_interrupts(efx);
  2775. }
  2776. rtnl_unlock();
  2777. return 0;
  2778. }
  2779. static int efx_pm_thaw(struct device *dev)
  2780. {
  2781. int rc;
  2782. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  2783. rtnl_lock();
  2784. if (efx->state != STATE_DISABLED) {
  2785. rc = efx_enable_interrupts(efx);
  2786. if (rc)
  2787. goto fail;
  2788. mutex_lock(&efx->mac_lock);
  2789. efx->phy_op->reconfigure(efx);
  2790. mutex_unlock(&efx->mac_lock);
  2791. efx_start_all(efx);
  2792. netif_device_attach(efx->net_dev);
  2793. efx->state = STATE_READY;
  2794. efx->type->resume_wol(efx);
  2795. }
  2796. rtnl_unlock();
  2797. /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
  2798. queue_work(reset_workqueue, &efx->reset_work);
  2799. return 0;
  2800. fail:
  2801. rtnl_unlock();
  2802. return rc;
  2803. }
  2804. static int efx_pm_poweroff(struct device *dev)
  2805. {
  2806. struct pci_dev *pci_dev = to_pci_dev(dev);
  2807. struct efx_nic *efx = pci_get_drvdata(pci_dev);
  2808. efx->type->fini(efx);
  2809. efx->reset_pending = 0;
  2810. pci_save_state(pci_dev);
  2811. return pci_set_power_state(pci_dev, PCI_D3hot);
  2812. }
  2813. /* Used for both resume and restore */
  2814. static int efx_pm_resume(struct device *dev)
  2815. {
  2816. struct pci_dev *pci_dev = to_pci_dev(dev);
  2817. struct efx_nic *efx = pci_get_drvdata(pci_dev);
  2818. int rc;
  2819. rc = pci_set_power_state(pci_dev, PCI_D0);
  2820. if (rc)
  2821. return rc;
  2822. pci_restore_state(pci_dev);
  2823. rc = pci_enable_device(pci_dev);
  2824. if (rc)
  2825. return rc;
  2826. pci_set_master(efx->pci_dev);
  2827. rc = efx->type->reset(efx, RESET_TYPE_ALL);
  2828. if (rc)
  2829. return rc;
  2830. rc = efx->type->init(efx);
  2831. if (rc)
  2832. return rc;
  2833. rc = efx_pm_thaw(dev);
  2834. return rc;
  2835. }
  2836. static int efx_pm_suspend(struct device *dev)
  2837. {
  2838. int rc;
  2839. efx_pm_freeze(dev);
  2840. rc = efx_pm_poweroff(dev);
  2841. if (rc)
  2842. efx_pm_resume(dev);
  2843. return rc;
  2844. }
  2845. static const struct dev_pm_ops efx_pm_ops = {
  2846. .suspend = efx_pm_suspend,
  2847. .resume = efx_pm_resume,
  2848. .freeze = efx_pm_freeze,
  2849. .thaw = efx_pm_thaw,
  2850. .poweroff = efx_pm_poweroff,
  2851. .restore = efx_pm_resume,
  2852. };
  2853. /* A PCI error affecting this device was detected.
  2854. * At this point MMIO and DMA may be disabled.
  2855. * Stop the software path and request a slot reset.
  2856. */
  2857. static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
  2858. enum pci_channel_state state)
  2859. {
  2860. pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
  2861. struct efx_nic *efx = pci_get_drvdata(pdev);
  2862. if (state == pci_channel_io_perm_failure)
  2863. return PCI_ERS_RESULT_DISCONNECT;
  2864. rtnl_lock();
  2865. if (efx->state != STATE_DISABLED) {
  2866. efx->state = STATE_RECOVERY;
  2867. efx->reset_pending = 0;
  2868. efx_device_detach_sync(efx);
  2869. efx_stop_all(efx);
  2870. efx_disable_interrupts(efx);
  2871. status = PCI_ERS_RESULT_NEED_RESET;
  2872. } else {
  2873. /* If the interface is disabled we don't want to do anything
  2874. * with it.
  2875. */
  2876. status = PCI_ERS_RESULT_RECOVERED;
  2877. }
  2878. rtnl_unlock();
  2879. pci_disable_device(pdev);
  2880. return status;
  2881. }
  2882. /* Fake a successful reset, which will be performed later in efx_io_resume. */
  2883. static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
  2884. {
  2885. struct efx_nic *efx = pci_get_drvdata(pdev);
  2886. pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
  2887. int rc;
  2888. if (pci_enable_device(pdev)) {
  2889. netif_err(efx, hw, efx->net_dev,
  2890. "Cannot re-enable PCI device after reset.\n");
  2891. status = PCI_ERS_RESULT_DISCONNECT;
  2892. }
  2893. rc = pci_cleanup_aer_uncorrect_error_status(pdev);
  2894. if (rc) {
  2895. netif_err(efx, hw, efx->net_dev,
  2896. "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
  2897. /* Non-fatal error. Continue. */
  2898. }
  2899. return status;
  2900. }
  2901. /* Perform the actual reset and resume I/O operations. */
  2902. static void efx_io_resume(struct pci_dev *pdev)
  2903. {
  2904. struct efx_nic *efx = pci_get_drvdata(pdev);
  2905. int rc;
  2906. rtnl_lock();
  2907. if (efx->state == STATE_DISABLED)
  2908. goto out;
  2909. rc = efx_reset(efx, RESET_TYPE_ALL);
  2910. if (rc) {
  2911. netif_err(efx, hw, efx->net_dev,
  2912. "efx_reset failed after PCI error (%d)\n", rc);
  2913. } else {
  2914. efx->state = STATE_READY;
  2915. netif_dbg(efx, hw, efx->net_dev,
  2916. "Done resetting and resuming IO after PCI error.\n");
  2917. }
  2918. out:
  2919. rtnl_unlock();
  2920. }
  2921. /* For simplicity and reliability, we always require a slot reset and try to
  2922. * reset the hardware when a pci error affecting the device is detected.
  2923. * We leave both the link_reset and mmio_enabled callback unimplemented:
  2924. * with our request for slot reset the mmio_enabled callback will never be
  2925. * called, and the link_reset callback is not used by AER or EEH mechanisms.
  2926. */
  2927. static const struct pci_error_handlers efx_err_handlers = {
  2928. .error_detected = efx_io_error_detected,
  2929. .slot_reset = efx_io_slot_reset,
  2930. .resume = efx_io_resume,
  2931. };
  2932. static struct pci_driver efx_pci_driver = {
  2933. .name = KBUILD_MODNAME,
  2934. .id_table = efx_pci_table,
  2935. .probe = efx_pci_probe,
  2936. .remove = efx_pci_remove,
  2937. .driver.pm = &efx_pm_ops,
  2938. .err_handler = &efx_err_handlers,
  2939. #ifdef CONFIG_SFC_SRIOV
  2940. .sriov_configure = efx_pci_sriov_configure,
  2941. #endif
  2942. };
  2943. /**************************************************************************
  2944. *
  2945. * Kernel module interface
  2946. *
  2947. *************************************************************************/
  2948. module_param(interrupt_mode, uint, 0444);
  2949. MODULE_PARM_DESC(interrupt_mode,
  2950. "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
  2951. static int __init efx_init_module(void)
  2952. {
  2953. int rc;
  2954. printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
  2955. rc = register_netdevice_notifier(&efx_netdev_notifier);
  2956. if (rc)
  2957. goto err_notifier;
  2958. #ifdef CONFIG_SFC_SRIOV
  2959. rc = efx_init_sriov();
  2960. if (rc)
  2961. goto err_sriov;
  2962. #endif
  2963. reset_workqueue = create_singlethread_workqueue("sfc_reset");
  2964. if (!reset_workqueue) {
  2965. rc = -ENOMEM;
  2966. goto err_reset;
  2967. }
  2968. rc = pci_register_driver(&efx_pci_driver);
  2969. if (rc < 0)
  2970. goto err_pci;
  2971. return 0;
  2972. err_pci:
  2973. destroy_workqueue(reset_workqueue);
  2974. err_reset:
  2975. #ifdef CONFIG_SFC_SRIOV
  2976. efx_fini_sriov();
  2977. err_sriov:
  2978. #endif
  2979. unregister_netdevice_notifier(&efx_netdev_notifier);
  2980. err_notifier:
  2981. return rc;
  2982. }
  2983. static void __exit efx_exit_module(void)
  2984. {
  2985. printk(KERN_INFO "Solarflare NET driver unloading\n");
  2986. pci_unregister_driver(&efx_pci_driver);
  2987. destroy_workqueue(reset_workqueue);
  2988. #ifdef CONFIG_SFC_SRIOV
  2989. efx_fini_sriov();
  2990. #endif
  2991. unregister_netdevice_notifier(&efx_netdev_notifier);
  2992. }
  2993. module_init(efx_init_module);
  2994. module_exit(efx_exit_module);
  2995. MODULE_AUTHOR("Solarflare Communications and "
  2996. "Michael Brown <mbrown@fensystems.co.uk>");
  2997. MODULE_DESCRIPTION("Solarflare network driver");
  2998. MODULE_LICENSE("GPL");
  2999. MODULE_DEVICE_TABLE(pci, efx_pci_table);