ef10.c 156 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2012-2013 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include "net_driver.h"
  10. #include "ef10_regs.h"
  11. #include "io.h"
  12. #include "mcdi.h"
  13. #include "mcdi_pcol.h"
  14. #include "nic.h"
  15. #include "workarounds.h"
  16. #include "selftest.h"
  17. #include "ef10_sriov.h"
  18. #include <linux/in.h>
  19. #include <linux/jhash.h>
  20. #include <linux/wait.h>
  21. #include <linux/workqueue.h>
  22. /* Hardware control for EF10 architecture including 'Huntington'. */
  23. #define EFX_EF10_DRVGEN_EV 7
  24. enum {
  25. EFX_EF10_TEST = 1,
  26. EFX_EF10_REFILL,
  27. };
  28. /* The reserved RSS context value */
  29. #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
  30. /* The maximum size of a shared RSS context */
  31. /* TODO: this should really be from the mcdi protocol export */
  32. #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  33. /* The filter table(s) are managed by firmware and we have write-only
  34. * access. When removing filters we must identify them to the
  35. * firmware by a 64-bit handle, but this is too wide for Linux kernel
  36. * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
  37. * be able to tell in advance whether a requested insertion will
  38. * replace an existing filter. Therefore we maintain a software hash
  39. * table, which should be at least as large as the hardware hash
  40. * table.
  41. *
  42. * Huntington has a single 8K filter table shared between all filter
  43. * types and both ports.
  44. */
  45. #define HUNT_FILTER_TBL_ROWS 8192
  46. #define EFX_EF10_FILTER_ID_INVALID 0xffff
  47. #define EFX_EF10_FILTER_DEV_UC_MAX 32
  48. #define EFX_EF10_FILTER_DEV_MC_MAX 256
  49. /* VLAN list entry */
  50. struct efx_ef10_vlan {
  51. struct list_head list;
  52. u16 vid;
  53. };
  54. /* Per-VLAN filters information */
  55. struct efx_ef10_filter_vlan {
  56. struct list_head list;
  57. u16 vid;
  58. u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  59. u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  60. u16 ucdef;
  61. u16 bcast;
  62. u16 mcdef;
  63. };
  64. struct efx_ef10_dev_addr {
  65. u8 addr[ETH_ALEN];
  66. };
  67. struct efx_ef10_filter_table {
  68. /* The MCDI match masks supported by this fw & hw, in order of priority */
  69. u32 rx_match_mcdi_flags[
  70. MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  71. unsigned int rx_match_count;
  72. struct {
  73. unsigned long spec; /* pointer to spec plus flag bits */
  74. /* BUSY flag indicates that an update is in progress. AUTO_OLD is
  75. * used to mark and sweep MAC filters for the device address lists.
  76. */
  77. #define EFX_EF10_FILTER_FLAG_BUSY 1UL
  78. #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
  79. #define EFX_EF10_FILTER_FLAGS 3UL
  80. u64 handle; /* firmware handle */
  81. } *entry;
  82. wait_queue_head_t waitq;
  83. /* Shadow of net_device address lists, guarded by mac_lock */
  84. struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
  85. struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  86. int dev_uc_count;
  87. int dev_mc_count;
  88. bool uc_promisc;
  89. bool mc_promisc;
  90. /* Whether in multicast promiscuous mode when last changed */
  91. bool mc_promisc_last;
  92. bool vlan_filter;
  93. struct list_head vlan_list;
  94. };
  95. /* An arbitrary search limit for the software hash table */
  96. #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  97. static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  98. static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  99. static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
  100. static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
  101. struct efx_ef10_filter_vlan *vlan);
  102. static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
  103. static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  104. {
  105. efx_dword_t reg;
  106. efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  107. return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  108. EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  109. }
  110. static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  111. {
  112. int bar;
  113. bar = efx->type->mem_bar;
  114. return resource_size(&efx->pci_dev->resource[bar]);
  115. }
  116. static bool efx_ef10_is_vf(struct efx_nic *efx)
  117. {
  118. return efx->type->is_vf;
  119. }
  120. static int efx_ef10_get_pf_index(struct efx_nic *efx)
  121. {
  122. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
  123. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  124. size_t outlen;
  125. int rc;
  126. rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
  127. sizeof(outbuf), &outlen);
  128. if (rc)
  129. return rc;
  130. if (outlen < sizeof(outbuf))
  131. return -EIO;
  132. nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
  133. return 0;
  134. }
  135. #ifdef CONFIG_SFC_SRIOV
  136. static int efx_ef10_get_vf_index(struct efx_nic *efx)
  137. {
  138. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
  139. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  140. size_t outlen;
  141. int rc;
  142. rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
  143. sizeof(outbuf), &outlen);
  144. if (rc)
  145. return rc;
  146. if (outlen < sizeof(outbuf))
  147. return -EIO;
  148. nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
  149. return 0;
  150. }
  151. #endif
  152. static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
  153. {
  154. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
  155. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  156. size_t outlen;
  157. int rc;
  158. BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
  159. rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
  160. outbuf, sizeof(outbuf), &outlen);
  161. if (rc)
  162. return rc;
  163. if (outlen < sizeof(outbuf)) {
  164. netif_err(efx, drv, efx->net_dev,
  165. "unable to read datapath firmware capabilities\n");
  166. return -EIO;
  167. }
  168. nic_data->datapath_caps =
  169. MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
  170. /* record the DPCPU firmware IDs to determine VEB vswitching support.
  171. */
  172. nic_data->rx_dpcpu_fw_id =
  173. MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
  174. nic_data->tx_dpcpu_fw_id =
  175. MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
  176. if (!(nic_data->datapath_caps &
  177. (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
  178. netif_err(efx, probe, efx->net_dev,
  179. "current firmware does not support an RX prefix\n");
  180. return -ENODEV;
  181. }
  182. return 0;
  183. }
  184. static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
  185. {
  186. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
  187. int rc;
  188. rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
  189. outbuf, sizeof(outbuf), NULL);
  190. if (rc)
  191. return rc;
  192. rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
  193. return rc > 0 ? rc : -ERANGE;
  194. }
  195. static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
  196. {
  197. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
  198. size_t outlen;
  199. int rc;
  200. BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
  201. rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
  202. outbuf, sizeof(outbuf), &outlen);
  203. if (rc)
  204. return rc;
  205. if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
  206. return -EIO;
  207. ether_addr_copy(mac_address,
  208. MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
  209. return 0;
  210. }
  211. static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
  212. {
  213. MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
  214. MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
  215. size_t outlen;
  216. int num_addrs, rc;
  217. MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
  218. EVB_PORT_ID_ASSIGNED);
  219. rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
  220. sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
  221. if (rc)
  222. return rc;
  223. if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
  224. return -EIO;
  225. num_addrs = MCDI_DWORD(outbuf,
  226. VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
  227. WARN_ON(num_addrs != 1);
  228. ether_addr_copy(mac_address,
  229. MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
  230. return 0;
  231. }
  232. static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
  233. struct device_attribute *attr,
  234. char *buf)
  235. {
  236. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  237. return sprintf(buf, "%d\n",
  238. ((efx->mcdi->fn_flags) &
  239. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
  240. ? 1 : 0);
  241. }
  242. static ssize_t efx_ef10_show_primary_flag(struct device *dev,
  243. struct device_attribute *attr,
  244. char *buf)
  245. {
  246. struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
  247. return sprintf(buf, "%d\n",
  248. ((efx->mcdi->fn_flags) &
  249. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
  250. ? 1 : 0);
  251. }
  252. static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
  253. {
  254. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  255. struct efx_ef10_vlan *vlan;
  256. WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
  257. list_for_each_entry(vlan, &nic_data->vlan_list, list) {
  258. if (vlan->vid == vid)
  259. return vlan;
  260. }
  261. return NULL;
  262. }
  263. static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
  264. {
  265. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  266. struct efx_ef10_vlan *vlan;
  267. int rc;
  268. mutex_lock(&nic_data->vlan_lock);
  269. vlan = efx_ef10_find_vlan(efx, vid);
  270. if (vlan) {
  271. /* We add VID 0 on init. 8021q adds it on module init
  272. * for all interfaces with VLAN filtring feature.
  273. */
  274. if (vid == 0)
  275. goto done_unlock;
  276. netif_warn(efx, drv, efx->net_dev,
  277. "VLAN %u already added\n", vid);
  278. rc = -EALREADY;
  279. goto fail_exist;
  280. }
  281. rc = -ENOMEM;
  282. vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
  283. if (!vlan)
  284. goto fail_alloc;
  285. vlan->vid = vid;
  286. list_add_tail(&vlan->list, &nic_data->vlan_list);
  287. if (efx->filter_state) {
  288. mutex_lock(&efx->mac_lock);
  289. down_write(&efx->filter_sem);
  290. rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
  291. up_write(&efx->filter_sem);
  292. mutex_unlock(&efx->mac_lock);
  293. if (rc)
  294. goto fail_filter_add_vlan;
  295. }
  296. done_unlock:
  297. mutex_unlock(&nic_data->vlan_lock);
  298. return 0;
  299. fail_filter_add_vlan:
  300. list_del(&vlan->list);
  301. kfree(vlan);
  302. fail_alloc:
  303. fail_exist:
  304. mutex_unlock(&nic_data->vlan_lock);
  305. return rc;
  306. }
  307. static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
  308. struct efx_ef10_vlan *vlan)
  309. {
  310. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  311. WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
  312. if (efx->filter_state) {
  313. down_write(&efx->filter_sem);
  314. efx_ef10_filter_del_vlan(efx, vlan->vid);
  315. up_write(&efx->filter_sem);
  316. }
  317. list_del(&vlan->list);
  318. kfree(vlan);
  319. }
  320. static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
  321. {
  322. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  323. struct efx_ef10_vlan *vlan;
  324. int rc = 0;
  325. /* 8021q removes VID 0 on module unload for all interfaces
  326. * with VLAN filtering feature. We need to keep it to receive
  327. * untagged traffic.
  328. */
  329. if (vid == 0)
  330. return 0;
  331. mutex_lock(&nic_data->vlan_lock);
  332. vlan = efx_ef10_find_vlan(efx, vid);
  333. if (!vlan) {
  334. netif_err(efx, drv, efx->net_dev,
  335. "VLAN %u to be deleted not found\n", vid);
  336. rc = -ENOENT;
  337. } else {
  338. efx_ef10_del_vlan_internal(efx, vlan);
  339. }
  340. mutex_unlock(&nic_data->vlan_lock);
  341. return rc;
  342. }
  343. static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
  344. {
  345. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  346. struct efx_ef10_vlan *vlan, *next_vlan;
  347. mutex_lock(&nic_data->vlan_lock);
  348. list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
  349. efx_ef10_del_vlan_internal(efx, vlan);
  350. mutex_unlock(&nic_data->vlan_lock);
  351. }
  352. static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
  353. NULL);
  354. static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
  355. static int efx_ef10_probe(struct efx_nic *efx)
  356. {
  357. struct efx_ef10_nic_data *nic_data;
  358. struct net_device *net_dev = efx->net_dev;
  359. int i, rc;
  360. /* We can have one VI for each 8K region. However, until we
  361. * use TX option descriptors we need two TX queues per channel.
  362. */
  363. efx->max_channels = min_t(unsigned int,
  364. EFX_MAX_CHANNELS,
  365. efx_ef10_mem_map_size(efx) /
  366. (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
  367. efx->max_tx_channels = efx->max_channels;
  368. if (WARN_ON(efx->max_channels == 0))
  369. return -EIO;
  370. nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
  371. if (!nic_data)
  372. return -ENOMEM;
  373. efx->nic_data = nic_data;
  374. /* we assume later that we can copy from this buffer in dwords */
  375. BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
  376. rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
  377. 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
  378. if (rc)
  379. goto fail1;
  380. /* Get the MC's warm boot count. In case it's rebooting right
  381. * now, be prepared to retry.
  382. */
  383. i = 0;
  384. for (;;) {
  385. rc = efx_ef10_get_warm_boot_count(efx);
  386. if (rc >= 0)
  387. break;
  388. if (++i == 5)
  389. goto fail2;
  390. ssleep(1);
  391. }
  392. nic_data->warm_boot_count = rc;
  393. nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
  394. nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
  395. /* In case we're recovering from a crash (kexec), we want to
  396. * cancel any outstanding request by the previous user of this
  397. * function. We send a special message using the least
  398. * significant bits of the 'high' (doorbell) register.
  399. */
  400. _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
  401. rc = efx_mcdi_init(efx);
  402. if (rc)
  403. goto fail2;
  404. /* Reset (most) configuration for this function */
  405. rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
  406. if (rc)
  407. goto fail3;
  408. /* Enable event logging */
  409. rc = efx_mcdi_log_ctrl(efx, true, false, 0);
  410. if (rc)
  411. goto fail3;
  412. rc = device_create_file(&efx->pci_dev->dev,
  413. &dev_attr_link_control_flag);
  414. if (rc)
  415. goto fail3;
  416. rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
  417. if (rc)
  418. goto fail4;
  419. rc = efx_ef10_get_pf_index(efx);
  420. if (rc)
  421. goto fail5;
  422. rc = efx_ef10_init_datapath_caps(efx);
  423. if (rc < 0)
  424. goto fail5;
  425. efx->rx_packet_len_offset =
  426. ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
  427. rc = efx_mcdi_port_get_number(efx);
  428. if (rc < 0)
  429. goto fail5;
  430. efx->port_num = rc;
  431. net_dev->dev_port = rc;
  432. rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
  433. if (rc)
  434. goto fail5;
  435. rc = efx_ef10_get_sysclk_freq(efx);
  436. if (rc < 0)
  437. goto fail5;
  438. efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
  439. /* Check whether firmware supports bug 35388 workaround.
  440. * First try to enable it, then if we get EPERM, just
  441. * ask if it's already enabled
  442. */
  443. rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
  444. if (rc == 0) {
  445. nic_data->workaround_35388 = true;
  446. } else if (rc == -EPERM) {
  447. unsigned int enabled;
  448. rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
  449. if (rc)
  450. goto fail3;
  451. nic_data->workaround_35388 = enabled &
  452. MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
  453. } else if (rc != -ENOSYS && rc != -ENOENT) {
  454. goto fail5;
  455. }
  456. netif_dbg(efx, probe, efx->net_dev,
  457. "workaround for bug 35388 is %sabled\n",
  458. nic_data->workaround_35388 ? "en" : "dis");
  459. rc = efx_mcdi_mon_probe(efx);
  460. if (rc && rc != -EPERM)
  461. goto fail5;
  462. efx_ptp_probe(efx, NULL);
  463. #ifdef CONFIG_SFC_SRIOV
  464. if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
  465. struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
  466. struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
  467. efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
  468. } else
  469. #endif
  470. ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
  471. INIT_LIST_HEAD(&nic_data->vlan_list);
  472. mutex_init(&nic_data->vlan_lock);
  473. /* Add unspecified VID to support VLAN filtering being disabled */
  474. rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
  475. if (rc)
  476. goto fail_add_vid_unspec;
  477. /* If VLAN filtering is enabled, we need VID 0 to get untagged
  478. * traffic. It is added automatically if 8021q module is loaded,
  479. * but we can't rely on it since module may be not loaded.
  480. */
  481. rc = efx_ef10_add_vlan(efx, 0);
  482. if (rc)
  483. goto fail_add_vid_0;
  484. return 0;
  485. fail_add_vid_0:
  486. efx_ef10_cleanup_vlans(efx);
  487. fail_add_vid_unspec:
  488. mutex_destroy(&nic_data->vlan_lock);
  489. efx_ptp_remove(efx);
  490. efx_mcdi_mon_remove(efx);
  491. fail5:
  492. device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
  493. fail4:
  494. device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
  495. fail3:
  496. efx_mcdi_fini(efx);
  497. fail2:
  498. efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
  499. fail1:
  500. kfree(nic_data);
  501. efx->nic_data = NULL;
  502. return rc;
  503. }
  504. static int efx_ef10_free_vis(struct efx_nic *efx)
  505. {
  506. MCDI_DECLARE_BUF_ERR(outbuf);
  507. size_t outlen;
  508. int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
  509. outbuf, sizeof(outbuf), &outlen);
  510. /* -EALREADY means nothing to free, so ignore */
  511. if (rc == -EALREADY)
  512. rc = 0;
  513. if (rc)
  514. efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
  515. rc);
  516. return rc;
  517. }
  518. #ifdef EFX_USE_PIO
  519. static void efx_ef10_free_piobufs(struct efx_nic *efx)
  520. {
  521. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  522. MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
  523. unsigned int i;
  524. int rc;
  525. BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
  526. for (i = 0; i < nic_data->n_piobufs; i++) {
  527. MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
  528. nic_data->piobuf_handle[i]);
  529. rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
  530. NULL, 0, NULL);
  531. WARN_ON(rc);
  532. }
  533. nic_data->n_piobufs = 0;
  534. }
  535. static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
  536. {
  537. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  538. MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
  539. unsigned int i;
  540. size_t outlen;
  541. int rc = 0;
  542. BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
  543. for (i = 0; i < n; i++) {
  544. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
  545. outbuf, sizeof(outbuf), &outlen);
  546. if (rc) {
  547. /* Don't display the MC error if we didn't have space
  548. * for a VF.
  549. */
  550. if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
  551. efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
  552. 0, outbuf, outlen, rc);
  553. break;
  554. }
  555. if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
  556. rc = -EIO;
  557. break;
  558. }
  559. nic_data->piobuf_handle[i] =
  560. MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
  561. netif_dbg(efx, probe, efx->net_dev,
  562. "allocated PIO buffer %u handle %x\n", i,
  563. nic_data->piobuf_handle[i]);
  564. }
  565. nic_data->n_piobufs = i;
  566. if (rc)
  567. efx_ef10_free_piobufs(efx);
  568. return rc;
  569. }
  570. static int efx_ef10_link_piobufs(struct efx_nic *efx)
  571. {
  572. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  573. _MCDI_DECLARE_BUF(inbuf,
  574. max(MC_CMD_LINK_PIOBUF_IN_LEN,
  575. MC_CMD_UNLINK_PIOBUF_IN_LEN));
  576. struct efx_channel *channel;
  577. struct efx_tx_queue *tx_queue;
  578. unsigned int offset, index;
  579. int rc;
  580. BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
  581. BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
  582. memset(inbuf, 0, sizeof(inbuf));
  583. /* Link a buffer to each VI in the write-combining mapping */
  584. for (index = 0; index < nic_data->n_piobufs; ++index) {
  585. MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
  586. nic_data->piobuf_handle[index]);
  587. MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
  588. nic_data->pio_write_vi_base + index);
  589. rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
  590. inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
  591. NULL, 0, NULL);
  592. if (rc) {
  593. netif_err(efx, drv, efx->net_dev,
  594. "failed to link VI %u to PIO buffer %u (%d)\n",
  595. nic_data->pio_write_vi_base + index, index,
  596. rc);
  597. goto fail;
  598. }
  599. netif_dbg(efx, probe, efx->net_dev,
  600. "linked VI %u to PIO buffer %u\n",
  601. nic_data->pio_write_vi_base + index, index);
  602. }
  603. /* Link a buffer to each TX queue */
  604. efx_for_each_channel(channel, efx) {
  605. efx_for_each_channel_tx_queue(tx_queue, channel) {
  606. /* We assign the PIO buffers to queues in
  607. * reverse order to allow for the following
  608. * special case.
  609. */
  610. offset = ((efx->tx_channel_offset + efx->n_tx_channels -
  611. tx_queue->channel->channel - 1) *
  612. efx_piobuf_size);
  613. index = offset / ER_DZ_TX_PIOBUF_SIZE;
  614. offset = offset % ER_DZ_TX_PIOBUF_SIZE;
  615. /* When the host page size is 4K, the first
  616. * host page in the WC mapping may be within
  617. * the same VI page as the last TX queue. We
  618. * can only link one buffer to each VI.
  619. */
  620. if (tx_queue->queue == nic_data->pio_write_vi_base) {
  621. BUG_ON(index != 0);
  622. rc = 0;
  623. } else {
  624. MCDI_SET_DWORD(inbuf,
  625. LINK_PIOBUF_IN_PIOBUF_HANDLE,
  626. nic_data->piobuf_handle[index]);
  627. MCDI_SET_DWORD(inbuf,
  628. LINK_PIOBUF_IN_TXQ_INSTANCE,
  629. tx_queue->queue);
  630. rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
  631. inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
  632. NULL, 0, NULL);
  633. }
  634. if (rc) {
  635. /* This is non-fatal; the TX path just
  636. * won't use PIO for this queue
  637. */
  638. netif_err(efx, drv, efx->net_dev,
  639. "failed to link VI %u to PIO buffer %u (%d)\n",
  640. tx_queue->queue, index, rc);
  641. tx_queue->piobuf = NULL;
  642. } else {
  643. tx_queue->piobuf =
  644. nic_data->pio_write_base +
  645. index * EFX_VI_PAGE_SIZE + offset;
  646. tx_queue->piobuf_offset = offset;
  647. netif_dbg(efx, probe, efx->net_dev,
  648. "linked VI %u to PIO buffer %u offset %x addr %p\n",
  649. tx_queue->queue, index,
  650. tx_queue->piobuf_offset,
  651. tx_queue->piobuf);
  652. }
  653. }
  654. }
  655. return 0;
  656. fail:
  657. while (index--) {
  658. MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
  659. nic_data->pio_write_vi_base + index);
  660. efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
  661. inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
  662. NULL, 0, NULL);
  663. }
  664. return rc;
  665. }
  666. static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
  667. {
  668. struct efx_channel *channel;
  669. struct efx_tx_queue *tx_queue;
  670. /* All our existing PIO buffers went away */
  671. efx_for_each_channel(channel, efx)
  672. efx_for_each_channel_tx_queue(tx_queue, channel)
  673. tx_queue->piobuf = NULL;
  674. }
  675. #else /* !EFX_USE_PIO */
  676. static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
  677. {
  678. return n == 0 ? 0 : -ENOBUFS;
  679. }
  680. static int efx_ef10_link_piobufs(struct efx_nic *efx)
  681. {
  682. return 0;
  683. }
  684. static void efx_ef10_free_piobufs(struct efx_nic *efx)
  685. {
  686. }
  687. static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
  688. {
  689. }
  690. #endif /* EFX_USE_PIO */
  691. static void efx_ef10_remove(struct efx_nic *efx)
  692. {
  693. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  694. int rc;
  695. #ifdef CONFIG_SFC_SRIOV
  696. struct efx_ef10_nic_data *nic_data_pf;
  697. struct pci_dev *pci_dev_pf;
  698. struct efx_nic *efx_pf;
  699. struct ef10_vf *vf;
  700. if (efx->pci_dev->is_virtfn) {
  701. pci_dev_pf = efx->pci_dev->physfn;
  702. if (pci_dev_pf) {
  703. efx_pf = pci_get_drvdata(pci_dev_pf);
  704. nic_data_pf = efx_pf->nic_data;
  705. vf = nic_data_pf->vf + nic_data->vf_index;
  706. vf->efx = NULL;
  707. } else
  708. netif_info(efx, drv, efx->net_dev,
  709. "Could not get the PF id from VF\n");
  710. }
  711. #endif
  712. efx_ef10_cleanup_vlans(efx);
  713. mutex_destroy(&nic_data->vlan_lock);
  714. efx_ptp_remove(efx);
  715. efx_mcdi_mon_remove(efx);
  716. efx_ef10_rx_free_indir_table(efx);
  717. if (nic_data->wc_membase)
  718. iounmap(nic_data->wc_membase);
  719. rc = efx_ef10_free_vis(efx);
  720. WARN_ON(rc != 0);
  721. if (!nic_data->must_restore_piobufs)
  722. efx_ef10_free_piobufs(efx);
  723. device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
  724. device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
  725. efx_mcdi_fini(efx);
  726. efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
  727. kfree(nic_data);
  728. }
  729. static int efx_ef10_probe_pf(struct efx_nic *efx)
  730. {
  731. return efx_ef10_probe(efx);
  732. }
  733. int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
  734. u32 *port_flags, u32 *vadaptor_flags,
  735. unsigned int *vlan_tags)
  736. {
  737. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  738. MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
  739. MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
  740. size_t outlen;
  741. int rc;
  742. if (nic_data->datapath_caps &
  743. (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
  744. MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
  745. port_id);
  746. rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
  747. outbuf, sizeof(outbuf), &outlen);
  748. if (rc)
  749. return rc;
  750. if (outlen < sizeof(outbuf)) {
  751. rc = -EIO;
  752. return rc;
  753. }
  754. }
  755. if (port_flags)
  756. *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
  757. if (vadaptor_flags)
  758. *vadaptor_flags =
  759. MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
  760. if (vlan_tags)
  761. *vlan_tags =
  762. MCDI_DWORD(outbuf,
  763. VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
  764. return 0;
  765. }
  766. int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
  767. {
  768. MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
  769. MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
  770. return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
  771. NULL, 0, NULL);
  772. }
  773. int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
  774. {
  775. MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
  776. MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
  777. return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
  778. NULL, 0, NULL);
  779. }
  780. int efx_ef10_vport_add_mac(struct efx_nic *efx,
  781. unsigned int port_id, u8 *mac)
  782. {
  783. MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
  784. MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
  785. ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
  786. return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
  787. sizeof(inbuf), NULL, 0, NULL);
  788. }
  789. int efx_ef10_vport_del_mac(struct efx_nic *efx,
  790. unsigned int port_id, u8 *mac)
  791. {
  792. MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
  793. MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
  794. ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
  795. return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
  796. sizeof(inbuf), NULL, 0, NULL);
  797. }
  798. #ifdef CONFIG_SFC_SRIOV
  799. static int efx_ef10_probe_vf(struct efx_nic *efx)
  800. {
  801. int rc;
  802. struct pci_dev *pci_dev_pf;
  803. /* If the parent PF has no VF data structure, it doesn't know about this
  804. * VF so fail probe. The VF needs to be re-created. This can happen
  805. * if the PF driver is unloaded while the VF is assigned to a guest.
  806. */
  807. pci_dev_pf = efx->pci_dev->physfn;
  808. if (pci_dev_pf) {
  809. struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
  810. struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
  811. if (!nic_data_pf->vf) {
  812. netif_info(efx, drv, efx->net_dev,
  813. "The VF cannot link to its parent PF; "
  814. "please destroy and re-create the VF\n");
  815. return -EBUSY;
  816. }
  817. }
  818. rc = efx_ef10_probe(efx);
  819. if (rc)
  820. return rc;
  821. rc = efx_ef10_get_vf_index(efx);
  822. if (rc)
  823. goto fail;
  824. if (efx->pci_dev->is_virtfn) {
  825. if (efx->pci_dev->physfn) {
  826. struct efx_nic *efx_pf =
  827. pci_get_drvdata(efx->pci_dev->physfn);
  828. struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
  829. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  830. nic_data_p->vf[nic_data->vf_index].efx = efx;
  831. nic_data_p->vf[nic_data->vf_index].pci_dev =
  832. efx->pci_dev;
  833. } else
  834. netif_info(efx, drv, efx->net_dev,
  835. "Could not get the PF id from VF\n");
  836. }
  837. return 0;
  838. fail:
  839. efx_ef10_remove(efx);
  840. return rc;
  841. }
  842. #else
  843. static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
  844. {
  845. return 0;
  846. }
  847. #endif
  848. static int efx_ef10_alloc_vis(struct efx_nic *efx,
  849. unsigned int min_vis, unsigned int max_vis)
  850. {
  851. MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
  852. MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
  853. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  854. size_t outlen;
  855. int rc;
  856. MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
  857. MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
  858. rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
  859. outbuf, sizeof(outbuf), &outlen);
  860. if (rc != 0)
  861. return rc;
  862. if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
  863. return -EIO;
  864. netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
  865. MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
  866. nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
  867. nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
  868. return 0;
  869. }
  870. /* Note that the failure path of this function does not free
  871. * resources, as this will be done by efx_ef10_remove().
  872. */
  873. static int efx_ef10_dimension_resources(struct efx_nic *efx)
  874. {
  875. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  876. unsigned int uc_mem_map_size, wc_mem_map_size;
  877. unsigned int min_vis = max(EFX_TXQ_TYPES,
  878. efx_separate_tx_channels ? 2 : 1);
  879. unsigned int channel_vis, pio_write_vi_base, max_vis;
  880. void __iomem *membase;
  881. int rc;
  882. channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
  883. #ifdef EFX_USE_PIO
  884. /* Try to allocate PIO buffers if wanted and if the full
  885. * number of PIO buffers would be sufficient to allocate one
  886. * copy-buffer per TX channel. Failure is non-fatal, as there
  887. * are only a small number of PIO buffers shared between all
  888. * functions of the controller.
  889. */
  890. if (efx_piobuf_size != 0 &&
  891. ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
  892. efx->n_tx_channels) {
  893. unsigned int n_piobufs =
  894. DIV_ROUND_UP(efx->n_tx_channels,
  895. ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
  896. rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
  897. if (rc)
  898. netif_err(efx, probe, efx->net_dev,
  899. "failed to allocate PIO buffers (%d)\n", rc);
  900. else
  901. netif_dbg(efx, probe, efx->net_dev,
  902. "allocated %u PIO buffers\n", n_piobufs);
  903. }
  904. #else
  905. nic_data->n_piobufs = 0;
  906. #endif
  907. /* PIO buffers should be mapped with write-combining enabled,
  908. * and we want to make single UC and WC mappings rather than
  909. * several of each (in fact that's the only option if host
  910. * page size is >4K). So we may allocate some extra VIs just
  911. * for writing PIO buffers through.
  912. *
  913. * The UC mapping contains (channel_vis - 1) complete VIs and the
  914. * first half of the next VI. Then the WC mapping begins with
  915. * the second half of this last VI.
  916. */
  917. uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
  918. ER_DZ_TX_PIOBUF);
  919. if (nic_data->n_piobufs) {
  920. /* pio_write_vi_base rounds down to give the number of complete
  921. * VIs inside the UC mapping.
  922. */
  923. pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
  924. wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
  925. nic_data->n_piobufs) *
  926. EFX_VI_PAGE_SIZE) -
  927. uc_mem_map_size);
  928. max_vis = pio_write_vi_base + nic_data->n_piobufs;
  929. } else {
  930. pio_write_vi_base = 0;
  931. wc_mem_map_size = 0;
  932. max_vis = channel_vis;
  933. }
  934. /* In case the last attached driver failed to free VIs, do it now */
  935. rc = efx_ef10_free_vis(efx);
  936. if (rc != 0)
  937. return rc;
  938. rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
  939. if (rc != 0)
  940. return rc;
  941. if (nic_data->n_allocated_vis < channel_vis) {
  942. netif_info(efx, drv, efx->net_dev,
  943. "Could not allocate enough VIs to satisfy RSS"
  944. " requirements. Performance may not be optimal.\n");
  945. /* We didn't get the VIs to populate our channels.
  946. * We could keep what we got but then we'd have more
  947. * interrupts than we need.
  948. * Instead calculate new max_channels and restart
  949. */
  950. efx->max_channels = nic_data->n_allocated_vis;
  951. efx->max_tx_channels =
  952. nic_data->n_allocated_vis / EFX_TXQ_TYPES;
  953. efx_ef10_free_vis(efx);
  954. return -EAGAIN;
  955. }
  956. /* If we didn't get enough VIs to map all the PIO buffers, free the
  957. * PIO buffers
  958. */
  959. if (nic_data->n_piobufs &&
  960. nic_data->n_allocated_vis <
  961. pio_write_vi_base + nic_data->n_piobufs) {
  962. netif_dbg(efx, probe, efx->net_dev,
  963. "%u VIs are not sufficient to map %u PIO buffers\n",
  964. nic_data->n_allocated_vis, nic_data->n_piobufs);
  965. efx_ef10_free_piobufs(efx);
  966. }
  967. /* Shrink the original UC mapping of the memory BAR */
  968. membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
  969. if (!membase) {
  970. netif_err(efx, probe, efx->net_dev,
  971. "could not shrink memory BAR to %x\n",
  972. uc_mem_map_size);
  973. return -ENOMEM;
  974. }
  975. iounmap(efx->membase);
  976. efx->membase = membase;
  977. /* Set up the WC mapping if needed */
  978. if (wc_mem_map_size) {
  979. nic_data->wc_membase = ioremap_wc(efx->membase_phys +
  980. uc_mem_map_size,
  981. wc_mem_map_size);
  982. if (!nic_data->wc_membase) {
  983. netif_err(efx, probe, efx->net_dev,
  984. "could not allocate WC mapping of size %x\n",
  985. wc_mem_map_size);
  986. return -ENOMEM;
  987. }
  988. nic_data->pio_write_vi_base = pio_write_vi_base;
  989. nic_data->pio_write_base =
  990. nic_data->wc_membase +
  991. (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
  992. uc_mem_map_size);
  993. rc = efx_ef10_link_piobufs(efx);
  994. if (rc)
  995. efx_ef10_free_piobufs(efx);
  996. }
  997. netif_dbg(efx, probe, efx->net_dev,
  998. "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
  999. &efx->membase_phys, efx->membase, uc_mem_map_size,
  1000. nic_data->wc_membase, wc_mem_map_size);
  1001. return 0;
  1002. }
  1003. static int efx_ef10_init_nic(struct efx_nic *efx)
  1004. {
  1005. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1006. int rc;
  1007. if (nic_data->must_check_datapath_caps) {
  1008. rc = efx_ef10_init_datapath_caps(efx);
  1009. if (rc)
  1010. return rc;
  1011. nic_data->must_check_datapath_caps = false;
  1012. }
  1013. if (nic_data->must_realloc_vis) {
  1014. /* We cannot let the number of VIs change now */
  1015. rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
  1016. nic_data->n_allocated_vis);
  1017. if (rc)
  1018. return rc;
  1019. nic_data->must_realloc_vis = false;
  1020. }
  1021. if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
  1022. rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
  1023. if (rc == 0) {
  1024. rc = efx_ef10_link_piobufs(efx);
  1025. if (rc)
  1026. efx_ef10_free_piobufs(efx);
  1027. }
  1028. /* Log an error on failure, but this is non-fatal */
  1029. if (rc)
  1030. netif_err(efx, drv, efx->net_dev,
  1031. "failed to restore PIO buffers (%d)\n", rc);
  1032. nic_data->must_restore_piobufs = false;
  1033. }
  1034. /* don't fail init if RSS setup doesn't work */
  1035. efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
  1036. return 0;
  1037. }
  1038. static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
  1039. {
  1040. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1041. #ifdef CONFIG_SFC_SRIOV
  1042. unsigned int i;
  1043. #endif
  1044. /* All our allocations have been reset */
  1045. nic_data->must_realloc_vis = true;
  1046. nic_data->must_restore_filters = true;
  1047. nic_data->must_restore_piobufs = true;
  1048. efx_ef10_forget_old_piobufs(efx);
  1049. nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
  1050. /* Driver-created vswitches and vports must be re-created */
  1051. nic_data->must_probe_vswitching = true;
  1052. nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
  1053. #ifdef CONFIG_SFC_SRIOV
  1054. if (nic_data->vf)
  1055. for (i = 0; i < efx->vf_count; i++)
  1056. nic_data->vf[i].vport_id = 0;
  1057. #endif
  1058. }
  1059. static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
  1060. {
  1061. if (reason == RESET_TYPE_MC_FAILURE)
  1062. return RESET_TYPE_DATAPATH;
  1063. return efx_mcdi_map_reset_reason(reason);
  1064. }
  1065. static int efx_ef10_map_reset_flags(u32 *flags)
  1066. {
  1067. enum {
  1068. EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
  1069. ETH_RESET_SHARED_SHIFT),
  1070. EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
  1071. ETH_RESET_OFFLOAD | ETH_RESET_MAC |
  1072. ETH_RESET_PHY | ETH_RESET_MGMT) <<
  1073. ETH_RESET_SHARED_SHIFT)
  1074. };
  1075. /* We assume for now that our PCI function is permitted to
  1076. * reset everything.
  1077. */
  1078. if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
  1079. *flags &= ~EF10_RESET_MC;
  1080. return RESET_TYPE_WORLD;
  1081. }
  1082. if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
  1083. *flags &= ~EF10_RESET_PORT;
  1084. return RESET_TYPE_ALL;
  1085. }
  1086. /* no invisible reset implemented */
  1087. return -EINVAL;
  1088. }
  1089. static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
  1090. {
  1091. int rc = efx_mcdi_reset(efx, reset_type);
  1092. /* Unprivileged functions return -EPERM, but need to return success
  1093. * here so that the datapath is brought back up.
  1094. */
  1095. if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
  1096. rc = 0;
  1097. /* If it was a port reset, trigger reallocation of MC resources.
  1098. * Note that on an MC reset nothing needs to be done now because we'll
  1099. * detect the MC reset later and handle it then.
  1100. * For an FLR, we never get an MC reset event, but the MC has reset all
  1101. * resources assigned to us, so we have to trigger reallocation now.
  1102. */
  1103. if ((reset_type == RESET_TYPE_ALL ||
  1104. reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
  1105. efx_ef10_reset_mc_allocations(efx);
  1106. return rc;
  1107. }
  1108. #define EF10_DMA_STAT(ext_name, mcdi_name) \
  1109. [EF10_STAT_ ## ext_name] = \
  1110. { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
  1111. #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
  1112. [EF10_STAT_ ## int_name] = \
  1113. { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
  1114. #define EF10_OTHER_STAT(ext_name) \
  1115. [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
  1116. #define GENERIC_SW_STAT(ext_name) \
  1117. [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
  1118. static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
  1119. EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
  1120. EF10_DMA_STAT(port_tx_packets, TX_PKTS),
  1121. EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
  1122. EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
  1123. EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
  1124. EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
  1125. EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
  1126. EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
  1127. EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
  1128. EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
  1129. EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
  1130. EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
  1131. EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
  1132. EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
  1133. EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
  1134. EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
  1135. EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
  1136. EF10_OTHER_STAT(port_rx_good_bytes),
  1137. EF10_OTHER_STAT(port_rx_bad_bytes),
  1138. EF10_DMA_STAT(port_rx_packets, RX_PKTS),
  1139. EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
  1140. EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
  1141. EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
  1142. EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
  1143. EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
  1144. EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
  1145. EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
  1146. EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
  1147. EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
  1148. EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
  1149. EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
  1150. EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
  1151. EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
  1152. EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
  1153. EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
  1154. EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
  1155. EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
  1156. EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
  1157. EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
  1158. EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
  1159. EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
  1160. GENERIC_SW_STAT(rx_nodesc_trunc),
  1161. GENERIC_SW_STAT(rx_noskb_drops),
  1162. EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
  1163. EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
  1164. EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
  1165. EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
  1166. EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
  1167. EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
  1168. EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
  1169. EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
  1170. EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
  1171. EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
  1172. EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
  1173. EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
  1174. EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
  1175. EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
  1176. EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
  1177. EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
  1178. EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
  1179. EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
  1180. EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
  1181. EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
  1182. EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
  1183. EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
  1184. EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
  1185. EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
  1186. EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
  1187. EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
  1188. EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
  1189. EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
  1190. EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
  1191. EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
  1192. };
  1193. #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
  1194. (1ULL << EF10_STAT_port_tx_packets) | \
  1195. (1ULL << EF10_STAT_port_tx_pause) | \
  1196. (1ULL << EF10_STAT_port_tx_unicast) | \
  1197. (1ULL << EF10_STAT_port_tx_multicast) | \
  1198. (1ULL << EF10_STAT_port_tx_broadcast) | \
  1199. (1ULL << EF10_STAT_port_rx_bytes) | \
  1200. (1ULL << \
  1201. EF10_STAT_port_rx_bytes_minus_good_bytes) | \
  1202. (1ULL << EF10_STAT_port_rx_good_bytes) | \
  1203. (1ULL << EF10_STAT_port_rx_bad_bytes) | \
  1204. (1ULL << EF10_STAT_port_rx_packets) | \
  1205. (1ULL << EF10_STAT_port_rx_good) | \
  1206. (1ULL << EF10_STAT_port_rx_bad) | \
  1207. (1ULL << EF10_STAT_port_rx_pause) | \
  1208. (1ULL << EF10_STAT_port_rx_control) | \
  1209. (1ULL << EF10_STAT_port_rx_unicast) | \
  1210. (1ULL << EF10_STAT_port_rx_multicast) | \
  1211. (1ULL << EF10_STAT_port_rx_broadcast) | \
  1212. (1ULL << EF10_STAT_port_rx_lt64) | \
  1213. (1ULL << EF10_STAT_port_rx_64) | \
  1214. (1ULL << EF10_STAT_port_rx_65_to_127) | \
  1215. (1ULL << EF10_STAT_port_rx_128_to_255) | \
  1216. (1ULL << EF10_STAT_port_rx_256_to_511) | \
  1217. (1ULL << EF10_STAT_port_rx_512_to_1023) |\
  1218. (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
  1219. (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
  1220. (1ULL << EF10_STAT_port_rx_gtjumbo) | \
  1221. (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
  1222. (1ULL << EF10_STAT_port_rx_overflow) | \
  1223. (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
  1224. (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
  1225. (1ULL << GENERIC_STAT_rx_noskb_drops))
  1226. /* These statistics are only provided by the 10G MAC. For a 10G/40G
  1227. * switchable port we do not expose these because they might not
  1228. * include all the packets they should.
  1229. */
  1230. #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
  1231. (1ULL << EF10_STAT_port_tx_lt64) | \
  1232. (1ULL << EF10_STAT_port_tx_64) | \
  1233. (1ULL << EF10_STAT_port_tx_65_to_127) |\
  1234. (1ULL << EF10_STAT_port_tx_128_to_255) |\
  1235. (1ULL << EF10_STAT_port_tx_256_to_511) |\
  1236. (1ULL << EF10_STAT_port_tx_512_to_1023) |\
  1237. (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
  1238. (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
  1239. /* These statistics are only provided by the 40G MAC. For a 10G/40G
  1240. * switchable port we do expose these because the errors will otherwise
  1241. * be silent.
  1242. */
  1243. #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
  1244. (1ULL << EF10_STAT_port_rx_length_error))
  1245. /* These statistics are only provided if the firmware supports the
  1246. * capability PM_AND_RXDP_COUNTERS.
  1247. */
  1248. #define HUNT_PM_AND_RXDP_STAT_MASK ( \
  1249. (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
  1250. (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
  1251. (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
  1252. (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
  1253. (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
  1254. (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
  1255. (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
  1256. (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
  1257. (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
  1258. (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
  1259. (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
  1260. (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
  1261. static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
  1262. {
  1263. u64 raw_mask = HUNT_COMMON_STAT_MASK;
  1264. u32 port_caps = efx_mcdi_phy_get_caps(efx);
  1265. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1266. if (!(efx->mcdi->fn_flags &
  1267. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
  1268. return 0;
  1269. if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
  1270. raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
  1271. else
  1272. raw_mask |= HUNT_10G_ONLY_STAT_MASK;
  1273. if (nic_data->datapath_caps &
  1274. (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
  1275. raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
  1276. return raw_mask;
  1277. }
  1278. static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
  1279. {
  1280. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1281. u64 raw_mask[2];
  1282. raw_mask[0] = efx_ef10_raw_stat_mask(efx);
  1283. /* Only show vadaptor stats when EVB capability is present */
  1284. if (nic_data->datapath_caps &
  1285. (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
  1286. raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
  1287. raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
  1288. } else {
  1289. raw_mask[1] = 0;
  1290. }
  1291. #if BITS_PER_LONG == 64
  1292. BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
  1293. mask[0] = raw_mask[0];
  1294. mask[1] = raw_mask[1];
  1295. #else
  1296. BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
  1297. mask[0] = raw_mask[0] & 0xffffffff;
  1298. mask[1] = raw_mask[0] >> 32;
  1299. mask[2] = raw_mask[1] & 0xffffffff;
  1300. #endif
  1301. }
  1302. static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
  1303. {
  1304. DECLARE_BITMAP(mask, EF10_STAT_COUNT);
  1305. efx_ef10_get_stat_mask(efx, mask);
  1306. return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
  1307. mask, names);
  1308. }
  1309. static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
  1310. struct rtnl_link_stats64 *core_stats)
  1311. {
  1312. DECLARE_BITMAP(mask, EF10_STAT_COUNT);
  1313. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1314. u64 *stats = nic_data->stats;
  1315. size_t stats_count = 0, index;
  1316. efx_ef10_get_stat_mask(efx, mask);
  1317. if (full_stats) {
  1318. for_each_set_bit(index, mask, EF10_STAT_COUNT) {
  1319. if (efx_ef10_stat_desc[index].name) {
  1320. *full_stats++ = stats[index];
  1321. ++stats_count;
  1322. }
  1323. }
  1324. }
  1325. if (!core_stats)
  1326. return stats_count;
  1327. if (nic_data->datapath_caps &
  1328. 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
  1329. /* Use vadaptor stats. */
  1330. core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
  1331. stats[EF10_STAT_rx_multicast] +
  1332. stats[EF10_STAT_rx_broadcast];
  1333. core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
  1334. stats[EF10_STAT_tx_multicast] +
  1335. stats[EF10_STAT_tx_broadcast];
  1336. core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
  1337. stats[EF10_STAT_rx_multicast_bytes] +
  1338. stats[EF10_STAT_rx_broadcast_bytes];
  1339. core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
  1340. stats[EF10_STAT_tx_multicast_bytes] +
  1341. stats[EF10_STAT_tx_broadcast_bytes];
  1342. core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
  1343. stats[GENERIC_STAT_rx_noskb_drops];
  1344. core_stats->multicast = stats[EF10_STAT_rx_multicast];
  1345. core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
  1346. core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
  1347. core_stats->rx_errors = core_stats->rx_crc_errors;
  1348. core_stats->tx_errors = stats[EF10_STAT_tx_bad];
  1349. } else {
  1350. /* Use port stats. */
  1351. core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
  1352. core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
  1353. core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
  1354. core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
  1355. core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
  1356. stats[GENERIC_STAT_rx_nodesc_trunc] +
  1357. stats[GENERIC_STAT_rx_noskb_drops];
  1358. core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
  1359. core_stats->rx_length_errors =
  1360. stats[EF10_STAT_port_rx_gtjumbo] +
  1361. stats[EF10_STAT_port_rx_length_error];
  1362. core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
  1363. core_stats->rx_frame_errors =
  1364. stats[EF10_STAT_port_rx_align_error];
  1365. core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
  1366. core_stats->rx_errors = (core_stats->rx_length_errors +
  1367. core_stats->rx_crc_errors +
  1368. core_stats->rx_frame_errors);
  1369. }
  1370. return stats_count;
  1371. }
  1372. static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
  1373. {
  1374. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1375. DECLARE_BITMAP(mask, EF10_STAT_COUNT);
  1376. __le64 generation_start, generation_end;
  1377. u64 *stats = nic_data->stats;
  1378. __le64 *dma_stats;
  1379. efx_ef10_get_stat_mask(efx, mask);
  1380. dma_stats = efx->stats_buffer.addr;
  1381. nic_data = efx->nic_data;
  1382. generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
  1383. if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
  1384. return 0;
  1385. rmb();
  1386. efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
  1387. stats, efx->stats_buffer.addr, false);
  1388. rmb();
  1389. generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
  1390. if (generation_end != generation_start)
  1391. return -EAGAIN;
  1392. /* Update derived statistics */
  1393. efx_nic_fix_nodesc_drop_stat(efx,
  1394. &stats[EF10_STAT_port_rx_nodesc_drops]);
  1395. stats[EF10_STAT_port_rx_good_bytes] =
  1396. stats[EF10_STAT_port_rx_bytes] -
  1397. stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
  1398. efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
  1399. stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
  1400. efx_update_sw_stats(efx, stats);
  1401. return 0;
  1402. }
  1403. static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
  1404. struct rtnl_link_stats64 *core_stats)
  1405. {
  1406. int retry;
  1407. /* If we're unlucky enough to read statistics during the DMA, wait
  1408. * up to 10ms for it to finish (typically takes <500us)
  1409. */
  1410. for (retry = 0; retry < 100; ++retry) {
  1411. if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
  1412. break;
  1413. udelay(100);
  1414. }
  1415. return efx_ef10_update_stats_common(efx, full_stats, core_stats);
  1416. }
  1417. static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
  1418. {
  1419. MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
  1420. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1421. DECLARE_BITMAP(mask, EF10_STAT_COUNT);
  1422. __le64 generation_start, generation_end;
  1423. u64 *stats = nic_data->stats;
  1424. u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
  1425. struct efx_buffer stats_buf;
  1426. __le64 *dma_stats;
  1427. int rc;
  1428. spin_unlock_bh(&efx->stats_lock);
  1429. if (in_interrupt()) {
  1430. /* If in atomic context, cannot update stats. Just update the
  1431. * software stats and return so the caller can continue.
  1432. */
  1433. spin_lock_bh(&efx->stats_lock);
  1434. efx_update_sw_stats(efx, stats);
  1435. return 0;
  1436. }
  1437. efx_ef10_get_stat_mask(efx, mask);
  1438. rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
  1439. if (rc) {
  1440. spin_lock_bh(&efx->stats_lock);
  1441. return rc;
  1442. }
  1443. dma_stats = stats_buf.addr;
  1444. dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
  1445. MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
  1446. MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
  1447. MAC_STATS_IN_DMA, 1);
  1448. MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
  1449. MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
  1450. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
  1451. NULL, 0, NULL);
  1452. spin_lock_bh(&efx->stats_lock);
  1453. if (rc) {
  1454. /* Expect ENOENT if DMA queues have not been set up */
  1455. if (rc != -ENOENT || atomic_read(&efx->active_queues))
  1456. efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
  1457. sizeof(inbuf), NULL, 0, rc);
  1458. goto out;
  1459. }
  1460. generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
  1461. if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
  1462. WARN_ON_ONCE(1);
  1463. goto out;
  1464. }
  1465. rmb();
  1466. efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
  1467. stats, stats_buf.addr, false);
  1468. rmb();
  1469. generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
  1470. if (generation_end != generation_start) {
  1471. rc = -EAGAIN;
  1472. goto out;
  1473. }
  1474. efx_update_sw_stats(efx, stats);
  1475. out:
  1476. efx_nic_free_buffer(efx, &stats_buf);
  1477. return rc;
  1478. }
  1479. static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
  1480. struct rtnl_link_stats64 *core_stats)
  1481. {
  1482. if (efx_ef10_try_update_nic_stats_vf(efx))
  1483. return 0;
  1484. return efx_ef10_update_stats_common(efx, full_stats, core_stats);
  1485. }
  1486. static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
  1487. {
  1488. struct efx_nic *efx = channel->efx;
  1489. unsigned int mode, value;
  1490. efx_dword_t timer_cmd;
  1491. if (channel->irq_moderation) {
  1492. mode = 3;
  1493. value = channel->irq_moderation - 1;
  1494. } else {
  1495. mode = 0;
  1496. value = 0;
  1497. }
  1498. if (EFX_EF10_WORKAROUND_35388(efx)) {
  1499. EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
  1500. EFE_DD_EVQ_IND_TIMER_FLAGS,
  1501. ERF_DD_EVQ_IND_TIMER_MODE, mode,
  1502. ERF_DD_EVQ_IND_TIMER_VAL, value);
  1503. efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
  1504. channel->channel);
  1505. } else {
  1506. EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
  1507. ERF_DZ_TC_TIMER_VAL, value);
  1508. efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
  1509. channel->channel);
  1510. }
  1511. }
  1512. static void efx_ef10_get_wol_vf(struct efx_nic *efx,
  1513. struct ethtool_wolinfo *wol) {}
  1514. static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
  1515. {
  1516. return -EOPNOTSUPP;
  1517. }
  1518. static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
  1519. {
  1520. wol->supported = 0;
  1521. wol->wolopts = 0;
  1522. memset(&wol->sopass, 0, sizeof(wol->sopass));
  1523. }
  1524. static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
  1525. {
  1526. if (type != 0)
  1527. return -EINVAL;
  1528. return 0;
  1529. }
  1530. static void efx_ef10_mcdi_request(struct efx_nic *efx,
  1531. const efx_dword_t *hdr, size_t hdr_len,
  1532. const efx_dword_t *sdu, size_t sdu_len)
  1533. {
  1534. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1535. u8 *pdu = nic_data->mcdi_buf.addr;
  1536. memcpy(pdu, hdr, hdr_len);
  1537. memcpy(pdu + hdr_len, sdu, sdu_len);
  1538. wmb();
  1539. /* The hardware provides 'low' and 'high' (doorbell) registers
  1540. * for passing the 64-bit address of an MCDI request to
  1541. * firmware. However the dwords are swapped by firmware. The
  1542. * least significant bits of the doorbell are then 0 for all
  1543. * MCDI requests due to alignment.
  1544. */
  1545. _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
  1546. ER_DZ_MC_DB_LWRD);
  1547. _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
  1548. ER_DZ_MC_DB_HWRD);
  1549. }
  1550. static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
  1551. {
  1552. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1553. const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
  1554. rmb();
  1555. return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
  1556. }
  1557. static void
  1558. efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
  1559. size_t offset, size_t outlen)
  1560. {
  1561. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1562. const u8 *pdu = nic_data->mcdi_buf.addr;
  1563. memcpy(outbuf, pdu + offset, outlen);
  1564. }
  1565. static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
  1566. {
  1567. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1568. /* All our allocations have been reset */
  1569. efx_ef10_reset_mc_allocations(efx);
  1570. /* The datapath firmware might have been changed */
  1571. nic_data->must_check_datapath_caps = true;
  1572. /* MAC statistics have been cleared on the NIC; clear the local
  1573. * statistic that we update with efx_update_diff_stat().
  1574. */
  1575. nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
  1576. }
  1577. static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
  1578. {
  1579. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1580. int rc;
  1581. rc = efx_ef10_get_warm_boot_count(efx);
  1582. if (rc < 0) {
  1583. /* The firmware is presumably in the process of
  1584. * rebooting. However, we are supposed to report each
  1585. * reboot just once, so we must only do that once we
  1586. * can read and store the updated warm boot count.
  1587. */
  1588. return 0;
  1589. }
  1590. if (rc == nic_data->warm_boot_count)
  1591. return 0;
  1592. nic_data->warm_boot_count = rc;
  1593. efx_ef10_mcdi_reboot_detected(efx);
  1594. return -EIO;
  1595. }
  1596. /* Handle an MSI interrupt
  1597. *
  1598. * Handle an MSI hardware interrupt. This routine schedules event
  1599. * queue processing. No interrupt acknowledgement cycle is necessary.
  1600. * Also, we never need to check that the interrupt is for us, since
  1601. * MSI interrupts cannot be shared.
  1602. */
  1603. static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
  1604. {
  1605. struct efx_msi_context *context = dev_id;
  1606. struct efx_nic *efx = context->efx;
  1607. netif_vdbg(efx, intr, efx->net_dev,
  1608. "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
  1609. if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
  1610. /* Note test interrupts */
  1611. if (context->index == efx->irq_level)
  1612. efx->last_irq_cpu = raw_smp_processor_id();
  1613. /* Schedule processing of the channel */
  1614. efx_schedule_channel_irq(efx->channel[context->index]);
  1615. }
  1616. return IRQ_HANDLED;
  1617. }
  1618. static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
  1619. {
  1620. struct efx_nic *efx = dev_id;
  1621. bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
  1622. struct efx_channel *channel;
  1623. efx_dword_t reg;
  1624. u32 queues;
  1625. /* Read the ISR which also ACKs the interrupts */
  1626. efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
  1627. queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
  1628. if (queues == 0)
  1629. return IRQ_NONE;
  1630. if (likely(soft_enabled)) {
  1631. /* Note test interrupts */
  1632. if (queues & (1U << efx->irq_level))
  1633. efx->last_irq_cpu = raw_smp_processor_id();
  1634. efx_for_each_channel(channel, efx) {
  1635. if (queues & 1)
  1636. efx_schedule_channel_irq(channel);
  1637. queues >>= 1;
  1638. }
  1639. }
  1640. netif_vdbg(efx, intr, efx->net_dev,
  1641. "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
  1642. irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
  1643. return IRQ_HANDLED;
  1644. }
  1645. static void efx_ef10_irq_test_generate(struct efx_nic *efx)
  1646. {
  1647. MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
  1648. BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
  1649. MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
  1650. (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
  1651. inbuf, sizeof(inbuf), NULL, 0, NULL);
  1652. }
  1653. static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
  1654. {
  1655. return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
  1656. (tx_queue->ptr_mask + 1) *
  1657. sizeof(efx_qword_t),
  1658. GFP_KERNEL);
  1659. }
  1660. /* This writes to the TX_DESC_WPTR and also pushes data */
  1661. static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
  1662. const efx_qword_t *txd)
  1663. {
  1664. unsigned int write_ptr;
  1665. efx_oword_t reg;
  1666. write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
  1667. EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
  1668. reg.qword[0] = *txd;
  1669. efx_writeo_page(tx_queue->efx, &reg,
  1670. ER_DZ_TX_DESC_UPD, tx_queue->queue);
  1671. }
  1672. static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
  1673. {
  1674. MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
  1675. EFX_BUF_SIZE));
  1676. bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
  1677. size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
  1678. struct efx_channel *channel = tx_queue->channel;
  1679. struct efx_nic *efx = tx_queue->efx;
  1680. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1681. size_t inlen;
  1682. dma_addr_t dma_addr;
  1683. efx_qword_t *txd;
  1684. int rc;
  1685. int i;
  1686. BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
  1687. MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
  1688. MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
  1689. MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
  1690. MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
  1691. MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
  1692. INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
  1693. INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
  1694. MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
  1695. MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
  1696. dma_addr = tx_queue->txd.buf.dma_addr;
  1697. netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
  1698. tx_queue->queue, entries, (u64)dma_addr);
  1699. for (i = 0; i < entries; ++i) {
  1700. MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
  1701. dma_addr += EFX_BUF_SIZE;
  1702. }
  1703. inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
  1704. rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
  1705. NULL, 0, NULL);
  1706. if (rc)
  1707. goto fail;
  1708. /* A previous user of this TX queue might have set us up the
  1709. * bomb by writing a descriptor to the TX push collector but
  1710. * not the doorbell. (Each collector belongs to a port, not a
  1711. * queue or function, so cannot easily be reset.) We must
  1712. * attempt to push a no-op descriptor in its place.
  1713. */
  1714. tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
  1715. tx_queue->insert_count = 1;
  1716. txd = efx_tx_desc(tx_queue, 0);
  1717. EFX_POPULATE_QWORD_4(*txd,
  1718. ESF_DZ_TX_DESC_IS_OPT, true,
  1719. ESF_DZ_TX_OPTION_TYPE,
  1720. ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
  1721. ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
  1722. ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
  1723. tx_queue->write_count = 1;
  1724. if (nic_data->datapath_caps &
  1725. (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
  1726. tx_queue->tso_version = 1;
  1727. }
  1728. wmb();
  1729. efx_ef10_push_tx_desc(tx_queue, txd);
  1730. return;
  1731. fail:
  1732. netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
  1733. tx_queue->queue);
  1734. }
  1735. static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
  1736. {
  1737. MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
  1738. MCDI_DECLARE_BUF_ERR(outbuf);
  1739. struct efx_nic *efx = tx_queue->efx;
  1740. size_t outlen;
  1741. int rc;
  1742. MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
  1743. tx_queue->queue);
  1744. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
  1745. outbuf, sizeof(outbuf), &outlen);
  1746. if (rc && rc != -EALREADY)
  1747. goto fail;
  1748. return;
  1749. fail:
  1750. efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
  1751. outbuf, outlen, rc);
  1752. }
  1753. static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
  1754. {
  1755. efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
  1756. }
  1757. /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
  1758. static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
  1759. {
  1760. unsigned int write_ptr;
  1761. efx_dword_t reg;
  1762. write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
  1763. EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
  1764. efx_writed_page(tx_queue->efx, &reg,
  1765. ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
  1766. }
  1767. static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
  1768. {
  1769. unsigned int old_write_count = tx_queue->write_count;
  1770. struct efx_tx_buffer *buffer;
  1771. unsigned int write_ptr;
  1772. efx_qword_t *txd;
  1773. tx_queue->xmit_more_available = false;
  1774. if (unlikely(tx_queue->write_count == tx_queue->insert_count))
  1775. return;
  1776. do {
  1777. write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
  1778. buffer = &tx_queue->buffer[write_ptr];
  1779. txd = efx_tx_desc(tx_queue, write_ptr);
  1780. ++tx_queue->write_count;
  1781. /* Create TX descriptor ring entry */
  1782. if (buffer->flags & EFX_TX_BUF_OPTION) {
  1783. *txd = buffer->option;
  1784. } else {
  1785. BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
  1786. EFX_POPULATE_QWORD_3(
  1787. *txd,
  1788. ESF_DZ_TX_KER_CONT,
  1789. buffer->flags & EFX_TX_BUF_CONT,
  1790. ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
  1791. ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
  1792. }
  1793. } while (tx_queue->write_count != tx_queue->insert_count);
  1794. wmb(); /* Ensure descriptors are written before they are fetched */
  1795. if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
  1796. txd = efx_tx_desc(tx_queue,
  1797. old_write_count & tx_queue->ptr_mask);
  1798. efx_ef10_push_tx_desc(tx_queue, txd);
  1799. ++tx_queue->pushes;
  1800. } else {
  1801. efx_ef10_notify_tx_desc(tx_queue);
  1802. }
  1803. }
  1804. static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
  1805. bool exclusive, unsigned *context_size)
  1806. {
  1807. MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
  1808. MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
  1809. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1810. size_t outlen;
  1811. int rc;
  1812. u32 alloc_type = exclusive ?
  1813. MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
  1814. MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
  1815. unsigned rss_spread = exclusive ?
  1816. efx->rss_spread :
  1817. min(rounddown_pow_of_two(efx->rss_spread),
  1818. EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
  1819. if (!exclusive && rss_spread == 1) {
  1820. *context = EFX_EF10_RSS_CONTEXT_INVALID;
  1821. if (context_size)
  1822. *context_size = 1;
  1823. return 0;
  1824. }
  1825. if (nic_data->datapath_caps &
  1826. 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
  1827. return -EOPNOTSUPP;
  1828. MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
  1829. nic_data->vport_id);
  1830. MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
  1831. MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
  1832. rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
  1833. outbuf, sizeof(outbuf), &outlen);
  1834. if (rc != 0)
  1835. return rc;
  1836. if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
  1837. return -EIO;
  1838. *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
  1839. if (context_size)
  1840. *context_size = rss_spread;
  1841. return 0;
  1842. }
  1843. static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
  1844. {
  1845. MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
  1846. int rc;
  1847. MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
  1848. context);
  1849. rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
  1850. NULL, 0, NULL);
  1851. WARN_ON(rc != 0);
  1852. }
  1853. static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
  1854. const u32 *rx_indir_table)
  1855. {
  1856. MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
  1857. MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
  1858. int i, rc;
  1859. MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
  1860. context);
  1861. BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
  1862. MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
  1863. for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
  1864. MCDI_PTR(tablebuf,
  1865. RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
  1866. (u8) rx_indir_table[i];
  1867. rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
  1868. sizeof(tablebuf), NULL, 0, NULL);
  1869. if (rc != 0)
  1870. return rc;
  1871. MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
  1872. context);
  1873. BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
  1874. MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
  1875. for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
  1876. MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
  1877. efx->rx_hash_key[i];
  1878. return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
  1879. sizeof(keybuf), NULL, 0, NULL);
  1880. }
  1881. static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
  1882. {
  1883. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1884. if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
  1885. efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
  1886. nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
  1887. }
  1888. static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
  1889. unsigned *context_size)
  1890. {
  1891. u32 new_rx_rss_context;
  1892. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1893. int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
  1894. false, context_size);
  1895. if (rc != 0)
  1896. return rc;
  1897. nic_data->rx_rss_context = new_rx_rss_context;
  1898. nic_data->rx_rss_context_exclusive = false;
  1899. efx_set_default_rx_indir_table(efx);
  1900. return 0;
  1901. }
  1902. static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
  1903. const u32 *rx_indir_table)
  1904. {
  1905. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1906. int rc;
  1907. u32 new_rx_rss_context;
  1908. if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
  1909. !nic_data->rx_rss_context_exclusive) {
  1910. rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
  1911. true, NULL);
  1912. if (rc == -EOPNOTSUPP)
  1913. return rc;
  1914. else if (rc != 0)
  1915. goto fail1;
  1916. } else {
  1917. new_rx_rss_context = nic_data->rx_rss_context;
  1918. }
  1919. rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
  1920. rx_indir_table);
  1921. if (rc != 0)
  1922. goto fail2;
  1923. if (nic_data->rx_rss_context != new_rx_rss_context)
  1924. efx_ef10_rx_free_indir_table(efx);
  1925. nic_data->rx_rss_context = new_rx_rss_context;
  1926. nic_data->rx_rss_context_exclusive = true;
  1927. if (rx_indir_table != efx->rx_indir_table)
  1928. memcpy(efx->rx_indir_table, rx_indir_table,
  1929. sizeof(efx->rx_indir_table));
  1930. return 0;
  1931. fail2:
  1932. if (new_rx_rss_context != nic_data->rx_rss_context)
  1933. efx_ef10_free_rss_context(efx, new_rx_rss_context);
  1934. fail1:
  1935. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1936. return rc;
  1937. }
  1938. static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
  1939. const u32 *rx_indir_table)
  1940. {
  1941. int rc;
  1942. if (efx->rss_spread == 1)
  1943. return 0;
  1944. rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
  1945. if (rc == -ENOBUFS && !user) {
  1946. unsigned context_size;
  1947. bool mismatch = false;
  1948. size_t i;
  1949. for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
  1950. i++)
  1951. mismatch = rx_indir_table[i] !=
  1952. ethtool_rxfh_indir_default(i, efx->rss_spread);
  1953. rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
  1954. if (rc == 0) {
  1955. if (context_size != efx->rss_spread)
  1956. netif_warn(efx, probe, efx->net_dev,
  1957. "Could not allocate an exclusive RSS"
  1958. " context; allocated a shared one of"
  1959. " different size."
  1960. " Wanted %u, got %u.\n",
  1961. efx->rss_spread, context_size);
  1962. else if (mismatch)
  1963. netif_warn(efx, probe, efx->net_dev,
  1964. "Could not allocate an exclusive RSS"
  1965. " context; allocated a shared one but"
  1966. " could not apply custom"
  1967. " indirection.\n");
  1968. else
  1969. netif_info(efx, probe, efx->net_dev,
  1970. "Could not allocate an exclusive RSS"
  1971. " context; allocated a shared one.\n");
  1972. }
  1973. }
  1974. return rc;
  1975. }
  1976. static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
  1977. const u32 *rx_indir_table
  1978. __attribute__ ((unused)))
  1979. {
  1980. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  1981. if (user)
  1982. return -EOPNOTSUPP;
  1983. if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
  1984. return 0;
  1985. return efx_ef10_rx_push_shared_rss_config(efx, NULL);
  1986. }
  1987. static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
  1988. {
  1989. return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
  1990. (rx_queue->ptr_mask + 1) *
  1991. sizeof(efx_qword_t),
  1992. GFP_KERNEL);
  1993. }
  1994. static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
  1995. {
  1996. MCDI_DECLARE_BUF(inbuf,
  1997. MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
  1998. EFX_BUF_SIZE));
  1999. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  2000. size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
  2001. struct efx_nic *efx = rx_queue->efx;
  2002. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  2003. size_t inlen;
  2004. dma_addr_t dma_addr;
  2005. int rc;
  2006. int i;
  2007. BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
  2008. rx_queue->scatter_n = 0;
  2009. rx_queue->scatter_len = 0;
  2010. MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
  2011. MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
  2012. MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
  2013. MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
  2014. efx_rx_queue_index(rx_queue));
  2015. MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
  2016. INIT_RXQ_IN_FLAG_PREFIX, 1,
  2017. INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
  2018. MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
  2019. MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
  2020. dma_addr = rx_queue->rxd.buf.dma_addr;
  2021. netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
  2022. efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
  2023. for (i = 0; i < entries; ++i) {
  2024. MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
  2025. dma_addr += EFX_BUF_SIZE;
  2026. }
  2027. inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
  2028. rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
  2029. NULL, 0, NULL);
  2030. if (rc)
  2031. netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
  2032. efx_rx_queue_index(rx_queue));
  2033. }
  2034. static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
  2035. {
  2036. MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
  2037. MCDI_DECLARE_BUF_ERR(outbuf);
  2038. struct efx_nic *efx = rx_queue->efx;
  2039. size_t outlen;
  2040. int rc;
  2041. MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
  2042. efx_rx_queue_index(rx_queue));
  2043. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
  2044. outbuf, sizeof(outbuf), &outlen);
  2045. if (rc && rc != -EALREADY)
  2046. goto fail;
  2047. return;
  2048. fail:
  2049. efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
  2050. outbuf, outlen, rc);
  2051. }
  2052. static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
  2053. {
  2054. efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
  2055. }
  2056. /* This creates an entry in the RX descriptor queue */
  2057. static inline void
  2058. efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
  2059. {
  2060. struct efx_rx_buffer *rx_buf;
  2061. efx_qword_t *rxd;
  2062. rxd = efx_rx_desc(rx_queue, index);
  2063. rx_buf = efx_rx_buffer(rx_queue, index);
  2064. EFX_POPULATE_QWORD_2(*rxd,
  2065. ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
  2066. ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
  2067. }
  2068. static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
  2069. {
  2070. struct efx_nic *efx = rx_queue->efx;
  2071. unsigned int write_count;
  2072. efx_dword_t reg;
  2073. /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
  2074. write_count = rx_queue->added_count & ~7;
  2075. if (rx_queue->notified_count == write_count)
  2076. return;
  2077. do
  2078. efx_ef10_build_rx_desc(
  2079. rx_queue,
  2080. rx_queue->notified_count & rx_queue->ptr_mask);
  2081. while (++rx_queue->notified_count != write_count);
  2082. wmb();
  2083. EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
  2084. write_count & rx_queue->ptr_mask);
  2085. efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
  2086. efx_rx_queue_index(rx_queue));
  2087. }
  2088. static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
  2089. static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
  2090. {
  2091. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  2092. MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
  2093. efx_qword_t event;
  2094. EFX_POPULATE_QWORD_2(event,
  2095. ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
  2096. ESF_DZ_EV_DATA, EFX_EF10_REFILL);
  2097. MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
  2098. /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
  2099. * already swapped the data to little-endian order.
  2100. */
  2101. memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
  2102. sizeof(efx_qword_t));
  2103. efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
  2104. inbuf, sizeof(inbuf), 0,
  2105. efx_ef10_rx_defer_refill_complete, 0);
  2106. }
  2107. static void
  2108. efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
  2109. int rc, efx_dword_t *outbuf,
  2110. size_t outlen_actual)
  2111. {
  2112. /* nothing to do */
  2113. }
  2114. static int efx_ef10_ev_probe(struct efx_channel *channel)
  2115. {
  2116. return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
  2117. (channel->eventq_mask + 1) *
  2118. sizeof(efx_qword_t),
  2119. GFP_KERNEL);
  2120. }
  2121. static void efx_ef10_ev_fini(struct efx_channel *channel)
  2122. {
  2123. MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
  2124. MCDI_DECLARE_BUF_ERR(outbuf);
  2125. struct efx_nic *efx = channel->efx;
  2126. size_t outlen;
  2127. int rc;
  2128. MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
  2129. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
  2130. outbuf, sizeof(outbuf), &outlen);
  2131. if (rc && rc != -EALREADY)
  2132. goto fail;
  2133. return;
  2134. fail:
  2135. efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
  2136. outbuf, outlen, rc);
  2137. }
  2138. static int efx_ef10_ev_init(struct efx_channel *channel)
  2139. {
  2140. MCDI_DECLARE_BUF(inbuf,
  2141. MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
  2142. EFX_BUF_SIZE));
  2143. MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
  2144. size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
  2145. struct efx_nic *efx = channel->efx;
  2146. struct efx_ef10_nic_data *nic_data;
  2147. bool supports_rx_merge;
  2148. size_t inlen, outlen;
  2149. unsigned int enabled, implemented;
  2150. dma_addr_t dma_addr;
  2151. int rc;
  2152. int i;
  2153. nic_data = efx->nic_data;
  2154. supports_rx_merge =
  2155. !!(nic_data->datapath_caps &
  2156. 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
  2157. /* Fill event queue with all ones (i.e. empty events) */
  2158. memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
  2159. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
  2160. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
  2161. /* INIT_EVQ expects index in vector table, not absolute */
  2162. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
  2163. MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
  2164. INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
  2165. INIT_EVQ_IN_FLAG_RX_MERGE, 1,
  2166. INIT_EVQ_IN_FLAG_TX_MERGE, 1,
  2167. INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
  2168. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
  2169. MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
  2170. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
  2171. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
  2172. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
  2173. MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
  2174. MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
  2175. dma_addr = channel->eventq.buf.dma_addr;
  2176. for (i = 0; i < entries; ++i) {
  2177. MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
  2178. dma_addr += EFX_BUF_SIZE;
  2179. }
  2180. inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
  2181. rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
  2182. outbuf, sizeof(outbuf), &outlen);
  2183. /* IRQ return is ignored */
  2184. if (channel->channel || rc)
  2185. return rc;
  2186. /* Successfully created event queue on channel 0 */
  2187. rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
  2188. if (rc == -ENOSYS) {
  2189. /* GET_WORKAROUNDS was implemented before the bug26807
  2190. * workaround, thus the latter must be unavailable in this fw
  2191. */
  2192. nic_data->workaround_26807 = false;
  2193. rc = 0;
  2194. } else if (rc) {
  2195. goto fail;
  2196. } else {
  2197. nic_data->workaround_26807 =
  2198. !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
  2199. if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
  2200. !nic_data->workaround_26807) {
  2201. unsigned int flags;
  2202. rc = efx_mcdi_set_workaround(efx,
  2203. MC_CMD_WORKAROUND_BUG26807,
  2204. true, &flags);
  2205. if (!rc) {
  2206. if (flags &
  2207. 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
  2208. netif_info(efx, drv, efx->net_dev,
  2209. "other functions on NIC have been reset\n");
  2210. /* With MCFW v4.6.x and earlier, the
  2211. * boot count will have incremented,
  2212. * so re-read the warm_boot_count
  2213. * value now to ensure this function
  2214. * doesn't think it has changed next
  2215. * time it checks.
  2216. */
  2217. rc = efx_ef10_get_warm_boot_count(efx);
  2218. if (rc >= 0) {
  2219. nic_data->warm_boot_count = rc;
  2220. rc = 0;
  2221. }
  2222. }
  2223. nic_data->workaround_26807 = true;
  2224. } else if (rc == -EPERM) {
  2225. rc = 0;
  2226. }
  2227. }
  2228. }
  2229. if (!rc)
  2230. return 0;
  2231. fail:
  2232. efx_ef10_ev_fini(channel);
  2233. return rc;
  2234. }
  2235. static void efx_ef10_ev_remove(struct efx_channel *channel)
  2236. {
  2237. efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
  2238. }
  2239. static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
  2240. unsigned int rx_queue_label)
  2241. {
  2242. struct efx_nic *efx = rx_queue->efx;
  2243. netif_info(efx, hw, efx->net_dev,
  2244. "rx event arrived on queue %d labeled as queue %u\n",
  2245. efx_rx_queue_index(rx_queue), rx_queue_label);
  2246. efx_schedule_reset(efx, RESET_TYPE_DISABLE);
  2247. }
  2248. static void
  2249. efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
  2250. unsigned int actual, unsigned int expected)
  2251. {
  2252. unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
  2253. struct efx_nic *efx = rx_queue->efx;
  2254. netif_info(efx, hw, efx->net_dev,
  2255. "dropped %d events (index=%d expected=%d)\n",
  2256. dropped, actual, expected);
  2257. efx_schedule_reset(efx, RESET_TYPE_DISABLE);
  2258. }
  2259. /* partially received RX was aborted. clean up. */
  2260. static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
  2261. {
  2262. unsigned int rx_desc_ptr;
  2263. netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
  2264. "scattered RX aborted (dropping %u buffers)\n",
  2265. rx_queue->scatter_n);
  2266. rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
  2267. efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
  2268. 0, EFX_RX_PKT_DISCARD);
  2269. rx_queue->removed_count += rx_queue->scatter_n;
  2270. rx_queue->scatter_n = 0;
  2271. rx_queue->scatter_len = 0;
  2272. ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
  2273. }
  2274. static int efx_ef10_handle_rx_event(struct efx_channel *channel,
  2275. const efx_qword_t *event)
  2276. {
  2277. unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
  2278. unsigned int n_descs, n_packets, i;
  2279. struct efx_nic *efx = channel->efx;
  2280. struct efx_rx_queue *rx_queue;
  2281. bool rx_cont;
  2282. u16 flags = 0;
  2283. if (unlikely(ACCESS_ONCE(efx->reset_pending)))
  2284. return 0;
  2285. /* Basic packet information */
  2286. rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
  2287. next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
  2288. rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
  2289. rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
  2290. rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
  2291. if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
  2292. netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
  2293. EFX_QWORD_FMT "\n",
  2294. EFX_QWORD_VAL(*event));
  2295. rx_queue = efx_channel_get_rx_queue(channel);
  2296. if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
  2297. efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
  2298. n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
  2299. ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
  2300. if (n_descs != rx_queue->scatter_n + 1) {
  2301. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  2302. /* detect rx abort */
  2303. if (unlikely(n_descs == rx_queue->scatter_n)) {
  2304. if (rx_queue->scatter_n == 0 || rx_bytes != 0)
  2305. netdev_WARN(efx->net_dev,
  2306. "invalid RX abort: scatter_n=%u event="
  2307. EFX_QWORD_FMT "\n",
  2308. rx_queue->scatter_n,
  2309. EFX_QWORD_VAL(*event));
  2310. efx_ef10_handle_rx_abort(rx_queue);
  2311. return 0;
  2312. }
  2313. /* Check that RX completion merging is valid, i.e.
  2314. * the current firmware supports it and this is a
  2315. * non-scattered packet.
  2316. */
  2317. if (!(nic_data->datapath_caps &
  2318. (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
  2319. rx_queue->scatter_n != 0 || rx_cont) {
  2320. efx_ef10_handle_rx_bad_lbits(
  2321. rx_queue, next_ptr_lbits,
  2322. (rx_queue->removed_count +
  2323. rx_queue->scatter_n + 1) &
  2324. ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
  2325. return 0;
  2326. }
  2327. /* Merged completion for multiple non-scattered packets */
  2328. rx_queue->scatter_n = 1;
  2329. rx_queue->scatter_len = 0;
  2330. n_packets = n_descs;
  2331. ++channel->n_rx_merge_events;
  2332. channel->n_rx_merge_packets += n_packets;
  2333. flags |= EFX_RX_PKT_PREFIX_LEN;
  2334. } else {
  2335. ++rx_queue->scatter_n;
  2336. rx_queue->scatter_len += rx_bytes;
  2337. if (rx_cont)
  2338. return 0;
  2339. n_packets = 1;
  2340. }
  2341. if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
  2342. flags |= EFX_RX_PKT_DISCARD;
  2343. if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
  2344. channel->n_rx_ip_hdr_chksum_err += n_packets;
  2345. } else if (unlikely(EFX_QWORD_FIELD(*event,
  2346. ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
  2347. channel->n_rx_tcp_udp_chksum_err += n_packets;
  2348. } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
  2349. rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
  2350. flags |= EFX_RX_PKT_CSUMMED;
  2351. }
  2352. if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
  2353. flags |= EFX_RX_PKT_TCP;
  2354. channel->irq_mod_score += 2 * n_packets;
  2355. /* Handle received packet(s) */
  2356. for (i = 0; i < n_packets; i++) {
  2357. efx_rx_packet(rx_queue,
  2358. rx_queue->removed_count & rx_queue->ptr_mask,
  2359. rx_queue->scatter_n, rx_queue->scatter_len,
  2360. flags);
  2361. rx_queue->removed_count += rx_queue->scatter_n;
  2362. }
  2363. rx_queue->scatter_n = 0;
  2364. rx_queue->scatter_len = 0;
  2365. return n_packets;
  2366. }
  2367. static int
  2368. efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
  2369. {
  2370. struct efx_nic *efx = channel->efx;
  2371. struct efx_tx_queue *tx_queue;
  2372. unsigned int tx_ev_desc_ptr;
  2373. unsigned int tx_ev_q_label;
  2374. int tx_descs = 0;
  2375. if (unlikely(ACCESS_ONCE(efx->reset_pending)))
  2376. return 0;
  2377. if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
  2378. return 0;
  2379. /* Transmit completion */
  2380. tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
  2381. tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
  2382. tx_queue = efx_channel_get_tx_queue(channel,
  2383. tx_ev_q_label % EFX_TXQ_TYPES);
  2384. tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
  2385. tx_queue->ptr_mask);
  2386. efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
  2387. return tx_descs;
  2388. }
  2389. static void
  2390. efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
  2391. {
  2392. struct efx_nic *efx = channel->efx;
  2393. int subcode;
  2394. subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
  2395. switch (subcode) {
  2396. case ESE_DZ_DRV_TIMER_EV:
  2397. case ESE_DZ_DRV_WAKE_UP_EV:
  2398. break;
  2399. case ESE_DZ_DRV_START_UP_EV:
  2400. /* event queue init complete. ok. */
  2401. break;
  2402. default:
  2403. netif_err(efx, hw, efx->net_dev,
  2404. "channel %d unknown driver event type %d"
  2405. " (data " EFX_QWORD_FMT ")\n",
  2406. channel->channel, subcode,
  2407. EFX_QWORD_VAL(*event));
  2408. }
  2409. }
  2410. static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
  2411. efx_qword_t *event)
  2412. {
  2413. struct efx_nic *efx = channel->efx;
  2414. u32 subcode;
  2415. subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
  2416. switch (subcode) {
  2417. case EFX_EF10_TEST:
  2418. channel->event_test_cpu = raw_smp_processor_id();
  2419. break;
  2420. case EFX_EF10_REFILL:
  2421. /* The queue must be empty, so we won't receive any rx
  2422. * events, so efx_process_channel() won't refill the
  2423. * queue. Refill it here
  2424. */
  2425. efx_fast_push_rx_descriptors(&channel->rx_queue, true);
  2426. break;
  2427. default:
  2428. netif_err(efx, hw, efx->net_dev,
  2429. "channel %d unknown driver event type %u"
  2430. " (data " EFX_QWORD_FMT ")\n",
  2431. channel->channel, (unsigned) subcode,
  2432. EFX_QWORD_VAL(*event));
  2433. }
  2434. }
  2435. static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
  2436. {
  2437. struct efx_nic *efx = channel->efx;
  2438. efx_qword_t event, *p_event;
  2439. unsigned int read_ptr;
  2440. int ev_code;
  2441. int tx_descs = 0;
  2442. int spent = 0;
  2443. if (quota <= 0)
  2444. return spent;
  2445. read_ptr = channel->eventq_read_ptr;
  2446. for (;;) {
  2447. p_event = efx_event(channel, read_ptr);
  2448. event = *p_event;
  2449. if (!efx_event_present(&event))
  2450. break;
  2451. EFX_SET_QWORD(*p_event);
  2452. ++read_ptr;
  2453. ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
  2454. netif_vdbg(efx, drv, efx->net_dev,
  2455. "processing event on %d " EFX_QWORD_FMT "\n",
  2456. channel->channel, EFX_QWORD_VAL(event));
  2457. switch (ev_code) {
  2458. case ESE_DZ_EV_CODE_MCDI_EV:
  2459. efx_mcdi_process_event(channel, &event);
  2460. break;
  2461. case ESE_DZ_EV_CODE_RX_EV:
  2462. spent += efx_ef10_handle_rx_event(channel, &event);
  2463. if (spent >= quota) {
  2464. /* XXX can we split a merged event to
  2465. * avoid going over-quota?
  2466. */
  2467. spent = quota;
  2468. goto out;
  2469. }
  2470. break;
  2471. case ESE_DZ_EV_CODE_TX_EV:
  2472. tx_descs += efx_ef10_handle_tx_event(channel, &event);
  2473. if (tx_descs > efx->txq_entries) {
  2474. spent = quota;
  2475. goto out;
  2476. } else if (++spent == quota) {
  2477. goto out;
  2478. }
  2479. break;
  2480. case ESE_DZ_EV_CODE_DRIVER_EV:
  2481. efx_ef10_handle_driver_event(channel, &event);
  2482. if (++spent == quota)
  2483. goto out;
  2484. break;
  2485. case EFX_EF10_DRVGEN_EV:
  2486. efx_ef10_handle_driver_generated_event(channel, &event);
  2487. break;
  2488. default:
  2489. netif_err(efx, hw, efx->net_dev,
  2490. "channel %d unknown event type %d"
  2491. " (data " EFX_QWORD_FMT ")\n",
  2492. channel->channel, ev_code,
  2493. EFX_QWORD_VAL(event));
  2494. }
  2495. }
  2496. out:
  2497. channel->eventq_read_ptr = read_ptr;
  2498. return spent;
  2499. }
  2500. static void efx_ef10_ev_read_ack(struct efx_channel *channel)
  2501. {
  2502. struct efx_nic *efx = channel->efx;
  2503. efx_dword_t rptr;
  2504. if (EFX_EF10_WORKAROUND_35388(efx)) {
  2505. BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
  2506. (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
  2507. BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
  2508. (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
  2509. EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
  2510. EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
  2511. ERF_DD_EVQ_IND_RPTR,
  2512. (channel->eventq_read_ptr &
  2513. channel->eventq_mask) >>
  2514. ERF_DD_EVQ_IND_RPTR_WIDTH);
  2515. efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
  2516. channel->channel);
  2517. EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
  2518. EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
  2519. ERF_DD_EVQ_IND_RPTR,
  2520. channel->eventq_read_ptr &
  2521. ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
  2522. efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
  2523. channel->channel);
  2524. } else {
  2525. EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
  2526. channel->eventq_read_ptr &
  2527. channel->eventq_mask);
  2528. efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
  2529. }
  2530. }
  2531. static void efx_ef10_ev_test_generate(struct efx_channel *channel)
  2532. {
  2533. MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
  2534. struct efx_nic *efx = channel->efx;
  2535. efx_qword_t event;
  2536. int rc;
  2537. EFX_POPULATE_QWORD_2(event,
  2538. ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
  2539. ESF_DZ_EV_DATA, EFX_EF10_TEST);
  2540. MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
  2541. /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
  2542. * already swapped the data to little-endian order.
  2543. */
  2544. memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
  2545. sizeof(efx_qword_t));
  2546. rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
  2547. NULL, 0, NULL);
  2548. if (rc != 0)
  2549. goto fail;
  2550. return;
  2551. fail:
  2552. WARN_ON(true);
  2553. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  2554. }
  2555. void efx_ef10_handle_drain_event(struct efx_nic *efx)
  2556. {
  2557. if (atomic_dec_and_test(&efx->active_queues))
  2558. wake_up(&efx->flush_wq);
  2559. WARN_ON(atomic_read(&efx->active_queues) < 0);
  2560. }
  2561. static int efx_ef10_fini_dmaq(struct efx_nic *efx)
  2562. {
  2563. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  2564. struct efx_channel *channel;
  2565. struct efx_tx_queue *tx_queue;
  2566. struct efx_rx_queue *rx_queue;
  2567. int pending;
  2568. /* If the MC has just rebooted, the TX/RX queues will have already been
  2569. * torn down, but efx->active_queues needs to be set to zero.
  2570. */
  2571. if (nic_data->must_realloc_vis) {
  2572. atomic_set(&efx->active_queues, 0);
  2573. return 0;
  2574. }
  2575. /* Do not attempt to write to the NIC during EEH recovery */
  2576. if (efx->state != STATE_RECOVERY) {
  2577. efx_for_each_channel(channel, efx) {
  2578. efx_for_each_channel_rx_queue(rx_queue, channel)
  2579. efx_ef10_rx_fini(rx_queue);
  2580. efx_for_each_channel_tx_queue(tx_queue, channel)
  2581. efx_ef10_tx_fini(tx_queue);
  2582. }
  2583. wait_event_timeout(efx->flush_wq,
  2584. atomic_read(&efx->active_queues) == 0,
  2585. msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
  2586. pending = atomic_read(&efx->active_queues);
  2587. if (pending) {
  2588. netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
  2589. pending);
  2590. return -ETIMEDOUT;
  2591. }
  2592. }
  2593. return 0;
  2594. }
  2595. static void efx_ef10_prepare_flr(struct efx_nic *efx)
  2596. {
  2597. atomic_set(&efx->active_queues, 0);
  2598. }
  2599. static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
  2600. const struct efx_filter_spec *right)
  2601. {
  2602. if ((left->match_flags ^ right->match_flags) |
  2603. ((left->flags ^ right->flags) &
  2604. (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
  2605. return false;
  2606. return memcmp(&left->outer_vid, &right->outer_vid,
  2607. sizeof(struct efx_filter_spec) -
  2608. offsetof(struct efx_filter_spec, outer_vid)) == 0;
  2609. }
  2610. static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
  2611. {
  2612. BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
  2613. return jhash2((const u32 *)&spec->outer_vid,
  2614. (sizeof(struct efx_filter_spec) -
  2615. offsetof(struct efx_filter_spec, outer_vid)) / 4,
  2616. 0);
  2617. /* XXX should we randomise the initval? */
  2618. }
  2619. /* Decide whether a filter should be exclusive or else should allow
  2620. * delivery to additional recipients. Currently we decide that
  2621. * filters for specific local unicast MAC and IP addresses are
  2622. * exclusive.
  2623. */
  2624. static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
  2625. {
  2626. if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
  2627. !is_multicast_ether_addr(spec->loc_mac))
  2628. return true;
  2629. if ((spec->match_flags &
  2630. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
  2631. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
  2632. if (spec->ether_type == htons(ETH_P_IP) &&
  2633. !ipv4_is_multicast(spec->loc_host[0]))
  2634. return true;
  2635. if (spec->ether_type == htons(ETH_P_IPV6) &&
  2636. ((const u8 *)spec->loc_host)[0] != 0xff)
  2637. return true;
  2638. }
  2639. return false;
  2640. }
  2641. static struct efx_filter_spec *
  2642. efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
  2643. unsigned int filter_idx)
  2644. {
  2645. return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
  2646. ~EFX_EF10_FILTER_FLAGS);
  2647. }
  2648. static unsigned int
  2649. efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
  2650. unsigned int filter_idx)
  2651. {
  2652. return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
  2653. }
  2654. static void
  2655. efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
  2656. unsigned int filter_idx,
  2657. const struct efx_filter_spec *spec,
  2658. unsigned int flags)
  2659. {
  2660. table->entry[filter_idx].spec = (unsigned long)spec | flags;
  2661. }
  2662. static void efx_ef10_filter_push_prep(struct efx_nic *efx,
  2663. const struct efx_filter_spec *spec,
  2664. efx_dword_t *inbuf, u64 handle,
  2665. bool replacing)
  2666. {
  2667. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  2668. u32 flags = spec->flags;
  2669. memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
  2670. /* Remove RSS flag if we don't have an RSS context. */
  2671. if (flags & EFX_FILTER_FLAG_RX_RSS &&
  2672. spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
  2673. nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
  2674. flags &= ~EFX_FILTER_FLAG_RX_RSS;
  2675. if (replacing) {
  2676. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
  2677. MC_CMD_FILTER_OP_IN_OP_REPLACE);
  2678. MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
  2679. } else {
  2680. u32 match_fields = 0;
  2681. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
  2682. efx_ef10_filter_is_exclusive(spec) ?
  2683. MC_CMD_FILTER_OP_IN_OP_INSERT :
  2684. MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
  2685. /* Convert match flags and values. Unlike almost
  2686. * everything else in MCDI, these fields are in
  2687. * network byte order.
  2688. */
  2689. if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
  2690. match_fields |=
  2691. is_multicast_ether_addr(spec->loc_mac) ?
  2692. 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
  2693. 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
  2694. #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
  2695. if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
  2696. match_fields |= \
  2697. 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
  2698. mcdi_field ## _LBN; \
  2699. BUILD_BUG_ON( \
  2700. MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
  2701. sizeof(spec->gen_field)); \
  2702. memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
  2703. &spec->gen_field, sizeof(spec->gen_field)); \
  2704. }
  2705. COPY_FIELD(REM_HOST, rem_host, SRC_IP);
  2706. COPY_FIELD(LOC_HOST, loc_host, DST_IP);
  2707. COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
  2708. COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
  2709. COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
  2710. COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
  2711. COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
  2712. COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
  2713. COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
  2714. COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
  2715. #undef COPY_FIELD
  2716. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
  2717. match_fields);
  2718. }
  2719. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
  2720. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
  2721. spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
  2722. MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
  2723. MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
  2724. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
  2725. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
  2726. MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
  2727. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
  2728. spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
  2729. 0 : spec->dmaq_id);
  2730. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
  2731. (flags & EFX_FILTER_FLAG_RX_RSS) ?
  2732. MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
  2733. MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
  2734. if (flags & EFX_FILTER_FLAG_RX_RSS)
  2735. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
  2736. spec->rss_context !=
  2737. EFX_FILTER_RSS_CONTEXT_DEFAULT ?
  2738. spec->rss_context : nic_data->rx_rss_context);
  2739. }
  2740. static int efx_ef10_filter_push(struct efx_nic *efx,
  2741. const struct efx_filter_spec *spec,
  2742. u64 *handle, bool replacing)
  2743. {
  2744. MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
  2745. MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
  2746. int rc;
  2747. efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
  2748. rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
  2749. outbuf, sizeof(outbuf), NULL);
  2750. if (rc == 0)
  2751. *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
  2752. if (rc == -ENOSPC)
  2753. rc = -EBUSY; /* to match efx_farch_filter_insert() */
  2754. return rc;
  2755. }
  2756. static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
  2757. {
  2758. unsigned int match_flags = spec->match_flags;
  2759. u32 mcdi_flags = 0;
  2760. if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
  2761. match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
  2762. mcdi_flags |=
  2763. is_multicast_ether_addr(spec->loc_mac) ?
  2764. (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
  2765. (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
  2766. }
  2767. #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
  2768. unsigned int old_match_flags = match_flags; \
  2769. match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
  2770. if (match_flags != old_match_flags) \
  2771. mcdi_flags |= \
  2772. (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
  2773. mcdi_field ## _LBN); \
  2774. }
  2775. MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
  2776. MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
  2777. MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
  2778. MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
  2779. MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
  2780. MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
  2781. MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
  2782. MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
  2783. MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
  2784. MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
  2785. #undef MAP_FILTER_TO_MCDI_FLAG
  2786. /* Did we map them all? */
  2787. WARN_ON_ONCE(match_flags);
  2788. return mcdi_flags;
  2789. }
  2790. static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
  2791. const struct efx_filter_spec *spec)
  2792. {
  2793. u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
  2794. unsigned int match_pri;
  2795. for (match_pri = 0;
  2796. match_pri < table->rx_match_count;
  2797. match_pri++)
  2798. if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
  2799. return match_pri;
  2800. return -EPROTONOSUPPORT;
  2801. }
  2802. static s32 efx_ef10_filter_insert(struct efx_nic *efx,
  2803. struct efx_filter_spec *spec,
  2804. bool replace_equal)
  2805. {
  2806. struct efx_ef10_filter_table *table = efx->filter_state;
  2807. DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
  2808. struct efx_filter_spec *saved_spec;
  2809. unsigned int match_pri, hash;
  2810. unsigned int priv_flags;
  2811. bool replacing = false;
  2812. int ins_index = -1;
  2813. DEFINE_WAIT(wait);
  2814. bool is_mc_recip;
  2815. s32 rc;
  2816. /* For now, only support RX filters */
  2817. if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
  2818. EFX_FILTER_FLAG_RX)
  2819. return -EINVAL;
  2820. rc = efx_ef10_filter_pri(table, spec);
  2821. if (rc < 0)
  2822. return rc;
  2823. match_pri = rc;
  2824. hash = efx_ef10_filter_hash(spec);
  2825. is_mc_recip = efx_filter_is_mc_recipient(spec);
  2826. if (is_mc_recip)
  2827. bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
  2828. /* Find any existing filters with the same match tuple or
  2829. * else a free slot to insert at. If any of them are busy,
  2830. * we have to wait and retry.
  2831. */
  2832. for (;;) {
  2833. unsigned int depth = 1;
  2834. unsigned int i;
  2835. spin_lock_bh(&efx->filter_lock);
  2836. for (;;) {
  2837. i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
  2838. saved_spec = efx_ef10_filter_entry_spec(table, i);
  2839. if (!saved_spec) {
  2840. if (ins_index < 0)
  2841. ins_index = i;
  2842. } else if (efx_ef10_filter_equal(spec, saved_spec)) {
  2843. if (table->entry[i].spec &
  2844. EFX_EF10_FILTER_FLAG_BUSY)
  2845. break;
  2846. if (spec->priority < saved_spec->priority &&
  2847. spec->priority != EFX_FILTER_PRI_AUTO) {
  2848. rc = -EPERM;
  2849. goto out_unlock;
  2850. }
  2851. if (!is_mc_recip) {
  2852. /* This is the only one */
  2853. if (spec->priority ==
  2854. saved_spec->priority &&
  2855. !replace_equal) {
  2856. rc = -EEXIST;
  2857. goto out_unlock;
  2858. }
  2859. ins_index = i;
  2860. goto found;
  2861. } else if (spec->priority >
  2862. saved_spec->priority ||
  2863. (spec->priority ==
  2864. saved_spec->priority &&
  2865. replace_equal)) {
  2866. if (ins_index < 0)
  2867. ins_index = i;
  2868. else
  2869. __set_bit(depth, mc_rem_map);
  2870. }
  2871. }
  2872. /* Once we reach the maximum search depth, use
  2873. * the first suitable slot or return -EBUSY if
  2874. * there was none
  2875. */
  2876. if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
  2877. if (ins_index < 0) {
  2878. rc = -EBUSY;
  2879. goto out_unlock;
  2880. }
  2881. goto found;
  2882. }
  2883. ++depth;
  2884. }
  2885. prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
  2886. spin_unlock_bh(&efx->filter_lock);
  2887. schedule();
  2888. }
  2889. found:
  2890. /* Create a software table entry if necessary, and mark it
  2891. * busy. We might yet fail to insert, but any attempt to
  2892. * insert a conflicting filter while we're waiting for the
  2893. * firmware must find the busy entry.
  2894. */
  2895. saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
  2896. if (saved_spec) {
  2897. if (spec->priority == EFX_FILTER_PRI_AUTO &&
  2898. saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
  2899. /* Just make sure it won't be removed */
  2900. if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
  2901. saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
  2902. table->entry[ins_index].spec &=
  2903. ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
  2904. rc = ins_index;
  2905. goto out_unlock;
  2906. }
  2907. replacing = true;
  2908. priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
  2909. } else {
  2910. saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
  2911. if (!saved_spec) {
  2912. rc = -ENOMEM;
  2913. goto out_unlock;
  2914. }
  2915. *saved_spec = *spec;
  2916. priv_flags = 0;
  2917. }
  2918. efx_ef10_filter_set_entry(table, ins_index, saved_spec,
  2919. priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
  2920. /* Mark lower-priority multicast recipients busy prior to removal */
  2921. if (is_mc_recip) {
  2922. unsigned int depth, i;
  2923. for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
  2924. i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
  2925. if (test_bit(depth, mc_rem_map))
  2926. table->entry[i].spec |=
  2927. EFX_EF10_FILTER_FLAG_BUSY;
  2928. }
  2929. }
  2930. spin_unlock_bh(&efx->filter_lock);
  2931. rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
  2932. replacing);
  2933. /* Finalise the software table entry */
  2934. spin_lock_bh(&efx->filter_lock);
  2935. if (rc == 0) {
  2936. if (replacing) {
  2937. /* Update the fields that may differ */
  2938. if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
  2939. saved_spec->flags |=
  2940. EFX_FILTER_FLAG_RX_OVER_AUTO;
  2941. saved_spec->priority = spec->priority;
  2942. saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
  2943. saved_spec->flags |= spec->flags;
  2944. saved_spec->rss_context = spec->rss_context;
  2945. saved_spec->dmaq_id = spec->dmaq_id;
  2946. }
  2947. } else if (!replacing) {
  2948. kfree(saved_spec);
  2949. saved_spec = NULL;
  2950. }
  2951. efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
  2952. /* Remove and finalise entries for lower-priority multicast
  2953. * recipients
  2954. */
  2955. if (is_mc_recip) {
  2956. MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
  2957. unsigned int depth, i;
  2958. memset(inbuf, 0, sizeof(inbuf));
  2959. for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
  2960. if (!test_bit(depth, mc_rem_map))
  2961. continue;
  2962. i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
  2963. saved_spec = efx_ef10_filter_entry_spec(table, i);
  2964. priv_flags = efx_ef10_filter_entry_flags(table, i);
  2965. if (rc == 0) {
  2966. spin_unlock_bh(&efx->filter_lock);
  2967. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
  2968. MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
  2969. MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
  2970. table->entry[i].handle);
  2971. rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
  2972. inbuf, sizeof(inbuf),
  2973. NULL, 0, NULL);
  2974. spin_lock_bh(&efx->filter_lock);
  2975. }
  2976. if (rc == 0) {
  2977. kfree(saved_spec);
  2978. saved_spec = NULL;
  2979. priv_flags = 0;
  2980. } else {
  2981. priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
  2982. }
  2983. efx_ef10_filter_set_entry(table, i, saved_spec,
  2984. priv_flags);
  2985. }
  2986. }
  2987. /* If successful, return the inserted filter ID */
  2988. if (rc == 0)
  2989. rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
  2990. wake_up_all(&table->waitq);
  2991. out_unlock:
  2992. spin_unlock_bh(&efx->filter_lock);
  2993. finish_wait(&table->waitq, &wait);
  2994. return rc;
  2995. }
  2996. static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
  2997. {
  2998. /* no need to do anything here on EF10 */
  2999. }
  3000. /* Remove a filter.
  3001. * If !by_index, remove by ID
  3002. * If by_index, remove by index
  3003. * Filter ID may come from userland and must be range-checked.
  3004. */
  3005. static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
  3006. unsigned int priority_mask,
  3007. u32 filter_id, bool by_index)
  3008. {
  3009. unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
  3010. struct efx_ef10_filter_table *table = efx->filter_state;
  3011. MCDI_DECLARE_BUF(inbuf,
  3012. MC_CMD_FILTER_OP_IN_HANDLE_OFST +
  3013. MC_CMD_FILTER_OP_IN_HANDLE_LEN);
  3014. struct efx_filter_spec *spec;
  3015. DEFINE_WAIT(wait);
  3016. int rc;
  3017. /* Find the software table entry and mark it busy. Don't
  3018. * remove it yet; any attempt to update while we're waiting
  3019. * for the firmware must find the busy entry.
  3020. */
  3021. for (;;) {
  3022. spin_lock_bh(&efx->filter_lock);
  3023. if (!(table->entry[filter_idx].spec &
  3024. EFX_EF10_FILTER_FLAG_BUSY))
  3025. break;
  3026. prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
  3027. spin_unlock_bh(&efx->filter_lock);
  3028. schedule();
  3029. }
  3030. spec = efx_ef10_filter_entry_spec(table, filter_idx);
  3031. if (!spec ||
  3032. (!by_index &&
  3033. efx_ef10_filter_pri(table, spec) !=
  3034. filter_id / HUNT_FILTER_TBL_ROWS)) {
  3035. rc = -ENOENT;
  3036. goto out_unlock;
  3037. }
  3038. if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
  3039. priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
  3040. /* Just remove flags */
  3041. spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
  3042. table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
  3043. rc = 0;
  3044. goto out_unlock;
  3045. }
  3046. if (!(priority_mask & (1U << spec->priority))) {
  3047. rc = -ENOENT;
  3048. goto out_unlock;
  3049. }
  3050. table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
  3051. spin_unlock_bh(&efx->filter_lock);
  3052. if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
  3053. /* Reset to an automatic filter */
  3054. struct efx_filter_spec new_spec = *spec;
  3055. new_spec.priority = EFX_FILTER_PRI_AUTO;
  3056. new_spec.flags = (EFX_FILTER_FLAG_RX |
  3057. (efx_rss_enabled(efx) ?
  3058. EFX_FILTER_FLAG_RX_RSS : 0));
  3059. new_spec.dmaq_id = 0;
  3060. new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
  3061. rc = efx_ef10_filter_push(efx, &new_spec,
  3062. &table->entry[filter_idx].handle,
  3063. true);
  3064. spin_lock_bh(&efx->filter_lock);
  3065. if (rc == 0)
  3066. *spec = new_spec;
  3067. } else {
  3068. /* Really remove the filter */
  3069. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
  3070. efx_ef10_filter_is_exclusive(spec) ?
  3071. MC_CMD_FILTER_OP_IN_OP_REMOVE :
  3072. MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
  3073. MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
  3074. table->entry[filter_idx].handle);
  3075. rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
  3076. inbuf, sizeof(inbuf), NULL, 0, NULL);
  3077. spin_lock_bh(&efx->filter_lock);
  3078. if (rc == 0) {
  3079. kfree(spec);
  3080. efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
  3081. }
  3082. }
  3083. table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
  3084. wake_up_all(&table->waitq);
  3085. out_unlock:
  3086. spin_unlock_bh(&efx->filter_lock);
  3087. finish_wait(&table->waitq, &wait);
  3088. return rc;
  3089. }
  3090. static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
  3091. enum efx_filter_priority priority,
  3092. u32 filter_id)
  3093. {
  3094. return efx_ef10_filter_remove_internal(efx, 1U << priority,
  3095. filter_id, false);
  3096. }
  3097. static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
  3098. {
  3099. return filter_id % HUNT_FILTER_TBL_ROWS;
  3100. }
  3101. static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
  3102. enum efx_filter_priority priority,
  3103. u32 filter_id)
  3104. {
  3105. if (filter_id == EFX_EF10_FILTER_ID_INVALID)
  3106. return;
  3107. efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
  3108. }
  3109. static int efx_ef10_filter_get_safe(struct efx_nic *efx,
  3110. enum efx_filter_priority priority,
  3111. u32 filter_id, struct efx_filter_spec *spec)
  3112. {
  3113. unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
  3114. struct efx_ef10_filter_table *table = efx->filter_state;
  3115. const struct efx_filter_spec *saved_spec;
  3116. int rc;
  3117. spin_lock_bh(&efx->filter_lock);
  3118. saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
  3119. if (saved_spec && saved_spec->priority == priority &&
  3120. efx_ef10_filter_pri(table, saved_spec) ==
  3121. filter_id / HUNT_FILTER_TBL_ROWS) {
  3122. *spec = *saved_spec;
  3123. rc = 0;
  3124. } else {
  3125. rc = -ENOENT;
  3126. }
  3127. spin_unlock_bh(&efx->filter_lock);
  3128. return rc;
  3129. }
  3130. static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
  3131. enum efx_filter_priority priority)
  3132. {
  3133. unsigned int priority_mask;
  3134. unsigned int i;
  3135. int rc;
  3136. priority_mask = (((1U << (priority + 1)) - 1) &
  3137. ~(1U << EFX_FILTER_PRI_AUTO));
  3138. for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
  3139. rc = efx_ef10_filter_remove_internal(efx, priority_mask,
  3140. i, true);
  3141. if (rc && rc != -ENOENT)
  3142. return rc;
  3143. }
  3144. return 0;
  3145. }
  3146. static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
  3147. enum efx_filter_priority priority)
  3148. {
  3149. struct efx_ef10_filter_table *table = efx->filter_state;
  3150. unsigned int filter_idx;
  3151. s32 count = 0;
  3152. spin_lock_bh(&efx->filter_lock);
  3153. for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
  3154. if (table->entry[filter_idx].spec &&
  3155. efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
  3156. priority)
  3157. ++count;
  3158. }
  3159. spin_unlock_bh(&efx->filter_lock);
  3160. return count;
  3161. }
  3162. static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
  3163. {
  3164. struct efx_ef10_filter_table *table = efx->filter_state;
  3165. return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
  3166. }
  3167. static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
  3168. enum efx_filter_priority priority,
  3169. u32 *buf, u32 size)
  3170. {
  3171. struct efx_ef10_filter_table *table = efx->filter_state;
  3172. struct efx_filter_spec *spec;
  3173. unsigned int filter_idx;
  3174. s32 count = 0;
  3175. spin_lock_bh(&efx->filter_lock);
  3176. for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
  3177. spec = efx_ef10_filter_entry_spec(table, filter_idx);
  3178. if (spec && spec->priority == priority) {
  3179. if (count == size) {
  3180. count = -EMSGSIZE;
  3181. break;
  3182. }
  3183. buf[count++] = (efx_ef10_filter_pri(table, spec) *
  3184. HUNT_FILTER_TBL_ROWS +
  3185. filter_idx);
  3186. }
  3187. }
  3188. spin_unlock_bh(&efx->filter_lock);
  3189. return count;
  3190. }
  3191. #ifdef CONFIG_RFS_ACCEL
  3192. static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
  3193. static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
  3194. struct efx_filter_spec *spec)
  3195. {
  3196. struct efx_ef10_filter_table *table = efx->filter_state;
  3197. MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
  3198. struct efx_filter_spec *saved_spec;
  3199. unsigned int hash, i, depth = 1;
  3200. bool replacing = false;
  3201. int ins_index = -1;
  3202. u64 cookie;
  3203. s32 rc;
  3204. /* Must be an RX filter without RSS and not for a multicast
  3205. * destination address (RFS only works for connected sockets).
  3206. * These restrictions allow us to pass only a tiny amount of
  3207. * data through to the completion function.
  3208. */
  3209. EFX_WARN_ON_PARANOID(spec->flags !=
  3210. (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
  3211. EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
  3212. EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
  3213. hash = efx_ef10_filter_hash(spec);
  3214. spin_lock_bh(&efx->filter_lock);
  3215. /* Find any existing filter with the same match tuple or else
  3216. * a free slot to insert at. If an existing filter is busy,
  3217. * we have to give up.
  3218. */
  3219. for (;;) {
  3220. i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
  3221. saved_spec = efx_ef10_filter_entry_spec(table, i);
  3222. if (!saved_spec) {
  3223. if (ins_index < 0)
  3224. ins_index = i;
  3225. } else if (efx_ef10_filter_equal(spec, saved_spec)) {
  3226. if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
  3227. rc = -EBUSY;
  3228. goto fail_unlock;
  3229. }
  3230. if (spec->priority < saved_spec->priority) {
  3231. rc = -EPERM;
  3232. goto fail_unlock;
  3233. }
  3234. ins_index = i;
  3235. break;
  3236. }
  3237. /* Once we reach the maximum search depth, use the
  3238. * first suitable slot or return -EBUSY if there was
  3239. * none
  3240. */
  3241. if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
  3242. if (ins_index < 0) {
  3243. rc = -EBUSY;
  3244. goto fail_unlock;
  3245. }
  3246. break;
  3247. }
  3248. ++depth;
  3249. }
  3250. /* Create a software table entry if necessary, and mark it
  3251. * busy. We might yet fail to insert, but any attempt to
  3252. * insert a conflicting filter while we're waiting for the
  3253. * firmware must find the busy entry.
  3254. */
  3255. saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
  3256. if (saved_spec) {
  3257. replacing = true;
  3258. } else {
  3259. saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
  3260. if (!saved_spec) {
  3261. rc = -ENOMEM;
  3262. goto fail_unlock;
  3263. }
  3264. *saved_spec = *spec;
  3265. }
  3266. efx_ef10_filter_set_entry(table, ins_index, saved_spec,
  3267. EFX_EF10_FILTER_FLAG_BUSY);
  3268. spin_unlock_bh(&efx->filter_lock);
  3269. /* Pack up the variables needed on completion */
  3270. cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
  3271. efx_ef10_filter_push_prep(efx, spec, inbuf,
  3272. table->entry[ins_index].handle, replacing);
  3273. efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
  3274. MC_CMD_FILTER_OP_OUT_LEN,
  3275. efx_ef10_filter_rfs_insert_complete, cookie);
  3276. return ins_index;
  3277. fail_unlock:
  3278. spin_unlock_bh(&efx->filter_lock);
  3279. return rc;
  3280. }
  3281. static void
  3282. efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
  3283. int rc, efx_dword_t *outbuf,
  3284. size_t outlen_actual)
  3285. {
  3286. struct efx_ef10_filter_table *table = efx->filter_state;
  3287. unsigned int ins_index, dmaq_id;
  3288. struct efx_filter_spec *spec;
  3289. bool replacing;
  3290. /* Unpack the cookie */
  3291. replacing = cookie >> 31;
  3292. ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
  3293. dmaq_id = cookie & 0xffff;
  3294. spin_lock_bh(&efx->filter_lock);
  3295. spec = efx_ef10_filter_entry_spec(table, ins_index);
  3296. if (rc == 0) {
  3297. table->entry[ins_index].handle =
  3298. MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
  3299. if (replacing)
  3300. spec->dmaq_id = dmaq_id;
  3301. } else if (!replacing) {
  3302. kfree(spec);
  3303. spec = NULL;
  3304. }
  3305. efx_ef10_filter_set_entry(table, ins_index, spec, 0);
  3306. spin_unlock_bh(&efx->filter_lock);
  3307. wake_up_all(&table->waitq);
  3308. }
  3309. static void
  3310. efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
  3311. unsigned long filter_idx,
  3312. int rc, efx_dword_t *outbuf,
  3313. size_t outlen_actual);
  3314. static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
  3315. unsigned int filter_idx)
  3316. {
  3317. struct efx_ef10_filter_table *table = efx->filter_state;
  3318. struct efx_filter_spec *spec =
  3319. efx_ef10_filter_entry_spec(table, filter_idx);
  3320. MCDI_DECLARE_BUF(inbuf,
  3321. MC_CMD_FILTER_OP_IN_HANDLE_OFST +
  3322. MC_CMD_FILTER_OP_IN_HANDLE_LEN);
  3323. if (!spec ||
  3324. (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
  3325. spec->priority != EFX_FILTER_PRI_HINT ||
  3326. !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
  3327. flow_id, filter_idx))
  3328. return false;
  3329. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
  3330. MC_CMD_FILTER_OP_IN_OP_REMOVE);
  3331. MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
  3332. table->entry[filter_idx].handle);
  3333. if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
  3334. efx_ef10_filter_rfs_expire_complete, filter_idx))
  3335. return false;
  3336. table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
  3337. return true;
  3338. }
  3339. static void
  3340. efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
  3341. unsigned long filter_idx,
  3342. int rc, efx_dword_t *outbuf,
  3343. size_t outlen_actual)
  3344. {
  3345. struct efx_ef10_filter_table *table = efx->filter_state;
  3346. struct efx_filter_spec *spec =
  3347. efx_ef10_filter_entry_spec(table, filter_idx);
  3348. spin_lock_bh(&efx->filter_lock);
  3349. if (rc == 0) {
  3350. kfree(spec);
  3351. efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
  3352. }
  3353. table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
  3354. wake_up_all(&table->waitq);
  3355. spin_unlock_bh(&efx->filter_lock);
  3356. }
  3357. #endif /* CONFIG_RFS_ACCEL */
  3358. static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
  3359. {
  3360. int match_flags = 0;
  3361. #define MAP_FLAG(gen_flag, mcdi_field) { \
  3362. u32 old_mcdi_flags = mcdi_flags; \
  3363. mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
  3364. mcdi_field ## _LBN); \
  3365. if (mcdi_flags != old_mcdi_flags) \
  3366. match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
  3367. }
  3368. MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
  3369. MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
  3370. MAP_FLAG(REM_HOST, SRC_IP);
  3371. MAP_FLAG(LOC_HOST, DST_IP);
  3372. MAP_FLAG(REM_MAC, SRC_MAC);
  3373. MAP_FLAG(REM_PORT, SRC_PORT);
  3374. MAP_FLAG(LOC_MAC, DST_MAC);
  3375. MAP_FLAG(LOC_PORT, DST_PORT);
  3376. MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
  3377. MAP_FLAG(INNER_VID, INNER_VLAN);
  3378. MAP_FLAG(OUTER_VID, OUTER_VLAN);
  3379. MAP_FLAG(IP_PROTO, IP_PROTO);
  3380. #undef MAP_FLAG
  3381. /* Did we map them all? */
  3382. if (mcdi_flags)
  3383. return -EINVAL;
  3384. return match_flags;
  3385. }
  3386. static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
  3387. {
  3388. struct efx_ef10_filter_table *table = efx->filter_state;
  3389. struct efx_ef10_filter_vlan *vlan, *next_vlan;
  3390. /* See comment in efx_ef10_filter_table_remove() */
  3391. if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
  3392. return;
  3393. if (!table)
  3394. return;
  3395. list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
  3396. efx_ef10_filter_del_vlan_internal(efx, vlan);
  3397. }
  3398. static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
  3399. enum efx_filter_match_flags match_flags)
  3400. {
  3401. unsigned int match_pri;
  3402. int mf;
  3403. for (match_pri = 0;
  3404. match_pri < table->rx_match_count;
  3405. match_pri++) {
  3406. mf = efx_ef10_filter_match_flags_from_mcdi(
  3407. table->rx_match_mcdi_flags[match_pri]);
  3408. if (mf == match_flags)
  3409. return true;
  3410. }
  3411. return false;
  3412. }
  3413. static int efx_ef10_filter_table_probe(struct efx_nic *efx)
  3414. {
  3415. MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
  3416. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
  3417. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  3418. struct net_device *net_dev = efx->net_dev;
  3419. unsigned int pd_match_pri, pd_match_count;
  3420. struct efx_ef10_filter_table *table;
  3421. struct efx_ef10_vlan *vlan;
  3422. size_t outlen;
  3423. int rc;
  3424. if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
  3425. return -EINVAL;
  3426. if (efx->filter_state) /* already probed */
  3427. return 0;
  3428. table = kzalloc(sizeof(*table), GFP_KERNEL);
  3429. if (!table)
  3430. return -ENOMEM;
  3431. /* Find out which RX filter types are supported, and their priorities */
  3432. MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
  3433. MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
  3434. rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
  3435. inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
  3436. &outlen);
  3437. if (rc)
  3438. goto fail;
  3439. pd_match_count = MCDI_VAR_ARRAY_LEN(
  3440. outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
  3441. table->rx_match_count = 0;
  3442. for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
  3443. u32 mcdi_flags =
  3444. MCDI_ARRAY_DWORD(
  3445. outbuf,
  3446. GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
  3447. pd_match_pri);
  3448. rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
  3449. if (rc < 0) {
  3450. netif_dbg(efx, probe, efx->net_dev,
  3451. "%s: fw flags %#x pri %u not supported in driver\n",
  3452. __func__, mcdi_flags, pd_match_pri);
  3453. } else {
  3454. netif_dbg(efx, probe, efx->net_dev,
  3455. "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
  3456. __func__, mcdi_flags, pd_match_pri,
  3457. rc, table->rx_match_count);
  3458. table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
  3459. table->rx_match_count++;
  3460. }
  3461. }
  3462. if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  3463. !(efx_ef10_filter_match_supported(table,
  3464. (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
  3465. efx_ef10_filter_match_supported(table,
  3466. (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
  3467. netif_info(efx, probe, net_dev,
  3468. "VLAN filters are not supported in this firmware variant\n");
  3469. net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
  3470. efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
  3471. net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
  3472. }
  3473. table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
  3474. if (!table->entry) {
  3475. rc = -ENOMEM;
  3476. goto fail;
  3477. }
  3478. table->mc_promisc_last = false;
  3479. table->vlan_filter =
  3480. !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
  3481. INIT_LIST_HEAD(&table->vlan_list);
  3482. efx->filter_state = table;
  3483. init_waitqueue_head(&table->waitq);
  3484. list_for_each_entry(vlan, &nic_data->vlan_list, list) {
  3485. rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
  3486. if (rc)
  3487. goto fail_add_vlan;
  3488. }
  3489. return 0;
  3490. fail_add_vlan:
  3491. efx_ef10_filter_cleanup_vlans(efx);
  3492. efx->filter_state = NULL;
  3493. fail:
  3494. kfree(table);
  3495. return rc;
  3496. }
  3497. /* Caller must hold efx->filter_sem for read if race against
  3498. * efx_ef10_filter_table_remove() is possible
  3499. */
  3500. static void efx_ef10_filter_table_restore(struct efx_nic *efx)
  3501. {
  3502. struct efx_ef10_filter_table *table = efx->filter_state;
  3503. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  3504. struct efx_filter_spec *spec;
  3505. unsigned int filter_idx;
  3506. bool failed = false;
  3507. int rc;
  3508. WARN_ON(!rwsem_is_locked(&efx->filter_sem));
  3509. if (!nic_data->must_restore_filters)
  3510. return;
  3511. if (!table)
  3512. return;
  3513. spin_lock_bh(&efx->filter_lock);
  3514. for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
  3515. spec = efx_ef10_filter_entry_spec(table, filter_idx);
  3516. if (!spec)
  3517. continue;
  3518. table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
  3519. spin_unlock_bh(&efx->filter_lock);
  3520. rc = efx_ef10_filter_push(efx, spec,
  3521. &table->entry[filter_idx].handle,
  3522. false);
  3523. if (rc)
  3524. failed = true;
  3525. spin_lock_bh(&efx->filter_lock);
  3526. if (rc) {
  3527. kfree(spec);
  3528. efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
  3529. } else {
  3530. table->entry[filter_idx].spec &=
  3531. ~EFX_EF10_FILTER_FLAG_BUSY;
  3532. }
  3533. }
  3534. spin_unlock_bh(&efx->filter_lock);
  3535. if (failed)
  3536. netif_err(efx, hw, efx->net_dev,
  3537. "unable to restore all filters\n");
  3538. else
  3539. nic_data->must_restore_filters = false;
  3540. }
  3541. static void efx_ef10_filter_table_remove(struct efx_nic *efx)
  3542. {
  3543. struct efx_ef10_filter_table *table = efx->filter_state;
  3544. MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
  3545. struct efx_filter_spec *spec;
  3546. unsigned int filter_idx;
  3547. int rc;
  3548. efx_ef10_filter_cleanup_vlans(efx);
  3549. efx->filter_state = NULL;
  3550. /* If we were called without locking, then it's not safe to free
  3551. * the table as others might be using it. So we just WARN, leak
  3552. * the memory, and potentially get an inconsistent filter table
  3553. * state.
  3554. * This should never actually happen.
  3555. */
  3556. if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
  3557. return;
  3558. if (!table)
  3559. return;
  3560. for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
  3561. spec = efx_ef10_filter_entry_spec(table, filter_idx);
  3562. if (!spec)
  3563. continue;
  3564. MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
  3565. efx_ef10_filter_is_exclusive(spec) ?
  3566. MC_CMD_FILTER_OP_IN_OP_REMOVE :
  3567. MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
  3568. MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
  3569. table->entry[filter_idx].handle);
  3570. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
  3571. sizeof(inbuf), NULL, 0, NULL);
  3572. if (rc)
  3573. netif_info(efx, drv, efx->net_dev,
  3574. "%s: filter %04x remove failed\n",
  3575. __func__, filter_idx);
  3576. kfree(spec);
  3577. }
  3578. vfree(table->entry);
  3579. kfree(table);
  3580. }
  3581. static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
  3582. {
  3583. struct efx_ef10_filter_table *table = efx->filter_state;
  3584. unsigned int filter_idx;
  3585. if (*id != EFX_EF10_FILTER_ID_INVALID) {
  3586. filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
  3587. if (!table->entry[filter_idx].spec)
  3588. netif_dbg(efx, drv, efx->net_dev,
  3589. "marked null spec old %04x:%04x\n", *id,
  3590. filter_idx);
  3591. table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
  3592. *id = EFX_EF10_FILTER_ID_INVALID;
  3593. }
  3594. }
  3595. /* Mark old per-VLAN filters that may need to be removed */
  3596. static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
  3597. struct efx_ef10_filter_vlan *vlan)
  3598. {
  3599. struct efx_ef10_filter_table *table = efx->filter_state;
  3600. unsigned int i;
  3601. for (i = 0; i < table->dev_uc_count; i++)
  3602. efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
  3603. for (i = 0; i < table->dev_mc_count; i++)
  3604. efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
  3605. efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
  3606. efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
  3607. efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
  3608. }
  3609. /* Mark old filters that may need to be removed.
  3610. * Caller must hold efx->filter_sem for read if race against
  3611. * efx_ef10_filter_table_remove() is possible
  3612. */
  3613. static void efx_ef10_filter_mark_old(struct efx_nic *efx)
  3614. {
  3615. struct efx_ef10_filter_table *table = efx->filter_state;
  3616. struct efx_ef10_filter_vlan *vlan;
  3617. spin_lock_bh(&efx->filter_lock);
  3618. list_for_each_entry(vlan, &table->vlan_list, list)
  3619. _efx_ef10_filter_vlan_mark_old(efx, vlan);
  3620. spin_unlock_bh(&efx->filter_lock);
  3621. }
  3622. static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
  3623. {
  3624. struct efx_ef10_filter_table *table = efx->filter_state;
  3625. struct net_device *net_dev = efx->net_dev;
  3626. struct netdev_hw_addr *uc;
  3627. int addr_count;
  3628. unsigned int i;
  3629. addr_count = netdev_uc_count(net_dev);
  3630. table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
  3631. table->dev_uc_count = 1 + addr_count;
  3632. ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
  3633. i = 1;
  3634. netdev_for_each_uc_addr(uc, net_dev) {
  3635. if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
  3636. table->uc_promisc = true;
  3637. break;
  3638. }
  3639. ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
  3640. i++;
  3641. }
  3642. }
  3643. static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
  3644. {
  3645. struct efx_ef10_filter_table *table = efx->filter_state;
  3646. struct net_device *net_dev = efx->net_dev;
  3647. struct netdev_hw_addr *mc;
  3648. unsigned int i, addr_count;
  3649. table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
  3650. addr_count = netdev_mc_count(net_dev);
  3651. i = 0;
  3652. netdev_for_each_mc_addr(mc, net_dev) {
  3653. if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
  3654. table->mc_promisc = true;
  3655. break;
  3656. }
  3657. ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
  3658. i++;
  3659. }
  3660. table->dev_mc_count = i;
  3661. }
  3662. static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
  3663. struct efx_ef10_filter_vlan *vlan,
  3664. bool multicast, bool rollback)
  3665. {
  3666. struct efx_ef10_filter_table *table = efx->filter_state;
  3667. struct efx_ef10_dev_addr *addr_list;
  3668. enum efx_filter_flags filter_flags;
  3669. struct efx_filter_spec spec;
  3670. u8 baddr[ETH_ALEN];
  3671. unsigned int i, j;
  3672. int addr_count;
  3673. u16 *ids;
  3674. int rc;
  3675. if (multicast) {
  3676. addr_list = table->dev_mc_list;
  3677. addr_count = table->dev_mc_count;
  3678. ids = vlan->mc;
  3679. } else {
  3680. addr_list = table->dev_uc_list;
  3681. addr_count = table->dev_uc_count;
  3682. ids = vlan->uc;
  3683. }
  3684. filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
  3685. /* Insert/renew filters */
  3686. for (i = 0; i < addr_count; i++) {
  3687. efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
  3688. efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
  3689. rc = efx_ef10_filter_insert(efx, &spec, true);
  3690. if (rc < 0) {
  3691. if (rollback) {
  3692. netif_info(efx, drv, efx->net_dev,
  3693. "efx_ef10_filter_insert failed rc=%d\n",
  3694. rc);
  3695. /* Fall back to promiscuous */
  3696. for (j = 0; j < i; j++) {
  3697. efx_ef10_filter_remove_unsafe(
  3698. efx, EFX_FILTER_PRI_AUTO,
  3699. ids[j]);
  3700. ids[j] = EFX_EF10_FILTER_ID_INVALID;
  3701. }
  3702. return rc;
  3703. } else {
  3704. /* mark as not inserted, and carry on */
  3705. rc = EFX_EF10_FILTER_ID_INVALID;
  3706. }
  3707. }
  3708. ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
  3709. }
  3710. if (multicast && rollback) {
  3711. /* Also need an Ethernet broadcast filter */
  3712. efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
  3713. eth_broadcast_addr(baddr);
  3714. efx_filter_set_eth_local(&spec, vlan->vid, baddr);
  3715. rc = efx_ef10_filter_insert(efx, &spec, true);
  3716. if (rc < 0) {
  3717. netif_warn(efx, drv, efx->net_dev,
  3718. "Broadcast filter insert failed rc=%d\n", rc);
  3719. /* Fall back to promiscuous */
  3720. for (j = 0; j < i; j++) {
  3721. efx_ef10_filter_remove_unsafe(
  3722. efx, EFX_FILTER_PRI_AUTO,
  3723. ids[j]);
  3724. ids[j] = EFX_EF10_FILTER_ID_INVALID;
  3725. }
  3726. return rc;
  3727. } else {
  3728. EFX_WARN_ON_PARANOID(vlan->bcast !=
  3729. EFX_EF10_FILTER_ID_INVALID);
  3730. vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
  3731. }
  3732. }
  3733. return 0;
  3734. }
  3735. static int efx_ef10_filter_insert_def(struct efx_nic *efx,
  3736. struct efx_ef10_filter_vlan *vlan,
  3737. bool multicast, bool rollback)
  3738. {
  3739. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  3740. enum efx_filter_flags filter_flags;
  3741. struct efx_filter_spec spec;
  3742. u8 baddr[ETH_ALEN];
  3743. int rc;
  3744. filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
  3745. efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
  3746. if (multicast)
  3747. efx_filter_set_mc_def(&spec);
  3748. else
  3749. efx_filter_set_uc_def(&spec);
  3750. if (vlan->vid != EFX_FILTER_VID_UNSPEC)
  3751. efx_filter_set_eth_local(&spec, vlan->vid, NULL);
  3752. rc = efx_ef10_filter_insert(efx, &spec, true);
  3753. if (rc < 0) {
  3754. netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
  3755. efx->net_dev,
  3756. "%scast mismatch filter insert failed rc=%d\n",
  3757. multicast ? "Multi" : "Uni", rc);
  3758. } else if (multicast) {
  3759. EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
  3760. vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
  3761. if (!nic_data->workaround_26807) {
  3762. /* Also need an Ethernet broadcast filter */
  3763. efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
  3764. filter_flags, 0);
  3765. eth_broadcast_addr(baddr);
  3766. efx_filter_set_eth_local(&spec, vlan->vid, baddr);
  3767. rc = efx_ef10_filter_insert(efx, &spec, true);
  3768. if (rc < 0) {
  3769. netif_warn(efx, drv, efx->net_dev,
  3770. "Broadcast filter insert failed rc=%d\n",
  3771. rc);
  3772. if (rollback) {
  3773. /* Roll back the mc_def filter */
  3774. efx_ef10_filter_remove_unsafe(
  3775. efx, EFX_FILTER_PRI_AUTO,
  3776. vlan->mcdef);
  3777. vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
  3778. return rc;
  3779. }
  3780. } else {
  3781. EFX_WARN_ON_PARANOID(vlan->bcast !=
  3782. EFX_EF10_FILTER_ID_INVALID);
  3783. vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
  3784. }
  3785. }
  3786. rc = 0;
  3787. } else {
  3788. EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
  3789. vlan->ucdef = rc;
  3790. rc = 0;
  3791. }
  3792. return rc;
  3793. }
  3794. /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
  3795. * flag or removes these filters, we don't need to hold the filter_lock while
  3796. * scanning for these filters.
  3797. */
  3798. static void efx_ef10_filter_remove_old(struct efx_nic *efx)
  3799. {
  3800. struct efx_ef10_filter_table *table = efx->filter_state;
  3801. int remove_failed = 0;
  3802. int remove_noent = 0;
  3803. int rc;
  3804. int i;
  3805. for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
  3806. if (ACCESS_ONCE(table->entry[i].spec) &
  3807. EFX_EF10_FILTER_FLAG_AUTO_OLD) {
  3808. rc = efx_ef10_filter_remove_internal(efx,
  3809. 1U << EFX_FILTER_PRI_AUTO, i, true);
  3810. if (rc == -ENOENT)
  3811. remove_noent++;
  3812. else if (rc)
  3813. remove_failed++;
  3814. }
  3815. }
  3816. if (remove_failed)
  3817. netif_info(efx, drv, efx->net_dev,
  3818. "%s: failed to remove %d filters\n",
  3819. __func__, remove_failed);
  3820. if (remove_noent)
  3821. netif_info(efx, drv, efx->net_dev,
  3822. "%s: failed to remove %d non-existent filters\n",
  3823. __func__, remove_noent);
  3824. }
  3825. static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
  3826. {
  3827. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  3828. u8 mac_old[ETH_ALEN];
  3829. int rc, rc2;
  3830. /* Only reconfigure a PF-created vport */
  3831. if (is_zero_ether_addr(nic_data->vport_mac))
  3832. return 0;
  3833. efx_device_detach_sync(efx);
  3834. efx_net_stop(efx->net_dev);
  3835. down_write(&efx->filter_sem);
  3836. efx_ef10_filter_table_remove(efx);
  3837. up_write(&efx->filter_sem);
  3838. rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
  3839. if (rc)
  3840. goto restore_filters;
  3841. ether_addr_copy(mac_old, nic_data->vport_mac);
  3842. rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
  3843. nic_data->vport_mac);
  3844. if (rc)
  3845. goto restore_vadaptor;
  3846. rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
  3847. efx->net_dev->dev_addr);
  3848. if (!rc) {
  3849. ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
  3850. } else {
  3851. rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
  3852. if (rc2) {
  3853. /* Failed to add original MAC, so clear vport_mac */
  3854. eth_zero_addr(nic_data->vport_mac);
  3855. goto reset_nic;
  3856. }
  3857. }
  3858. restore_vadaptor:
  3859. rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
  3860. if (rc2)
  3861. goto reset_nic;
  3862. restore_filters:
  3863. down_write(&efx->filter_sem);
  3864. rc2 = efx_ef10_filter_table_probe(efx);
  3865. up_write(&efx->filter_sem);
  3866. if (rc2)
  3867. goto reset_nic;
  3868. rc2 = efx_net_open(efx->net_dev);
  3869. if (rc2)
  3870. goto reset_nic;
  3871. netif_device_attach(efx->net_dev);
  3872. return rc;
  3873. reset_nic:
  3874. netif_err(efx, drv, efx->net_dev,
  3875. "Failed to restore when changing MAC address - scheduling reset\n");
  3876. efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
  3877. return rc ? rc : rc2;
  3878. }
  3879. /* Caller must hold efx->filter_sem for read if race against
  3880. * efx_ef10_filter_table_remove() is possible
  3881. */
  3882. static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
  3883. struct efx_ef10_filter_vlan *vlan)
  3884. {
  3885. struct efx_ef10_filter_table *table = efx->filter_state;
  3886. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  3887. /* Do not install unspecified VID if VLAN filtering is enabled.
  3888. * Do not install all specified VIDs if VLAN filtering is disabled.
  3889. */
  3890. if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
  3891. return;
  3892. /* Insert/renew unicast filters */
  3893. if (table->uc_promisc) {
  3894. efx_ef10_filter_insert_def(efx, vlan, false, false);
  3895. efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
  3896. } else {
  3897. /* If any of the filters failed to insert, fall back to
  3898. * promiscuous mode - add in the uc_def filter. But keep
  3899. * our individual unicast filters.
  3900. */
  3901. if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
  3902. efx_ef10_filter_insert_def(efx, vlan, false, false);
  3903. }
  3904. /* Insert/renew multicast filters */
  3905. /* If changing promiscuous state with cascaded multicast filters, remove
  3906. * old filters first, so that packets are dropped rather than duplicated
  3907. */
  3908. if (nic_data->workaround_26807 &&
  3909. table->mc_promisc_last != table->mc_promisc)
  3910. efx_ef10_filter_remove_old(efx);
  3911. if (table->mc_promisc) {
  3912. if (nic_data->workaround_26807) {
  3913. /* If we failed to insert promiscuous filters, rollback
  3914. * and fall back to individual multicast filters
  3915. */
  3916. if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
  3917. /* Changing promisc state, so remove old filters */
  3918. efx_ef10_filter_remove_old(efx);
  3919. efx_ef10_filter_insert_addr_list(efx, vlan,
  3920. true, false);
  3921. }
  3922. } else {
  3923. /* If we failed to insert promiscuous filters, don't
  3924. * rollback. Regardless, also insert the mc_list
  3925. */
  3926. efx_ef10_filter_insert_def(efx, vlan, true, false);
  3927. efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
  3928. }
  3929. } else {
  3930. /* If any filters failed to insert, rollback and fall back to
  3931. * promiscuous mode - mc_def filter and maybe broadcast. If
  3932. * that fails, roll back again and insert as many of our
  3933. * individual multicast filters as we can.
  3934. */
  3935. if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
  3936. /* Changing promisc state, so remove old filters */
  3937. if (nic_data->workaround_26807)
  3938. efx_ef10_filter_remove_old(efx);
  3939. if (efx_ef10_filter_insert_def(efx, vlan, true, true))
  3940. efx_ef10_filter_insert_addr_list(efx, vlan,
  3941. true, false);
  3942. }
  3943. }
  3944. }
  3945. /* Caller must hold efx->filter_sem for read if race against
  3946. * efx_ef10_filter_table_remove() is possible
  3947. */
  3948. static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
  3949. {
  3950. struct efx_ef10_filter_table *table = efx->filter_state;
  3951. struct net_device *net_dev = efx->net_dev;
  3952. struct efx_ef10_filter_vlan *vlan;
  3953. bool vlan_filter;
  3954. if (!efx_dev_registered(efx))
  3955. return;
  3956. if (!table)
  3957. return;
  3958. efx_ef10_filter_mark_old(efx);
  3959. /* Copy/convert the address lists; add the primary station
  3960. * address and broadcast address
  3961. */
  3962. netif_addr_lock_bh(net_dev);
  3963. efx_ef10_filter_uc_addr_list(efx);
  3964. efx_ef10_filter_mc_addr_list(efx);
  3965. netif_addr_unlock_bh(net_dev);
  3966. /* If VLAN filtering changes, all old filters are finally removed.
  3967. * Do it in advance to avoid conflicts for unicast untagged and
  3968. * VLAN 0 tagged filters.
  3969. */
  3970. vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
  3971. if (table->vlan_filter != vlan_filter) {
  3972. table->vlan_filter = vlan_filter;
  3973. efx_ef10_filter_remove_old(efx);
  3974. }
  3975. list_for_each_entry(vlan, &table->vlan_list, list)
  3976. efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
  3977. efx_ef10_filter_remove_old(efx);
  3978. table->mc_promisc_last = table->mc_promisc;
  3979. }
  3980. static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
  3981. {
  3982. struct efx_ef10_filter_table *table = efx->filter_state;
  3983. struct efx_ef10_filter_vlan *vlan;
  3984. WARN_ON(!rwsem_is_locked(&efx->filter_sem));
  3985. list_for_each_entry(vlan, &table->vlan_list, list) {
  3986. if (vlan->vid == vid)
  3987. return vlan;
  3988. }
  3989. return NULL;
  3990. }
  3991. static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
  3992. {
  3993. struct efx_ef10_filter_table *table = efx->filter_state;
  3994. struct efx_ef10_filter_vlan *vlan;
  3995. unsigned int i;
  3996. if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
  3997. return -EINVAL;
  3998. vlan = efx_ef10_filter_find_vlan(efx, vid);
  3999. if (WARN_ON(vlan)) {
  4000. netif_err(efx, drv, efx->net_dev,
  4001. "VLAN %u already added\n", vid);
  4002. return -EALREADY;
  4003. }
  4004. vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
  4005. if (!vlan)
  4006. return -ENOMEM;
  4007. vlan->vid = vid;
  4008. for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
  4009. vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
  4010. for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
  4011. vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
  4012. vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
  4013. vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
  4014. vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
  4015. list_add_tail(&vlan->list, &table->vlan_list);
  4016. if (efx_dev_registered(efx))
  4017. efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
  4018. return 0;
  4019. }
  4020. static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
  4021. struct efx_ef10_filter_vlan *vlan)
  4022. {
  4023. unsigned int i;
  4024. /* See comment in efx_ef10_filter_table_remove() */
  4025. if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
  4026. return;
  4027. list_del(&vlan->list);
  4028. for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
  4029. efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
  4030. vlan->uc[i]);
  4031. for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
  4032. efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
  4033. vlan->mc[i]);
  4034. efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
  4035. efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
  4036. efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
  4037. kfree(vlan);
  4038. }
  4039. static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
  4040. {
  4041. struct efx_ef10_filter_vlan *vlan;
  4042. /* See comment in efx_ef10_filter_table_remove() */
  4043. if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
  4044. return;
  4045. vlan = efx_ef10_filter_find_vlan(efx, vid);
  4046. if (!vlan) {
  4047. netif_err(efx, drv, efx->net_dev,
  4048. "VLAN %u not found in filter state\n", vid);
  4049. return;
  4050. }
  4051. efx_ef10_filter_del_vlan_internal(efx, vlan);
  4052. }
  4053. static int efx_ef10_set_mac_address(struct efx_nic *efx)
  4054. {
  4055. MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
  4056. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  4057. bool was_enabled = efx->port_enabled;
  4058. int rc;
  4059. efx_device_detach_sync(efx);
  4060. efx_net_stop(efx->net_dev);
  4061. mutex_lock(&efx->mac_lock);
  4062. down_write(&efx->filter_sem);
  4063. efx_ef10_filter_table_remove(efx);
  4064. ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
  4065. efx->net_dev->dev_addr);
  4066. MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
  4067. nic_data->vport_id);
  4068. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
  4069. sizeof(inbuf), NULL, 0, NULL);
  4070. efx_ef10_filter_table_probe(efx);
  4071. up_write(&efx->filter_sem);
  4072. mutex_unlock(&efx->mac_lock);
  4073. if (was_enabled)
  4074. efx_net_open(efx->net_dev);
  4075. netif_device_attach(efx->net_dev);
  4076. #ifdef CONFIG_SFC_SRIOV
  4077. if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
  4078. struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
  4079. if (rc == -EPERM) {
  4080. struct efx_nic *efx_pf;
  4081. /* Switch to PF and change MAC address on vport */
  4082. efx_pf = pci_get_drvdata(pci_dev_pf);
  4083. rc = efx_ef10_sriov_set_vf_mac(efx_pf,
  4084. nic_data->vf_index,
  4085. efx->net_dev->dev_addr);
  4086. } else if (!rc) {
  4087. struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
  4088. struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
  4089. unsigned int i;
  4090. /* MAC address successfully changed by VF (with MAC
  4091. * spoofing) so update the parent PF if possible.
  4092. */
  4093. for (i = 0; i < efx_pf->vf_count; ++i) {
  4094. struct ef10_vf *vf = nic_data->vf + i;
  4095. if (vf->efx == efx) {
  4096. ether_addr_copy(vf->mac,
  4097. efx->net_dev->dev_addr);
  4098. return 0;
  4099. }
  4100. }
  4101. }
  4102. } else
  4103. #endif
  4104. if (rc == -EPERM) {
  4105. netif_err(efx, drv, efx->net_dev,
  4106. "Cannot change MAC address; use sfboot to enable"
  4107. " mac-spoofing on this interface\n");
  4108. } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
  4109. /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
  4110. * fall-back to the method of changing the MAC address on the
  4111. * vport. This only applies to PFs because such versions of
  4112. * MCFW do not support VFs.
  4113. */
  4114. rc = efx_ef10_vport_set_mac_address(efx);
  4115. } else {
  4116. efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
  4117. sizeof(inbuf), NULL, 0, rc);
  4118. }
  4119. return rc;
  4120. }
  4121. static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
  4122. {
  4123. efx_ef10_filter_sync_rx_mode(efx);
  4124. return efx_mcdi_set_mac(efx);
  4125. }
  4126. static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
  4127. {
  4128. efx_ef10_filter_sync_rx_mode(efx);
  4129. return 0;
  4130. }
  4131. static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
  4132. {
  4133. MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
  4134. MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
  4135. return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
  4136. NULL, 0, NULL);
  4137. }
  4138. /* MC BISTs follow a different poll mechanism to phy BISTs.
  4139. * The BIST is done in the poll handler on the MC, and the MCDI command
  4140. * will block until the BIST is done.
  4141. */
  4142. static int efx_ef10_poll_bist(struct efx_nic *efx)
  4143. {
  4144. int rc;
  4145. MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
  4146. size_t outlen;
  4147. u32 result;
  4148. rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
  4149. outbuf, sizeof(outbuf), &outlen);
  4150. if (rc != 0)
  4151. return rc;
  4152. if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
  4153. return -EIO;
  4154. result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
  4155. switch (result) {
  4156. case MC_CMD_POLL_BIST_PASSED:
  4157. netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
  4158. return 0;
  4159. case MC_CMD_POLL_BIST_TIMEOUT:
  4160. netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
  4161. return -EIO;
  4162. case MC_CMD_POLL_BIST_FAILED:
  4163. netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
  4164. return -EIO;
  4165. default:
  4166. netif_err(efx, hw, efx->net_dev,
  4167. "BIST returned unknown result %u", result);
  4168. return -EIO;
  4169. }
  4170. }
  4171. static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
  4172. {
  4173. int rc;
  4174. netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
  4175. rc = efx_ef10_start_bist(efx, bist_type);
  4176. if (rc != 0)
  4177. return rc;
  4178. return efx_ef10_poll_bist(efx);
  4179. }
  4180. static int
  4181. efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
  4182. {
  4183. int rc, rc2;
  4184. efx_reset_down(efx, RESET_TYPE_WORLD);
  4185. rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
  4186. NULL, 0, NULL, 0, NULL);
  4187. if (rc != 0)
  4188. goto out;
  4189. tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
  4190. tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
  4191. rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
  4192. out:
  4193. if (rc == -EPERM)
  4194. rc = 0;
  4195. rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
  4196. return rc ? rc : rc2;
  4197. }
  4198. #ifdef CONFIG_SFC_MTD
  4199. struct efx_ef10_nvram_type_info {
  4200. u16 type, type_mask;
  4201. u8 port;
  4202. const char *name;
  4203. };
  4204. static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
  4205. { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
  4206. { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
  4207. { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
  4208. { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
  4209. { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
  4210. { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
  4211. { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
  4212. { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
  4213. { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
  4214. { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
  4215. { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
  4216. };
  4217. static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
  4218. struct efx_mcdi_mtd_partition *part,
  4219. unsigned int type)
  4220. {
  4221. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
  4222. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
  4223. const struct efx_ef10_nvram_type_info *info;
  4224. size_t size, erase_size, outlen;
  4225. bool protected;
  4226. int rc;
  4227. for (info = efx_ef10_nvram_types; ; info++) {
  4228. if (info ==
  4229. efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
  4230. return -ENODEV;
  4231. if ((type & ~info->type_mask) == info->type)
  4232. break;
  4233. }
  4234. if (info->port != efx_port_num(efx))
  4235. return -ENODEV;
  4236. rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
  4237. if (rc)
  4238. return rc;
  4239. if (protected)
  4240. return -ENODEV; /* hide it */
  4241. part->nvram_type = type;
  4242. MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
  4243. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
  4244. outbuf, sizeof(outbuf), &outlen);
  4245. if (rc)
  4246. return rc;
  4247. if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
  4248. return -EIO;
  4249. if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
  4250. (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
  4251. part->fw_subtype = MCDI_DWORD(outbuf,
  4252. NVRAM_METADATA_OUT_SUBTYPE);
  4253. part->common.dev_type_name = "EF10 NVRAM manager";
  4254. part->common.type_name = info->name;
  4255. part->common.mtd.type = MTD_NORFLASH;
  4256. part->common.mtd.flags = MTD_CAP_NORFLASH;
  4257. part->common.mtd.size = size;
  4258. part->common.mtd.erasesize = erase_size;
  4259. return 0;
  4260. }
  4261. static int efx_ef10_mtd_probe(struct efx_nic *efx)
  4262. {
  4263. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
  4264. struct efx_mcdi_mtd_partition *parts;
  4265. size_t outlen, n_parts_total, i, n_parts;
  4266. unsigned int type;
  4267. int rc;
  4268. ASSERT_RTNL();
  4269. BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
  4270. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
  4271. outbuf, sizeof(outbuf), &outlen);
  4272. if (rc)
  4273. return rc;
  4274. if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
  4275. return -EIO;
  4276. n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
  4277. if (n_parts_total >
  4278. MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
  4279. return -EIO;
  4280. parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
  4281. if (!parts)
  4282. return -ENOMEM;
  4283. n_parts = 0;
  4284. for (i = 0; i < n_parts_total; i++) {
  4285. type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
  4286. i);
  4287. rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
  4288. if (rc == 0)
  4289. n_parts++;
  4290. else if (rc != -ENODEV)
  4291. goto fail;
  4292. }
  4293. rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
  4294. fail:
  4295. if (rc)
  4296. kfree(parts);
  4297. return rc;
  4298. }
  4299. #endif /* CONFIG_SFC_MTD */
  4300. static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
  4301. {
  4302. _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
  4303. }
  4304. static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
  4305. u32 host_time) {}
  4306. static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
  4307. bool temp)
  4308. {
  4309. MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
  4310. int rc;
  4311. if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
  4312. channel->sync_events_state == SYNC_EVENTS_VALID ||
  4313. (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
  4314. return 0;
  4315. channel->sync_events_state = SYNC_EVENTS_REQUESTED;
  4316. MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
  4317. MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
  4318. MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
  4319. channel->channel);
  4320. rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
  4321. inbuf, sizeof(inbuf), NULL, 0, NULL);
  4322. if (rc != 0)
  4323. channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
  4324. SYNC_EVENTS_DISABLED;
  4325. return rc;
  4326. }
  4327. static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
  4328. bool temp)
  4329. {
  4330. MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
  4331. int rc;
  4332. if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
  4333. (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
  4334. return 0;
  4335. if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
  4336. channel->sync_events_state = SYNC_EVENTS_DISABLED;
  4337. return 0;
  4338. }
  4339. channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
  4340. SYNC_EVENTS_DISABLED;
  4341. MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
  4342. MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
  4343. MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
  4344. MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
  4345. MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
  4346. channel->channel);
  4347. rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
  4348. inbuf, sizeof(inbuf), NULL, 0, NULL);
  4349. return rc;
  4350. }
  4351. static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
  4352. bool temp)
  4353. {
  4354. int (*set)(struct efx_channel *channel, bool temp);
  4355. struct efx_channel *channel;
  4356. set = en ?
  4357. efx_ef10_rx_enable_timestamping :
  4358. efx_ef10_rx_disable_timestamping;
  4359. efx_for_each_channel(channel, efx) {
  4360. int rc = set(channel, temp);
  4361. if (en && rc != 0) {
  4362. efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
  4363. return rc;
  4364. }
  4365. }
  4366. return 0;
  4367. }
  4368. static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
  4369. struct hwtstamp_config *init)
  4370. {
  4371. return -EOPNOTSUPP;
  4372. }
  4373. static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
  4374. struct hwtstamp_config *init)
  4375. {
  4376. int rc;
  4377. switch (init->rx_filter) {
  4378. case HWTSTAMP_FILTER_NONE:
  4379. efx_ef10_ptp_set_ts_sync_events(efx, false, false);
  4380. /* if TX timestamping is still requested then leave PTP on */
  4381. return efx_ptp_change_mode(efx,
  4382. init->tx_type != HWTSTAMP_TX_OFF, 0);
  4383. case HWTSTAMP_FILTER_ALL:
  4384. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  4385. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  4386. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  4387. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  4388. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  4389. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  4390. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  4391. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  4392. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  4393. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  4394. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  4395. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  4396. init->rx_filter = HWTSTAMP_FILTER_ALL;
  4397. rc = efx_ptp_change_mode(efx, true, 0);
  4398. if (!rc)
  4399. rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
  4400. if (rc)
  4401. efx_ptp_change_mode(efx, false, 0);
  4402. return rc;
  4403. default:
  4404. return -ERANGE;
  4405. }
  4406. }
  4407. static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
  4408. {
  4409. if (proto != htons(ETH_P_8021Q))
  4410. return -EINVAL;
  4411. return efx_ef10_add_vlan(efx, vid);
  4412. }
  4413. static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
  4414. {
  4415. if (proto != htons(ETH_P_8021Q))
  4416. return -EINVAL;
  4417. return efx_ef10_del_vlan(efx, vid);
  4418. }
  4419. #define EF10_OFFLOAD_FEATURES \
  4420. (NETIF_F_IP_CSUM | \
  4421. NETIF_F_HW_VLAN_CTAG_FILTER | \
  4422. NETIF_F_IPV6_CSUM | \
  4423. NETIF_F_RXHASH | \
  4424. NETIF_F_NTUPLE)
  4425. const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
  4426. .is_vf = true,
  4427. .mem_bar = EFX_MEM_VF_BAR,
  4428. .mem_map_size = efx_ef10_mem_map_size,
  4429. .probe = efx_ef10_probe_vf,
  4430. .remove = efx_ef10_remove,
  4431. .dimension_resources = efx_ef10_dimension_resources,
  4432. .init = efx_ef10_init_nic,
  4433. .fini = efx_port_dummy_op_void,
  4434. .map_reset_reason = efx_ef10_map_reset_reason,
  4435. .map_reset_flags = efx_ef10_map_reset_flags,
  4436. .reset = efx_ef10_reset,
  4437. .probe_port = efx_mcdi_port_probe,
  4438. .remove_port = efx_mcdi_port_remove,
  4439. .fini_dmaq = efx_ef10_fini_dmaq,
  4440. .prepare_flr = efx_ef10_prepare_flr,
  4441. .finish_flr = efx_port_dummy_op_void,
  4442. .describe_stats = efx_ef10_describe_stats,
  4443. .update_stats = efx_ef10_update_stats_vf,
  4444. .start_stats = efx_port_dummy_op_void,
  4445. .pull_stats = efx_port_dummy_op_void,
  4446. .stop_stats = efx_port_dummy_op_void,
  4447. .set_id_led = efx_mcdi_set_id_led,
  4448. .push_irq_moderation = efx_ef10_push_irq_moderation,
  4449. .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
  4450. .check_mac_fault = efx_mcdi_mac_check_fault,
  4451. .reconfigure_port = efx_mcdi_port_reconfigure,
  4452. .get_wol = efx_ef10_get_wol_vf,
  4453. .set_wol = efx_ef10_set_wol_vf,
  4454. .resume_wol = efx_port_dummy_op_void,
  4455. .mcdi_request = efx_ef10_mcdi_request,
  4456. .mcdi_poll_response = efx_ef10_mcdi_poll_response,
  4457. .mcdi_read_response = efx_ef10_mcdi_read_response,
  4458. .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
  4459. .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
  4460. .irq_enable_master = efx_port_dummy_op_void,
  4461. .irq_test_generate = efx_ef10_irq_test_generate,
  4462. .irq_disable_non_ev = efx_port_dummy_op_void,
  4463. .irq_handle_msi = efx_ef10_msi_interrupt,
  4464. .irq_handle_legacy = efx_ef10_legacy_interrupt,
  4465. .tx_probe = efx_ef10_tx_probe,
  4466. .tx_init = efx_ef10_tx_init,
  4467. .tx_remove = efx_ef10_tx_remove,
  4468. .tx_write = efx_ef10_tx_write,
  4469. .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
  4470. .rx_probe = efx_ef10_rx_probe,
  4471. .rx_init = efx_ef10_rx_init,
  4472. .rx_remove = efx_ef10_rx_remove,
  4473. .rx_write = efx_ef10_rx_write,
  4474. .rx_defer_refill = efx_ef10_rx_defer_refill,
  4475. .ev_probe = efx_ef10_ev_probe,
  4476. .ev_init = efx_ef10_ev_init,
  4477. .ev_fini = efx_ef10_ev_fini,
  4478. .ev_remove = efx_ef10_ev_remove,
  4479. .ev_process = efx_ef10_ev_process,
  4480. .ev_read_ack = efx_ef10_ev_read_ack,
  4481. .ev_test_generate = efx_ef10_ev_test_generate,
  4482. .filter_table_probe = efx_ef10_filter_table_probe,
  4483. .filter_table_restore = efx_ef10_filter_table_restore,
  4484. .filter_table_remove = efx_ef10_filter_table_remove,
  4485. .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
  4486. .filter_insert = efx_ef10_filter_insert,
  4487. .filter_remove_safe = efx_ef10_filter_remove_safe,
  4488. .filter_get_safe = efx_ef10_filter_get_safe,
  4489. .filter_clear_rx = efx_ef10_filter_clear_rx,
  4490. .filter_count_rx_used = efx_ef10_filter_count_rx_used,
  4491. .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
  4492. .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
  4493. #ifdef CONFIG_RFS_ACCEL
  4494. .filter_rfs_insert = efx_ef10_filter_rfs_insert,
  4495. .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
  4496. #endif
  4497. #ifdef CONFIG_SFC_MTD
  4498. .mtd_probe = efx_port_dummy_op_int,
  4499. #endif
  4500. .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
  4501. .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
  4502. .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
  4503. .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
  4504. #ifdef CONFIG_SFC_SRIOV
  4505. .vswitching_probe = efx_ef10_vswitching_probe_vf,
  4506. .vswitching_restore = efx_ef10_vswitching_restore_vf,
  4507. .vswitching_remove = efx_ef10_vswitching_remove_vf,
  4508. .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
  4509. #endif
  4510. .get_mac_address = efx_ef10_get_mac_address_vf,
  4511. .set_mac_address = efx_ef10_set_mac_address,
  4512. .revision = EFX_REV_HUNT_A0,
  4513. .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
  4514. .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
  4515. .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
  4516. .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
  4517. .can_rx_scatter = true,
  4518. .always_rx_scatter = true,
  4519. .max_interrupt_mode = EFX_INT_MODE_MSIX,
  4520. .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
  4521. .offload_features = EF10_OFFLOAD_FEATURES,
  4522. .mcdi_max_ver = 2,
  4523. .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
  4524. .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
  4525. 1 << HWTSTAMP_FILTER_ALL,
  4526. };
  4527. const struct efx_nic_type efx_hunt_a0_nic_type = {
  4528. .is_vf = false,
  4529. .mem_bar = EFX_MEM_BAR,
  4530. .mem_map_size = efx_ef10_mem_map_size,
  4531. .probe = efx_ef10_probe_pf,
  4532. .remove = efx_ef10_remove,
  4533. .dimension_resources = efx_ef10_dimension_resources,
  4534. .init = efx_ef10_init_nic,
  4535. .fini = efx_port_dummy_op_void,
  4536. .map_reset_reason = efx_ef10_map_reset_reason,
  4537. .map_reset_flags = efx_ef10_map_reset_flags,
  4538. .reset = efx_ef10_reset,
  4539. .probe_port = efx_mcdi_port_probe,
  4540. .remove_port = efx_mcdi_port_remove,
  4541. .fini_dmaq = efx_ef10_fini_dmaq,
  4542. .prepare_flr = efx_ef10_prepare_flr,
  4543. .finish_flr = efx_port_dummy_op_void,
  4544. .describe_stats = efx_ef10_describe_stats,
  4545. .update_stats = efx_ef10_update_stats_pf,
  4546. .start_stats = efx_mcdi_mac_start_stats,
  4547. .pull_stats = efx_mcdi_mac_pull_stats,
  4548. .stop_stats = efx_mcdi_mac_stop_stats,
  4549. .set_id_led = efx_mcdi_set_id_led,
  4550. .push_irq_moderation = efx_ef10_push_irq_moderation,
  4551. .reconfigure_mac = efx_ef10_mac_reconfigure,
  4552. .check_mac_fault = efx_mcdi_mac_check_fault,
  4553. .reconfigure_port = efx_mcdi_port_reconfigure,
  4554. .get_wol = efx_ef10_get_wol,
  4555. .set_wol = efx_ef10_set_wol,
  4556. .resume_wol = efx_port_dummy_op_void,
  4557. .test_chip = efx_ef10_test_chip,
  4558. .test_nvram = efx_mcdi_nvram_test_all,
  4559. .mcdi_request = efx_ef10_mcdi_request,
  4560. .mcdi_poll_response = efx_ef10_mcdi_poll_response,
  4561. .mcdi_read_response = efx_ef10_mcdi_read_response,
  4562. .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
  4563. .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
  4564. .irq_enable_master = efx_port_dummy_op_void,
  4565. .irq_test_generate = efx_ef10_irq_test_generate,
  4566. .irq_disable_non_ev = efx_port_dummy_op_void,
  4567. .irq_handle_msi = efx_ef10_msi_interrupt,
  4568. .irq_handle_legacy = efx_ef10_legacy_interrupt,
  4569. .tx_probe = efx_ef10_tx_probe,
  4570. .tx_init = efx_ef10_tx_init,
  4571. .tx_remove = efx_ef10_tx_remove,
  4572. .tx_write = efx_ef10_tx_write,
  4573. .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
  4574. .rx_probe = efx_ef10_rx_probe,
  4575. .rx_init = efx_ef10_rx_init,
  4576. .rx_remove = efx_ef10_rx_remove,
  4577. .rx_write = efx_ef10_rx_write,
  4578. .rx_defer_refill = efx_ef10_rx_defer_refill,
  4579. .ev_probe = efx_ef10_ev_probe,
  4580. .ev_init = efx_ef10_ev_init,
  4581. .ev_fini = efx_ef10_ev_fini,
  4582. .ev_remove = efx_ef10_ev_remove,
  4583. .ev_process = efx_ef10_ev_process,
  4584. .ev_read_ack = efx_ef10_ev_read_ack,
  4585. .ev_test_generate = efx_ef10_ev_test_generate,
  4586. .filter_table_probe = efx_ef10_filter_table_probe,
  4587. .filter_table_restore = efx_ef10_filter_table_restore,
  4588. .filter_table_remove = efx_ef10_filter_table_remove,
  4589. .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
  4590. .filter_insert = efx_ef10_filter_insert,
  4591. .filter_remove_safe = efx_ef10_filter_remove_safe,
  4592. .filter_get_safe = efx_ef10_filter_get_safe,
  4593. .filter_clear_rx = efx_ef10_filter_clear_rx,
  4594. .filter_count_rx_used = efx_ef10_filter_count_rx_used,
  4595. .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
  4596. .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
  4597. #ifdef CONFIG_RFS_ACCEL
  4598. .filter_rfs_insert = efx_ef10_filter_rfs_insert,
  4599. .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
  4600. #endif
  4601. #ifdef CONFIG_SFC_MTD
  4602. .mtd_probe = efx_ef10_mtd_probe,
  4603. .mtd_rename = efx_mcdi_mtd_rename,
  4604. .mtd_read = efx_mcdi_mtd_read,
  4605. .mtd_erase = efx_mcdi_mtd_erase,
  4606. .mtd_write = efx_mcdi_mtd_write,
  4607. .mtd_sync = efx_mcdi_mtd_sync,
  4608. #endif
  4609. .ptp_write_host_time = efx_ef10_ptp_write_host_time,
  4610. .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
  4611. .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
  4612. .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
  4613. .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
  4614. #ifdef CONFIG_SFC_SRIOV
  4615. .sriov_configure = efx_ef10_sriov_configure,
  4616. .sriov_init = efx_ef10_sriov_init,
  4617. .sriov_fini = efx_ef10_sriov_fini,
  4618. .sriov_wanted = efx_ef10_sriov_wanted,
  4619. .sriov_reset = efx_ef10_sriov_reset,
  4620. .sriov_flr = efx_ef10_sriov_flr,
  4621. .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
  4622. .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
  4623. .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
  4624. .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
  4625. .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
  4626. .vswitching_probe = efx_ef10_vswitching_probe_pf,
  4627. .vswitching_restore = efx_ef10_vswitching_restore_pf,
  4628. .vswitching_remove = efx_ef10_vswitching_remove_pf,
  4629. #endif
  4630. .get_mac_address = efx_ef10_get_mac_address_pf,
  4631. .set_mac_address = efx_ef10_set_mac_address,
  4632. .revision = EFX_REV_HUNT_A0,
  4633. .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
  4634. .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
  4635. .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
  4636. .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
  4637. .can_rx_scatter = true,
  4638. .always_rx_scatter = true,
  4639. .max_interrupt_mode = EFX_INT_MODE_MSIX,
  4640. .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
  4641. .offload_features = EF10_OFFLOAD_FEATURES,
  4642. .mcdi_max_ver = 2,
  4643. .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
  4644. .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
  4645. 1 << HWTSTAMP_FILTER_ALL,
  4646. };