qede_main.c 100 KB

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  1. /* QLogic qede NIC Driver
  2. * Copyright (c) 2015 QLogic Corporation
  3. *
  4. * This software is available under the terms of the GNU General Public License
  5. * (GPL) Version 2, available from the file COPYING in the main directory of
  6. * this source tree.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/pci.h>
  10. #include <linux/version.h>
  11. #include <linux/device.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/skbuff.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/string.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/interrupt.h>
  20. #include <asm/byteorder.h>
  21. #include <asm/param.h>
  22. #include <linux/io.h>
  23. #include <linux/netdev_features.h>
  24. #include <linux/udp.h>
  25. #include <linux/tcp.h>
  26. #include <net/udp_tunnel.h>
  27. #include <linux/ip.h>
  28. #include <net/ipv6.h>
  29. #include <net/tcp.h>
  30. #include <linux/if_ether.h>
  31. #include <linux/if_vlan.h>
  32. #include <linux/pkt_sched.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/in.h>
  35. #include <linux/random.h>
  36. #include <net/ip6_checksum.h>
  37. #include <linux/bitops.h>
  38. #include "qede.h"
  39. static char version[] =
  40. "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
  41. MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
  42. MODULE_LICENSE("GPL");
  43. MODULE_VERSION(DRV_MODULE_VERSION);
  44. static uint debug;
  45. module_param(debug, uint, 0);
  46. MODULE_PARM_DESC(debug, " Default debug msglevel");
  47. static const struct qed_eth_ops *qed_ops;
  48. #define CHIP_NUM_57980S_40 0x1634
  49. #define CHIP_NUM_57980S_10 0x1666
  50. #define CHIP_NUM_57980S_MF 0x1636
  51. #define CHIP_NUM_57980S_100 0x1644
  52. #define CHIP_NUM_57980S_50 0x1654
  53. #define CHIP_NUM_57980S_25 0x1656
  54. #define CHIP_NUM_57980S_IOV 0x1664
  55. #ifndef PCI_DEVICE_ID_NX2_57980E
  56. #define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
  57. #define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
  58. #define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
  59. #define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
  60. #define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
  61. #define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
  62. #define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
  63. #endif
  64. enum qede_pci_private {
  65. QEDE_PRIVATE_PF,
  66. QEDE_PRIVATE_VF
  67. };
  68. static const struct pci_device_id qede_pci_tbl[] = {
  69. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
  70. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
  71. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
  72. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
  73. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
  74. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
  75. #ifdef CONFIG_QED_SRIOV
  76. {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
  77. #endif
  78. { 0 }
  79. };
  80. MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
  81. static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
  82. #define TX_TIMEOUT (5 * HZ)
  83. static void qede_remove(struct pci_dev *pdev);
  84. static int qede_alloc_rx_buffer(struct qede_dev *edev,
  85. struct qede_rx_queue *rxq);
  86. static void qede_link_update(void *dev, struct qed_link_output *link);
  87. #ifdef CONFIG_QED_SRIOV
  88. static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos)
  89. {
  90. struct qede_dev *edev = netdev_priv(ndev);
  91. if (vlan > 4095) {
  92. DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
  93. return -EINVAL;
  94. }
  95. DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
  96. vlan, vf);
  97. return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
  98. }
  99. static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
  100. {
  101. struct qede_dev *edev = netdev_priv(ndev);
  102. DP_VERBOSE(edev, QED_MSG_IOV,
  103. "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
  104. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
  105. if (!is_valid_ether_addr(mac)) {
  106. DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
  107. return -EINVAL;
  108. }
  109. return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
  110. }
  111. static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
  112. {
  113. struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
  114. struct qed_dev_info *qed_info = &edev->dev_info.common;
  115. int rc;
  116. DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
  117. rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
  118. /* Enable/Disable Tx switching for PF */
  119. if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
  120. qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
  121. struct qed_update_vport_params params;
  122. memset(&params, 0, sizeof(params));
  123. params.vport_id = 0;
  124. params.update_tx_switching_flg = 1;
  125. params.tx_switching_flg = num_vfs_param ? 1 : 0;
  126. edev->ops->vport_update(edev->cdev, &params);
  127. }
  128. return rc;
  129. }
  130. #endif
  131. static struct pci_driver qede_pci_driver = {
  132. .name = "qede",
  133. .id_table = qede_pci_tbl,
  134. .probe = qede_probe,
  135. .remove = qede_remove,
  136. #ifdef CONFIG_QED_SRIOV
  137. .sriov_configure = qede_sriov_configure,
  138. #endif
  139. };
  140. static void qede_force_mac(void *dev, u8 *mac)
  141. {
  142. struct qede_dev *edev = dev;
  143. ether_addr_copy(edev->ndev->dev_addr, mac);
  144. ether_addr_copy(edev->primary_mac, mac);
  145. }
  146. static struct qed_eth_cb_ops qede_ll_ops = {
  147. {
  148. .link_update = qede_link_update,
  149. },
  150. .force_mac = qede_force_mac,
  151. };
  152. static int qede_netdev_event(struct notifier_block *this, unsigned long event,
  153. void *ptr)
  154. {
  155. struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
  156. struct ethtool_drvinfo drvinfo;
  157. struct qede_dev *edev;
  158. /* Currently only support name change */
  159. if (event != NETDEV_CHANGENAME)
  160. goto done;
  161. /* Check whether this is a qede device */
  162. if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
  163. goto done;
  164. memset(&drvinfo, 0, sizeof(drvinfo));
  165. ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
  166. if (strcmp(drvinfo.driver, "qede"))
  167. goto done;
  168. edev = netdev_priv(ndev);
  169. /* Notify qed of the name change */
  170. if (!edev->ops || !edev->ops->common)
  171. goto done;
  172. edev->ops->common->set_id(edev->cdev, edev->ndev->name,
  173. "qede");
  174. done:
  175. return NOTIFY_DONE;
  176. }
  177. static struct notifier_block qede_netdev_notifier = {
  178. .notifier_call = qede_netdev_event,
  179. };
  180. static
  181. int __init qede_init(void)
  182. {
  183. int ret;
  184. pr_notice("qede_init: %s\n", version);
  185. qed_ops = qed_get_eth_ops();
  186. if (!qed_ops) {
  187. pr_notice("Failed to get qed ethtool operations\n");
  188. return -EINVAL;
  189. }
  190. /* Must register notifier before pci ops, since we might miss
  191. * interface rename after pci probe and netdev registeration.
  192. */
  193. ret = register_netdevice_notifier(&qede_netdev_notifier);
  194. if (ret) {
  195. pr_notice("Failed to register netdevice_notifier\n");
  196. qed_put_eth_ops();
  197. return -EINVAL;
  198. }
  199. ret = pci_register_driver(&qede_pci_driver);
  200. if (ret) {
  201. pr_notice("Failed to register driver\n");
  202. unregister_netdevice_notifier(&qede_netdev_notifier);
  203. qed_put_eth_ops();
  204. return -EINVAL;
  205. }
  206. return 0;
  207. }
  208. static void __exit qede_cleanup(void)
  209. {
  210. pr_notice("qede_cleanup called\n");
  211. unregister_netdevice_notifier(&qede_netdev_notifier);
  212. pci_unregister_driver(&qede_pci_driver);
  213. qed_put_eth_ops();
  214. }
  215. module_init(qede_init);
  216. module_exit(qede_cleanup);
  217. /* -------------------------------------------------------------------------
  218. * START OF FAST-PATH
  219. * -------------------------------------------------------------------------
  220. */
  221. /* Unmap the data and free skb */
  222. static int qede_free_tx_pkt(struct qede_dev *edev,
  223. struct qede_tx_queue *txq,
  224. int *len)
  225. {
  226. u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
  227. struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
  228. struct eth_tx_1st_bd *first_bd;
  229. struct eth_tx_bd *tx_data_bd;
  230. int bds_consumed = 0;
  231. int nbds;
  232. bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
  233. int i, split_bd_len = 0;
  234. if (unlikely(!skb)) {
  235. DP_ERR(edev,
  236. "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
  237. idx, txq->sw_tx_cons, txq->sw_tx_prod);
  238. return -1;
  239. }
  240. *len = skb->len;
  241. first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
  242. bds_consumed++;
  243. nbds = first_bd->data.nbds;
  244. if (data_split) {
  245. struct eth_tx_bd *split = (struct eth_tx_bd *)
  246. qed_chain_consume(&txq->tx_pbl);
  247. split_bd_len = BD_UNMAP_LEN(split);
  248. bds_consumed++;
  249. }
  250. dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
  251. BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
  252. /* Unmap the data of the skb frags */
  253. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
  254. tx_data_bd = (struct eth_tx_bd *)
  255. qed_chain_consume(&txq->tx_pbl);
  256. dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
  257. BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
  258. }
  259. while (bds_consumed++ < nbds)
  260. qed_chain_consume(&txq->tx_pbl);
  261. /* Free skb */
  262. dev_kfree_skb_any(skb);
  263. txq->sw_tx_ring[idx].skb = NULL;
  264. txq->sw_tx_ring[idx].flags = 0;
  265. return 0;
  266. }
  267. /* Unmap the data and free skb when mapping failed during start_xmit */
  268. static void qede_free_failed_tx_pkt(struct qede_dev *edev,
  269. struct qede_tx_queue *txq,
  270. struct eth_tx_1st_bd *first_bd,
  271. int nbd,
  272. bool data_split)
  273. {
  274. u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
  275. struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
  276. struct eth_tx_bd *tx_data_bd;
  277. int i, split_bd_len = 0;
  278. /* Return prod to its position before this skb was handled */
  279. qed_chain_set_prod(&txq->tx_pbl,
  280. le16_to_cpu(txq->tx_db.data.bd_prod),
  281. first_bd);
  282. first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
  283. if (data_split) {
  284. struct eth_tx_bd *split = (struct eth_tx_bd *)
  285. qed_chain_produce(&txq->tx_pbl);
  286. split_bd_len = BD_UNMAP_LEN(split);
  287. nbd--;
  288. }
  289. dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
  290. BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
  291. /* Unmap the data of the skb frags */
  292. for (i = 0; i < nbd; i++) {
  293. tx_data_bd = (struct eth_tx_bd *)
  294. qed_chain_produce(&txq->tx_pbl);
  295. if (tx_data_bd->nbytes)
  296. dma_unmap_page(&edev->pdev->dev,
  297. BD_UNMAP_ADDR(tx_data_bd),
  298. BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
  299. }
  300. /* Return again prod to its position before this skb was handled */
  301. qed_chain_set_prod(&txq->tx_pbl,
  302. le16_to_cpu(txq->tx_db.data.bd_prod),
  303. first_bd);
  304. /* Free skb */
  305. dev_kfree_skb_any(skb);
  306. txq->sw_tx_ring[idx].skb = NULL;
  307. txq->sw_tx_ring[idx].flags = 0;
  308. }
  309. static u32 qede_xmit_type(struct qede_dev *edev,
  310. struct sk_buff *skb,
  311. int *ipv6_ext)
  312. {
  313. u32 rc = XMIT_L4_CSUM;
  314. __be16 l3_proto;
  315. if (skb->ip_summed != CHECKSUM_PARTIAL)
  316. return XMIT_PLAIN;
  317. l3_proto = vlan_get_protocol(skb);
  318. if (l3_proto == htons(ETH_P_IPV6) &&
  319. (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
  320. *ipv6_ext = 1;
  321. if (skb->encapsulation)
  322. rc |= XMIT_ENC;
  323. if (skb_is_gso(skb))
  324. rc |= XMIT_LSO;
  325. return rc;
  326. }
  327. static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
  328. struct eth_tx_2nd_bd *second_bd,
  329. struct eth_tx_3rd_bd *third_bd)
  330. {
  331. u8 l4_proto;
  332. u16 bd2_bits1 = 0, bd2_bits2 = 0;
  333. bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
  334. bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
  335. ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
  336. << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
  337. bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
  338. ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
  339. if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
  340. l4_proto = ipv6_hdr(skb)->nexthdr;
  341. else
  342. l4_proto = ip_hdr(skb)->protocol;
  343. if (l4_proto == IPPROTO_UDP)
  344. bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
  345. if (third_bd)
  346. third_bd->data.bitfields |=
  347. cpu_to_le16(((tcp_hdrlen(skb) / 4) &
  348. ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
  349. ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
  350. second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
  351. second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
  352. }
  353. static int map_frag_to_bd(struct qede_dev *edev,
  354. skb_frag_t *frag,
  355. struct eth_tx_bd *bd)
  356. {
  357. dma_addr_t mapping;
  358. /* Map skb non-linear frag data for DMA */
  359. mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
  360. skb_frag_size(frag),
  361. DMA_TO_DEVICE);
  362. if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
  363. DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
  364. return -ENOMEM;
  365. }
  366. /* Setup the data pointer of the frag data */
  367. BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
  368. return 0;
  369. }
  370. static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
  371. {
  372. if (is_encap_pkt)
  373. return (skb_inner_transport_header(skb) +
  374. inner_tcp_hdrlen(skb) - skb->data);
  375. else
  376. return (skb_transport_header(skb) +
  377. tcp_hdrlen(skb) - skb->data);
  378. }
  379. /* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
  380. #if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
  381. static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
  382. u8 xmit_type)
  383. {
  384. int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
  385. if (xmit_type & XMIT_LSO) {
  386. int hlen;
  387. hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
  388. /* linear payload would require its own BD */
  389. if (skb_headlen(skb) > hlen)
  390. allowed_frags--;
  391. }
  392. return (skb_shinfo(skb)->nr_frags > allowed_frags);
  393. }
  394. #endif
  395. static inline void qede_update_tx_producer(struct qede_tx_queue *txq)
  396. {
  397. /* wmb makes sure that the BDs data is updated before updating the
  398. * producer, otherwise FW may read old data from the BDs.
  399. */
  400. wmb();
  401. barrier();
  402. writel(txq->tx_db.raw, txq->doorbell_addr);
  403. /* mmiowb is needed to synchronize doorbell writes from more than one
  404. * processor. It guarantees that the write arrives to the device before
  405. * the queue lock is released and another start_xmit is called (possibly
  406. * on another CPU). Without this barrier, the next doorbell can bypass
  407. * this doorbell. This is applicable to IA64/Altix systems.
  408. */
  409. mmiowb();
  410. }
  411. /* Main transmit function */
  412. static
  413. netdev_tx_t qede_start_xmit(struct sk_buff *skb,
  414. struct net_device *ndev)
  415. {
  416. struct qede_dev *edev = netdev_priv(ndev);
  417. struct netdev_queue *netdev_txq;
  418. struct qede_tx_queue *txq;
  419. struct eth_tx_1st_bd *first_bd;
  420. struct eth_tx_2nd_bd *second_bd = NULL;
  421. struct eth_tx_3rd_bd *third_bd = NULL;
  422. struct eth_tx_bd *tx_data_bd = NULL;
  423. u16 txq_index;
  424. u8 nbd = 0;
  425. dma_addr_t mapping;
  426. int rc, frag_idx = 0, ipv6_ext = 0;
  427. u8 xmit_type;
  428. u16 idx;
  429. u16 hlen;
  430. bool data_split = false;
  431. /* Get tx-queue context and netdev index */
  432. txq_index = skb_get_queue_mapping(skb);
  433. WARN_ON(txq_index >= QEDE_TSS_CNT(edev));
  434. txq = QEDE_TX_QUEUE(edev, txq_index);
  435. netdev_txq = netdev_get_tx_queue(ndev, txq_index);
  436. WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) <
  437. (MAX_SKB_FRAGS + 1));
  438. xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
  439. #if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
  440. if (qede_pkt_req_lin(edev, skb, xmit_type)) {
  441. if (skb_linearize(skb)) {
  442. DP_NOTICE(edev,
  443. "SKB linearization failed - silently dropping this SKB\n");
  444. dev_kfree_skb_any(skb);
  445. return NETDEV_TX_OK;
  446. }
  447. }
  448. #endif
  449. /* Fill the entry in the SW ring and the BDs in the FW ring */
  450. idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
  451. txq->sw_tx_ring[idx].skb = skb;
  452. first_bd = (struct eth_tx_1st_bd *)
  453. qed_chain_produce(&txq->tx_pbl);
  454. memset(first_bd, 0, sizeof(*first_bd));
  455. first_bd->data.bd_flags.bitfields =
  456. 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
  457. /* Map skb linear data for DMA and set in the first BD */
  458. mapping = dma_map_single(&edev->pdev->dev, skb->data,
  459. skb_headlen(skb), DMA_TO_DEVICE);
  460. if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
  461. DP_NOTICE(edev, "SKB mapping failed\n");
  462. qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
  463. qede_update_tx_producer(txq);
  464. return NETDEV_TX_OK;
  465. }
  466. nbd++;
  467. BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
  468. /* In case there is IPv6 with extension headers or LSO we need 2nd and
  469. * 3rd BDs.
  470. */
  471. if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
  472. second_bd = (struct eth_tx_2nd_bd *)
  473. qed_chain_produce(&txq->tx_pbl);
  474. memset(second_bd, 0, sizeof(*second_bd));
  475. nbd++;
  476. third_bd = (struct eth_tx_3rd_bd *)
  477. qed_chain_produce(&txq->tx_pbl);
  478. memset(third_bd, 0, sizeof(*third_bd));
  479. nbd++;
  480. /* We need to fill in additional data in second_bd... */
  481. tx_data_bd = (struct eth_tx_bd *)second_bd;
  482. }
  483. if (skb_vlan_tag_present(skb)) {
  484. first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
  485. first_bd->data.bd_flags.bitfields |=
  486. 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
  487. }
  488. /* Fill the parsing flags & params according to the requested offload */
  489. if (xmit_type & XMIT_L4_CSUM) {
  490. /* We don't re-calculate IP checksum as it is already done by
  491. * the upper stack
  492. */
  493. first_bd->data.bd_flags.bitfields |=
  494. 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
  495. if (xmit_type & XMIT_ENC) {
  496. first_bd->data.bd_flags.bitfields |=
  497. 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
  498. first_bd->data.bitfields |=
  499. 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
  500. }
  501. /* If the packet is IPv6 with extension header, indicate that
  502. * to FW and pass few params, since the device cracker doesn't
  503. * support parsing IPv6 with extension header/s.
  504. */
  505. if (unlikely(ipv6_ext))
  506. qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
  507. }
  508. if (xmit_type & XMIT_LSO) {
  509. first_bd->data.bd_flags.bitfields |=
  510. (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
  511. third_bd->data.lso_mss =
  512. cpu_to_le16(skb_shinfo(skb)->gso_size);
  513. if (unlikely(xmit_type & XMIT_ENC)) {
  514. first_bd->data.bd_flags.bitfields |=
  515. 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
  516. hlen = qede_get_skb_hlen(skb, true);
  517. } else {
  518. first_bd->data.bd_flags.bitfields |=
  519. 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
  520. hlen = qede_get_skb_hlen(skb, false);
  521. }
  522. /* @@@TBD - if will not be removed need to check */
  523. third_bd->data.bitfields |=
  524. cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
  525. /* Make life easier for FW guys who can't deal with header and
  526. * data on same BD. If we need to split, use the second bd...
  527. */
  528. if (unlikely(skb_headlen(skb) > hlen)) {
  529. DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
  530. "TSO split header size is %d (%x:%x)\n",
  531. first_bd->nbytes, first_bd->addr.hi,
  532. first_bd->addr.lo);
  533. mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
  534. le32_to_cpu(first_bd->addr.lo)) +
  535. hlen;
  536. BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
  537. le16_to_cpu(first_bd->nbytes) -
  538. hlen);
  539. /* this marks the BD as one that has no
  540. * individual mapping
  541. */
  542. txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
  543. first_bd->nbytes = cpu_to_le16(hlen);
  544. tx_data_bd = (struct eth_tx_bd *)third_bd;
  545. data_split = true;
  546. }
  547. } else {
  548. first_bd->data.bitfields |=
  549. (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
  550. ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
  551. }
  552. /* Handle fragmented skb */
  553. /* special handle for frags inside 2nd and 3rd bds.. */
  554. while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
  555. rc = map_frag_to_bd(edev,
  556. &skb_shinfo(skb)->frags[frag_idx],
  557. tx_data_bd);
  558. if (rc) {
  559. qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
  560. data_split);
  561. qede_update_tx_producer(txq);
  562. return NETDEV_TX_OK;
  563. }
  564. if (tx_data_bd == (struct eth_tx_bd *)second_bd)
  565. tx_data_bd = (struct eth_tx_bd *)third_bd;
  566. else
  567. tx_data_bd = NULL;
  568. frag_idx++;
  569. }
  570. /* map last frags into 4th, 5th .... */
  571. for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
  572. tx_data_bd = (struct eth_tx_bd *)
  573. qed_chain_produce(&txq->tx_pbl);
  574. memset(tx_data_bd, 0, sizeof(*tx_data_bd));
  575. rc = map_frag_to_bd(edev,
  576. &skb_shinfo(skb)->frags[frag_idx],
  577. tx_data_bd);
  578. if (rc) {
  579. qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
  580. data_split);
  581. qede_update_tx_producer(txq);
  582. return NETDEV_TX_OK;
  583. }
  584. }
  585. /* update the first BD with the actual num BDs */
  586. first_bd->data.nbds = nbd;
  587. netdev_tx_sent_queue(netdev_txq, skb->len);
  588. skb_tx_timestamp(skb);
  589. /* Advance packet producer only before sending the packet since mapping
  590. * of pages may fail.
  591. */
  592. txq->sw_tx_prod++;
  593. /* 'next page' entries are counted in the producer value */
  594. txq->tx_db.data.bd_prod =
  595. cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
  596. if (!skb->xmit_more || netif_xmit_stopped(netdev_txq))
  597. qede_update_tx_producer(txq);
  598. if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
  599. < (MAX_SKB_FRAGS + 1))) {
  600. if (skb->xmit_more)
  601. qede_update_tx_producer(txq);
  602. netif_tx_stop_queue(netdev_txq);
  603. DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
  604. "Stop queue was called\n");
  605. /* paired memory barrier is in qede_tx_int(), we have to keep
  606. * ordering of set_bit() in netif_tx_stop_queue() and read of
  607. * fp->bd_tx_cons
  608. */
  609. smp_mb();
  610. if (qed_chain_get_elem_left(&txq->tx_pbl)
  611. >= (MAX_SKB_FRAGS + 1) &&
  612. (edev->state == QEDE_STATE_OPEN)) {
  613. netif_tx_wake_queue(netdev_txq);
  614. DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
  615. "Wake queue was called\n");
  616. }
  617. }
  618. return NETDEV_TX_OK;
  619. }
  620. int qede_txq_has_work(struct qede_tx_queue *txq)
  621. {
  622. u16 hw_bd_cons;
  623. /* Tell compiler that consumer and producer can change */
  624. barrier();
  625. hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
  626. if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
  627. return 0;
  628. return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
  629. }
  630. static int qede_tx_int(struct qede_dev *edev,
  631. struct qede_tx_queue *txq)
  632. {
  633. struct netdev_queue *netdev_txq;
  634. u16 hw_bd_cons;
  635. unsigned int pkts_compl = 0, bytes_compl = 0;
  636. int rc;
  637. netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
  638. hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
  639. barrier();
  640. while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
  641. int len = 0;
  642. rc = qede_free_tx_pkt(edev, txq, &len);
  643. if (rc) {
  644. DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
  645. hw_bd_cons,
  646. qed_chain_get_cons_idx(&txq->tx_pbl));
  647. break;
  648. }
  649. bytes_compl += len;
  650. pkts_compl++;
  651. txq->sw_tx_cons++;
  652. }
  653. netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
  654. /* Need to make the tx_bd_cons update visible to start_xmit()
  655. * before checking for netif_tx_queue_stopped(). Without the
  656. * memory barrier, there is a small possibility that
  657. * start_xmit() will miss it and cause the queue to be stopped
  658. * forever.
  659. * On the other hand we need an rmb() here to ensure the proper
  660. * ordering of bit testing in the following
  661. * netif_tx_queue_stopped(txq) call.
  662. */
  663. smp_mb();
  664. if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
  665. /* Taking tx_lock is needed to prevent reenabling the queue
  666. * while it's empty. This could have happen if rx_action() gets
  667. * suspended in qede_tx_int() after the condition before
  668. * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
  669. *
  670. * stops the queue->sees fresh tx_bd_cons->releases the queue->
  671. * sends some packets consuming the whole queue again->
  672. * stops the queue
  673. */
  674. __netif_tx_lock(netdev_txq, smp_processor_id());
  675. if ((netif_tx_queue_stopped(netdev_txq)) &&
  676. (edev->state == QEDE_STATE_OPEN) &&
  677. (qed_chain_get_elem_left(&txq->tx_pbl)
  678. >= (MAX_SKB_FRAGS + 1))) {
  679. netif_tx_wake_queue(netdev_txq);
  680. DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
  681. "Wake queue was called\n");
  682. }
  683. __netif_tx_unlock(netdev_txq);
  684. }
  685. return 0;
  686. }
  687. bool qede_has_rx_work(struct qede_rx_queue *rxq)
  688. {
  689. u16 hw_comp_cons, sw_comp_cons;
  690. /* Tell compiler that status block fields can change */
  691. barrier();
  692. hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
  693. sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
  694. return hw_comp_cons != sw_comp_cons;
  695. }
  696. static bool qede_has_tx_work(struct qede_fastpath *fp)
  697. {
  698. u8 tc;
  699. for (tc = 0; tc < fp->edev->num_tc; tc++)
  700. if (qede_txq_has_work(&fp->txqs[tc]))
  701. return true;
  702. return false;
  703. }
  704. static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
  705. {
  706. qed_chain_consume(&rxq->rx_bd_ring);
  707. rxq->sw_rx_cons++;
  708. }
  709. /* This function reuses the buffer(from an offset) from
  710. * consumer index to producer index in the bd ring
  711. */
  712. static inline void qede_reuse_page(struct qede_dev *edev,
  713. struct qede_rx_queue *rxq,
  714. struct sw_rx_data *curr_cons)
  715. {
  716. struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
  717. struct sw_rx_data *curr_prod;
  718. dma_addr_t new_mapping;
  719. curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
  720. *curr_prod = *curr_cons;
  721. new_mapping = curr_prod->mapping + curr_prod->page_offset;
  722. rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
  723. rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
  724. rxq->sw_rx_prod++;
  725. curr_cons->data = NULL;
  726. }
  727. /* In case of allocation failures reuse buffers
  728. * from consumer index to produce buffers for firmware
  729. */
  730. void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
  731. struct qede_dev *edev, u8 count)
  732. {
  733. struct sw_rx_data *curr_cons;
  734. for (; count > 0; count--) {
  735. curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
  736. qede_reuse_page(edev, rxq, curr_cons);
  737. qede_rx_bd_ring_consume(rxq);
  738. }
  739. }
  740. static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
  741. struct qede_rx_queue *rxq,
  742. struct sw_rx_data *curr_cons)
  743. {
  744. /* Move to the next segment in the page */
  745. curr_cons->page_offset += rxq->rx_buf_seg_size;
  746. if (curr_cons->page_offset == PAGE_SIZE) {
  747. if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
  748. /* Since we failed to allocate new buffer
  749. * current buffer can be used again.
  750. */
  751. curr_cons->page_offset -= rxq->rx_buf_seg_size;
  752. return -ENOMEM;
  753. }
  754. dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
  755. PAGE_SIZE, DMA_FROM_DEVICE);
  756. } else {
  757. /* Increment refcount of the page as we don't want
  758. * network stack to take the ownership of the page
  759. * which can be recycled multiple times by the driver.
  760. */
  761. page_ref_inc(curr_cons->data);
  762. qede_reuse_page(edev, rxq, curr_cons);
  763. }
  764. return 0;
  765. }
  766. static inline void qede_update_rx_prod(struct qede_dev *edev,
  767. struct qede_rx_queue *rxq)
  768. {
  769. u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
  770. u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
  771. struct eth_rx_prod_data rx_prods = {0};
  772. /* Update producers */
  773. rx_prods.bd_prod = cpu_to_le16(bd_prod);
  774. rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
  775. /* Make sure that the BD and SGE data is updated before updating the
  776. * producers since FW might read the BD/SGE right after the producer
  777. * is updated.
  778. */
  779. wmb();
  780. internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
  781. (u32 *)&rx_prods);
  782. /* mmiowb is needed to synchronize doorbell writes from more than one
  783. * processor. It guarantees that the write arrives to the device before
  784. * the napi lock is released and another qede_poll is called (possibly
  785. * on another CPU). Without this barrier, the next doorbell can bypass
  786. * this doorbell. This is applicable to IA64/Altix systems.
  787. */
  788. mmiowb();
  789. }
  790. static u32 qede_get_rxhash(struct qede_dev *edev,
  791. u8 bitfields,
  792. __le32 rss_hash,
  793. enum pkt_hash_types *rxhash_type)
  794. {
  795. enum rss_hash_type htype;
  796. htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
  797. if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
  798. *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
  799. (htype == RSS_HASH_TYPE_IPV6)) ?
  800. PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
  801. return le32_to_cpu(rss_hash);
  802. }
  803. *rxhash_type = PKT_HASH_TYPE_NONE;
  804. return 0;
  805. }
  806. static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
  807. {
  808. skb_checksum_none_assert(skb);
  809. if (csum_flag & QEDE_CSUM_UNNECESSARY)
  810. skb->ip_summed = CHECKSUM_UNNECESSARY;
  811. if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
  812. skb->csum_level = 1;
  813. }
  814. static inline void qede_skb_receive(struct qede_dev *edev,
  815. struct qede_fastpath *fp,
  816. struct sk_buff *skb,
  817. u16 vlan_tag)
  818. {
  819. if (vlan_tag)
  820. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  821. vlan_tag);
  822. napi_gro_receive(&fp->napi, skb);
  823. }
  824. static void qede_set_gro_params(struct qede_dev *edev,
  825. struct sk_buff *skb,
  826. struct eth_fast_path_rx_tpa_start_cqe *cqe)
  827. {
  828. u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
  829. if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
  830. PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
  831. skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
  832. else
  833. skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
  834. skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
  835. cqe->header_len;
  836. }
  837. static int qede_fill_frag_skb(struct qede_dev *edev,
  838. struct qede_rx_queue *rxq,
  839. u8 tpa_agg_index,
  840. u16 len_on_bd)
  841. {
  842. struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
  843. NUM_RX_BDS_MAX];
  844. struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
  845. struct sk_buff *skb = tpa_info->skb;
  846. if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
  847. goto out;
  848. /* Add one frag and update the appropriate fields in the skb */
  849. skb_fill_page_desc(skb, tpa_info->frag_id++,
  850. current_bd->data, current_bd->page_offset,
  851. len_on_bd);
  852. if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
  853. /* Incr page ref count to reuse on allocation failure
  854. * so that it doesn't get freed while freeing SKB.
  855. */
  856. page_ref_inc(current_bd->data);
  857. goto out;
  858. }
  859. qed_chain_consume(&rxq->rx_bd_ring);
  860. rxq->sw_rx_cons++;
  861. skb->data_len += len_on_bd;
  862. skb->truesize += rxq->rx_buf_seg_size;
  863. skb->len += len_on_bd;
  864. return 0;
  865. out:
  866. tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
  867. qede_recycle_rx_bd_ring(rxq, edev, 1);
  868. return -ENOMEM;
  869. }
  870. static void qede_tpa_start(struct qede_dev *edev,
  871. struct qede_rx_queue *rxq,
  872. struct eth_fast_path_rx_tpa_start_cqe *cqe)
  873. {
  874. struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
  875. struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
  876. struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
  877. struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
  878. dma_addr_t mapping = tpa_info->replace_buf_mapping;
  879. struct sw_rx_data *sw_rx_data_cons;
  880. struct sw_rx_data *sw_rx_data_prod;
  881. enum pkt_hash_types rxhash_type;
  882. u32 rxhash;
  883. sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
  884. sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
  885. /* Use pre-allocated replacement buffer - we can't release the agg.
  886. * start until its over and we don't want to risk allocation failing
  887. * here, so re-allocate when aggregation will be over.
  888. */
  889. sw_rx_data_prod->mapping = replace_buf->mapping;
  890. sw_rx_data_prod->data = replace_buf->data;
  891. rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
  892. rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
  893. sw_rx_data_prod->page_offset = replace_buf->page_offset;
  894. rxq->sw_rx_prod++;
  895. /* move partial skb from cons to pool (don't unmap yet)
  896. * save mapping, incase we drop the packet later on.
  897. */
  898. tpa_info->start_buf = *sw_rx_data_cons;
  899. mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
  900. le32_to_cpu(rx_bd_cons->addr.lo));
  901. tpa_info->start_buf_mapping = mapping;
  902. rxq->sw_rx_cons++;
  903. /* set tpa state to start only if we are able to allocate skb
  904. * for this aggregation, otherwise mark as error and aggregation will
  905. * be dropped
  906. */
  907. tpa_info->skb = netdev_alloc_skb(edev->ndev,
  908. le16_to_cpu(cqe->len_on_first_bd));
  909. if (unlikely(!tpa_info->skb)) {
  910. DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
  911. tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
  912. goto cons_buf;
  913. }
  914. skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
  915. memcpy(&tpa_info->start_cqe, cqe, sizeof(tpa_info->start_cqe));
  916. /* Start filling in the aggregation info */
  917. tpa_info->frag_id = 0;
  918. tpa_info->agg_state = QEDE_AGG_STATE_START;
  919. rxhash = qede_get_rxhash(edev, cqe->bitfields,
  920. cqe->rss_hash, &rxhash_type);
  921. skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
  922. if ((le16_to_cpu(cqe->pars_flags.flags) >>
  923. PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
  924. PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
  925. tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
  926. else
  927. tpa_info->vlan_tag = 0;
  928. /* This is needed in order to enable forwarding support */
  929. qede_set_gro_params(edev, tpa_info->skb, cqe);
  930. cons_buf: /* We still need to handle bd_len_list to consume buffers */
  931. if (likely(cqe->ext_bd_len_list[0]))
  932. qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
  933. le16_to_cpu(cqe->ext_bd_len_list[0]));
  934. if (unlikely(cqe->ext_bd_len_list[1])) {
  935. DP_ERR(edev,
  936. "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
  937. tpa_info->agg_state = QEDE_AGG_STATE_ERROR;
  938. }
  939. }
  940. #ifdef CONFIG_INET
  941. static void qede_gro_ip_csum(struct sk_buff *skb)
  942. {
  943. const struct iphdr *iph = ip_hdr(skb);
  944. struct tcphdr *th;
  945. skb_set_transport_header(skb, sizeof(struct iphdr));
  946. th = tcp_hdr(skb);
  947. th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
  948. iph->saddr, iph->daddr, 0);
  949. tcp_gro_complete(skb);
  950. }
  951. static void qede_gro_ipv6_csum(struct sk_buff *skb)
  952. {
  953. struct ipv6hdr *iph = ipv6_hdr(skb);
  954. struct tcphdr *th;
  955. skb_set_transport_header(skb, sizeof(struct ipv6hdr));
  956. th = tcp_hdr(skb);
  957. th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
  958. &iph->saddr, &iph->daddr, 0);
  959. tcp_gro_complete(skb);
  960. }
  961. #endif
  962. static void qede_gro_receive(struct qede_dev *edev,
  963. struct qede_fastpath *fp,
  964. struct sk_buff *skb,
  965. u16 vlan_tag)
  966. {
  967. /* FW can send a single MTU sized packet from gro flow
  968. * due to aggregation timeout/last segment etc. which
  969. * is not expected to be a gro packet. If a skb has zero
  970. * frags then simply push it in the stack as non gso skb.
  971. */
  972. if (unlikely(!skb->data_len)) {
  973. skb_shinfo(skb)->gso_type = 0;
  974. skb_shinfo(skb)->gso_size = 0;
  975. goto send_skb;
  976. }
  977. #ifdef CONFIG_INET
  978. if (skb_shinfo(skb)->gso_size) {
  979. skb_set_network_header(skb, 0);
  980. switch (skb->protocol) {
  981. case htons(ETH_P_IP):
  982. qede_gro_ip_csum(skb);
  983. break;
  984. case htons(ETH_P_IPV6):
  985. qede_gro_ipv6_csum(skb);
  986. break;
  987. default:
  988. DP_ERR(edev,
  989. "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
  990. ntohs(skb->protocol));
  991. }
  992. }
  993. #endif
  994. send_skb:
  995. skb_record_rx_queue(skb, fp->rss_id);
  996. qede_skb_receive(edev, fp, skb, vlan_tag);
  997. }
  998. static inline void qede_tpa_cont(struct qede_dev *edev,
  999. struct qede_rx_queue *rxq,
  1000. struct eth_fast_path_rx_tpa_cont_cqe *cqe)
  1001. {
  1002. int i;
  1003. for (i = 0; cqe->len_list[i]; i++)
  1004. qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
  1005. le16_to_cpu(cqe->len_list[i]));
  1006. if (unlikely(i > 1))
  1007. DP_ERR(edev,
  1008. "Strange - TPA cont with more than a single len_list entry\n");
  1009. }
  1010. static void qede_tpa_end(struct qede_dev *edev,
  1011. struct qede_fastpath *fp,
  1012. struct eth_fast_path_rx_tpa_end_cqe *cqe)
  1013. {
  1014. struct qede_rx_queue *rxq = fp->rxq;
  1015. struct qede_agg_info *tpa_info;
  1016. struct sk_buff *skb;
  1017. int i;
  1018. tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
  1019. skb = tpa_info->skb;
  1020. for (i = 0; cqe->len_list[i]; i++)
  1021. qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
  1022. le16_to_cpu(cqe->len_list[i]));
  1023. if (unlikely(i > 1))
  1024. DP_ERR(edev,
  1025. "Strange - TPA emd with more than a single len_list entry\n");
  1026. if (unlikely(tpa_info->agg_state != QEDE_AGG_STATE_START))
  1027. goto err;
  1028. /* Sanity */
  1029. if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
  1030. DP_ERR(edev,
  1031. "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
  1032. cqe->num_of_bds, tpa_info->frag_id);
  1033. if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
  1034. DP_ERR(edev,
  1035. "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
  1036. le16_to_cpu(cqe->total_packet_len), skb->len);
  1037. memcpy(skb->data,
  1038. page_address(tpa_info->start_buf.data) +
  1039. tpa_info->start_cqe.placement_offset +
  1040. tpa_info->start_buf.page_offset,
  1041. le16_to_cpu(tpa_info->start_cqe.len_on_first_bd));
  1042. /* Recycle [mapped] start buffer for the next replacement */
  1043. tpa_info->replace_buf = tpa_info->start_buf;
  1044. tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
  1045. /* Finalize the SKB */
  1046. skb->protocol = eth_type_trans(skb, edev->ndev);
  1047. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1048. /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
  1049. * to skb_shinfo(skb)->gso_segs
  1050. */
  1051. NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
  1052. qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
  1053. tpa_info->agg_state = QEDE_AGG_STATE_NONE;
  1054. return;
  1055. err:
  1056. /* The BD starting the aggregation is still mapped; Re-use it for
  1057. * future aggregations [as replacement buffer]
  1058. */
  1059. memcpy(&tpa_info->replace_buf, &tpa_info->start_buf,
  1060. sizeof(struct sw_rx_data));
  1061. tpa_info->replace_buf_mapping = tpa_info->start_buf_mapping;
  1062. tpa_info->start_buf.data = NULL;
  1063. tpa_info->agg_state = QEDE_AGG_STATE_NONE;
  1064. dev_kfree_skb_any(tpa_info->skb);
  1065. tpa_info->skb = NULL;
  1066. }
  1067. static bool qede_tunn_exist(u16 flag)
  1068. {
  1069. return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
  1070. PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
  1071. }
  1072. static u8 qede_check_tunn_csum(u16 flag)
  1073. {
  1074. u16 csum_flag = 0;
  1075. u8 tcsum = 0;
  1076. if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
  1077. PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
  1078. csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
  1079. PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
  1080. if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
  1081. PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
  1082. csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
  1083. PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
  1084. tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
  1085. }
  1086. csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
  1087. PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
  1088. PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
  1089. PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
  1090. if (csum_flag & flag)
  1091. return QEDE_CSUM_ERROR;
  1092. return QEDE_CSUM_UNNECESSARY | tcsum;
  1093. }
  1094. static u8 qede_check_notunn_csum(u16 flag)
  1095. {
  1096. u16 csum_flag = 0;
  1097. u8 csum = 0;
  1098. if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
  1099. PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
  1100. csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
  1101. PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
  1102. csum = QEDE_CSUM_UNNECESSARY;
  1103. }
  1104. csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
  1105. PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
  1106. if (csum_flag & flag)
  1107. return QEDE_CSUM_ERROR;
  1108. return csum;
  1109. }
  1110. static u8 qede_check_csum(u16 flag)
  1111. {
  1112. if (!qede_tunn_exist(flag))
  1113. return qede_check_notunn_csum(flag);
  1114. else
  1115. return qede_check_tunn_csum(flag);
  1116. }
  1117. static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
  1118. u16 flag)
  1119. {
  1120. u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
  1121. if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
  1122. ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
  1123. (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
  1124. PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
  1125. return true;
  1126. return false;
  1127. }
  1128. static int qede_rx_int(struct qede_fastpath *fp, int budget)
  1129. {
  1130. struct qede_dev *edev = fp->edev;
  1131. struct qede_rx_queue *rxq = fp->rxq;
  1132. u16 hw_comp_cons, sw_comp_cons, sw_rx_index, parse_flag;
  1133. int rx_pkt = 0;
  1134. u8 csum_flag;
  1135. hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
  1136. sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
  1137. /* Memory barrier to prevent the CPU from doing speculative reads of CQE
  1138. * / BD in the while-loop before reading hw_comp_cons. If the CQE is
  1139. * read before it is written by FW, then FW writes CQE and SB, and then
  1140. * the CPU reads the hw_comp_cons, it will use an old CQE.
  1141. */
  1142. rmb();
  1143. /* Loop to complete all indicated BDs */
  1144. while (sw_comp_cons != hw_comp_cons) {
  1145. struct eth_fast_path_rx_reg_cqe *fp_cqe;
  1146. enum pkt_hash_types rxhash_type;
  1147. enum eth_rx_cqe_type cqe_type;
  1148. struct sw_rx_data *sw_rx_data;
  1149. union eth_rx_cqe *cqe;
  1150. struct sk_buff *skb;
  1151. struct page *data;
  1152. __le16 flags;
  1153. u16 len, pad;
  1154. u32 rx_hash;
  1155. /* Get the CQE from the completion ring */
  1156. cqe = (union eth_rx_cqe *)
  1157. qed_chain_consume(&rxq->rx_comp_ring);
  1158. cqe_type = cqe->fast_path_regular.type;
  1159. if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
  1160. edev->ops->eth_cqe_completion(
  1161. edev->cdev, fp->rss_id,
  1162. (struct eth_slow_path_rx_cqe *)cqe);
  1163. goto next_cqe;
  1164. }
  1165. if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
  1166. switch (cqe_type) {
  1167. case ETH_RX_CQE_TYPE_TPA_START:
  1168. qede_tpa_start(edev, rxq,
  1169. &cqe->fast_path_tpa_start);
  1170. goto next_cqe;
  1171. case ETH_RX_CQE_TYPE_TPA_CONT:
  1172. qede_tpa_cont(edev, rxq,
  1173. &cqe->fast_path_tpa_cont);
  1174. goto next_cqe;
  1175. case ETH_RX_CQE_TYPE_TPA_END:
  1176. qede_tpa_end(edev, fp,
  1177. &cqe->fast_path_tpa_end);
  1178. goto next_rx_only;
  1179. default:
  1180. break;
  1181. }
  1182. }
  1183. /* Get the data from the SW ring */
  1184. sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
  1185. sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
  1186. data = sw_rx_data->data;
  1187. fp_cqe = &cqe->fast_path_regular;
  1188. len = le16_to_cpu(fp_cqe->len_on_first_bd);
  1189. pad = fp_cqe->placement_offset;
  1190. flags = cqe->fast_path_regular.pars_flags.flags;
  1191. /* If this is an error packet then drop it */
  1192. parse_flag = le16_to_cpu(flags);
  1193. csum_flag = qede_check_csum(parse_flag);
  1194. if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
  1195. if (qede_pkt_is_ip_fragmented(&cqe->fast_path_regular,
  1196. parse_flag)) {
  1197. rxq->rx_ip_frags++;
  1198. goto alloc_skb;
  1199. }
  1200. DP_NOTICE(edev,
  1201. "CQE in CONS = %u has error, flags = %x, dropping incoming packet\n",
  1202. sw_comp_cons, parse_flag);
  1203. rxq->rx_hw_errors++;
  1204. qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
  1205. goto next_cqe;
  1206. }
  1207. alloc_skb:
  1208. skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
  1209. if (unlikely(!skb)) {
  1210. DP_NOTICE(edev,
  1211. "Build_skb failed, dropping incoming packet\n");
  1212. qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
  1213. rxq->rx_alloc_errors++;
  1214. goto next_cqe;
  1215. }
  1216. /* Copy data into SKB */
  1217. if (len + pad <= edev->rx_copybreak) {
  1218. memcpy(skb_put(skb, len),
  1219. page_address(data) + pad +
  1220. sw_rx_data->page_offset, len);
  1221. qede_reuse_page(edev, rxq, sw_rx_data);
  1222. } else {
  1223. struct skb_frag_struct *frag;
  1224. unsigned int pull_len;
  1225. unsigned char *va;
  1226. frag = &skb_shinfo(skb)->frags[0];
  1227. skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, data,
  1228. pad + sw_rx_data->page_offset,
  1229. len, rxq->rx_buf_seg_size);
  1230. va = skb_frag_address(frag);
  1231. pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
  1232. /* Align the pull_len to optimize memcpy */
  1233. memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
  1234. skb_frag_size_sub(frag, pull_len);
  1235. frag->page_offset += pull_len;
  1236. skb->data_len -= pull_len;
  1237. skb->tail += pull_len;
  1238. if (unlikely(qede_realloc_rx_buffer(edev, rxq,
  1239. sw_rx_data))) {
  1240. DP_ERR(edev, "Failed to allocate rx buffer\n");
  1241. /* Incr page ref count to reuse on allocation
  1242. * failure so that it doesn't get freed while
  1243. * freeing SKB.
  1244. */
  1245. page_ref_inc(sw_rx_data->data);
  1246. rxq->rx_alloc_errors++;
  1247. qede_recycle_rx_bd_ring(rxq, edev,
  1248. fp_cqe->bd_num);
  1249. dev_kfree_skb_any(skb);
  1250. goto next_cqe;
  1251. }
  1252. }
  1253. qede_rx_bd_ring_consume(rxq);
  1254. if (fp_cqe->bd_num != 1) {
  1255. u16 pkt_len = le16_to_cpu(fp_cqe->pkt_len);
  1256. u8 num_frags;
  1257. pkt_len -= len;
  1258. for (num_frags = fp_cqe->bd_num - 1; num_frags > 0;
  1259. num_frags--) {
  1260. u16 cur_size = pkt_len > rxq->rx_buf_size ?
  1261. rxq->rx_buf_size : pkt_len;
  1262. if (unlikely(!cur_size)) {
  1263. DP_ERR(edev,
  1264. "Still got %d BDs for mapping jumbo, but length became 0\n",
  1265. num_frags);
  1266. qede_recycle_rx_bd_ring(rxq, edev,
  1267. num_frags);
  1268. dev_kfree_skb_any(skb);
  1269. goto next_cqe;
  1270. }
  1271. if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
  1272. qede_recycle_rx_bd_ring(rxq, edev,
  1273. num_frags);
  1274. dev_kfree_skb_any(skb);
  1275. goto next_cqe;
  1276. }
  1277. sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
  1278. sw_rx_data = &rxq->sw_rx_ring[sw_rx_index];
  1279. qede_rx_bd_ring_consume(rxq);
  1280. dma_unmap_page(&edev->pdev->dev,
  1281. sw_rx_data->mapping,
  1282. PAGE_SIZE, DMA_FROM_DEVICE);
  1283. skb_fill_page_desc(skb,
  1284. skb_shinfo(skb)->nr_frags++,
  1285. sw_rx_data->data, 0,
  1286. cur_size);
  1287. skb->truesize += PAGE_SIZE;
  1288. skb->data_len += cur_size;
  1289. skb->len += cur_size;
  1290. pkt_len -= cur_size;
  1291. }
  1292. if (unlikely(pkt_len))
  1293. DP_ERR(edev,
  1294. "Mapped all BDs of jumbo, but still have %d bytes\n",
  1295. pkt_len);
  1296. }
  1297. skb->protocol = eth_type_trans(skb, edev->ndev);
  1298. rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
  1299. fp_cqe->rss_hash,
  1300. &rxhash_type);
  1301. skb_set_hash(skb, rx_hash, rxhash_type);
  1302. qede_set_skb_csum(skb, csum_flag);
  1303. skb_record_rx_queue(skb, fp->rss_id);
  1304. qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
  1305. next_rx_only:
  1306. rx_pkt++;
  1307. next_cqe: /* don't consume bd rx buffer */
  1308. qed_chain_recycle_consumed(&rxq->rx_comp_ring);
  1309. sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
  1310. /* CR TPA - revisit how to handle budget in TPA perhaps
  1311. * increase on "end"
  1312. */
  1313. if (rx_pkt == budget)
  1314. break;
  1315. } /* repeat while sw_comp_cons != hw_comp_cons... */
  1316. /* Update producers */
  1317. qede_update_rx_prod(edev, rxq);
  1318. return rx_pkt;
  1319. }
  1320. static int qede_poll(struct napi_struct *napi, int budget)
  1321. {
  1322. struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
  1323. napi);
  1324. struct qede_dev *edev = fp->edev;
  1325. int rx_work_done = 0;
  1326. u8 tc;
  1327. for (tc = 0; tc < edev->num_tc; tc++)
  1328. if (qede_txq_has_work(&fp->txqs[tc]))
  1329. qede_tx_int(edev, &fp->txqs[tc]);
  1330. rx_work_done = qede_has_rx_work(fp->rxq) ?
  1331. qede_rx_int(fp, budget) : 0;
  1332. if (rx_work_done < budget) {
  1333. qed_sb_update_sb_idx(fp->sb_info);
  1334. /* *_has_*_work() reads the status block,
  1335. * thus we need to ensure that status block indices
  1336. * have been actually read (qed_sb_update_sb_idx)
  1337. * prior to this check (*_has_*_work) so that
  1338. * we won't write the "newer" value of the status block
  1339. * to HW (if there was a DMA right after
  1340. * qede_has_rx_work and if there is no rmb, the memory
  1341. * reading (qed_sb_update_sb_idx) may be postponed
  1342. * to right before *_ack_sb). In this case there
  1343. * will never be another interrupt until there is
  1344. * another update of the status block, while there
  1345. * is still unhandled work.
  1346. */
  1347. rmb();
  1348. /* Fall out from the NAPI loop if needed */
  1349. if (!(qede_has_rx_work(fp->rxq) ||
  1350. qede_has_tx_work(fp))) {
  1351. napi_complete(napi);
  1352. /* Update and reenable interrupts */
  1353. qed_sb_ack(fp->sb_info, IGU_INT_ENABLE,
  1354. 1 /*update*/);
  1355. } else {
  1356. rx_work_done = budget;
  1357. }
  1358. }
  1359. return rx_work_done;
  1360. }
  1361. static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
  1362. {
  1363. struct qede_fastpath *fp = fp_cookie;
  1364. qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
  1365. napi_schedule_irqoff(&fp->napi);
  1366. return IRQ_HANDLED;
  1367. }
  1368. /* -------------------------------------------------------------------------
  1369. * END OF FAST-PATH
  1370. * -------------------------------------------------------------------------
  1371. */
  1372. static int qede_open(struct net_device *ndev);
  1373. static int qede_close(struct net_device *ndev);
  1374. static int qede_set_mac_addr(struct net_device *ndev, void *p);
  1375. static void qede_set_rx_mode(struct net_device *ndev);
  1376. static void qede_config_rx_mode(struct net_device *ndev);
  1377. static int qede_set_ucast_rx_mac(struct qede_dev *edev,
  1378. enum qed_filter_xcast_params_type opcode,
  1379. unsigned char mac[ETH_ALEN])
  1380. {
  1381. struct qed_filter_params filter_cmd;
  1382. memset(&filter_cmd, 0, sizeof(filter_cmd));
  1383. filter_cmd.type = QED_FILTER_TYPE_UCAST;
  1384. filter_cmd.filter.ucast.type = opcode;
  1385. filter_cmd.filter.ucast.mac_valid = 1;
  1386. ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
  1387. return edev->ops->filter_config(edev->cdev, &filter_cmd);
  1388. }
  1389. static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
  1390. enum qed_filter_xcast_params_type opcode,
  1391. u16 vid)
  1392. {
  1393. struct qed_filter_params filter_cmd;
  1394. memset(&filter_cmd, 0, sizeof(filter_cmd));
  1395. filter_cmd.type = QED_FILTER_TYPE_UCAST;
  1396. filter_cmd.filter.ucast.type = opcode;
  1397. filter_cmd.filter.ucast.vlan_valid = 1;
  1398. filter_cmd.filter.ucast.vlan = vid;
  1399. return edev->ops->filter_config(edev->cdev, &filter_cmd);
  1400. }
  1401. void qede_fill_by_demand_stats(struct qede_dev *edev)
  1402. {
  1403. struct qed_eth_stats stats;
  1404. edev->ops->get_vport_stats(edev->cdev, &stats);
  1405. edev->stats.no_buff_discards = stats.no_buff_discards;
  1406. edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
  1407. edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
  1408. edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
  1409. edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
  1410. edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
  1411. edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
  1412. edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
  1413. edev->stats.mac_filter_discards = stats.mac_filter_discards;
  1414. edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
  1415. edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
  1416. edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
  1417. edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
  1418. edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
  1419. edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
  1420. edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
  1421. edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
  1422. edev->stats.coalesced_events = stats.tpa_coalesced_events;
  1423. edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
  1424. edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
  1425. edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
  1426. edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
  1427. edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
  1428. edev->stats.rx_128_to_255_byte_packets =
  1429. stats.rx_128_to_255_byte_packets;
  1430. edev->stats.rx_256_to_511_byte_packets =
  1431. stats.rx_256_to_511_byte_packets;
  1432. edev->stats.rx_512_to_1023_byte_packets =
  1433. stats.rx_512_to_1023_byte_packets;
  1434. edev->stats.rx_1024_to_1518_byte_packets =
  1435. stats.rx_1024_to_1518_byte_packets;
  1436. edev->stats.rx_1519_to_1522_byte_packets =
  1437. stats.rx_1519_to_1522_byte_packets;
  1438. edev->stats.rx_1519_to_2047_byte_packets =
  1439. stats.rx_1519_to_2047_byte_packets;
  1440. edev->stats.rx_2048_to_4095_byte_packets =
  1441. stats.rx_2048_to_4095_byte_packets;
  1442. edev->stats.rx_4096_to_9216_byte_packets =
  1443. stats.rx_4096_to_9216_byte_packets;
  1444. edev->stats.rx_9217_to_16383_byte_packets =
  1445. stats.rx_9217_to_16383_byte_packets;
  1446. edev->stats.rx_crc_errors = stats.rx_crc_errors;
  1447. edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
  1448. edev->stats.rx_pause_frames = stats.rx_pause_frames;
  1449. edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
  1450. edev->stats.rx_align_errors = stats.rx_align_errors;
  1451. edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
  1452. edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
  1453. edev->stats.rx_jabbers = stats.rx_jabbers;
  1454. edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
  1455. edev->stats.rx_fragments = stats.rx_fragments;
  1456. edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
  1457. edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
  1458. edev->stats.tx_128_to_255_byte_packets =
  1459. stats.tx_128_to_255_byte_packets;
  1460. edev->stats.tx_256_to_511_byte_packets =
  1461. stats.tx_256_to_511_byte_packets;
  1462. edev->stats.tx_512_to_1023_byte_packets =
  1463. stats.tx_512_to_1023_byte_packets;
  1464. edev->stats.tx_1024_to_1518_byte_packets =
  1465. stats.tx_1024_to_1518_byte_packets;
  1466. edev->stats.tx_1519_to_2047_byte_packets =
  1467. stats.tx_1519_to_2047_byte_packets;
  1468. edev->stats.tx_2048_to_4095_byte_packets =
  1469. stats.tx_2048_to_4095_byte_packets;
  1470. edev->stats.tx_4096_to_9216_byte_packets =
  1471. stats.tx_4096_to_9216_byte_packets;
  1472. edev->stats.tx_9217_to_16383_byte_packets =
  1473. stats.tx_9217_to_16383_byte_packets;
  1474. edev->stats.tx_pause_frames = stats.tx_pause_frames;
  1475. edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
  1476. edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
  1477. edev->stats.tx_total_collisions = stats.tx_total_collisions;
  1478. edev->stats.brb_truncates = stats.brb_truncates;
  1479. edev->stats.brb_discards = stats.brb_discards;
  1480. edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
  1481. }
  1482. static struct rtnl_link_stats64 *qede_get_stats64(
  1483. struct net_device *dev,
  1484. struct rtnl_link_stats64 *stats)
  1485. {
  1486. struct qede_dev *edev = netdev_priv(dev);
  1487. qede_fill_by_demand_stats(edev);
  1488. stats->rx_packets = edev->stats.rx_ucast_pkts +
  1489. edev->stats.rx_mcast_pkts +
  1490. edev->stats.rx_bcast_pkts;
  1491. stats->tx_packets = edev->stats.tx_ucast_pkts +
  1492. edev->stats.tx_mcast_pkts +
  1493. edev->stats.tx_bcast_pkts;
  1494. stats->rx_bytes = edev->stats.rx_ucast_bytes +
  1495. edev->stats.rx_mcast_bytes +
  1496. edev->stats.rx_bcast_bytes;
  1497. stats->tx_bytes = edev->stats.tx_ucast_bytes +
  1498. edev->stats.tx_mcast_bytes +
  1499. edev->stats.tx_bcast_bytes;
  1500. stats->tx_errors = edev->stats.tx_err_drop_pkts;
  1501. stats->multicast = edev->stats.rx_mcast_pkts +
  1502. edev->stats.rx_bcast_pkts;
  1503. stats->rx_fifo_errors = edev->stats.no_buff_discards;
  1504. stats->collisions = edev->stats.tx_total_collisions;
  1505. stats->rx_crc_errors = edev->stats.rx_crc_errors;
  1506. stats->rx_frame_errors = edev->stats.rx_align_errors;
  1507. return stats;
  1508. }
  1509. #ifdef CONFIG_QED_SRIOV
  1510. static int qede_get_vf_config(struct net_device *dev, int vfidx,
  1511. struct ifla_vf_info *ivi)
  1512. {
  1513. struct qede_dev *edev = netdev_priv(dev);
  1514. if (!edev->ops)
  1515. return -EINVAL;
  1516. return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
  1517. }
  1518. static int qede_set_vf_rate(struct net_device *dev, int vfidx,
  1519. int min_tx_rate, int max_tx_rate)
  1520. {
  1521. struct qede_dev *edev = netdev_priv(dev);
  1522. return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
  1523. max_tx_rate);
  1524. }
  1525. static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
  1526. {
  1527. struct qede_dev *edev = netdev_priv(dev);
  1528. if (!edev->ops)
  1529. return -EINVAL;
  1530. return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
  1531. }
  1532. static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
  1533. int link_state)
  1534. {
  1535. struct qede_dev *edev = netdev_priv(dev);
  1536. if (!edev->ops)
  1537. return -EINVAL;
  1538. return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
  1539. }
  1540. #endif
  1541. static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
  1542. {
  1543. struct qed_update_vport_params params;
  1544. int rc;
  1545. /* Proceed only if action actually needs to be performed */
  1546. if (edev->accept_any_vlan == action)
  1547. return;
  1548. memset(&params, 0, sizeof(params));
  1549. params.vport_id = 0;
  1550. params.accept_any_vlan = action;
  1551. params.update_accept_any_vlan_flg = 1;
  1552. rc = edev->ops->vport_update(edev->cdev, &params);
  1553. if (rc) {
  1554. DP_ERR(edev, "Failed to %s accept-any-vlan\n",
  1555. action ? "enable" : "disable");
  1556. } else {
  1557. DP_INFO(edev, "%s accept-any-vlan\n",
  1558. action ? "enabled" : "disabled");
  1559. edev->accept_any_vlan = action;
  1560. }
  1561. }
  1562. static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
  1563. {
  1564. struct qede_dev *edev = netdev_priv(dev);
  1565. struct qede_vlan *vlan, *tmp;
  1566. int rc;
  1567. DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
  1568. vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
  1569. if (!vlan) {
  1570. DP_INFO(edev, "Failed to allocate struct for vlan\n");
  1571. return -ENOMEM;
  1572. }
  1573. INIT_LIST_HEAD(&vlan->list);
  1574. vlan->vid = vid;
  1575. vlan->configured = false;
  1576. /* Verify vlan isn't already configured */
  1577. list_for_each_entry(tmp, &edev->vlan_list, list) {
  1578. if (tmp->vid == vlan->vid) {
  1579. DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
  1580. "vlan already configured\n");
  1581. kfree(vlan);
  1582. return -EEXIST;
  1583. }
  1584. }
  1585. /* If interface is down, cache this VLAN ID and return */
  1586. if (edev->state != QEDE_STATE_OPEN) {
  1587. DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
  1588. "Interface is down, VLAN %d will be configured when interface is up\n",
  1589. vid);
  1590. if (vid != 0)
  1591. edev->non_configured_vlans++;
  1592. list_add(&vlan->list, &edev->vlan_list);
  1593. return 0;
  1594. }
  1595. /* Check for the filter limit.
  1596. * Note - vlan0 has a reserved filter and can be added without
  1597. * worrying about quota
  1598. */
  1599. if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
  1600. (vlan->vid == 0)) {
  1601. rc = qede_set_ucast_rx_vlan(edev,
  1602. QED_FILTER_XCAST_TYPE_ADD,
  1603. vlan->vid);
  1604. if (rc) {
  1605. DP_ERR(edev, "Failed to configure VLAN %d\n",
  1606. vlan->vid);
  1607. kfree(vlan);
  1608. return -EINVAL;
  1609. }
  1610. vlan->configured = true;
  1611. /* vlan0 filter isn't consuming out of our quota */
  1612. if (vlan->vid != 0)
  1613. edev->configured_vlans++;
  1614. } else {
  1615. /* Out of quota; Activate accept-any-VLAN mode */
  1616. if (!edev->non_configured_vlans)
  1617. qede_config_accept_any_vlan(edev, true);
  1618. edev->non_configured_vlans++;
  1619. }
  1620. list_add(&vlan->list, &edev->vlan_list);
  1621. return 0;
  1622. }
  1623. static void qede_del_vlan_from_list(struct qede_dev *edev,
  1624. struct qede_vlan *vlan)
  1625. {
  1626. /* vlan0 filter isn't consuming out of our quota */
  1627. if (vlan->vid != 0) {
  1628. if (vlan->configured)
  1629. edev->configured_vlans--;
  1630. else
  1631. edev->non_configured_vlans--;
  1632. }
  1633. list_del(&vlan->list);
  1634. kfree(vlan);
  1635. }
  1636. static int qede_configure_vlan_filters(struct qede_dev *edev)
  1637. {
  1638. int rc = 0, real_rc = 0, accept_any_vlan = 0;
  1639. struct qed_dev_eth_info *dev_info;
  1640. struct qede_vlan *vlan = NULL;
  1641. if (list_empty(&edev->vlan_list))
  1642. return 0;
  1643. dev_info = &edev->dev_info;
  1644. /* Configure non-configured vlans */
  1645. list_for_each_entry(vlan, &edev->vlan_list, list) {
  1646. if (vlan->configured)
  1647. continue;
  1648. /* We have used all our credits, now enable accept_any_vlan */
  1649. if ((vlan->vid != 0) &&
  1650. (edev->configured_vlans == dev_info->num_vlan_filters)) {
  1651. accept_any_vlan = 1;
  1652. continue;
  1653. }
  1654. DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
  1655. rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
  1656. vlan->vid);
  1657. if (rc) {
  1658. DP_ERR(edev, "Failed to configure VLAN %u\n",
  1659. vlan->vid);
  1660. real_rc = rc;
  1661. continue;
  1662. }
  1663. vlan->configured = true;
  1664. /* vlan0 filter doesn't consume our VLAN filter's quota */
  1665. if (vlan->vid != 0) {
  1666. edev->non_configured_vlans--;
  1667. edev->configured_vlans++;
  1668. }
  1669. }
  1670. /* enable accept_any_vlan mode if we have more VLANs than credits,
  1671. * or remove accept_any_vlan mode if we've actually removed
  1672. * a non-configured vlan, and all remaining vlans are truly configured.
  1673. */
  1674. if (accept_any_vlan)
  1675. qede_config_accept_any_vlan(edev, true);
  1676. else if (!edev->non_configured_vlans)
  1677. qede_config_accept_any_vlan(edev, false);
  1678. return real_rc;
  1679. }
  1680. static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
  1681. {
  1682. struct qede_dev *edev = netdev_priv(dev);
  1683. struct qede_vlan *vlan = NULL;
  1684. int rc;
  1685. DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
  1686. /* Find whether entry exists */
  1687. list_for_each_entry(vlan, &edev->vlan_list, list)
  1688. if (vlan->vid == vid)
  1689. break;
  1690. if (!vlan || (vlan->vid != vid)) {
  1691. DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
  1692. "Vlan isn't configured\n");
  1693. return 0;
  1694. }
  1695. if (edev->state != QEDE_STATE_OPEN) {
  1696. /* As interface is already down, we don't have a VPORT
  1697. * instance to remove vlan filter. So just update vlan list
  1698. */
  1699. DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
  1700. "Interface is down, removing VLAN from list only\n");
  1701. qede_del_vlan_from_list(edev, vlan);
  1702. return 0;
  1703. }
  1704. /* Remove vlan */
  1705. if (vlan->configured) {
  1706. rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL,
  1707. vid);
  1708. if (rc) {
  1709. DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
  1710. return -EINVAL;
  1711. }
  1712. }
  1713. qede_del_vlan_from_list(edev, vlan);
  1714. /* We have removed a VLAN - try to see if we can
  1715. * configure non-configured VLAN from the list.
  1716. */
  1717. rc = qede_configure_vlan_filters(edev);
  1718. return rc;
  1719. }
  1720. static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
  1721. {
  1722. struct qede_vlan *vlan = NULL;
  1723. if (list_empty(&edev->vlan_list))
  1724. return;
  1725. list_for_each_entry(vlan, &edev->vlan_list, list) {
  1726. if (!vlan->configured)
  1727. continue;
  1728. vlan->configured = false;
  1729. /* vlan0 filter isn't consuming out of our quota */
  1730. if (vlan->vid != 0) {
  1731. edev->non_configured_vlans++;
  1732. edev->configured_vlans--;
  1733. }
  1734. DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
  1735. "marked vlan %d as non-configured\n",
  1736. vlan->vid);
  1737. }
  1738. edev->accept_any_vlan = false;
  1739. }
  1740. int qede_set_features(struct net_device *dev, netdev_features_t features)
  1741. {
  1742. struct qede_dev *edev = netdev_priv(dev);
  1743. netdev_features_t changes = features ^ dev->features;
  1744. bool need_reload = false;
  1745. /* No action needed if hardware GRO is disabled during driver load */
  1746. if (changes & NETIF_F_GRO) {
  1747. if (dev->features & NETIF_F_GRO)
  1748. need_reload = !edev->gro_disable;
  1749. else
  1750. need_reload = edev->gro_disable;
  1751. }
  1752. if (need_reload && netif_running(edev->ndev)) {
  1753. dev->features = features;
  1754. qede_reload(edev, NULL, NULL);
  1755. return 1;
  1756. }
  1757. return 0;
  1758. }
  1759. static void qede_udp_tunnel_add(struct net_device *dev,
  1760. struct udp_tunnel_info *ti)
  1761. {
  1762. struct qede_dev *edev = netdev_priv(dev);
  1763. u16 t_port = ntohs(ti->port);
  1764. switch (ti->type) {
  1765. case UDP_TUNNEL_TYPE_VXLAN:
  1766. if (edev->vxlan_dst_port)
  1767. return;
  1768. edev->vxlan_dst_port = t_port;
  1769. DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d",
  1770. t_port);
  1771. set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
  1772. break;
  1773. case UDP_TUNNEL_TYPE_GENEVE:
  1774. if (edev->geneve_dst_port)
  1775. return;
  1776. edev->geneve_dst_port = t_port;
  1777. DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d",
  1778. t_port);
  1779. set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
  1780. break;
  1781. default:
  1782. return;
  1783. }
  1784. schedule_delayed_work(&edev->sp_task, 0);
  1785. }
  1786. static void qede_udp_tunnel_del(struct net_device *dev,
  1787. struct udp_tunnel_info *ti)
  1788. {
  1789. struct qede_dev *edev = netdev_priv(dev);
  1790. u16 t_port = ntohs(ti->port);
  1791. switch (ti->type) {
  1792. case UDP_TUNNEL_TYPE_VXLAN:
  1793. if (t_port != edev->vxlan_dst_port)
  1794. return;
  1795. edev->vxlan_dst_port = 0;
  1796. DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d",
  1797. t_port);
  1798. set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
  1799. break;
  1800. case UDP_TUNNEL_TYPE_GENEVE:
  1801. if (t_port != edev->geneve_dst_port)
  1802. return;
  1803. edev->geneve_dst_port = 0;
  1804. DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d",
  1805. t_port);
  1806. set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
  1807. break;
  1808. default:
  1809. return;
  1810. }
  1811. schedule_delayed_work(&edev->sp_task, 0);
  1812. }
  1813. static const struct net_device_ops qede_netdev_ops = {
  1814. .ndo_open = qede_open,
  1815. .ndo_stop = qede_close,
  1816. .ndo_start_xmit = qede_start_xmit,
  1817. .ndo_set_rx_mode = qede_set_rx_mode,
  1818. .ndo_set_mac_address = qede_set_mac_addr,
  1819. .ndo_validate_addr = eth_validate_addr,
  1820. .ndo_change_mtu = qede_change_mtu,
  1821. #ifdef CONFIG_QED_SRIOV
  1822. .ndo_set_vf_mac = qede_set_vf_mac,
  1823. .ndo_set_vf_vlan = qede_set_vf_vlan,
  1824. #endif
  1825. .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
  1826. .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
  1827. .ndo_set_features = qede_set_features,
  1828. .ndo_get_stats64 = qede_get_stats64,
  1829. #ifdef CONFIG_QED_SRIOV
  1830. .ndo_set_vf_link_state = qede_set_vf_link_state,
  1831. .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
  1832. .ndo_get_vf_config = qede_get_vf_config,
  1833. .ndo_set_vf_rate = qede_set_vf_rate,
  1834. #endif
  1835. .ndo_udp_tunnel_add = qede_udp_tunnel_add,
  1836. .ndo_udp_tunnel_del = qede_udp_tunnel_del,
  1837. };
  1838. /* -------------------------------------------------------------------------
  1839. * START OF PROBE / REMOVE
  1840. * -------------------------------------------------------------------------
  1841. */
  1842. static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
  1843. struct pci_dev *pdev,
  1844. struct qed_dev_eth_info *info,
  1845. u32 dp_module,
  1846. u8 dp_level)
  1847. {
  1848. struct net_device *ndev;
  1849. struct qede_dev *edev;
  1850. ndev = alloc_etherdev_mqs(sizeof(*edev),
  1851. info->num_queues,
  1852. info->num_queues);
  1853. if (!ndev) {
  1854. pr_err("etherdev allocation failed\n");
  1855. return NULL;
  1856. }
  1857. edev = netdev_priv(ndev);
  1858. edev->ndev = ndev;
  1859. edev->cdev = cdev;
  1860. edev->pdev = pdev;
  1861. edev->dp_module = dp_module;
  1862. edev->dp_level = dp_level;
  1863. edev->ops = qed_ops;
  1864. edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
  1865. edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
  1866. SET_NETDEV_DEV(ndev, &pdev->dev);
  1867. memset(&edev->stats, 0, sizeof(edev->stats));
  1868. memcpy(&edev->dev_info, info, sizeof(*info));
  1869. edev->num_tc = edev->dev_info.num_tc;
  1870. INIT_LIST_HEAD(&edev->vlan_list);
  1871. return edev;
  1872. }
  1873. static void qede_init_ndev(struct qede_dev *edev)
  1874. {
  1875. struct net_device *ndev = edev->ndev;
  1876. struct pci_dev *pdev = edev->pdev;
  1877. u32 hw_features;
  1878. pci_set_drvdata(pdev, ndev);
  1879. ndev->mem_start = edev->dev_info.common.pci_mem_start;
  1880. ndev->base_addr = ndev->mem_start;
  1881. ndev->mem_end = edev->dev_info.common.pci_mem_end;
  1882. ndev->irq = edev->dev_info.common.pci_irq;
  1883. ndev->watchdog_timeo = TX_TIMEOUT;
  1884. ndev->netdev_ops = &qede_netdev_ops;
  1885. qede_set_ethtool_ops(ndev);
  1886. /* user-changeble features */
  1887. hw_features = NETIF_F_GRO | NETIF_F_SG |
  1888. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1889. NETIF_F_TSO | NETIF_F_TSO6;
  1890. /* Encap features*/
  1891. hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
  1892. NETIF_F_TSO_ECN;
  1893. ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1894. NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
  1895. NETIF_F_TSO6 | NETIF_F_GSO_GRE |
  1896. NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM;
  1897. ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
  1898. NETIF_F_HIGHDMA;
  1899. ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
  1900. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
  1901. NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
  1902. ndev->hw_features = hw_features;
  1903. /* Set network device HW mac */
  1904. ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
  1905. }
  1906. /* This function converts from 32b param to two params of level and module
  1907. * Input 32b decoding:
  1908. * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
  1909. * 'happy' flow, e.g. memory allocation failed.
  1910. * b30 - enable all INFO prints. INFO prints are for major steps in the flow
  1911. * and provide important parameters.
  1912. * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
  1913. * module. VERBOSE prints are for tracking the specific flow in low level.
  1914. *
  1915. * Notice that the level should be that of the lowest required logs.
  1916. */
  1917. void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
  1918. {
  1919. *p_dp_level = QED_LEVEL_NOTICE;
  1920. *p_dp_module = 0;
  1921. if (debug & QED_LOG_VERBOSE_MASK) {
  1922. *p_dp_level = QED_LEVEL_VERBOSE;
  1923. *p_dp_module = (debug & 0x3FFFFFFF);
  1924. } else if (debug & QED_LOG_INFO_MASK) {
  1925. *p_dp_level = QED_LEVEL_INFO;
  1926. } else if (debug & QED_LOG_NOTICE_MASK) {
  1927. *p_dp_level = QED_LEVEL_NOTICE;
  1928. }
  1929. }
  1930. static void qede_free_fp_array(struct qede_dev *edev)
  1931. {
  1932. if (edev->fp_array) {
  1933. struct qede_fastpath *fp;
  1934. int i;
  1935. for_each_rss(i) {
  1936. fp = &edev->fp_array[i];
  1937. kfree(fp->sb_info);
  1938. kfree(fp->rxq);
  1939. kfree(fp->txqs);
  1940. }
  1941. kfree(edev->fp_array);
  1942. }
  1943. edev->num_rss = 0;
  1944. }
  1945. static int qede_alloc_fp_array(struct qede_dev *edev)
  1946. {
  1947. struct qede_fastpath *fp;
  1948. int i;
  1949. edev->fp_array = kcalloc(QEDE_RSS_CNT(edev),
  1950. sizeof(*edev->fp_array), GFP_KERNEL);
  1951. if (!edev->fp_array) {
  1952. DP_NOTICE(edev, "fp array allocation failed\n");
  1953. goto err;
  1954. }
  1955. for_each_rss(i) {
  1956. fp = &edev->fp_array[i];
  1957. fp->sb_info = kcalloc(1, sizeof(*fp->sb_info), GFP_KERNEL);
  1958. if (!fp->sb_info) {
  1959. DP_NOTICE(edev, "sb info struct allocation failed\n");
  1960. goto err;
  1961. }
  1962. fp->rxq = kcalloc(1, sizeof(*fp->rxq), GFP_KERNEL);
  1963. if (!fp->rxq) {
  1964. DP_NOTICE(edev, "RXQ struct allocation failed\n");
  1965. goto err;
  1966. }
  1967. fp->txqs = kcalloc(edev->num_tc, sizeof(*fp->txqs), GFP_KERNEL);
  1968. if (!fp->txqs) {
  1969. DP_NOTICE(edev, "TXQ array allocation failed\n");
  1970. goto err;
  1971. }
  1972. }
  1973. return 0;
  1974. err:
  1975. qede_free_fp_array(edev);
  1976. return -ENOMEM;
  1977. }
  1978. static void qede_sp_task(struct work_struct *work)
  1979. {
  1980. struct qede_dev *edev = container_of(work, struct qede_dev,
  1981. sp_task.work);
  1982. struct qed_dev *cdev = edev->cdev;
  1983. mutex_lock(&edev->qede_lock);
  1984. if (edev->state == QEDE_STATE_OPEN) {
  1985. if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
  1986. qede_config_rx_mode(edev->ndev);
  1987. }
  1988. if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
  1989. struct qed_tunn_params tunn_params;
  1990. memset(&tunn_params, 0, sizeof(tunn_params));
  1991. tunn_params.update_vxlan_port = 1;
  1992. tunn_params.vxlan_port = edev->vxlan_dst_port;
  1993. qed_ops->tunn_config(cdev, &tunn_params);
  1994. }
  1995. if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
  1996. struct qed_tunn_params tunn_params;
  1997. memset(&tunn_params, 0, sizeof(tunn_params));
  1998. tunn_params.update_geneve_port = 1;
  1999. tunn_params.geneve_port = edev->geneve_dst_port;
  2000. qed_ops->tunn_config(cdev, &tunn_params);
  2001. }
  2002. mutex_unlock(&edev->qede_lock);
  2003. }
  2004. static void qede_update_pf_params(struct qed_dev *cdev)
  2005. {
  2006. struct qed_pf_params pf_params;
  2007. /* 64 rx + 64 tx */
  2008. memset(&pf_params, 0, sizeof(struct qed_pf_params));
  2009. pf_params.eth_pf_params.num_cons = 128;
  2010. qed_ops->common->update_pf_params(cdev, &pf_params);
  2011. }
  2012. enum qede_probe_mode {
  2013. QEDE_PROBE_NORMAL,
  2014. };
  2015. static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
  2016. bool is_vf, enum qede_probe_mode mode)
  2017. {
  2018. struct qed_probe_params probe_params;
  2019. struct qed_slowpath_params params;
  2020. struct qed_dev_eth_info dev_info;
  2021. struct qede_dev *edev;
  2022. struct qed_dev *cdev;
  2023. int rc;
  2024. if (unlikely(dp_level & QED_LEVEL_INFO))
  2025. pr_notice("Starting qede probe\n");
  2026. memset(&probe_params, 0, sizeof(probe_params));
  2027. probe_params.protocol = QED_PROTOCOL_ETH;
  2028. probe_params.dp_module = dp_module;
  2029. probe_params.dp_level = dp_level;
  2030. probe_params.is_vf = is_vf;
  2031. cdev = qed_ops->common->probe(pdev, &probe_params);
  2032. if (!cdev) {
  2033. rc = -ENODEV;
  2034. goto err0;
  2035. }
  2036. qede_update_pf_params(cdev);
  2037. /* Start the Slowpath-process */
  2038. memset(&params, 0, sizeof(struct qed_slowpath_params));
  2039. params.int_mode = QED_INT_MODE_MSIX;
  2040. params.drv_major = QEDE_MAJOR_VERSION;
  2041. params.drv_minor = QEDE_MINOR_VERSION;
  2042. params.drv_rev = QEDE_REVISION_VERSION;
  2043. params.drv_eng = QEDE_ENGINEERING_VERSION;
  2044. strlcpy(params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
  2045. rc = qed_ops->common->slowpath_start(cdev, &params);
  2046. if (rc) {
  2047. pr_notice("Cannot start slowpath\n");
  2048. goto err1;
  2049. }
  2050. /* Learn information crucial for qede to progress */
  2051. rc = qed_ops->fill_dev_info(cdev, &dev_info);
  2052. if (rc)
  2053. goto err2;
  2054. edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
  2055. dp_level);
  2056. if (!edev) {
  2057. rc = -ENOMEM;
  2058. goto err2;
  2059. }
  2060. if (is_vf)
  2061. edev->flags |= QEDE_FLAG_IS_VF;
  2062. qede_init_ndev(edev);
  2063. rc = register_netdev(edev->ndev);
  2064. if (rc) {
  2065. DP_NOTICE(edev, "Cannot register net-device\n");
  2066. goto err3;
  2067. }
  2068. edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
  2069. edev->ops->register_ops(cdev, &qede_ll_ops, edev);
  2070. #ifdef CONFIG_DCB
  2071. qede_set_dcbnl_ops(edev->ndev);
  2072. #endif
  2073. INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
  2074. mutex_init(&edev->qede_lock);
  2075. edev->rx_copybreak = QEDE_RX_HDR_SIZE;
  2076. DP_INFO(edev, "Ending successfully qede probe\n");
  2077. return 0;
  2078. err3:
  2079. free_netdev(edev->ndev);
  2080. err2:
  2081. qed_ops->common->slowpath_stop(cdev);
  2082. err1:
  2083. qed_ops->common->remove(cdev);
  2084. err0:
  2085. return rc;
  2086. }
  2087. static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  2088. {
  2089. bool is_vf = false;
  2090. u32 dp_module = 0;
  2091. u8 dp_level = 0;
  2092. switch ((enum qede_pci_private)id->driver_data) {
  2093. case QEDE_PRIVATE_VF:
  2094. if (debug & QED_LOG_VERBOSE_MASK)
  2095. dev_err(&pdev->dev, "Probing a VF\n");
  2096. is_vf = true;
  2097. break;
  2098. default:
  2099. if (debug & QED_LOG_VERBOSE_MASK)
  2100. dev_err(&pdev->dev, "Probing a PF\n");
  2101. }
  2102. qede_config_debug(debug, &dp_module, &dp_level);
  2103. return __qede_probe(pdev, dp_module, dp_level, is_vf,
  2104. QEDE_PROBE_NORMAL);
  2105. }
  2106. enum qede_remove_mode {
  2107. QEDE_REMOVE_NORMAL,
  2108. };
  2109. static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
  2110. {
  2111. struct net_device *ndev = pci_get_drvdata(pdev);
  2112. struct qede_dev *edev = netdev_priv(ndev);
  2113. struct qed_dev *cdev = edev->cdev;
  2114. DP_INFO(edev, "Starting qede_remove\n");
  2115. cancel_delayed_work_sync(&edev->sp_task);
  2116. unregister_netdev(ndev);
  2117. edev->ops->common->set_power_state(cdev, PCI_D0);
  2118. pci_set_drvdata(pdev, NULL);
  2119. free_netdev(ndev);
  2120. /* Use global ops since we've freed edev */
  2121. qed_ops->common->slowpath_stop(cdev);
  2122. qed_ops->common->remove(cdev);
  2123. pr_notice("Ending successfully qede_remove\n");
  2124. }
  2125. static void qede_remove(struct pci_dev *pdev)
  2126. {
  2127. __qede_remove(pdev, QEDE_REMOVE_NORMAL);
  2128. }
  2129. /* -------------------------------------------------------------------------
  2130. * START OF LOAD / UNLOAD
  2131. * -------------------------------------------------------------------------
  2132. */
  2133. static int qede_set_num_queues(struct qede_dev *edev)
  2134. {
  2135. int rc;
  2136. u16 rss_num;
  2137. /* Setup queues according to possible resources*/
  2138. if (edev->req_rss)
  2139. rss_num = edev->req_rss;
  2140. else
  2141. rss_num = netif_get_num_default_rss_queues() *
  2142. edev->dev_info.common.num_hwfns;
  2143. rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
  2144. rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
  2145. if (rc > 0) {
  2146. /* Managed to request interrupts for our queues */
  2147. edev->num_rss = rc;
  2148. DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
  2149. QEDE_RSS_CNT(edev), rss_num);
  2150. rc = 0;
  2151. }
  2152. return rc;
  2153. }
  2154. static void qede_free_mem_sb(struct qede_dev *edev,
  2155. struct qed_sb_info *sb_info)
  2156. {
  2157. if (sb_info->sb_virt)
  2158. dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
  2159. (void *)sb_info->sb_virt, sb_info->sb_phys);
  2160. }
  2161. /* This function allocates fast-path status block memory */
  2162. static int qede_alloc_mem_sb(struct qede_dev *edev,
  2163. struct qed_sb_info *sb_info,
  2164. u16 sb_id)
  2165. {
  2166. struct status_block *sb_virt;
  2167. dma_addr_t sb_phys;
  2168. int rc;
  2169. sb_virt = dma_alloc_coherent(&edev->pdev->dev,
  2170. sizeof(*sb_virt),
  2171. &sb_phys, GFP_KERNEL);
  2172. if (!sb_virt) {
  2173. DP_ERR(edev, "Status block allocation failed\n");
  2174. return -ENOMEM;
  2175. }
  2176. rc = edev->ops->common->sb_init(edev->cdev, sb_info,
  2177. sb_virt, sb_phys, sb_id,
  2178. QED_SB_TYPE_L2_QUEUE);
  2179. if (rc) {
  2180. DP_ERR(edev, "Status block initialization failed\n");
  2181. dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
  2182. sb_virt, sb_phys);
  2183. return rc;
  2184. }
  2185. return 0;
  2186. }
  2187. static void qede_free_rx_buffers(struct qede_dev *edev,
  2188. struct qede_rx_queue *rxq)
  2189. {
  2190. u16 i;
  2191. for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
  2192. struct sw_rx_data *rx_buf;
  2193. struct page *data;
  2194. rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
  2195. data = rx_buf->data;
  2196. dma_unmap_page(&edev->pdev->dev,
  2197. rx_buf->mapping,
  2198. PAGE_SIZE, DMA_FROM_DEVICE);
  2199. rx_buf->data = NULL;
  2200. __free_page(data);
  2201. }
  2202. }
  2203. static void qede_free_sge_mem(struct qede_dev *edev,
  2204. struct qede_rx_queue *rxq) {
  2205. int i;
  2206. if (edev->gro_disable)
  2207. return;
  2208. for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
  2209. struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
  2210. struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
  2211. if (replace_buf->data) {
  2212. dma_unmap_page(&edev->pdev->dev,
  2213. replace_buf->mapping,
  2214. PAGE_SIZE, DMA_FROM_DEVICE);
  2215. __free_page(replace_buf->data);
  2216. }
  2217. }
  2218. }
  2219. static void qede_free_mem_rxq(struct qede_dev *edev,
  2220. struct qede_rx_queue *rxq)
  2221. {
  2222. qede_free_sge_mem(edev, rxq);
  2223. /* Free rx buffers */
  2224. qede_free_rx_buffers(edev, rxq);
  2225. /* Free the parallel SW ring */
  2226. kfree(rxq->sw_rx_ring);
  2227. /* Free the real RQ ring used by FW */
  2228. edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
  2229. edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
  2230. }
  2231. static int qede_alloc_rx_buffer(struct qede_dev *edev,
  2232. struct qede_rx_queue *rxq)
  2233. {
  2234. struct sw_rx_data *sw_rx_data;
  2235. struct eth_rx_bd *rx_bd;
  2236. dma_addr_t mapping;
  2237. struct page *data;
  2238. u16 rx_buf_size;
  2239. rx_buf_size = rxq->rx_buf_size;
  2240. data = alloc_pages(GFP_ATOMIC, 0);
  2241. if (unlikely(!data)) {
  2242. DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
  2243. return -ENOMEM;
  2244. }
  2245. /* Map the entire page as it would be used
  2246. * for multiple RX buffer segment size mapping.
  2247. */
  2248. mapping = dma_map_page(&edev->pdev->dev, data, 0,
  2249. PAGE_SIZE, DMA_FROM_DEVICE);
  2250. if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
  2251. __free_page(data);
  2252. DP_NOTICE(edev, "Failed to map Rx buffer\n");
  2253. return -ENOMEM;
  2254. }
  2255. sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
  2256. sw_rx_data->page_offset = 0;
  2257. sw_rx_data->data = data;
  2258. sw_rx_data->mapping = mapping;
  2259. /* Advance PROD and get BD pointer */
  2260. rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
  2261. WARN_ON(!rx_bd);
  2262. rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
  2263. rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
  2264. rxq->sw_rx_prod++;
  2265. return 0;
  2266. }
  2267. static int qede_alloc_sge_mem(struct qede_dev *edev,
  2268. struct qede_rx_queue *rxq)
  2269. {
  2270. dma_addr_t mapping;
  2271. int i;
  2272. if (edev->gro_disable)
  2273. return 0;
  2274. if (edev->ndev->mtu > PAGE_SIZE) {
  2275. edev->gro_disable = 1;
  2276. return 0;
  2277. }
  2278. for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
  2279. struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
  2280. struct sw_rx_data *replace_buf = &tpa_info->replace_buf;
  2281. replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
  2282. if (unlikely(!replace_buf->data)) {
  2283. DP_NOTICE(edev,
  2284. "Failed to allocate TPA skb pool [replacement buffer]\n");
  2285. goto err;
  2286. }
  2287. mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
  2288. rxq->rx_buf_size, DMA_FROM_DEVICE);
  2289. if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
  2290. DP_NOTICE(edev,
  2291. "Failed to map TPA replacement buffer\n");
  2292. goto err;
  2293. }
  2294. replace_buf->mapping = mapping;
  2295. tpa_info->replace_buf.page_offset = 0;
  2296. tpa_info->replace_buf_mapping = mapping;
  2297. tpa_info->agg_state = QEDE_AGG_STATE_NONE;
  2298. }
  2299. return 0;
  2300. err:
  2301. qede_free_sge_mem(edev, rxq);
  2302. edev->gro_disable = 1;
  2303. return -ENOMEM;
  2304. }
  2305. /* This function allocates all memory needed per Rx queue */
  2306. static int qede_alloc_mem_rxq(struct qede_dev *edev,
  2307. struct qede_rx_queue *rxq)
  2308. {
  2309. int i, rc, size;
  2310. rxq->num_rx_buffers = edev->q_num_rx_buffers;
  2311. rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD +
  2312. edev->ndev->mtu;
  2313. if (rxq->rx_buf_size > PAGE_SIZE)
  2314. rxq->rx_buf_size = PAGE_SIZE;
  2315. /* Segment size to spilt a page in multiple equal parts */
  2316. rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
  2317. /* Allocate the parallel driver ring for Rx buffers */
  2318. size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
  2319. rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
  2320. if (!rxq->sw_rx_ring) {
  2321. DP_ERR(edev, "Rx buffers ring allocation failed\n");
  2322. rc = -ENOMEM;
  2323. goto err;
  2324. }
  2325. /* Allocate FW Rx ring */
  2326. rc = edev->ops->common->chain_alloc(edev->cdev,
  2327. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  2328. QED_CHAIN_MODE_NEXT_PTR,
  2329. QED_CHAIN_CNT_TYPE_U16,
  2330. RX_RING_SIZE,
  2331. sizeof(struct eth_rx_bd),
  2332. &rxq->rx_bd_ring);
  2333. if (rc)
  2334. goto err;
  2335. /* Allocate FW completion ring */
  2336. rc = edev->ops->common->chain_alloc(edev->cdev,
  2337. QED_CHAIN_USE_TO_CONSUME,
  2338. QED_CHAIN_MODE_PBL,
  2339. QED_CHAIN_CNT_TYPE_U16,
  2340. RX_RING_SIZE,
  2341. sizeof(union eth_rx_cqe),
  2342. &rxq->rx_comp_ring);
  2343. if (rc)
  2344. goto err;
  2345. /* Allocate buffers for the Rx ring */
  2346. for (i = 0; i < rxq->num_rx_buffers; i++) {
  2347. rc = qede_alloc_rx_buffer(edev, rxq);
  2348. if (rc) {
  2349. DP_ERR(edev,
  2350. "Rx buffers allocation failed at index %d\n", i);
  2351. goto err;
  2352. }
  2353. }
  2354. rc = qede_alloc_sge_mem(edev, rxq);
  2355. err:
  2356. return rc;
  2357. }
  2358. static void qede_free_mem_txq(struct qede_dev *edev,
  2359. struct qede_tx_queue *txq)
  2360. {
  2361. /* Free the parallel SW ring */
  2362. kfree(txq->sw_tx_ring);
  2363. /* Free the real RQ ring used by FW */
  2364. edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
  2365. }
  2366. /* This function allocates all memory needed per Tx queue */
  2367. static int qede_alloc_mem_txq(struct qede_dev *edev,
  2368. struct qede_tx_queue *txq)
  2369. {
  2370. int size, rc;
  2371. union eth_tx_bd_types *p_virt;
  2372. txq->num_tx_buffers = edev->q_num_tx_buffers;
  2373. /* Allocate the parallel driver ring for Tx buffers */
  2374. size = sizeof(*txq->sw_tx_ring) * NUM_TX_BDS_MAX;
  2375. txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
  2376. if (!txq->sw_tx_ring) {
  2377. DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
  2378. goto err;
  2379. }
  2380. rc = edev->ops->common->chain_alloc(edev->cdev,
  2381. QED_CHAIN_USE_TO_CONSUME_PRODUCE,
  2382. QED_CHAIN_MODE_PBL,
  2383. QED_CHAIN_CNT_TYPE_U16,
  2384. NUM_TX_BDS_MAX,
  2385. sizeof(*p_virt), &txq->tx_pbl);
  2386. if (rc)
  2387. goto err;
  2388. return 0;
  2389. err:
  2390. qede_free_mem_txq(edev, txq);
  2391. return -ENOMEM;
  2392. }
  2393. /* This function frees all memory of a single fp */
  2394. static void qede_free_mem_fp(struct qede_dev *edev,
  2395. struct qede_fastpath *fp)
  2396. {
  2397. int tc;
  2398. qede_free_mem_sb(edev, fp->sb_info);
  2399. qede_free_mem_rxq(edev, fp->rxq);
  2400. for (tc = 0; tc < edev->num_tc; tc++)
  2401. qede_free_mem_txq(edev, &fp->txqs[tc]);
  2402. }
  2403. /* This function allocates all memory needed for a single fp (i.e. an entity
  2404. * which contains status block, one rx queue and multiple per-TC tx queues.
  2405. */
  2406. static int qede_alloc_mem_fp(struct qede_dev *edev,
  2407. struct qede_fastpath *fp)
  2408. {
  2409. int rc, tc;
  2410. rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->rss_id);
  2411. if (rc)
  2412. goto err;
  2413. rc = qede_alloc_mem_rxq(edev, fp->rxq);
  2414. if (rc)
  2415. goto err;
  2416. for (tc = 0; tc < edev->num_tc; tc++) {
  2417. rc = qede_alloc_mem_txq(edev, &fp->txqs[tc]);
  2418. if (rc)
  2419. goto err;
  2420. }
  2421. return 0;
  2422. err:
  2423. return rc;
  2424. }
  2425. static void qede_free_mem_load(struct qede_dev *edev)
  2426. {
  2427. int i;
  2428. for_each_rss(i) {
  2429. struct qede_fastpath *fp = &edev->fp_array[i];
  2430. qede_free_mem_fp(edev, fp);
  2431. }
  2432. }
  2433. /* This function allocates all qede memory at NIC load. */
  2434. static int qede_alloc_mem_load(struct qede_dev *edev)
  2435. {
  2436. int rc = 0, rss_id;
  2437. for (rss_id = 0; rss_id < QEDE_RSS_CNT(edev); rss_id++) {
  2438. struct qede_fastpath *fp = &edev->fp_array[rss_id];
  2439. rc = qede_alloc_mem_fp(edev, fp);
  2440. if (rc) {
  2441. DP_ERR(edev,
  2442. "Failed to allocate memory for fastpath - rss id = %d\n",
  2443. rss_id);
  2444. qede_free_mem_load(edev);
  2445. return rc;
  2446. }
  2447. }
  2448. return 0;
  2449. }
  2450. /* This function inits fp content and resets the SB, RXQ and TXQ structures */
  2451. static void qede_init_fp(struct qede_dev *edev)
  2452. {
  2453. int rss_id, txq_index, tc;
  2454. struct qede_fastpath *fp;
  2455. for_each_rss(rss_id) {
  2456. fp = &edev->fp_array[rss_id];
  2457. fp->edev = edev;
  2458. fp->rss_id = rss_id;
  2459. memset((void *)&fp->napi, 0, sizeof(fp->napi));
  2460. memset((void *)fp->sb_info, 0, sizeof(*fp->sb_info));
  2461. memset((void *)fp->rxq, 0, sizeof(*fp->rxq));
  2462. fp->rxq->rxq_id = rss_id;
  2463. memset((void *)fp->txqs, 0, (edev->num_tc * sizeof(*fp->txqs)));
  2464. for (tc = 0; tc < edev->num_tc; tc++) {
  2465. txq_index = tc * QEDE_RSS_CNT(edev) + rss_id;
  2466. fp->txqs[tc].index = txq_index;
  2467. }
  2468. snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
  2469. edev->ndev->name, rss_id);
  2470. }
  2471. edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
  2472. }
  2473. static int qede_set_real_num_queues(struct qede_dev *edev)
  2474. {
  2475. int rc = 0;
  2476. rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_CNT(edev));
  2477. if (rc) {
  2478. DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
  2479. return rc;
  2480. }
  2481. rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_CNT(edev));
  2482. if (rc) {
  2483. DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
  2484. return rc;
  2485. }
  2486. return 0;
  2487. }
  2488. static void qede_napi_disable_remove(struct qede_dev *edev)
  2489. {
  2490. int i;
  2491. for_each_rss(i) {
  2492. napi_disable(&edev->fp_array[i].napi);
  2493. netif_napi_del(&edev->fp_array[i].napi);
  2494. }
  2495. }
  2496. static void qede_napi_add_enable(struct qede_dev *edev)
  2497. {
  2498. int i;
  2499. /* Add NAPI objects */
  2500. for_each_rss(i) {
  2501. netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
  2502. qede_poll, NAPI_POLL_WEIGHT);
  2503. napi_enable(&edev->fp_array[i].napi);
  2504. }
  2505. }
  2506. static void qede_sync_free_irqs(struct qede_dev *edev)
  2507. {
  2508. int i;
  2509. for (i = 0; i < edev->int_info.used_cnt; i++) {
  2510. if (edev->int_info.msix_cnt) {
  2511. synchronize_irq(edev->int_info.msix[i].vector);
  2512. free_irq(edev->int_info.msix[i].vector,
  2513. &edev->fp_array[i]);
  2514. } else {
  2515. edev->ops->common->simd_handler_clean(edev->cdev, i);
  2516. }
  2517. }
  2518. edev->int_info.used_cnt = 0;
  2519. }
  2520. static int qede_req_msix_irqs(struct qede_dev *edev)
  2521. {
  2522. int i, rc;
  2523. /* Sanitize number of interrupts == number of prepared RSS queues */
  2524. if (QEDE_RSS_CNT(edev) > edev->int_info.msix_cnt) {
  2525. DP_ERR(edev,
  2526. "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
  2527. QEDE_RSS_CNT(edev), edev->int_info.msix_cnt);
  2528. return -EINVAL;
  2529. }
  2530. for (i = 0; i < QEDE_RSS_CNT(edev); i++) {
  2531. rc = request_irq(edev->int_info.msix[i].vector,
  2532. qede_msix_fp_int, 0, edev->fp_array[i].name,
  2533. &edev->fp_array[i]);
  2534. if (rc) {
  2535. DP_ERR(edev, "Request fp %d irq failed\n", i);
  2536. qede_sync_free_irqs(edev);
  2537. return rc;
  2538. }
  2539. DP_VERBOSE(edev, NETIF_MSG_INTR,
  2540. "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
  2541. edev->fp_array[i].name, i,
  2542. &edev->fp_array[i]);
  2543. edev->int_info.used_cnt++;
  2544. }
  2545. return 0;
  2546. }
  2547. static void qede_simd_fp_handler(void *cookie)
  2548. {
  2549. struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
  2550. napi_schedule_irqoff(&fp->napi);
  2551. }
  2552. static int qede_setup_irqs(struct qede_dev *edev)
  2553. {
  2554. int i, rc = 0;
  2555. /* Learn Interrupt configuration */
  2556. rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
  2557. if (rc)
  2558. return rc;
  2559. if (edev->int_info.msix_cnt) {
  2560. rc = qede_req_msix_irqs(edev);
  2561. if (rc)
  2562. return rc;
  2563. edev->ndev->irq = edev->int_info.msix[0].vector;
  2564. } else {
  2565. const struct qed_common_ops *ops;
  2566. /* qed should learn receive the RSS ids and callbacks */
  2567. ops = edev->ops->common;
  2568. for (i = 0; i < QEDE_RSS_CNT(edev); i++)
  2569. ops->simd_handler_config(edev->cdev,
  2570. &edev->fp_array[i], i,
  2571. qede_simd_fp_handler);
  2572. edev->int_info.used_cnt = QEDE_RSS_CNT(edev);
  2573. }
  2574. return 0;
  2575. }
  2576. static int qede_drain_txq(struct qede_dev *edev,
  2577. struct qede_tx_queue *txq,
  2578. bool allow_drain)
  2579. {
  2580. int rc, cnt = 1000;
  2581. while (txq->sw_tx_cons != txq->sw_tx_prod) {
  2582. if (!cnt) {
  2583. if (allow_drain) {
  2584. DP_NOTICE(edev,
  2585. "Tx queue[%d] is stuck, requesting MCP to drain\n",
  2586. txq->index);
  2587. rc = edev->ops->common->drain(edev->cdev);
  2588. if (rc)
  2589. return rc;
  2590. return qede_drain_txq(edev, txq, false);
  2591. }
  2592. DP_NOTICE(edev,
  2593. "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
  2594. txq->index, txq->sw_tx_prod,
  2595. txq->sw_tx_cons);
  2596. return -ENODEV;
  2597. }
  2598. cnt--;
  2599. usleep_range(1000, 2000);
  2600. barrier();
  2601. }
  2602. /* FW finished processing, wait for HW to transmit all tx packets */
  2603. usleep_range(1000, 2000);
  2604. return 0;
  2605. }
  2606. static int qede_stop_queues(struct qede_dev *edev)
  2607. {
  2608. struct qed_update_vport_params vport_update_params;
  2609. struct qed_dev *cdev = edev->cdev;
  2610. int rc, tc, i;
  2611. /* Disable the vport */
  2612. memset(&vport_update_params, 0, sizeof(vport_update_params));
  2613. vport_update_params.vport_id = 0;
  2614. vport_update_params.update_vport_active_flg = 1;
  2615. vport_update_params.vport_active_flg = 0;
  2616. vport_update_params.update_rss_flg = 0;
  2617. rc = edev->ops->vport_update(cdev, &vport_update_params);
  2618. if (rc) {
  2619. DP_ERR(edev, "Failed to update vport\n");
  2620. return rc;
  2621. }
  2622. /* Flush Tx queues. If needed, request drain from MCP */
  2623. for_each_rss(i) {
  2624. struct qede_fastpath *fp = &edev->fp_array[i];
  2625. for (tc = 0; tc < edev->num_tc; tc++) {
  2626. struct qede_tx_queue *txq = &fp->txqs[tc];
  2627. rc = qede_drain_txq(edev, txq, true);
  2628. if (rc)
  2629. return rc;
  2630. }
  2631. }
  2632. /* Stop all Queues in reverse order*/
  2633. for (i = QEDE_RSS_CNT(edev) - 1; i >= 0; i--) {
  2634. struct qed_stop_rxq_params rx_params;
  2635. /* Stop the Tx Queue(s)*/
  2636. for (tc = 0; tc < edev->num_tc; tc++) {
  2637. struct qed_stop_txq_params tx_params;
  2638. tx_params.rss_id = i;
  2639. tx_params.tx_queue_id = tc * QEDE_RSS_CNT(edev) + i;
  2640. rc = edev->ops->q_tx_stop(cdev, &tx_params);
  2641. if (rc) {
  2642. DP_ERR(edev, "Failed to stop TXQ #%d\n",
  2643. tx_params.tx_queue_id);
  2644. return rc;
  2645. }
  2646. }
  2647. /* Stop the Rx Queue*/
  2648. memset(&rx_params, 0, sizeof(rx_params));
  2649. rx_params.rss_id = i;
  2650. rx_params.rx_queue_id = i;
  2651. rc = edev->ops->q_rx_stop(cdev, &rx_params);
  2652. if (rc) {
  2653. DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
  2654. return rc;
  2655. }
  2656. }
  2657. /* Stop the vport */
  2658. rc = edev->ops->vport_stop(cdev, 0);
  2659. if (rc)
  2660. DP_ERR(edev, "Failed to stop VPORT\n");
  2661. return rc;
  2662. }
  2663. static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
  2664. {
  2665. int rc, tc, i;
  2666. int vlan_removal_en = 1;
  2667. struct qed_dev *cdev = edev->cdev;
  2668. struct qed_update_vport_params vport_update_params;
  2669. struct qed_queue_start_common_params q_params;
  2670. struct qed_dev_info *qed_info = &edev->dev_info.common;
  2671. struct qed_start_vport_params start = {0};
  2672. bool reset_rss_indir = false;
  2673. if (!edev->num_rss) {
  2674. DP_ERR(edev,
  2675. "Cannot update V-VPORT as active as there are no Rx queues\n");
  2676. return -EINVAL;
  2677. }
  2678. start.gro_enable = !edev->gro_disable;
  2679. start.mtu = edev->ndev->mtu;
  2680. start.vport_id = 0;
  2681. start.drop_ttl0 = true;
  2682. start.remove_inner_vlan = vlan_removal_en;
  2683. start.clear_stats = clear_stats;
  2684. rc = edev->ops->vport_start(cdev, &start);
  2685. if (rc) {
  2686. DP_ERR(edev, "Start V-PORT failed %d\n", rc);
  2687. return rc;
  2688. }
  2689. DP_VERBOSE(edev, NETIF_MSG_IFUP,
  2690. "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
  2691. start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
  2692. for_each_rss(i) {
  2693. struct qede_fastpath *fp = &edev->fp_array[i];
  2694. dma_addr_t phys_table = fp->rxq->rx_comp_ring.pbl.p_phys_table;
  2695. memset(&q_params, 0, sizeof(q_params));
  2696. q_params.rss_id = i;
  2697. q_params.queue_id = i;
  2698. q_params.vport_id = 0;
  2699. q_params.sb = fp->sb_info->igu_sb_id;
  2700. q_params.sb_idx = RX_PI;
  2701. rc = edev->ops->q_rx_start(cdev, &q_params,
  2702. fp->rxq->rx_buf_size,
  2703. fp->rxq->rx_bd_ring.p_phys_addr,
  2704. phys_table,
  2705. fp->rxq->rx_comp_ring.page_cnt,
  2706. &fp->rxq->hw_rxq_prod_addr);
  2707. if (rc) {
  2708. DP_ERR(edev, "Start RXQ #%d failed %d\n", i, rc);
  2709. return rc;
  2710. }
  2711. fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
  2712. qede_update_rx_prod(edev, fp->rxq);
  2713. for (tc = 0; tc < edev->num_tc; tc++) {
  2714. struct qede_tx_queue *txq = &fp->txqs[tc];
  2715. int txq_index = tc * QEDE_RSS_CNT(edev) + i;
  2716. memset(&q_params, 0, sizeof(q_params));
  2717. q_params.rss_id = i;
  2718. q_params.queue_id = txq_index;
  2719. q_params.vport_id = 0;
  2720. q_params.sb = fp->sb_info->igu_sb_id;
  2721. q_params.sb_idx = TX_PI(tc);
  2722. rc = edev->ops->q_tx_start(cdev, &q_params,
  2723. txq->tx_pbl.pbl.p_phys_table,
  2724. txq->tx_pbl.page_cnt,
  2725. &txq->doorbell_addr);
  2726. if (rc) {
  2727. DP_ERR(edev, "Start TXQ #%d failed %d\n",
  2728. txq_index, rc);
  2729. return rc;
  2730. }
  2731. txq->hw_cons_ptr =
  2732. &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
  2733. SET_FIELD(txq->tx_db.data.params,
  2734. ETH_DB_DATA_DEST, DB_DEST_XCM);
  2735. SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
  2736. DB_AGG_CMD_SET);
  2737. SET_FIELD(txq->tx_db.data.params,
  2738. ETH_DB_DATA_AGG_VAL_SEL,
  2739. DQ_XCM_ETH_TX_BD_PROD_CMD);
  2740. txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
  2741. }
  2742. }
  2743. /* Prepare and send the vport enable */
  2744. memset(&vport_update_params, 0, sizeof(vport_update_params));
  2745. vport_update_params.vport_id = start.vport_id;
  2746. vport_update_params.update_vport_active_flg = 1;
  2747. vport_update_params.vport_active_flg = 1;
  2748. if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
  2749. qed_info->tx_switching) {
  2750. vport_update_params.update_tx_switching_flg = 1;
  2751. vport_update_params.tx_switching_flg = 1;
  2752. }
  2753. /* Fill struct with RSS params */
  2754. if (QEDE_RSS_CNT(edev) > 1) {
  2755. vport_update_params.update_rss_flg = 1;
  2756. /* Need to validate current RSS config uses valid entries */
  2757. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  2758. if (edev->rss_params.rss_ind_table[i] >=
  2759. edev->num_rss) {
  2760. reset_rss_indir = true;
  2761. break;
  2762. }
  2763. }
  2764. if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
  2765. reset_rss_indir) {
  2766. u16 val;
  2767. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  2768. u16 indir_val;
  2769. val = QEDE_RSS_CNT(edev);
  2770. indir_val = ethtool_rxfh_indir_default(i, val);
  2771. edev->rss_params.rss_ind_table[i] = indir_val;
  2772. }
  2773. edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
  2774. }
  2775. if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
  2776. netdev_rss_key_fill(edev->rss_params.rss_key,
  2777. sizeof(edev->rss_params.rss_key));
  2778. edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
  2779. }
  2780. if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
  2781. edev->rss_params.rss_caps = QED_RSS_IPV4 |
  2782. QED_RSS_IPV6 |
  2783. QED_RSS_IPV4_TCP |
  2784. QED_RSS_IPV6_TCP;
  2785. edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
  2786. }
  2787. memcpy(&vport_update_params.rss_params, &edev->rss_params,
  2788. sizeof(vport_update_params.rss_params));
  2789. } else {
  2790. memset(&vport_update_params.rss_params, 0,
  2791. sizeof(vport_update_params.rss_params));
  2792. }
  2793. rc = edev->ops->vport_update(cdev, &vport_update_params);
  2794. if (rc) {
  2795. DP_ERR(edev, "Update V-PORT failed %d\n", rc);
  2796. return rc;
  2797. }
  2798. return 0;
  2799. }
  2800. static int qede_set_mcast_rx_mac(struct qede_dev *edev,
  2801. enum qed_filter_xcast_params_type opcode,
  2802. unsigned char *mac, int num_macs)
  2803. {
  2804. struct qed_filter_params filter_cmd;
  2805. int i;
  2806. memset(&filter_cmd, 0, sizeof(filter_cmd));
  2807. filter_cmd.type = QED_FILTER_TYPE_MCAST;
  2808. filter_cmd.filter.mcast.type = opcode;
  2809. filter_cmd.filter.mcast.num = num_macs;
  2810. for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
  2811. ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
  2812. return edev->ops->filter_config(edev->cdev, &filter_cmd);
  2813. }
  2814. enum qede_unload_mode {
  2815. QEDE_UNLOAD_NORMAL,
  2816. };
  2817. static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
  2818. {
  2819. struct qed_link_params link_params;
  2820. int rc;
  2821. DP_INFO(edev, "Starting qede unload\n");
  2822. mutex_lock(&edev->qede_lock);
  2823. edev->state = QEDE_STATE_CLOSED;
  2824. /* Close OS Tx */
  2825. netif_tx_disable(edev->ndev);
  2826. netif_carrier_off(edev->ndev);
  2827. /* Reset the link */
  2828. memset(&link_params, 0, sizeof(link_params));
  2829. link_params.link_up = false;
  2830. edev->ops->common->set_link(edev->cdev, &link_params);
  2831. rc = qede_stop_queues(edev);
  2832. if (rc) {
  2833. qede_sync_free_irqs(edev);
  2834. goto out;
  2835. }
  2836. DP_INFO(edev, "Stopped Queues\n");
  2837. qede_vlan_mark_nonconfigured(edev);
  2838. edev->ops->fastpath_stop(edev->cdev);
  2839. /* Release the interrupts */
  2840. qede_sync_free_irqs(edev);
  2841. edev->ops->common->set_fp_int(edev->cdev, 0);
  2842. qede_napi_disable_remove(edev);
  2843. qede_free_mem_load(edev);
  2844. qede_free_fp_array(edev);
  2845. out:
  2846. mutex_unlock(&edev->qede_lock);
  2847. DP_INFO(edev, "Ending qede unload\n");
  2848. }
  2849. enum qede_load_mode {
  2850. QEDE_LOAD_NORMAL,
  2851. QEDE_LOAD_RELOAD,
  2852. };
  2853. static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
  2854. {
  2855. struct qed_link_params link_params;
  2856. struct qed_link_output link_output;
  2857. int rc;
  2858. DP_INFO(edev, "Starting qede load\n");
  2859. rc = qede_set_num_queues(edev);
  2860. if (rc)
  2861. goto err0;
  2862. rc = qede_alloc_fp_array(edev);
  2863. if (rc)
  2864. goto err0;
  2865. qede_init_fp(edev);
  2866. rc = qede_alloc_mem_load(edev);
  2867. if (rc)
  2868. goto err1;
  2869. DP_INFO(edev, "Allocated %d RSS queues on %d TC/s\n",
  2870. QEDE_RSS_CNT(edev), edev->num_tc);
  2871. rc = qede_set_real_num_queues(edev);
  2872. if (rc)
  2873. goto err2;
  2874. qede_napi_add_enable(edev);
  2875. DP_INFO(edev, "Napi added and enabled\n");
  2876. rc = qede_setup_irqs(edev);
  2877. if (rc)
  2878. goto err3;
  2879. DP_INFO(edev, "Setup IRQs succeeded\n");
  2880. rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
  2881. if (rc)
  2882. goto err4;
  2883. DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
  2884. /* Add primary mac and set Rx filters */
  2885. ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
  2886. mutex_lock(&edev->qede_lock);
  2887. edev->state = QEDE_STATE_OPEN;
  2888. mutex_unlock(&edev->qede_lock);
  2889. /* Program un-configured VLANs */
  2890. qede_configure_vlan_filters(edev);
  2891. /* Ask for link-up using current configuration */
  2892. memset(&link_params, 0, sizeof(link_params));
  2893. link_params.link_up = true;
  2894. edev->ops->common->set_link(edev->cdev, &link_params);
  2895. /* Query whether link is already-up */
  2896. memset(&link_output, 0, sizeof(link_output));
  2897. edev->ops->common->get_link(edev->cdev, &link_output);
  2898. qede_link_update(edev, &link_output);
  2899. DP_INFO(edev, "Ending successfully qede load\n");
  2900. return 0;
  2901. err4:
  2902. qede_sync_free_irqs(edev);
  2903. memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
  2904. err3:
  2905. qede_napi_disable_remove(edev);
  2906. err2:
  2907. qede_free_mem_load(edev);
  2908. err1:
  2909. edev->ops->common->set_fp_int(edev->cdev, 0);
  2910. qede_free_fp_array(edev);
  2911. edev->num_rss = 0;
  2912. err0:
  2913. return rc;
  2914. }
  2915. void qede_reload(struct qede_dev *edev,
  2916. void (*func)(struct qede_dev *, union qede_reload_args *),
  2917. union qede_reload_args *args)
  2918. {
  2919. qede_unload(edev, QEDE_UNLOAD_NORMAL);
  2920. /* Call function handler to update parameters
  2921. * needed for function load.
  2922. */
  2923. if (func)
  2924. func(edev, args);
  2925. qede_load(edev, QEDE_LOAD_RELOAD);
  2926. mutex_lock(&edev->qede_lock);
  2927. qede_config_rx_mode(edev->ndev);
  2928. mutex_unlock(&edev->qede_lock);
  2929. }
  2930. /* called with rtnl_lock */
  2931. static int qede_open(struct net_device *ndev)
  2932. {
  2933. struct qede_dev *edev = netdev_priv(ndev);
  2934. int rc;
  2935. netif_carrier_off(ndev);
  2936. edev->ops->common->set_power_state(edev->cdev, PCI_D0);
  2937. rc = qede_load(edev, QEDE_LOAD_NORMAL);
  2938. if (rc)
  2939. return rc;
  2940. udp_tunnel_get_rx_info(ndev);
  2941. return 0;
  2942. }
  2943. static int qede_close(struct net_device *ndev)
  2944. {
  2945. struct qede_dev *edev = netdev_priv(ndev);
  2946. qede_unload(edev, QEDE_UNLOAD_NORMAL);
  2947. return 0;
  2948. }
  2949. static void qede_link_update(void *dev, struct qed_link_output *link)
  2950. {
  2951. struct qede_dev *edev = dev;
  2952. if (!netif_running(edev->ndev)) {
  2953. DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
  2954. return;
  2955. }
  2956. if (link->link_up) {
  2957. if (!netif_carrier_ok(edev->ndev)) {
  2958. DP_NOTICE(edev, "Link is up\n");
  2959. netif_tx_start_all_queues(edev->ndev);
  2960. netif_carrier_on(edev->ndev);
  2961. }
  2962. } else {
  2963. if (netif_carrier_ok(edev->ndev)) {
  2964. DP_NOTICE(edev, "Link is down\n");
  2965. netif_tx_disable(edev->ndev);
  2966. netif_carrier_off(edev->ndev);
  2967. }
  2968. }
  2969. }
  2970. static int qede_set_mac_addr(struct net_device *ndev, void *p)
  2971. {
  2972. struct qede_dev *edev = netdev_priv(ndev);
  2973. struct sockaddr *addr = p;
  2974. int rc;
  2975. ASSERT_RTNL(); /* @@@TBD To be removed */
  2976. DP_INFO(edev, "Set_mac_addr called\n");
  2977. if (!is_valid_ether_addr(addr->sa_data)) {
  2978. DP_NOTICE(edev, "The MAC address is not valid\n");
  2979. return -EFAULT;
  2980. }
  2981. if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
  2982. DP_NOTICE(edev, "qed prevents setting MAC\n");
  2983. return -EINVAL;
  2984. }
  2985. ether_addr_copy(ndev->dev_addr, addr->sa_data);
  2986. if (!netif_running(ndev)) {
  2987. DP_NOTICE(edev, "The device is currently down\n");
  2988. return 0;
  2989. }
  2990. /* Remove the previous primary mac */
  2991. rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
  2992. edev->primary_mac);
  2993. if (rc)
  2994. return rc;
  2995. /* Add MAC filter according to the new unicast HW MAC address */
  2996. ether_addr_copy(edev->primary_mac, ndev->dev_addr);
  2997. return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
  2998. edev->primary_mac);
  2999. }
  3000. static int
  3001. qede_configure_mcast_filtering(struct net_device *ndev,
  3002. enum qed_filter_rx_mode_type *accept_flags)
  3003. {
  3004. struct qede_dev *edev = netdev_priv(ndev);
  3005. unsigned char *mc_macs, *temp;
  3006. struct netdev_hw_addr *ha;
  3007. int rc = 0, mc_count;
  3008. size_t size;
  3009. size = 64 * ETH_ALEN;
  3010. mc_macs = kzalloc(size, GFP_KERNEL);
  3011. if (!mc_macs) {
  3012. DP_NOTICE(edev,
  3013. "Failed to allocate memory for multicast MACs\n");
  3014. rc = -ENOMEM;
  3015. goto exit;
  3016. }
  3017. temp = mc_macs;
  3018. /* Remove all previously configured MAC filters */
  3019. rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
  3020. mc_macs, 1);
  3021. if (rc)
  3022. goto exit;
  3023. netif_addr_lock_bh(ndev);
  3024. mc_count = netdev_mc_count(ndev);
  3025. if (mc_count < 64) {
  3026. netdev_for_each_mc_addr(ha, ndev) {
  3027. ether_addr_copy(temp, ha->addr);
  3028. temp += ETH_ALEN;
  3029. }
  3030. }
  3031. netif_addr_unlock_bh(ndev);
  3032. /* Check for all multicast @@@TBD resource allocation */
  3033. if ((ndev->flags & IFF_ALLMULTI) ||
  3034. (mc_count > 64)) {
  3035. if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
  3036. *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
  3037. } else {
  3038. /* Add all multicast MAC filters */
  3039. rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
  3040. mc_macs, mc_count);
  3041. }
  3042. exit:
  3043. kfree(mc_macs);
  3044. return rc;
  3045. }
  3046. static void qede_set_rx_mode(struct net_device *ndev)
  3047. {
  3048. struct qede_dev *edev = netdev_priv(ndev);
  3049. DP_INFO(edev, "qede_set_rx_mode called\n");
  3050. if (edev->state != QEDE_STATE_OPEN) {
  3051. DP_INFO(edev,
  3052. "qede_set_rx_mode called while interface is down\n");
  3053. } else {
  3054. set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
  3055. schedule_delayed_work(&edev->sp_task, 0);
  3056. }
  3057. }
  3058. /* Must be called with qede_lock held */
  3059. static void qede_config_rx_mode(struct net_device *ndev)
  3060. {
  3061. enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
  3062. struct qede_dev *edev = netdev_priv(ndev);
  3063. struct qed_filter_params rx_mode;
  3064. unsigned char *uc_macs, *temp;
  3065. struct netdev_hw_addr *ha;
  3066. int rc, uc_count;
  3067. size_t size;
  3068. netif_addr_lock_bh(ndev);
  3069. uc_count = netdev_uc_count(ndev);
  3070. size = uc_count * ETH_ALEN;
  3071. uc_macs = kzalloc(size, GFP_ATOMIC);
  3072. if (!uc_macs) {
  3073. DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
  3074. netif_addr_unlock_bh(ndev);
  3075. return;
  3076. }
  3077. temp = uc_macs;
  3078. netdev_for_each_uc_addr(ha, ndev) {
  3079. ether_addr_copy(temp, ha->addr);
  3080. temp += ETH_ALEN;
  3081. }
  3082. netif_addr_unlock_bh(ndev);
  3083. /* Configure the struct for the Rx mode */
  3084. memset(&rx_mode, 0, sizeof(struct qed_filter_params));
  3085. rx_mode.type = QED_FILTER_TYPE_RX_MODE;
  3086. /* Remove all previous unicast secondary macs and multicast macs
  3087. * (configrue / leave the primary mac)
  3088. */
  3089. rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
  3090. edev->primary_mac);
  3091. if (rc)
  3092. goto out;
  3093. /* Check for promiscuous */
  3094. if ((ndev->flags & IFF_PROMISC) ||
  3095. (uc_count > 15)) { /* @@@TBD resource allocation - 1 */
  3096. accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
  3097. } else {
  3098. /* Add MAC filters according to the unicast secondary macs */
  3099. int i;
  3100. temp = uc_macs;
  3101. for (i = 0; i < uc_count; i++) {
  3102. rc = qede_set_ucast_rx_mac(edev,
  3103. QED_FILTER_XCAST_TYPE_ADD,
  3104. temp);
  3105. if (rc)
  3106. goto out;
  3107. temp += ETH_ALEN;
  3108. }
  3109. rc = qede_configure_mcast_filtering(ndev, &accept_flags);
  3110. if (rc)
  3111. goto out;
  3112. }
  3113. /* take care of VLAN mode */
  3114. if (ndev->flags & IFF_PROMISC) {
  3115. qede_config_accept_any_vlan(edev, true);
  3116. } else if (!edev->non_configured_vlans) {
  3117. /* It's possible that accept_any_vlan mode is set due to a
  3118. * previous setting of IFF_PROMISC. If vlan credits are
  3119. * sufficient, disable accept_any_vlan.
  3120. */
  3121. qede_config_accept_any_vlan(edev, false);
  3122. }
  3123. rx_mode.filter.accept_flags = accept_flags;
  3124. edev->ops->filter_config(edev->cdev, &rx_mode);
  3125. out:
  3126. kfree(uc_macs);
  3127. }