qed_l2.c 62 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015 QLogic Corporation
  3. *
  4. * This software is available under the terms of the GNU General Public License
  5. * (GPL) Version 2, available from the file COPYING in the main directory of
  6. * this source tree.
  7. */
  8. #include <linux/types.h>
  9. #include <asm/byteorder.h>
  10. #include <asm/param.h>
  11. #include <linux/delay.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/slab.h>
  19. #include <linux/stddef.h>
  20. #include <linux/string.h>
  21. #include <linux/version.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/bitops.h>
  24. #include <linux/bug.h>
  25. #include "qed.h"
  26. #include <linux/qed/qed_chain.h>
  27. #include "qed_cxt.h"
  28. #include "qed_dev_api.h"
  29. #include <linux/qed/qed_eth_if.h>
  30. #include "qed_hsi.h"
  31. #include "qed_hw.h"
  32. #include "qed_int.h"
  33. #include "qed_l2.h"
  34. #include "qed_mcp.h"
  35. #include "qed_reg_addr.h"
  36. #include "qed_sp.h"
  37. #include "qed_sriov.h"
  38. #define QED_MAX_SGES_NUM 16
  39. #define CRC32_POLY 0x1edc6f41
  40. int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
  41. struct qed_sp_vport_start_params *p_params)
  42. {
  43. struct vport_start_ramrod_data *p_ramrod = NULL;
  44. struct qed_spq_entry *p_ent = NULL;
  45. struct qed_sp_init_data init_data;
  46. u8 abs_vport_id = 0;
  47. int rc = -EINVAL;
  48. u16 rx_mode = 0;
  49. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  50. if (rc != 0)
  51. return rc;
  52. memset(&init_data, 0, sizeof(init_data));
  53. init_data.cid = qed_spq_get_cid(p_hwfn);
  54. init_data.opaque_fid = p_params->opaque_fid;
  55. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  56. rc = qed_sp_init_request(p_hwfn, &p_ent,
  57. ETH_RAMROD_VPORT_START,
  58. PROTOCOLID_ETH, &init_data);
  59. if (rc)
  60. return rc;
  61. p_ramrod = &p_ent->ramrod.vport_start;
  62. p_ramrod->vport_id = abs_vport_id;
  63. p_ramrod->mtu = cpu_to_le16(p_params->mtu);
  64. p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  65. p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  66. p_ramrod->untagged = p_params->only_untagged;
  67. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  68. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  69. p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
  70. /* TPA related fields */
  71. memset(&p_ramrod->tpa_param, 0,
  72. sizeof(struct eth_vport_tpa_param));
  73. p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  74. switch (p_params->tpa_mode) {
  75. case QED_TPA_MODE_GRO:
  76. p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  77. p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  78. p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  79. p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  80. p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  81. p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  82. p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  83. p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  84. break;
  85. default:
  86. break;
  87. }
  88. p_ramrod->tx_switching_en = p_params->tx_switching;
  89. /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
  90. p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
  91. p_params->concrete_fid);
  92. return qed_spq_post(p_hwfn, p_ent, NULL);
  93. }
  94. int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
  95. struct qed_sp_vport_start_params *p_params)
  96. {
  97. if (IS_VF(p_hwfn->cdev)) {
  98. return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
  99. p_params->mtu,
  100. p_params->remove_inner_vlan,
  101. p_params->tpa_mode,
  102. p_params->max_buffers_per_cqe,
  103. p_params->only_untagged);
  104. }
  105. return qed_sp_eth_vport_start(p_hwfn, p_params);
  106. }
  107. static int
  108. qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
  109. struct vport_update_ramrod_data *p_ramrod,
  110. struct qed_rss_params *p_params)
  111. {
  112. struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
  113. u16 abs_l2_queue = 0, capabilities = 0;
  114. int rc = 0, i;
  115. if (!p_params) {
  116. p_ramrod->common.update_rss_flg = 0;
  117. return rc;
  118. }
  119. BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
  120. ETH_RSS_IND_TABLE_ENTRIES_NUM);
  121. rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
  122. if (rc)
  123. return rc;
  124. p_ramrod->common.update_rss_flg = p_params->update_rss_config;
  125. rss->update_rss_capabilities = p_params->update_rss_capabilities;
  126. rss->update_rss_ind_table = p_params->update_rss_ind_table;
  127. rss->update_rss_key = p_params->update_rss_key;
  128. rss->rss_mode = p_params->rss_enable ?
  129. ETH_VPORT_RSS_MODE_REGULAR :
  130. ETH_VPORT_RSS_MODE_DISABLED;
  131. SET_FIELD(capabilities,
  132. ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
  133. !!(p_params->rss_caps & QED_RSS_IPV4));
  134. SET_FIELD(capabilities,
  135. ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
  136. !!(p_params->rss_caps & QED_RSS_IPV6));
  137. SET_FIELD(capabilities,
  138. ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
  139. !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
  140. SET_FIELD(capabilities,
  141. ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
  142. !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
  143. SET_FIELD(capabilities,
  144. ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
  145. !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
  146. SET_FIELD(capabilities,
  147. ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
  148. !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
  149. rss->tbl_size = p_params->rss_table_size_log;
  150. rss->capabilities = cpu_to_le16(capabilities);
  151. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  152. "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
  153. p_ramrod->common.update_rss_flg,
  154. rss->rss_mode, rss->update_rss_capabilities,
  155. capabilities, rss->update_rss_ind_table,
  156. rss->update_rss_key);
  157. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  158. rc = qed_fw_l2_queue(p_hwfn,
  159. (u8)p_params->rss_ind_table[i],
  160. &abs_l2_queue);
  161. if (rc)
  162. return rc;
  163. rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
  164. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
  165. i, rss->indirection_table[i]);
  166. }
  167. for (i = 0; i < 10; i++)
  168. rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
  169. return rc;
  170. }
  171. static void
  172. qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
  173. struct vport_update_ramrod_data *p_ramrod,
  174. struct qed_filter_accept_flags accept_flags)
  175. {
  176. p_ramrod->common.update_rx_mode_flg =
  177. accept_flags.update_rx_mode_config;
  178. p_ramrod->common.update_tx_mode_flg =
  179. accept_flags.update_tx_mode_config;
  180. /* Set Rx mode accept flags */
  181. if (p_ramrod->common.update_rx_mode_flg) {
  182. u8 accept_filter = accept_flags.rx_accept_filter;
  183. u16 state = 0;
  184. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
  185. !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
  186. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  187. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
  188. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
  189. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
  190. !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
  191. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  192. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
  193. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  194. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  195. SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
  196. !!(accept_filter & QED_ACCEPT_BCAST));
  197. p_ramrod->rx_mode.state = cpu_to_le16(state);
  198. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  199. "p_ramrod->rx_mode.state = 0x%x\n", state);
  200. }
  201. /* Set Tx mode accept flags */
  202. if (p_ramrod->common.update_tx_mode_flg) {
  203. u8 accept_filter = accept_flags.tx_accept_filter;
  204. u16 state = 0;
  205. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
  206. !!(accept_filter & QED_ACCEPT_NONE));
  207. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
  208. !!(accept_filter & QED_ACCEPT_NONE));
  209. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
  210. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  211. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  212. SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
  213. !!(accept_filter & QED_ACCEPT_BCAST));
  214. p_ramrod->tx_mode.state = cpu_to_le16(state);
  215. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  216. "p_ramrod->tx_mode.state = 0x%x\n", state);
  217. }
  218. }
  219. static void
  220. qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
  221. struct vport_update_ramrod_data *p_ramrod,
  222. struct qed_sge_tpa_params *p_params)
  223. {
  224. struct eth_vport_tpa_param *p_tpa;
  225. if (!p_params) {
  226. p_ramrod->common.update_tpa_param_flg = 0;
  227. p_ramrod->common.update_tpa_en_flg = 0;
  228. p_ramrod->common.update_tpa_param_flg = 0;
  229. return;
  230. }
  231. p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
  232. p_tpa = &p_ramrod->tpa_param;
  233. p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
  234. p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
  235. p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
  236. p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
  237. p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
  238. p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
  239. p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
  240. p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
  241. p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
  242. p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
  243. p_tpa->tpa_max_size = p_params->tpa_max_size;
  244. p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
  245. p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
  246. }
  247. static void
  248. qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
  249. struct vport_update_ramrod_data *p_ramrod,
  250. struct qed_sp_vport_update_params *p_params)
  251. {
  252. int i;
  253. memset(&p_ramrod->approx_mcast.bins, 0,
  254. sizeof(p_ramrod->approx_mcast.bins));
  255. if (p_params->update_approx_mcast_flg) {
  256. p_ramrod->common.update_approx_mcast_flg = 1;
  257. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  258. u32 *p_bins = (u32 *)p_params->bins;
  259. __le32 val = cpu_to_le32(p_bins[i]);
  260. p_ramrod->approx_mcast.bins[i] = val;
  261. }
  262. }
  263. }
  264. int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
  265. struct qed_sp_vport_update_params *p_params,
  266. enum spq_mode comp_mode,
  267. struct qed_spq_comp_cb *p_comp_data)
  268. {
  269. struct qed_rss_params *p_rss_params = p_params->rss_params;
  270. struct vport_update_ramrod_data_cmn *p_cmn;
  271. struct qed_sp_init_data init_data;
  272. struct vport_update_ramrod_data *p_ramrod = NULL;
  273. struct qed_spq_entry *p_ent = NULL;
  274. u8 abs_vport_id = 0, val;
  275. int rc = -EINVAL;
  276. if (IS_VF(p_hwfn->cdev)) {
  277. rc = qed_vf_pf_vport_update(p_hwfn, p_params);
  278. return rc;
  279. }
  280. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  281. if (rc != 0)
  282. return rc;
  283. memset(&init_data, 0, sizeof(init_data));
  284. init_data.cid = qed_spq_get_cid(p_hwfn);
  285. init_data.opaque_fid = p_params->opaque_fid;
  286. init_data.comp_mode = comp_mode;
  287. init_data.p_comp_data = p_comp_data;
  288. rc = qed_sp_init_request(p_hwfn, &p_ent,
  289. ETH_RAMROD_VPORT_UPDATE,
  290. PROTOCOLID_ETH, &init_data);
  291. if (rc)
  292. return rc;
  293. /* Copy input params to ramrod according to FW struct */
  294. p_ramrod = &p_ent->ramrod.vport_update;
  295. p_cmn = &p_ramrod->common;
  296. p_cmn->vport_id = abs_vport_id;
  297. p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
  298. p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
  299. p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
  300. p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
  301. p_cmn->accept_any_vlan = p_params->accept_any_vlan;
  302. p_cmn->update_accept_any_vlan_flg =
  303. p_params->update_accept_any_vlan_flg;
  304. p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
  305. val = p_params->update_inner_vlan_removal_flg;
  306. p_cmn->update_inner_vlan_removal_en_flg = val;
  307. p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
  308. val = p_params->update_default_vlan_enable_flg;
  309. p_cmn->update_default_vlan_en_flg = val;
  310. p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
  311. p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
  312. p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
  313. p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
  314. p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
  315. p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
  316. val = p_params->update_anti_spoofing_en_flg;
  317. p_ramrod->common.update_anti_spoofing_en_flg = val;
  318. rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
  319. if (rc) {
  320. /* Return spq entry which is taken in qed_sp_init_request()*/
  321. qed_spq_return_entry(p_hwfn, p_ent);
  322. return rc;
  323. }
  324. /* Update mcast bins for VFs, PF doesn't use this functionality */
  325. qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
  326. qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
  327. qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
  328. return qed_spq_post(p_hwfn, p_ent, NULL);
  329. }
  330. int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
  331. {
  332. struct vport_stop_ramrod_data *p_ramrod;
  333. struct qed_sp_init_data init_data;
  334. struct qed_spq_entry *p_ent;
  335. u8 abs_vport_id = 0;
  336. int rc;
  337. if (IS_VF(p_hwfn->cdev))
  338. return qed_vf_pf_vport_stop(p_hwfn);
  339. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  340. if (rc != 0)
  341. return rc;
  342. memset(&init_data, 0, sizeof(init_data));
  343. init_data.cid = qed_spq_get_cid(p_hwfn);
  344. init_data.opaque_fid = opaque_fid;
  345. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  346. rc = qed_sp_init_request(p_hwfn, &p_ent,
  347. ETH_RAMROD_VPORT_STOP,
  348. PROTOCOLID_ETH, &init_data);
  349. if (rc)
  350. return rc;
  351. p_ramrod = &p_ent->ramrod.vport_stop;
  352. p_ramrod->vport_id = abs_vport_id;
  353. return qed_spq_post(p_hwfn, p_ent, NULL);
  354. }
  355. static int
  356. qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
  357. struct qed_filter_accept_flags *p_accept_flags)
  358. {
  359. struct qed_sp_vport_update_params s_params;
  360. memset(&s_params, 0, sizeof(s_params));
  361. memcpy(&s_params.accept_flags, p_accept_flags,
  362. sizeof(struct qed_filter_accept_flags));
  363. return qed_vf_pf_vport_update(p_hwfn, &s_params);
  364. }
  365. static int qed_filter_accept_cmd(struct qed_dev *cdev,
  366. u8 vport,
  367. struct qed_filter_accept_flags accept_flags,
  368. u8 update_accept_any_vlan,
  369. u8 accept_any_vlan,
  370. enum spq_mode comp_mode,
  371. struct qed_spq_comp_cb *p_comp_data)
  372. {
  373. struct qed_sp_vport_update_params vport_update_params;
  374. int i, rc;
  375. /* Prepare and send the vport rx_mode change */
  376. memset(&vport_update_params, 0, sizeof(vport_update_params));
  377. vport_update_params.vport_id = vport;
  378. vport_update_params.accept_flags = accept_flags;
  379. vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
  380. vport_update_params.accept_any_vlan = accept_any_vlan;
  381. for_each_hwfn(cdev, i) {
  382. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  383. vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  384. if (IS_VF(cdev)) {
  385. rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
  386. if (rc)
  387. return rc;
  388. continue;
  389. }
  390. rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
  391. comp_mode, p_comp_data);
  392. if (rc != 0) {
  393. DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
  394. return rc;
  395. }
  396. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  397. "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
  398. accept_flags.rx_accept_filter,
  399. accept_flags.tx_accept_filter);
  400. if (update_accept_any_vlan)
  401. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  402. "accept_any_vlan=%d configured\n",
  403. accept_any_vlan);
  404. }
  405. return 0;
  406. }
  407. static int qed_sp_release_queue_cid(
  408. struct qed_hwfn *p_hwfn,
  409. struct qed_hw_cid_data *p_cid_data)
  410. {
  411. if (!p_cid_data->b_cid_allocated)
  412. return 0;
  413. qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
  414. p_cid_data->b_cid_allocated = false;
  415. return 0;
  416. }
  417. int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
  418. u16 opaque_fid,
  419. u32 cid,
  420. struct qed_queue_start_common_params *params,
  421. u8 stats_id,
  422. u16 bd_max_bytes,
  423. dma_addr_t bd_chain_phys_addr,
  424. dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
  425. {
  426. struct rx_queue_start_ramrod_data *p_ramrod = NULL;
  427. struct qed_spq_entry *p_ent = NULL;
  428. struct qed_sp_init_data init_data;
  429. struct qed_hw_cid_data *p_rx_cid;
  430. u16 abs_rx_q_id = 0;
  431. u8 abs_vport_id = 0;
  432. int rc = -EINVAL;
  433. /* Store information for the stop */
  434. p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
  435. p_rx_cid->cid = cid;
  436. p_rx_cid->opaque_fid = opaque_fid;
  437. p_rx_cid->vport_id = params->vport_id;
  438. rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
  439. if (rc != 0)
  440. return rc;
  441. rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
  442. if (rc != 0)
  443. return rc;
  444. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  445. "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  446. opaque_fid, cid, params->queue_id, params->vport_id,
  447. params->sb);
  448. /* Get SPQ entry */
  449. memset(&init_data, 0, sizeof(init_data));
  450. init_data.cid = cid;
  451. init_data.opaque_fid = opaque_fid;
  452. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  453. rc = qed_sp_init_request(p_hwfn, &p_ent,
  454. ETH_RAMROD_RX_QUEUE_START,
  455. PROTOCOLID_ETH, &init_data);
  456. if (rc)
  457. return rc;
  458. p_ramrod = &p_ent->ramrod.rx_queue_start;
  459. p_ramrod->sb_id = cpu_to_le16(params->sb);
  460. p_ramrod->sb_index = params->sb_idx;
  461. p_ramrod->vport_id = abs_vport_id;
  462. p_ramrod->stats_counter_id = stats_id;
  463. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  464. p_ramrod->complete_cqe_flg = 0;
  465. p_ramrod->complete_event_flg = 1;
  466. p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
  467. DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
  468. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  469. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
  470. p_ramrod->vf_rx_prod_index = params->vf_qid;
  471. if (params->vf_qid)
  472. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  473. "Queue is meant for VF rxq[%04x]\n", params->vf_qid);
  474. return qed_spq_post(p_hwfn, p_ent, NULL);
  475. }
  476. static int
  477. qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
  478. u16 opaque_fid,
  479. struct qed_queue_start_common_params *params,
  480. u16 bd_max_bytes,
  481. dma_addr_t bd_chain_phys_addr,
  482. dma_addr_t cqe_pbl_addr,
  483. u16 cqe_pbl_size, void __iomem **pp_prod)
  484. {
  485. struct qed_hw_cid_data *p_rx_cid;
  486. u32 init_prod_val = 0;
  487. u16 abs_l2_queue = 0;
  488. u8 abs_stats_id = 0;
  489. int rc;
  490. if (IS_VF(p_hwfn->cdev)) {
  491. return qed_vf_pf_rxq_start(p_hwfn,
  492. params->queue_id,
  493. params->sb,
  494. params->sb_idx,
  495. bd_max_bytes,
  496. bd_chain_phys_addr,
  497. cqe_pbl_addr, cqe_pbl_size, pp_prod);
  498. }
  499. rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
  500. if (rc != 0)
  501. return rc;
  502. rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
  503. if (rc != 0)
  504. return rc;
  505. *pp_prod = (u8 __iomem *)p_hwfn->regview +
  506. GTT_BAR0_MAP_REG_MSDM_RAM +
  507. MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
  508. /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
  509. __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
  510. (u32 *)(&init_prod_val));
  511. /* Allocate a CID for the queue */
  512. p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
  513. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
  514. &p_rx_cid->cid);
  515. if (rc) {
  516. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  517. return rc;
  518. }
  519. p_rx_cid->b_cid_allocated = true;
  520. rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
  521. opaque_fid,
  522. p_rx_cid->cid,
  523. params,
  524. abs_stats_id,
  525. bd_max_bytes,
  526. bd_chain_phys_addr,
  527. cqe_pbl_addr,
  528. cqe_pbl_size);
  529. if (rc != 0)
  530. qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
  531. return rc;
  532. }
  533. int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
  534. u16 rx_queue_id,
  535. u8 num_rxqs,
  536. u8 complete_cqe_flg,
  537. u8 complete_event_flg,
  538. enum spq_mode comp_mode,
  539. struct qed_spq_comp_cb *p_comp_data)
  540. {
  541. struct rx_queue_update_ramrod_data *p_ramrod = NULL;
  542. struct qed_spq_entry *p_ent = NULL;
  543. struct qed_sp_init_data init_data;
  544. struct qed_hw_cid_data *p_rx_cid;
  545. u16 qid, abs_rx_q_id = 0;
  546. int rc = -EINVAL;
  547. u8 i;
  548. memset(&init_data, 0, sizeof(init_data));
  549. init_data.comp_mode = comp_mode;
  550. init_data.p_comp_data = p_comp_data;
  551. for (i = 0; i < num_rxqs; i++) {
  552. qid = rx_queue_id + i;
  553. p_rx_cid = &p_hwfn->p_rx_cids[qid];
  554. /* Get SPQ entry */
  555. init_data.cid = p_rx_cid->cid;
  556. init_data.opaque_fid = p_rx_cid->opaque_fid;
  557. rc = qed_sp_init_request(p_hwfn, &p_ent,
  558. ETH_RAMROD_RX_QUEUE_UPDATE,
  559. PROTOCOLID_ETH, &init_data);
  560. if (rc)
  561. return rc;
  562. p_ramrod = &p_ent->ramrod.rx_queue_update;
  563. qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
  564. qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
  565. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  566. p_ramrod->complete_cqe_flg = complete_cqe_flg;
  567. p_ramrod->complete_event_flg = complete_event_flg;
  568. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  569. if (rc)
  570. return rc;
  571. }
  572. return rc;
  573. }
  574. int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
  575. u16 rx_queue_id,
  576. bool eq_completion_only, bool cqe_completion)
  577. {
  578. struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
  579. struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
  580. struct qed_spq_entry *p_ent = NULL;
  581. struct qed_sp_init_data init_data;
  582. u16 abs_rx_q_id = 0;
  583. int rc = -EINVAL;
  584. if (IS_VF(p_hwfn->cdev))
  585. return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion);
  586. /* Get SPQ entry */
  587. memset(&init_data, 0, sizeof(init_data));
  588. init_data.cid = p_rx_cid->cid;
  589. init_data.opaque_fid = p_rx_cid->opaque_fid;
  590. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  591. rc = qed_sp_init_request(p_hwfn, &p_ent,
  592. ETH_RAMROD_RX_QUEUE_STOP,
  593. PROTOCOLID_ETH, &init_data);
  594. if (rc)
  595. return rc;
  596. p_ramrod = &p_ent->ramrod.rx_queue_stop;
  597. qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
  598. qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
  599. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  600. /* Cleaning the queue requires the completion to arrive there.
  601. * In addition, VFs require the answer to come as eqe to PF.
  602. */
  603. p_ramrod->complete_cqe_flg =
  604. (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
  605. !eq_completion_only) || cqe_completion;
  606. p_ramrod->complete_event_flg =
  607. !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
  608. eq_completion_only;
  609. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  610. if (rc)
  611. return rc;
  612. return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
  613. }
  614. int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
  615. u16 opaque_fid,
  616. u32 cid,
  617. struct qed_queue_start_common_params *p_params,
  618. u8 stats_id,
  619. dma_addr_t pbl_addr,
  620. u16 pbl_size,
  621. union qed_qm_pq_params *p_pq_params)
  622. {
  623. struct tx_queue_start_ramrod_data *p_ramrod = NULL;
  624. struct qed_spq_entry *p_ent = NULL;
  625. struct qed_sp_init_data init_data;
  626. struct qed_hw_cid_data *p_tx_cid;
  627. u16 pq_id, abs_tx_q_id = 0;
  628. int rc = -EINVAL;
  629. u8 abs_vport_id;
  630. /* Store information for the stop */
  631. p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
  632. p_tx_cid->cid = cid;
  633. p_tx_cid->opaque_fid = opaque_fid;
  634. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  635. if (rc)
  636. return rc;
  637. rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_tx_q_id);
  638. if (rc)
  639. return rc;
  640. /* Get SPQ entry */
  641. memset(&init_data, 0, sizeof(init_data));
  642. init_data.cid = cid;
  643. init_data.opaque_fid = opaque_fid;
  644. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  645. rc = qed_sp_init_request(p_hwfn, &p_ent,
  646. ETH_RAMROD_TX_QUEUE_START,
  647. PROTOCOLID_ETH, &init_data);
  648. if (rc)
  649. return rc;
  650. p_ramrod = &p_ent->ramrod.tx_queue_start;
  651. p_ramrod->vport_id = abs_vport_id;
  652. p_ramrod->sb_id = cpu_to_le16(p_params->sb);
  653. p_ramrod->sb_index = p_params->sb_idx;
  654. p_ramrod->stats_counter_id = stats_id;
  655. p_ramrod->queue_zone_id = cpu_to_le16(abs_tx_q_id);
  656. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  657. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
  658. pq_id = qed_get_qm_pq(p_hwfn,
  659. PROTOCOLID_ETH,
  660. p_pq_params);
  661. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  662. return qed_spq_post(p_hwfn, p_ent, NULL);
  663. }
  664. static int
  665. qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
  666. u16 opaque_fid,
  667. struct qed_queue_start_common_params *p_params,
  668. dma_addr_t pbl_addr,
  669. u16 pbl_size, void __iomem **pp_doorbell)
  670. {
  671. struct qed_hw_cid_data *p_tx_cid;
  672. union qed_qm_pq_params pq_params;
  673. u8 abs_stats_id = 0;
  674. int rc;
  675. if (IS_VF(p_hwfn->cdev)) {
  676. return qed_vf_pf_txq_start(p_hwfn,
  677. p_params->queue_id,
  678. p_params->sb,
  679. p_params->sb_idx,
  680. pbl_addr, pbl_size, pp_doorbell);
  681. }
  682. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
  683. if (rc)
  684. return rc;
  685. p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
  686. memset(p_tx_cid, 0, sizeof(*p_tx_cid));
  687. memset(&pq_params, 0, sizeof(pq_params));
  688. /* Allocate a CID for the queue */
  689. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
  690. &p_tx_cid->cid);
  691. if (rc) {
  692. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  693. return rc;
  694. }
  695. p_tx_cid->b_cid_allocated = true;
  696. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  697. "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  698. opaque_fid, p_tx_cid->cid,
  699. p_params->queue_id, p_params->vport_id, p_params->sb);
  700. rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
  701. opaque_fid,
  702. p_tx_cid->cid,
  703. p_params,
  704. abs_stats_id,
  705. pbl_addr,
  706. pbl_size,
  707. &pq_params);
  708. *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
  709. qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
  710. if (rc)
  711. qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
  712. return rc;
  713. }
  714. int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id)
  715. {
  716. struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
  717. struct qed_spq_entry *p_ent = NULL;
  718. struct qed_sp_init_data init_data;
  719. int rc = -EINVAL;
  720. if (IS_VF(p_hwfn->cdev))
  721. return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id);
  722. /* Get SPQ entry */
  723. memset(&init_data, 0, sizeof(init_data));
  724. init_data.cid = p_tx_cid->cid;
  725. init_data.opaque_fid = p_tx_cid->opaque_fid;
  726. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  727. rc = qed_sp_init_request(p_hwfn, &p_ent,
  728. ETH_RAMROD_TX_QUEUE_STOP,
  729. PROTOCOLID_ETH, &init_data);
  730. if (rc)
  731. return rc;
  732. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  733. if (rc)
  734. return rc;
  735. return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
  736. }
  737. static enum eth_filter_action
  738. qed_filter_action(enum qed_filter_opcode opcode)
  739. {
  740. enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
  741. switch (opcode) {
  742. case QED_FILTER_ADD:
  743. action = ETH_FILTER_ACTION_ADD;
  744. break;
  745. case QED_FILTER_REMOVE:
  746. action = ETH_FILTER_ACTION_REMOVE;
  747. break;
  748. case QED_FILTER_FLUSH:
  749. action = ETH_FILTER_ACTION_REMOVE_ALL;
  750. break;
  751. default:
  752. action = MAX_ETH_FILTER_ACTION;
  753. }
  754. return action;
  755. }
  756. static void qed_set_fw_mac_addr(__le16 *fw_msb,
  757. __le16 *fw_mid,
  758. __le16 *fw_lsb,
  759. u8 *mac)
  760. {
  761. ((u8 *)fw_msb)[0] = mac[1];
  762. ((u8 *)fw_msb)[1] = mac[0];
  763. ((u8 *)fw_mid)[0] = mac[3];
  764. ((u8 *)fw_mid)[1] = mac[2];
  765. ((u8 *)fw_lsb)[0] = mac[5];
  766. ((u8 *)fw_lsb)[1] = mac[4];
  767. }
  768. static int
  769. qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
  770. u16 opaque_fid,
  771. struct qed_filter_ucast *p_filter_cmd,
  772. struct vport_filter_update_ramrod_data **pp_ramrod,
  773. struct qed_spq_entry **pp_ent,
  774. enum spq_mode comp_mode,
  775. struct qed_spq_comp_cb *p_comp_data)
  776. {
  777. u8 vport_to_add_to = 0, vport_to_remove_from = 0;
  778. struct vport_filter_update_ramrod_data *p_ramrod;
  779. struct eth_filter_cmd *p_first_filter;
  780. struct eth_filter_cmd *p_second_filter;
  781. struct qed_sp_init_data init_data;
  782. enum eth_filter_action action;
  783. int rc;
  784. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  785. &vport_to_remove_from);
  786. if (rc)
  787. return rc;
  788. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  789. &vport_to_add_to);
  790. if (rc)
  791. return rc;
  792. /* Get SPQ entry */
  793. memset(&init_data, 0, sizeof(init_data));
  794. init_data.cid = qed_spq_get_cid(p_hwfn);
  795. init_data.opaque_fid = opaque_fid;
  796. init_data.comp_mode = comp_mode;
  797. init_data.p_comp_data = p_comp_data;
  798. rc = qed_sp_init_request(p_hwfn, pp_ent,
  799. ETH_RAMROD_FILTERS_UPDATE,
  800. PROTOCOLID_ETH, &init_data);
  801. if (rc)
  802. return rc;
  803. *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
  804. p_ramrod = *pp_ramrod;
  805. p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
  806. p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
  807. switch (p_filter_cmd->opcode) {
  808. case QED_FILTER_REPLACE:
  809. case QED_FILTER_MOVE:
  810. p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
  811. default:
  812. p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
  813. }
  814. p_first_filter = &p_ramrod->filter_cmds[0];
  815. p_second_filter = &p_ramrod->filter_cmds[1];
  816. switch (p_filter_cmd->type) {
  817. case QED_FILTER_MAC:
  818. p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
  819. case QED_FILTER_VLAN:
  820. p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
  821. case QED_FILTER_MAC_VLAN:
  822. p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
  823. case QED_FILTER_INNER_MAC:
  824. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
  825. case QED_FILTER_INNER_VLAN:
  826. p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
  827. case QED_FILTER_INNER_PAIR:
  828. p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
  829. case QED_FILTER_INNER_MAC_VNI_PAIR:
  830. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
  831. break;
  832. case QED_FILTER_MAC_VNI_PAIR:
  833. p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
  834. case QED_FILTER_VNI:
  835. p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
  836. }
  837. if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
  838. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  839. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
  840. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
  841. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  842. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
  843. qed_set_fw_mac_addr(&p_first_filter->mac_msb,
  844. &p_first_filter->mac_mid,
  845. &p_first_filter->mac_lsb,
  846. (u8 *)p_filter_cmd->mac);
  847. }
  848. if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
  849. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  850. (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
  851. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
  852. p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
  853. if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  854. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
  855. (p_first_filter->type == ETH_FILTER_TYPE_VNI))
  856. p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
  857. if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
  858. p_second_filter->type = p_first_filter->type;
  859. p_second_filter->mac_msb = p_first_filter->mac_msb;
  860. p_second_filter->mac_mid = p_first_filter->mac_mid;
  861. p_second_filter->mac_lsb = p_first_filter->mac_lsb;
  862. p_second_filter->vlan_id = p_first_filter->vlan_id;
  863. p_second_filter->vni = p_first_filter->vni;
  864. p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
  865. p_first_filter->vport_id = vport_to_remove_from;
  866. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  867. p_second_filter->vport_id = vport_to_add_to;
  868. } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
  869. p_first_filter->vport_id = vport_to_add_to;
  870. memcpy(p_second_filter, p_first_filter,
  871. sizeof(*p_second_filter));
  872. p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
  873. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  874. } else {
  875. action = qed_filter_action(p_filter_cmd->opcode);
  876. if (action == MAX_ETH_FILTER_ACTION) {
  877. DP_NOTICE(p_hwfn,
  878. "%d is not supported yet\n",
  879. p_filter_cmd->opcode);
  880. return -EINVAL;
  881. }
  882. p_first_filter->action = action;
  883. p_first_filter->vport_id = (p_filter_cmd->opcode ==
  884. QED_FILTER_REMOVE) ?
  885. vport_to_remove_from :
  886. vport_to_add_to;
  887. }
  888. return 0;
  889. }
  890. int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
  891. u16 opaque_fid,
  892. struct qed_filter_ucast *p_filter_cmd,
  893. enum spq_mode comp_mode,
  894. struct qed_spq_comp_cb *p_comp_data)
  895. {
  896. struct vport_filter_update_ramrod_data *p_ramrod = NULL;
  897. struct qed_spq_entry *p_ent = NULL;
  898. struct eth_filter_cmd_header *p_header;
  899. int rc;
  900. rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
  901. &p_ramrod, &p_ent,
  902. comp_mode, p_comp_data);
  903. if (rc != 0) {
  904. DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
  905. return rc;
  906. }
  907. p_header = &p_ramrod->filter_cmd_hdr;
  908. p_header->assert_on_error = p_filter_cmd->assert_on_error;
  909. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  910. if (rc != 0) {
  911. DP_ERR(p_hwfn,
  912. "Unicast filter ADD command failed %d\n",
  913. rc);
  914. return rc;
  915. }
  916. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  917. "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
  918. (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
  919. ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
  920. "REMOVE" :
  921. ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
  922. "MOVE" : "REPLACE")),
  923. (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
  924. ((p_filter_cmd->type == QED_FILTER_VLAN) ?
  925. "VLAN" : "MAC & VLAN"),
  926. p_ramrod->filter_cmd_hdr.cmd_cnt,
  927. p_filter_cmd->is_rx_filter,
  928. p_filter_cmd->is_tx_filter);
  929. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  930. "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
  931. p_filter_cmd->vport_to_add_to,
  932. p_filter_cmd->vport_to_remove_from,
  933. p_filter_cmd->mac[0],
  934. p_filter_cmd->mac[1],
  935. p_filter_cmd->mac[2],
  936. p_filter_cmd->mac[3],
  937. p_filter_cmd->mac[4],
  938. p_filter_cmd->mac[5],
  939. p_filter_cmd->vlan);
  940. return 0;
  941. }
  942. /*******************************************************************************
  943. * Description:
  944. * Calculates crc 32 on a buffer
  945. * Note: crc32_length MUST be aligned to 8
  946. * Return:
  947. ******************************************************************************/
  948. static u32 qed_calc_crc32c(u8 *crc32_packet,
  949. u32 crc32_length,
  950. u32 crc32_seed,
  951. u8 complement)
  952. {
  953. u32 byte = 0;
  954. u32 bit = 0;
  955. u8 msb = 0;
  956. u8 current_byte = 0;
  957. u32 crc32_result = crc32_seed;
  958. if ((!crc32_packet) ||
  959. (crc32_length == 0) ||
  960. ((crc32_length % 8) != 0))
  961. return crc32_result;
  962. for (byte = 0; byte < crc32_length; byte++) {
  963. current_byte = crc32_packet[byte];
  964. for (bit = 0; bit < 8; bit++) {
  965. msb = (u8)(crc32_result >> 31);
  966. crc32_result = crc32_result << 1;
  967. if (msb != (0x1 & (current_byte >> bit))) {
  968. crc32_result = crc32_result ^ CRC32_POLY;
  969. crc32_result |= 1; /*crc32_result[0] = 1;*/
  970. }
  971. }
  972. }
  973. return crc32_result;
  974. }
  975. static inline u32 qed_crc32c_le(u32 seed,
  976. u8 *mac,
  977. u32 len)
  978. {
  979. u32 packet_buf[2] = { 0 };
  980. memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
  981. return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
  982. }
  983. u8 qed_mcast_bin_from_mac(u8 *mac)
  984. {
  985. u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
  986. mac, ETH_ALEN);
  987. return crc & 0xff;
  988. }
  989. static int
  990. qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
  991. u16 opaque_fid,
  992. struct qed_filter_mcast *p_filter_cmd,
  993. enum spq_mode comp_mode,
  994. struct qed_spq_comp_cb *p_comp_data)
  995. {
  996. unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
  997. struct vport_update_ramrod_data *p_ramrod = NULL;
  998. struct qed_spq_entry *p_ent = NULL;
  999. struct qed_sp_init_data init_data;
  1000. u8 abs_vport_id = 0;
  1001. int rc, i;
  1002. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1003. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  1004. &abs_vport_id);
  1005. if (rc)
  1006. return rc;
  1007. } else {
  1008. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  1009. &abs_vport_id);
  1010. if (rc)
  1011. return rc;
  1012. }
  1013. /* Get SPQ entry */
  1014. memset(&init_data, 0, sizeof(init_data));
  1015. init_data.cid = qed_spq_get_cid(p_hwfn);
  1016. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1017. init_data.comp_mode = comp_mode;
  1018. init_data.p_comp_data = p_comp_data;
  1019. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1020. ETH_RAMROD_VPORT_UPDATE,
  1021. PROTOCOLID_ETH, &init_data);
  1022. if (rc) {
  1023. DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
  1024. return rc;
  1025. }
  1026. p_ramrod = &p_ent->ramrod.vport_update;
  1027. p_ramrod->common.update_approx_mcast_flg = 1;
  1028. /* explicitly clear out the entire vector */
  1029. memset(&p_ramrod->approx_mcast.bins, 0,
  1030. sizeof(p_ramrod->approx_mcast.bins));
  1031. memset(bins, 0, sizeof(unsigned long) *
  1032. ETH_MULTICAST_MAC_BINS_IN_REGS);
  1033. /* filter ADD op is explicit set op and it removes
  1034. * any existing filters for the vport
  1035. */
  1036. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1037. for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
  1038. u32 bit;
  1039. bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
  1040. __set_bit(bit, bins);
  1041. }
  1042. /* Convert to correct endianity */
  1043. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  1044. u32 *p_bins = (u32 *)bins;
  1045. struct vport_update_ramrod_mcast *approx_mcast;
  1046. approx_mcast = &p_ramrod->approx_mcast;
  1047. approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
  1048. }
  1049. }
  1050. p_ramrod->common.vport_id = abs_vport_id;
  1051. return qed_spq_post(p_hwfn, p_ent, NULL);
  1052. }
  1053. static int qed_filter_mcast_cmd(struct qed_dev *cdev,
  1054. struct qed_filter_mcast *p_filter_cmd,
  1055. enum spq_mode comp_mode,
  1056. struct qed_spq_comp_cb *p_comp_data)
  1057. {
  1058. int rc = 0;
  1059. int i;
  1060. /* only ADD and REMOVE operations are supported for multi-cast */
  1061. if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
  1062. (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
  1063. (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
  1064. return -EINVAL;
  1065. for_each_hwfn(cdev, i) {
  1066. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1067. u16 opaque_fid;
  1068. if (IS_VF(cdev)) {
  1069. qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
  1070. continue;
  1071. }
  1072. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1073. rc = qed_sp_eth_filter_mcast(p_hwfn,
  1074. opaque_fid,
  1075. p_filter_cmd,
  1076. comp_mode,
  1077. p_comp_data);
  1078. }
  1079. return rc;
  1080. }
  1081. static int qed_filter_ucast_cmd(struct qed_dev *cdev,
  1082. struct qed_filter_ucast *p_filter_cmd,
  1083. enum spq_mode comp_mode,
  1084. struct qed_spq_comp_cb *p_comp_data)
  1085. {
  1086. int rc = 0;
  1087. int i;
  1088. for_each_hwfn(cdev, i) {
  1089. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1090. u16 opaque_fid;
  1091. if (IS_VF(cdev)) {
  1092. rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
  1093. continue;
  1094. }
  1095. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1096. rc = qed_sp_eth_filter_ucast(p_hwfn,
  1097. opaque_fid,
  1098. p_filter_cmd,
  1099. comp_mode,
  1100. p_comp_data);
  1101. if (rc != 0)
  1102. break;
  1103. }
  1104. return rc;
  1105. }
  1106. /* Statistics related code */
  1107. static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
  1108. u32 *p_addr,
  1109. u32 *p_len, u16 statistics_bin)
  1110. {
  1111. if (IS_PF(p_hwfn->cdev)) {
  1112. *p_addr = BAR0_MAP_REG_PSDM_RAM +
  1113. PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1114. *p_len = sizeof(struct eth_pstorm_per_queue_stat);
  1115. } else {
  1116. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1117. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1118. *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
  1119. *p_len = p_resp->pfdev_info.stats_info.pstats.len;
  1120. }
  1121. }
  1122. static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
  1123. struct qed_ptt *p_ptt,
  1124. struct qed_eth_stats *p_stats,
  1125. u16 statistics_bin)
  1126. {
  1127. struct eth_pstorm_per_queue_stat pstats;
  1128. u32 pstats_addr = 0, pstats_len = 0;
  1129. __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
  1130. statistics_bin);
  1131. memset(&pstats, 0, sizeof(pstats));
  1132. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
  1133. p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1134. p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1135. p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1136. p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1137. p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1138. p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1139. p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
  1140. }
  1141. static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
  1142. struct qed_ptt *p_ptt,
  1143. struct qed_eth_stats *p_stats,
  1144. u16 statistics_bin)
  1145. {
  1146. struct tstorm_per_port_stat tstats;
  1147. u32 tstats_addr, tstats_len;
  1148. if (IS_PF(p_hwfn->cdev)) {
  1149. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1150. TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
  1151. tstats_len = sizeof(struct tstorm_per_port_stat);
  1152. } else {
  1153. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1154. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1155. tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
  1156. tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
  1157. }
  1158. memset(&tstats, 0, sizeof(tstats));
  1159. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
  1160. p_stats->mftag_filter_discards +=
  1161. HILO_64_REGPAIR(tstats.mftag_filter_discard);
  1162. p_stats->mac_filter_discards +=
  1163. HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
  1164. }
  1165. static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
  1166. u32 *p_addr,
  1167. u32 *p_len, u16 statistics_bin)
  1168. {
  1169. if (IS_PF(p_hwfn->cdev)) {
  1170. *p_addr = BAR0_MAP_REG_USDM_RAM +
  1171. USTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1172. *p_len = sizeof(struct eth_ustorm_per_queue_stat);
  1173. } else {
  1174. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1175. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1176. *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
  1177. *p_len = p_resp->pfdev_info.stats_info.ustats.len;
  1178. }
  1179. }
  1180. static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
  1181. struct qed_ptt *p_ptt,
  1182. struct qed_eth_stats *p_stats,
  1183. u16 statistics_bin)
  1184. {
  1185. struct eth_ustorm_per_queue_stat ustats;
  1186. u32 ustats_addr = 0, ustats_len = 0;
  1187. __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
  1188. statistics_bin);
  1189. memset(&ustats, 0, sizeof(ustats));
  1190. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
  1191. p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1192. p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1193. p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1194. p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1195. p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1196. p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1197. }
  1198. static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
  1199. u32 *p_addr,
  1200. u32 *p_len, u16 statistics_bin)
  1201. {
  1202. if (IS_PF(p_hwfn->cdev)) {
  1203. *p_addr = BAR0_MAP_REG_MSDM_RAM +
  1204. MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1205. *p_len = sizeof(struct eth_mstorm_per_queue_stat);
  1206. } else {
  1207. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1208. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1209. *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
  1210. *p_len = p_resp->pfdev_info.stats_info.mstats.len;
  1211. }
  1212. }
  1213. static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
  1214. struct qed_ptt *p_ptt,
  1215. struct qed_eth_stats *p_stats,
  1216. u16 statistics_bin)
  1217. {
  1218. struct eth_mstorm_per_queue_stat mstats;
  1219. u32 mstats_addr = 0, mstats_len = 0;
  1220. __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
  1221. statistics_bin);
  1222. memset(&mstats, 0, sizeof(mstats));
  1223. qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
  1224. p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
  1225. p_stats->packet_too_big_discard +=
  1226. HILO_64_REGPAIR(mstats.packet_too_big_discard);
  1227. p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
  1228. p_stats->tpa_coalesced_pkts +=
  1229. HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
  1230. p_stats->tpa_coalesced_events +=
  1231. HILO_64_REGPAIR(mstats.tpa_coalesced_events);
  1232. p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
  1233. p_stats->tpa_coalesced_bytes +=
  1234. HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
  1235. }
  1236. static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
  1237. struct qed_ptt *p_ptt,
  1238. struct qed_eth_stats *p_stats)
  1239. {
  1240. struct port_stats port_stats;
  1241. int j;
  1242. memset(&port_stats, 0, sizeof(port_stats));
  1243. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1244. p_hwfn->mcp_info->port_addr +
  1245. offsetof(struct public_port, stats),
  1246. sizeof(port_stats));
  1247. p_stats->rx_64_byte_packets += port_stats.eth.r64;
  1248. p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
  1249. p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
  1250. p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
  1251. p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
  1252. p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
  1253. p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
  1254. p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
  1255. p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
  1256. p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
  1257. p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
  1258. p_stats->rx_crc_errors += port_stats.eth.rfcs;
  1259. p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
  1260. p_stats->rx_pause_frames += port_stats.eth.rxpf;
  1261. p_stats->rx_pfc_frames += port_stats.eth.rxpp;
  1262. p_stats->rx_align_errors += port_stats.eth.raln;
  1263. p_stats->rx_carrier_errors += port_stats.eth.rfcr;
  1264. p_stats->rx_oversize_packets += port_stats.eth.rovr;
  1265. p_stats->rx_jabbers += port_stats.eth.rjbr;
  1266. p_stats->rx_undersize_packets += port_stats.eth.rund;
  1267. p_stats->rx_fragments += port_stats.eth.rfrg;
  1268. p_stats->tx_64_byte_packets += port_stats.eth.t64;
  1269. p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
  1270. p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
  1271. p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
  1272. p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
  1273. p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
  1274. p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
  1275. p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
  1276. p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
  1277. p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
  1278. p_stats->tx_pause_frames += port_stats.eth.txpf;
  1279. p_stats->tx_pfc_frames += port_stats.eth.txpp;
  1280. p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
  1281. p_stats->tx_total_collisions += port_stats.eth.tncl;
  1282. p_stats->rx_mac_bytes += port_stats.eth.rbyte;
  1283. p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
  1284. p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
  1285. p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
  1286. p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
  1287. p_stats->tx_mac_bytes += port_stats.eth.tbyte;
  1288. p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
  1289. p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
  1290. p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
  1291. p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
  1292. for (j = 0; j < 8; j++) {
  1293. p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
  1294. p_stats->brb_discards += port_stats.brb.brb_discard[j];
  1295. }
  1296. }
  1297. static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
  1298. struct qed_ptt *p_ptt,
  1299. struct qed_eth_stats *stats,
  1300. u16 statistics_bin, bool b_get_port_stats)
  1301. {
  1302. __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
  1303. __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
  1304. __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
  1305. __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
  1306. if (b_get_port_stats && p_hwfn->mcp_info)
  1307. __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
  1308. }
  1309. static void _qed_get_vport_stats(struct qed_dev *cdev,
  1310. struct qed_eth_stats *stats)
  1311. {
  1312. u8 fw_vport = 0;
  1313. int i;
  1314. memset(stats, 0, sizeof(*stats));
  1315. for_each_hwfn(cdev, i) {
  1316. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1317. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1318. : NULL;
  1319. if (IS_PF(cdev)) {
  1320. /* The main vport index is relative first */
  1321. if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
  1322. DP_ERR(p_hwfn, "No vport available!\n");
  1323. goto out;
  1324. }
  1325. }
  1326. if (IS_PF(cdev) && !p_ptt) {
  1327. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1328. continue;
  1329. }
  1330. __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
  1331. IS_PF(cdev) ? true : false);
  1332. out:
  1333. if (IS_PF(cdev) && p_ptt)
  1334. qed_ptt_release(p_hwfn, p_ptt);
  1335. }
  1336. }
  1337. void qed_get_vport_stats(struct qed_dev *cdev,
  1338. struct qed_eth_stats *stats)
  1339. {
  1340. u32 i;
  1341. if (!cdev) {
  1342. memset(stats, 0, sizeof(*stats));
  1343. return;
  1344. }
  1345. _qed_get_vport_stats(cdev, stats);
  1346. if (!cdev->reset_stats)
  1347. return;
  1348. /* Reduce the statistics baseline */
  1349. for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
  1350. ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
  1351. }
  1352. /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
  1353. void qed_reset_vport_stats(struct qed_dev *cdev)
  1354. {
  1355. int i;
  1356. for_each_hwfn(cdev, i) {
  1357. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1358. struct eth_mstorm_per_queue_stat mstats;
  1359. struct eth_ustorm_per_queue_stat ustats;
  1360. struct eth_pstorm_per_queue_stat pstats;
  1361. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1362. : NULL;
  1363. u32 addr = 0, len = 0;
  1364. if (IS_PF(cdev) && !p_ptt) {
  1365. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1366. continue;
  1367. }
  1368. memset(&mstats, 0, sizeof(mstats));
  1369. __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
  1370. qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
  1371. memset(&ustats, 0, sizeof(ustats));
  1372. __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
  1373. qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
  1374. memset(&pstats, 0, sizeof(pstats));
  1375. __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
  1376. qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
  1377. if (IS_PF(cdev))
  1378. qed_ptt_release(p_hwfn, p_ptt);
  1379. }
  1380. /* PORT statistics are not necessarily reset, so we need to
  1381. * read and create a baseline for future statistics.
  1382. */
  1383. if (!cdev->reset_stats)
  1384. DP_INFO(cdev, "Reset stats not allocated\n");
  1385. else
  1386. _qed_get_vport_stats(cdev, cdev->reset_stats);
  1387. }
  1388. static int qed_fill_eth_dev_info(struct qed_dev *cdev,
  1389. struct qed_dev_eth_info *info)
  1390. {
  1391. int i;
  1392. memset(info, 0, sizeof(*info));
  1393. info->num_tc = 1;
  1394. if (IS_PF(cdev)) {
  1395. int max_vf_vlan_filters = 0;
  1396. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  1397. for_each_hwfn(cdev, i)
  1398. info->num_queues +=
  1399. FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
  1400. if (cdev->int_params.fp_msix_cnt)
  1401. info->num_queues =
  1402. min_t(u8, info->num_queues,
  1403. cdev->int_params.fp_msix_cnt);
  1404. } else {
  1405. info->num_queues = cdev->num_hwfns;
  1406. }
  1407. if (IS_QED_SRIOV(cdev))
  1408. max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
  1409. QED_ETH_VF_NUM_VLAN_FILTERS;
  1410. info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN) -
  1411. max_vf_vlan_filters;
  1412. ether_addr_copy(info->port_mac,
  1413. cdev->hwfns[0].hw_info.hw_mac_addr);
  1414. } else {
  1415. qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
  1416. if (cdev->num_hwfns > 1) {
  1417. u8 queues = 0;
  1418. qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
  1419. info->num_queues += queues;
  1420. }
  1421. qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
  1422. &info->num_vlan_filters);
  1423. qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
  1424. }
  1425. qed_fill_dev_info(cdev, &info->common);
  1426. if (IS_VF(cdev))
  1427. memset(info->common.hw_mac, 0, ETH_ALEN);
  1428. return 0;
  1429. }
  1430. static void qed_register_eth_ops(struct qed_dev *cdev,
  1431. struct qed_eth_cb_ops *ops, void *cookie)
  1432. {
  1433. cdev->protocol_ops.eth = ops;
  1434. cdev->ops_cookie = cookie;
  1435. /* For VF, we start bulletin reading */
  1436. if (IS_VF(cdev))
  1437. qed_vf_start_iov_wq(cdev);
  1438. }
  1439. static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
  1440. {
  1441. if (IS_PF(cdev))
  1442. return true;
  1443. return qed_vf_check_mac(&cdev->hwfns[0], mac);
  1444. }
  1445. static int qed_start_vport(struct qed_dev *cdev,
  1446. struct qed_start_vport_params *params)
  1447. {
  1448. int rc, i;
  1449. for_each_hwfn(cdev, i) {
  1450. struct qed_sp_vport_start_params start = { 0 };
  1451. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1452. start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
  1453. QED_TPA_MODE_NONE;
  1454. start.remove_inner_vlan = params->remove_inner_vlan;
  1455. start.only_untagged = true; /* untagged only */
  1456. start.drop_ttl0 = params->drop_ttl0;
  1457. start.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1458. start.concrete_fid = p_hwfn->hw_info.concrete_fid;
  1459. start.vport_id = params->vport_id;
  1460. start.max_buffers_per_cqe = 16;
  1461. start.mtu = params->mtu;
  1462. rc = qed_sp_vport_start(p_hwfn, &start);
  1463. if (rc) {
  1464. DP_ERR(cdev, "Failed to start VPORT\n");
  1465. return rc;
  1466. }
  1467. qed_hw_start_fastpath(p_hwfn);
  1468. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1469. "Started V-PORT %d with MTU %d\n",
  1470. start.vport_id, start.mtu);
  1471. }
  1472. if (params->clear_stats)
  1473. qed_reset_vport_stats(cdev);
  1474. return 0;
  1475. }
  1476. static int qed_stop_vport(struct qed_dev *cdev,
  1477. u8 vport_id)
  1478. {
  1479. int rc, i;
  1480. for_each_hwfn(cdev, i) {
  1481. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1482. rc = qed_sp_vport_stop(p_hwfn,
  1483. p_hwfn->hw_info.opaque_fid,
  1484. vport_id);
  1485. if (rc) {
  1486. DP_ERR(cdev, "Failed to stop VPORT\n");
  1487. return rc;
  1488. }
  1489. }
  1490. return 0;
  1491. }
  1492. static int qed_update_vport(struct qed_dev *cdev,
  1493. struct qed_update_vport_params *params)
  1494. {
  1495. struct qed_sp_vport_update_params sp_params;
  1496. struct qed_rss_params sp_rss_params;
  1497. int rc, i;
  1498. if (!cdev)
  1499. return -ENODEV;
  1500. memset(&sp_params, 0, sizeof(sp_params));
  1501. memset(&sp_rss_params, 0, sizeof(sp_rss_params));
  1502. /* Translate protocol params into sp params */
  1503. sp_params.vport_id = params->vport_id;
  1504. sp_params.update_vport_active_rx_flg =
  1505. params->update_vport_active_flg;
  1506. sp_params.update_vport_active_tx_flg =
  1507. params->update_vport_active_flg;
  1508. sp_params.vport_active_rx_flg = params->vport_active_flg;
  1509. sp_params.vport_active_tx_flg = params->vport_active_flg;
  1510. sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
  1511. sp_params.tx_switching_flg = params->tx_switching_flg;
  1512. sp_params.accept_any_vlan = params->accept_any_vlan;
  1513. sp_params.update_accept_any_vlan_flg =
  1514. params->update_accept_any_vlan_flg;
  1515. /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
  1516. * We need to re-fix the rss values per engine for CMT.
  1517. */
  1518. if (cdev->num_hwfns > 1 && params->update_rss_flg) {
  1519. struct qed_update_vport_rss_params *rss =
  1520. &params->rss_params;
  1521. int k, max = 0;
  1522. /* Find largest entry, since it's possible RSS needs to
  1523. * be disabled [in case only 1 queue per-hwfn]
  1524. */
  1525. for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
  1526. max = (max > rss->rss_ind_table[k]) ?
  1527. max : rss->rss_ind_table[k];
  1528. /* Either fix RSS values or disable RSS */
  1529. if (cdev->num_hwfns < max + 1) {
  1530. int divisor = (max + cdev->num_hwfns - 1) /
  1531. cdev->num_hwfns;
  1532. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1533. "CMT - fixing RSS values (modulo %02x)\n",
  1534. divisor);
  1535. for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
  1536. rss->rss_ind_table[k] =
  1537. rss->rss_ind_table[k] % divisor;
  1538. } else {
  1539. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1540. "CMT - 1 queue per-hwfn; Disabling RSS\n");
  1541. params->update_rss_flg = 0;
  1542. }
  1543. }
  1544. /* Now, update the RSS configuration for actual configuration */
  1545. if (params->update_rss_flg) {
  1546. sp_rss_params.update_rss_config = 1;
  1547. sp_rss_params.rss_enable = 1;
  1548. sp_rss_params.update_rss_capabilities = 1;
  1549. sp_rss_params.update_rss_ind_table = 1;
  1550. sp_rss_params.update_rss_key = 1;
  1551. sp_rss_params.rss_caps = params->rss_params.rss_caps;
  1552. sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
  1553. memcpy(sp_rss_params.rss_ind_table,
  1554. params->rss_params.rss_ind_table,
  1555. QED_RSS_IND_TABLE_SIZE * sizeof(u16));
  1556. memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
  1557. QED_RSS_KEY_SIZE * sizeof(u32));
  1558. }
  1559. sp_params.rss_params = &sp_rss_params;
  1560. for_each_hwfn(cdev, i) {
  1561. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1562. sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1563. rc = qed_sp_vport_update(p_hwfn, &sp_params,
  1564. QED_SPQ_MODE_EBLOCK,
  1565. NULL);
  1566. if (rc) {
  1567. DP_ERR(cdev, "Failed to update VPORT\n");
  1568. return rc;
  1569. }
  1570. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1571. "Updated V-PORT %d: active_flag %d [update %d]\n",
  1572. params->vport_id, params->vport_active_flg,
  1573. params->update_vport_active_flg);
  1574. }
  1575. return 0;
  1576. }
  1577. static int qed_start_rxq(struct qed_dev *cdev,
  1578. struct qed_queue_start_common_params *params,
  1579. u16 bd_max_bytes,
  1580. dma_addr_t bd_chain_phys_addr,
  1581. dma_addr_t cqe_pbl_addr,
  1582. u16 cqe_pbl_size,
  1583. void __iomem **pp_prod)
  1584. {
  1585. int rc, hwfn_index;
  1586. struct qed_hwfn *p_hwfn;
  1587. hwfn_index = params->rss_id % cdev->num_hwfns;
  1588. p_hwfn = &cdev->hwfns[hwfn_index];
  1589. /* Fix queue ID in 100g mode */
  1590. params->queue_id /= cdev->num_hwfns;
  1591. rc = qed_sp_eth_rx_queue_start(p_hwfn,
  1592. p_hwfn->hw_info.opaque_fid,
  1593. params,
  1594. bd_max_bytes,
  1595. bd_chain_phys_addr,
  1596. cqe_pbl_addr,
  1597. cqe_pbl_size,
  1598. pp_prod);
  1599. if (rc) {
  1600. DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
  1601. return rc;
  1602. }
  1603. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1604. "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
  1605. params->queue_id, params->rss_id, params->vport_id,
  1606. params->sb);
  1607. return 0;
  1608. }
  1609. static int qed_stop_rxq(struct qed_dev *cdev,
  1610. struct qed_stop_rxq_params *params)
  1611. {
  1612. int rc, hwfn_index;
  1613. struct qed_hwfn *p_hwfn;
  1614. hwfn_index = params->rss_id % cdev->num_hwfns;
  1615. p_hwfn = &cdev->hwfns[hwfn_index];
  1616. rc = qed_sp_eth_rx_queue_stop(p_hwfn,
  1617. params->rx_queue_id / cdev->num_hwfns,
  1618. params->eq_completion_only,
  1619. false);
  1620. if (rc) {
  1621. DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
  1622. return rc;
  1623. }
  1624. return 0;
  1625. }
  1626. static int qed_start_txq(struct qed_dev *cdev,
  1627. struct qed_queue_start_common_params *p_params,
  1628. dma_addr_t pbl_addr,
  1629. u16 pbl_size,
  1630. void __iomem **pp_doorbell)
  1631. {
  1632. struct qed_hwfn *p_hwfn;
  1633. int rc, hwfn_index;
  1634. hwfn_index = p_params->rss_id % cdev->num_hwfns;
  1635. p_hwfn = &cdev->hwfns[hwfn_index];
  1636. /* Fix queue ID in 100g mode */
  1637. p_params->queue_id /= cdev->num_hwfns;
  1638. rc = qed_sp_eth_tx_queue_start(p_hwfn,
  1639. p_hwfn->hw_info.opaque_fid,
  1640. p_params,
  1641. pbl_addr,
  1642. pbl_size,
  1643. pp_doorbell);
  1644. if (rc) {
  1645. DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
  1646. return rc;
  1647. }
  1648. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1649. "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
  1650. p_params->queue_id, p_params->rss_id, p_params->vport_id,
  1651. p_params->sb);
  1652. return 0;
  1653. }
  1654. #define QED_HW_STOP_RETRY_LIMIT (10)
  1655. static int qed_fastpath_stop(struct qed_dev *cdev)
  1656. {
  1657. qed_hw_stop_fastpath(cdev);
  1658. return 0;
  1659. }
  1660. static int qed_stop_txq(struct qed_dev *cdev,
  1661. struct qed_stop_txq_params *params)
  1662. {
  1663. struct qed_hwfn *p_hwfn;
  1664. int rc, hwfn_index;
  1665. hwfn_index = params->rss_id % cdev->num_hwfns;
  1666. p_hwfn = &cdev->hwfns[hwfn_index];
  1667. rc = qed_sp_eth_tx_queue_stop(p_hwfn,
  1668. params->tx_queue_id / cdev->num_hwfns);
  1669. if (rc) {
  1670. DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
  1671. return rc;
  1672. }
  1673. return 0;
  1674. }
  1675. static int qed_tunn_configure(struct qed_dev *cdev,
  1676. struct qed_tunn_params *tunn_params)
  1677. {
  1678. struct qed_tunn_update_params tunn_info;
  1679. int i, rc;
  1680. if (IS_VF(cdev))
  1681. return 0;
  1682. memset(&tunn_info, 0, sizeof(tunn_info));
  1683. if (tunn_params->update_vxlan_port == 1) {
  1684. tunn_info.update_vxlan_udp_port = 1;
  1685. tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
  1686. }
  1687. if (tunn_params->update_geneve_port == 1) {
  1688. tunn_info.update_geneve_udp_port = 1;
  1689. tunn_info.geneve_udp_port = tunn_params->geneve_port;
  1690. }
  1691. for_each_hwfn(cdev, i) {
  1692. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  1693. rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
  1694. QED_SPQ_MODE_EBLOCK, NULL);
  1695. if (rc)
  1696. return rc;
  1697. }
  1698. return 0;
  1699. }
  1700. static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
  1701. enum qed_filter_rx_mode_type type)
  1702. {
  1703. struct qed_filter_accept_flags accept_flags;
  1704. memset(&accept_flags, 0, sizeof(accept_flags));
  1705. accept_flags.update_rx_mode_config = 1;
  1706. accept_flags.update_tx_mode_config = 1;
  1707. accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1708. QED_ACCEPT_MCAST_MATCHED |
  1709. QED_ACCEPT_BCAST;
  1710. accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1711. QED_ACCEPT_MCAST_MATCHED |
  1712. QED_ACCEPT_BCAST;
  1713. if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
  1714. accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
  1715. QED_ACCEPT_MCAST_UNMATCHED;
  1716. else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
  1717. accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  1718. return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
  1719. QED_SPQ_MODE_CB, NULL);
  1720. }
  1721. static int qed_configure_filter_ucast(struct qed_dev *cdev,
  1722. struct qed_filter_ucast_params *params)
  1723. {
  1724. struct qed_filter_ucast ucast;
  1725. if (!params->vlan_valid && !params->mac_valid) {
  1726. DP_NOTICE(
  1727. cdev,
  1728. "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
  1729. return -EINVAL;
  1730. }
  1731. memset(&ucast, 0, sizeof(ucast));
  1732. switch (params->type) {
  1733. case QED_FILTER_XCAST_TYPE_ADD:
  1734. ucast.opcode = QED_FILTER_ADD;
  1735. break;
  1736. case QED_FILTER_XCAST_TYPE_DEL:
  1737. ucast.opcode = QED_FILTER_REMOVE;
  1738. break;
  1739. case QED_FILTER_XCAST_TYPE_REPLACE:
  1740. ucast.opcode = QED_FILTER_REPLACE;
  1741. break;
  1742. default:
  1743. DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
  1744. params->type);
  1745. }
  1746. if (params->vlan_valid && params->mac_valid) {
  1747. ucast.type = QED_FILTER_MAC_VLAN;
  1748. ether_addr_copy(ucast.mac, params->mac);
  1749. ucast.vlan = params->vlan;
  1750. } else if (params->mac_valid) {
  1751. ucast.type = QED_FILTER_MAC;
  1752. ether_addr_copy(ucast.mac, params->mac);
  1753. } else {
  1754. ucast.type = QED_FILTER_VLAN;
  1755. ucast.vlan = params->vlan;
  1756. }
  1757. ucast.is_rx_filter = true;
  1758. ucast.is_tx_filter = true;
  1759. return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
  1760. }
  1761. static int qed_configure_filter_mcast(struct qed_dev *cdev,
  1762. struct qed_filter_mcast_params *params)
  1763. {
  1764. struct qed_filter_mcast mcast;
  1765. int i;
  1766. memset(&mcast, 0, sizeof(mcast));
  1767. switch (params->type) {
  1768. case QED_FILTER_XCAST_TYPE_ADD:
  1769. mcast.opcode = QED_FILTER_ADD;
  1770. break;
  1771. case QED_FILTER_XCAST_TYPE_DEL:
  1772. mcast.opcode = QED_FILTER_REMOVE;
  1773. break;
  1774. default:
  1775. DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
  1776. params->type);
  1777. }
  1778. mcast.num_mc_addrs = params->num;
  1779. for (i = 0; i < mcast.num_mc_addrs; i++)
  1780. ether_addr_copy(mcast.mac[i], params->mac[i]);
  1781. return qed_filter_mcast_cmd(cdev, &mcast,
  1782. QED_SPQ_MODE_CB, NULL);
  1783. }
  1784. static int qed_configure_filter(struct qed_dev *cdev,
  1785. struct qed_filter_params *params)
  1786. {
  1787. enum qed_filter_rx_mode_type accept_flags;
  1788. switch (params->type) {
  1789. case QED_FILTER_TYPE_UCAST:
  1790. return qed_configure_filter_ucast(cdev, &params->filter.ucast);
  1791. case QED_FILTER_TYPE_MCAST:
  1792. return qed_configure_filter_mcast(cdev, &params->filter.mcast);
  1793. case QED_FILTER_TYPE_RX_MODE:
  1794. accept_flags = params->filter.accept_flags;
  1795. return qed_configure_filter_rx_mode(cdev, accept_flags);
  1796. default:
  1797. DP_NOTICE(cdev, "Unknown filter type %d\n",
  1798. (int)params->type);
  1799. return -EINVAL;
  1800. }
  1801. }
  1802. static int qed_fp_cqe_completion(struct qed_dev *dev,
  1803. u8 rss_id,
  1804. struct eth_slow_path_rx_cqe *cqe)
  1805. {
  1806. return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
  1807. cqe);
  1808. }
  1809. #ifdef CONFIG_QED_SRIOV
  1810. extern const struct qed_iov_hv_ops qed_iov_ops_pass;
  1811. #endif
  1812. #ifdef CONFIG_DCB
  1813. extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
  1814. #endif
  1815. static const struct qed_eth_ops qed_eth_ops_pass = {
  1816. .common = &qed_common_ops_pass,
  1817. #ifdef CONFIG_QED_SRIOV
  1818. .iov = &qed_iov_ops_pass,
  1819. #endif
  1820. #ifdef CONFIG_DCB
  1821. .dcb = &qed_dcbnl_ops_pass,
  1822. #endif
  1823. .fill_dev_info = &qed_fill_eth_dev_info,
  1824. .register_ops = &qed_register_eth_ops,
  1825. .check_mac = &qed_check_mac,
  1826. .vport_start = &qed_start_vport,
  1827. .vport_stop = &qed_stop_vport,
  1828. .vport_update = &qed_update_vport,
  1829. .q_rx_start = &qed_start_rxq,
  1830. .q_rx_stop = &qed_stop_rxq,
  1831. .q_tx_start = &qed_start_txq,
  1832. .q_tx_stop = &qed_stop_txq,
  1833. .filter_config = &qed_configure_filter,
  1834. .fastpath_stop = &qed_fastpath_stop,
  1835. .eth_cqe_completion = &qed_fp_cqe_completion,
  1836. .get_vport_stats = &qed_get_vport_stats,
  1837. .tunn_config = &qed_tunn_configure,
  1838. };
  1839. const struct qed_eth_ops *qed_get_eth_ops(void)
  1840. {
  1841. return &qed_eth_ops_pass;
  1842. }
  1843. EXPORT_SYMBOL(qed_get_eth_ops);
  1844. void qed_put_eth_ops(void)
  1845. {
  1846. /* TODO - reference count for module? */
  1847. }
  1848. EXPORT_SYMBOL(qed_put_eth_ops);