mtk_eth_soc.c 46 KB

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  1. /* This program is free software; you can redistribute it and/or modify
  2. * it under the terms of the GNU General Public License as published by
  3. * the Free Software Foundation; version 2 of the License
  4. *
  5. * This program is distributed in the hope that it will be useful,
  6. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  7. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  8. * GNU General Public License for more details.
  9. *
  10. * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
  11. * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
  12. * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
  13. */
  14. #include <linux/of_device.h>
  15. #include <linux/of_mdio.h>
  16. #include <linux/of_net.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/regmap.h>
  19. #include <linux/clk.h>
  20. #include <linux/if_vlan.h>
  21. #include <linux/reset.h>
  22. #include <linux/tcp.h>
  23. #include "mtk_eth_soc.h"
  24. static int mtk_msg_level = -1;
  25. module_param_named(msg_level, mtk_msg_level, int, 0);
  26. MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  27. #define MTK_ETHTOOL_STAT(x) { #x, \
  28. offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
  29. /* strings used by ethtool */
  30. static const struct mtk_ethtool_stats {
  31. char str[ETH_GSTRING_LEN];
  32. u32 offset;
  33. } mtk_ethtool_stats[] = {
  34. MTK_ETHTOOL_STAT(tx_bytes),
  35. MTK_ETHTOOL_STAT(tx_packets),
  36. MTK_ETHTOOL_STAT(tx_skip),
  37. MTK_ETHTOOL_STAT(tx_collisions),
  38. MTK_ETHTOOL_STAT(rx_bytes),
  39. MTK_ETHTOOL_STAT(rx_packets),
  40. MTK_ETHTOOL_STAT(rx_overflow),
  41. MTK_ETHTOOL_STAT(rx_fcs_errors),
  42. MTK_ETHTOOL_STAT(rx_short_errors),
  43. MTK_ETHTOOL_STAT(rx_long_errors),
  44. MTK_ETHTOOL_STAT(rx_checksum_errors),
  45. MTK_ETHTOOL_STAT(rx_flow_control_packets),
  46. };
  47. void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
  48. {
  49. __raw_writel(val, eth->base + reg);
  50. }
  51. u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
  52. {
  53. return __raw_readl(eth->base + reg);
  54. }
  55. static int mtk_mdio_busy_wait(struct mtk_eth *eth)
  56. {
  57. unsigned long t_start = jiffies;
  58. while (1) {
  59. if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
  60. return 0;
  61. if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
  62. break;
  63. usleep_range(10, 20);
  64. }
  65. dev_err(eth->dev, "mdio: MDIO timeout\n");
  66. return -1;
  67. }
  68. static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
  69. u32 phy_register, u32 write_data)
  70. {
  71. if (mtk_mdio_busy_wait(eth))
  72. return -1;
  73. write_data &= 0xffff;
  74. mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
  75. (phy_register << PHY_IAC_REG_SHIFT) |
  76. (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
  77. MTK_PHY_IAC);
  78. if (mtk_mdio_busy_wait(eth))
  79. return -1;
  80. return 0;
  81. }
  82. static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
  83. {
  84. u32 d;
  85. if (mtk_mdio_busy_wait(eth))
  86. return 0xffff;
  87. mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
  88. (phy_reg << PHY_IAC_REG_SHIFT) |
  89. (phy_addr << PHY_IAC_ADDR_SHIFT),
  90. MTK_PHY_IAC);
  91. if (mtk_mdio_busy_wait(eth))
  92. return 0xffff;
  93. d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
  94. return d;
  95. }
  96. static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
  97. int phy_reg, u16 val)
  98. {
  99. struct mtk_eth *eth = bus->priv;
  100. return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
  101. }
  102. static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
  103. {
  104. struct mtk_eth *eth = bus->priv;
  105. return _mtk_mdio_read(eth, phy_addr, phy_reg);
  106. }
  107. static void mtk_phy_link_adjust(struct net_device *dev)
  108. {
  109. struct mtk_mac *mac = netdev_priv(dev);
  110. u16 lcl_adv = 0, rmt_adv = 0;
  111. u8 flowctrl;
  112. u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
  113. MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
  114. MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
  115. MAC_MCR_BACKPR_EN;
  116. switch (mac->phy_dev->speed) {
  117. case SPEED_1000:
  118. mcr |= MAC_MCR_SPEED_1000;
  119. break;
  120. case SPEED_100:
  121. mcr |= MAC_MCR_SPEED_100;
  122. break;
  123. };
  124. if (mac->phy_dev->link)
  125. mcr |= MAC_MCR_FORCE_LINK;
  126. if (mac->phy_dev->duplex) {
  127. mcr |= MAC_MCR_FORCE_DPX;
  128. if (mac->phy_dev->pause)
  129. rmt_adv = LPA_PAUSE_CAP;
  130. if (mac->phy_dev->asym_pause)
  131. rmt_adv |= LPA_PAUSE_ASYM;
  132. if (mac->phy_dev->advertising & ADVERTISED_Pause)
  133. lcl_adv |= ADVERTISE_PAUSE_CAP;
  134. if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
  135. lcl_adv |= ADVERTISE_PAUSE_ASYM;
  136. flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  137. if (flowctrl & FLOW_CTRL_TX)
  138. mcr |= MAC_MCR_FORCE_TX_FC;
  139. if (flowctrl & FLOW_CTRL_RX)
  140. mcr |= MAC_MCR_FORCE_RX_FC;
  141. netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
  142. flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
  143. flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
  144. }
  145. mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
  146. if (mac->phy_dev->link)
  147. netif_carrier_on(dev);
  148. else
  149. netif_carrier_off(dev);
  150. }
  151. static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
  152. struct device_node *phy_node)
  153. {
  154. const __be32 *_addr = NULL;
  155. struct phy_device *phydev;
  156. int phy_mode, addr;
  157. _addr = of_get_property(phy_node, "reg", NULL);
  158. if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
  159. pr_err("%s: invalid phy address\n", phy_node->name);
  160. return -EINVAL;
  161. }
  162. addr = be32_to_cpu(*_addr);
  163. phy_mode = of_get_phy_mode(phy_node);
  164. if (phy_mode < 0) {
  165. dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
  166. return -EINVAL;
  167. }
  168. phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
  169. mtk_phy_link_adjust, 0, phy_mode);
  170. if (!phydev) {
  171. dev_err(eth->dev, "could not connect to PHY\n");
  172. return -ENODEV;
  173. }
  174. dev_info(eth->dev,
  175. "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
  176. mac->id, phydev_name(phydev), phydev->phy_id,
  177. phydev->drv->name);
  178. mac->phy_dev = phydev;
  179. return 0;
  180. }
  181. static int mtk_phy_connect(struct mtk_mac *mac)
  182. {
  183. struct mtk_eth *eth = mac->hw;
  184. struct device_node *np;
  185. u32 val, ge_mode;
  186. np = of_parse_phandle(mac->of_node, "phy-handle", 0);
  187. if (!np && of_phy_is_fixed_link(mac->of_node))
  188. if (!of_phy_register_fixed_link(mac->of_node))
  189. np = of_node_get(mac->of_node);
  190. if (!np)
  191. return -ENODEV;
  192. switch (of_get_phy_mode(np)) {
  193. case PHY_INTERFACE_MODE_RGMII_TXID:
  194. case PHY_INTERFACE_MODE_RGMII_RXID:
  195. case PHY_INTERFACE_MODE_RGMII_ID:
  196. case PHY_INTERFACE_MODE_RGMII:
  197. ge_mode = 0;
  198. break;
  199. case PHY_INTERFACE_MODE_MII:
  200. ge_mode = 1;
  201. break;
  202. case PHY_INTERFACE_MODE_REVMII:
  203. ge_mode = 2;
  204. break;
  205. case PHY_INTERFACE_MODE_RMII:
  206. if (!mac->id)
  207. goto err_phy;
  208. ge_mode = 3;
  209. break;
  210. default:
  211. goto err_phy;
  212. }
  213. /* put the gmac into the right mode */
  214. regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
  215. val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
  216. val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
  217. regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
  218. mtk_phy_connect_node(eth, mac, np);
  219. mac->phy_dev->autoneg = AUTONEG_ENABLE;
  220. mac->phy_dev->speed = 0;
  221. mac->phy_dev->duplex = 0;
  222. if (of_phy_is_fixed_link(mac->of_node))
  223. mac->phy_dev->supported |=
  224. SUPPORTED_Pause | SUPPORTED_Asym_Pause;
  225. mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
  226. SUPPORTED_Asym_Pause;
  227. mac->phy_dev->advertising = mac->phy_dev->supported |
  228. ADVERTISED_Autoneg;
  229. phy_start_aneg(mac->phy_dev);
  230. of_node_put(np);
  231. return 0;
  232. err_phy:
  233. of_node_put(np);
  234. dev_err(eth->dev, "invalid phy_mode\n");
  235. return -EINVAL;
  236. }
  237. static int mtk_mdio_init(struct mtk_eth *eth)
  238. {
  239. struct device_node *mii_np;
  240. int err;
  241. mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
  242. if (!mii_np) {
  243. dev_err(eth->dev, "no %s child node found", "mdio-bus");
  244. return -ENODEV;
  245. }
  246. if (!of_device_is_available(mii_np)) {
  247. err = 0;
  248. goto err_put_node;
  249. }
  250. eth->mii_bus = mdiobus_alloc();
  251. if (!eth->mii_bus) {
  252. err = -ENOMEM;
  253. goto err_put_node;
  254. }
  255. eth->mii_bus->name = "mdio";
  256. eth->mii_bus->read = mtk_mdio_read;
  257. eth->mii_bus->write = mtk_mdio_write;
  258. eth->mii_bus->priv = eth;
  259. eth->mii_bus->parent = eth->dev;
  260. snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
  261. err = of_mdiobus_register(eth->mii_bus, mii_np);
  262. if (err)
  263. goto err_free_bus;
  264. return 0;
  265. err_free_bus:
  266. mdiobus_free(eth->mii_bus);
  267. err_put_node:
  268. of_node_put(mii_np);
  269. eth->mii_bus = NULL;
  270. return err;
  271. }
  272. static void mtk_mdio_cleanup(struct mtk_eth *eth)
  273. {
  274. if (!eth->mii_bus)
  275. return;
  276. mdiobus_unregister(eth->mii_bus);
  277. of_node_put(eth->mii_bus->dev.of_node);
  278. mdiobus_free(eth->mii_bus);
  279. }
  280. static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
  281. {
  282. unsigned long flags;
  283. u32 val;
  284. spin_lock_irqsave(&eth->irq_lock, flags);
  285. val = mtk_r32(eth, MTK_QDMA_INT_MASK);
  286. mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
  287. spin_unlock_irqrestore(&eth->irq_lock, flags);
  288. }
  289. static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
  290. {
  291. unsigned long flags;
  292. u32 val;
  293. spin_lock_irqsave(&eth->irq_lock, flags);
  294. val = mtk_r32(eth, MTK_QDMA_INT_MASK);
  295. mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
  296. spin_unlock_irqrestore(&eth->irq_lock, flags);
  297. }
  298. static int mtk_set_mac_address(struct net_device *dev, void *p)
  299. {
  300. int ret = eth_mac_addr(dev, p);
  301. struct mtk_mac *mac = netdev_priv(dev);
  302. const char *macaddr = dev->dev_addr;
  303. unsigned long flags;
  304. if (ret)
  305. return ret;
  306. spin_lock_irqsave(&mac->hw->page_lock, flags);
  307. mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
  308. MTK_GDMA_MAC_ADRH(mac->id));
  309. mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
  310. (macaddr[4] << 8) | macaddr[5],
  311. MTK_GDMA_MAC_ADRL(mac->id));
  312. spin_unlock_irqrestore(&mac->hw->page_lock, flags);
  313. return 0;
  314. }
  315. void mtk_stats_update_mac(struct mtk_mac *mac)
  316. {
  317. struct mtk_hw_stats *hw_stats = mac->hw_stats;
  318. unsigned int base = MTK_GDM1_TX_GBCNT;
  319. u64 stats;
  320. base += hw_stats->reg_offset;
  321. u64_stats_update_begin(&hw_stats->syncp);
  322. hw_stats->rx_bytes += mtk_r32(mac->hw, base);
  323. stats = mtk_r32(mac->hw, base + 0x04);
  324. if (stats)
  325. hw_stats->rx_bytes += (stats << 32);
  326. hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
  327. hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
  328. hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
  329. hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
  330. hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
  331. hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
  332. hw_stats->rx_flow_control_packets +=
  333. mtk_r32(mac->hw, base + 0x24);
  334. hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
  335. hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
  336. hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
  337. stats = mtk_r32(mac->hw, base + 0x34);
  338. if (stats)
  339. hw_stats->tx_bytes += (stats << 32);
  340. hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
  341. u64_stats_update_end(&hw_stats->syncp);
  342. }
  343. static void mtk_stats_update(struct mtk_eth *eth)
  344. {
  345. int i;
  346. for (i = 0; i < MTK_MAC_COUNT; i++) {
  347. if (!eth->mac[i] || !eth->mac[i]->hw_stats)
  348. continue;
  349. if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
  350. mtk_stats_update_mac(eth->mac[i]);
  351. spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
  352. }
  353. }
  354. }
  355. static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
  356. struct rtnl_link_stats64 *storage)
  357. {
  358. struct mtk_mac *mac = netdev_priv(dev);
  359. struct mtk_hw_stats *hw_stats = mac->hw_stats;
  360. unsigned int start;
  361. if (netif_running(dev) && netif_device_present(dev)) {
  362. if (spin_trylock(&hw_stats->stats_lock)) {
  363. mtk_stats_update_mac(mac);
  364. spin_unlock(&hw_stats->stats_lock);
  365. }
  366. }
  367. do {
  368. start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
  369. storage->rx_packets = hw_stats->rx_packets;
  370. storage->tx_packets = hw_stats->tx_packets;
  371. storage->rx_bytes = hw_stats->rx_bytes;
  372. storage->tx_bytes = hw_stats->tx_bytes;
  373. storage->collisions = hw_stats->tx_collisions;
  374. storage->rx_length_errors = hw_stats->rx_short_errors +
  375. hw_stats->rx_long_errors;
  376. storage->rx_over_errors = hw_stats->rx_overflow;
  377. storage->rx_crc_errors = hw_stats->rx_fcs_errors;
  378. storage->rx_errors = hw_stats->rx_checksum_errors;
  379. storage->tx_aborted_errors = hw_stats->tx_skip;
  380. } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
  381. storage->tx_errors = dev->stats.tx_errors;
  382. storage->rx_dropped = dev->stats.rx_dropped;
  383. storage->tx_dropped = dev->stats.tx_dropped;
  384. return storage;
  385. }
  386. static inline int mtk_max_frag_size(int mtu)
  387. {
  388. /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
  389. if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
  390. mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
  391. return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
  392. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  393. }
  394. static inline int mtk_max_buf_size(int frag_size)
  395. {
  396. int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
  397. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  398. WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
  399. return buf_size;
  400. }
  401. static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
  402. struct mtk_rx_dma *dma_rxd)
  403. {
  404. rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  405. rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
  406. rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  407. rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
  408. }
  409. /* the qdma core needs scratch memory to be setup */
  410. static int mtk_init_fq_dma(struct mtk_eth *eth)
  411. {
  412. dma_addr_t phy_ring_tail;
  413. int cnt = MTK_DMA_SIZE;
  414. dma_addr_t dma_addr;
  415. int i;
  416. eth->scratch_ring = dma_alloc_coherent(eth->dev,
  417. cnt * sizeof(struct mtk_tx_dma),
  418. &eth->phy_scratch_ring,
  419. GFP_ATOMIC | __GFP_ZERO);
  420. if (unlikely(!eth->scratch_ring))
  421. return -ENOMEM;
  422. eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
  423. GFP_KERNEL);
  424. if (unlikely(!eth->scratch_head))
  425. return -ENOMEM;
  426. dma_addr = dma_map_single(eth->dev,
  427. eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
  428. DMA_FROM_DEVICE);
  429. if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
  430. return -ENOMEM;
  431. memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
  432. phy_ring_tail = eth->phy_scratch_ring +
  433. (sizeof(struct mtk_tx_dma) * (cnt - 1));
  434. for (i = 0; i < cnt; i++) {
  435. eth->scratch_ring[i].txd1 =
  436. (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
  437. if (i < cnt - 1)
  438. eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
  439. ((i + 1) * sizeof(struct mtk_tx_dma)));
  440. eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
  441. }
  442. mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
  443. mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
  444. mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
  445. mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
  446. return 0;
  447. }
  448. static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
  449. {
  450. void *ret = ring->dma;
  451. return ret + (desc - ring->phys);
  452. }
  453. static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
  454. struct mtk_tx_dma *txd)
  455. {
  456. int idx = txd - ring->dma;
  457. return &ring->buf[idx];
  458. }
  459. static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
  460. {
  461. if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
  462. dma_unmap_single(eth->dev,
  463. dma_unmap_addr(tx_buf, dma_addr0),
  464. dma_unmap_len(tx_buf, dma_len0),
  465. DMA_TO_DEVICE);
  466. } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
  467. dma_unmap_page(eth->dev,
  468. dma_unmap_addr(tx_buf, dma_addr0),
  469. dma_unmap_len(tx_buf, dma_len0),
  470. DMA_TO_DEVICE);
  471. }
  472. tx_buf->flags = 0;
  473. if (tx_buf->skb &&
  474. (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
  475. dev_kfree_skb_any(tx_buf->skb);
  476. tx_buf->skb = NULL;
  477. }
  478. static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  479. int tx_num, struct mtk_tx_ring *ring, bool gso)
  480. {
  481. struct mtk_mac *mac = netdev_priv(dev);
  482. struct mtk_eth *eth = mac->hw;
  483. struct mtk_tx_dma *itxd, *txd;
  484. struct mtk_tx_buf *tx_buf;
  485. dma_addr_t mapped_addr;
  486. unsigned int nr_frags;
  487. int i, n_desc = 1;
  488. u32 txd4 = 0;
  489. itxd = ring->next_free;
  490. if (itxd == ring->last_free)
  491. return -ENOMEM;
  492. /* set the forward port */
  493. txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
  494. tx_buf = mtk_desc_to_tx_buf(ring, itxd);
  495. memset(tx_buf, 0, sizeof(*tx_buf));
  496. if (gso)
  497. txd4 |= TX_DMA_TSO;
  498. /* TX Checksum offload */
  499. if (skb->ip_summed == CHECKSUM_PARTIAL)
  500. txd4 |= TX_DMA_CHKSUM;
  501. /* VLAN header offload */
  502. if (skb_vlan_tag_present(skb))
  503. txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
  504. mapped_addr = dma_map_single(eth->dev, skb->data,
  505. skb_headlen(skb), DMA_TO_DEVICE);
  506. if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
  507. return -ENOMEM;
  508. WRITE_ONCE(itxd->txd1, mapped_addr);
  509. tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
  510. dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
  511. dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
  512. /* TX SG offload */
  513. txd = itxd;
  514. nr_frags = skb_shinfo(skb)->nr_frags;
  515. for (i = 0; i < nr_frags; i++) {
  516. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
  517. unsigned int offset = 0;
  518. int frag_size = skb_frag_size(frag);
  519. while (frag_size) {
  520. bool last_frag = false;
  521. unsigned int frag_map_size;
  522. txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
  523. if (txd == ring->last_free)
  524. goto err_dma;
  525. n_desc++;
  526. frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
  527. mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
  528. frag_map_size,
  529. DMA_TO_DEVICE);
  530. if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
  531. goto err_dma;
  532. if (i == nr_frags - 1 &&
  533. (frag_size - frag_map_size) == 0)
  534. last_frag = true;
  535. WRITE_ONCE(txd->txd1, mapped_addr);
  536. WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
  537. TX_DMA_PLEN0(frag_map_size) |
  538. last_frag * TX_DMA_LS0));
  539. WRITE_ONCE(txd->txd4, 0);
  540. tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
  541. tx_buf = mtk_desc_to_tx_buf(ring, txd);
  542. memset(tx_buf, 0, sizeof(*tx_buf));
  543. tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
  544. dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
  545. dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
  546. frag_size -= frag_map_size;
  547. offset += frag_map_size;
  548. }
  549. }
  550. /* store skb to cleanup */
  551. tx_buf->skb = skb;
  552. WRITE_ONCE(itxd->txd4, txd4);
  553. WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
  554. (!nr_frags * TX_DMA_LS0)));
  555. netdev_sent_queue(dev, skb->len);
  556. skb_tx_timestamp(skb);
  557. ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
  558. atomic_sub(n_desc, &ring->free_count);
  559. /* make sure that all changes to the dma ring are flushed before we
  560. * continue
  561. */
  562. wmb();
  563. if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
  564. mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
  565. return 0;
  566. err_dma:
  567. do {
  568. tx_buf = mtk_desc_to_tx_buf(ring, itxd);
  569. /* unmap dma */
  570. mtk_tx_unmap(eth, tx_buf);
  571. itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
  572. itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
  573. } while (itxd != txd);
  574. return -ENOMEM;
  575. }
  576. static inline int mtk_cal_txd_req(struct sk_buff *skb)
  577. {
  578. int i, nfrags;
  579. struct skb_frag_struct *frag;
  580. nfrags = 1;
  581. if (skb_is_gso(skb)) {
  582. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  583. frag = &skb_shinfo(skb)->frags[i];
  584. nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
  585. }
  586. } else {
  587. nfrags += skb_shinfo(skb)->nr_frags;
  588. }
  589. return nfrags;
  590. }
  591. static int mtk_queue_stopped(struct mtk_eth *eth)
  592. {
  593. int i;
  594. for (i = 0; i < MTK_MAC_COUNT; i++) {
  595. if (!eth->netdev[i])
  596. continue;
  597. if (netif_queue_stopped(eth->netdev[i]))
  598. return 1;
  599. }
  600. return 0;
  601. }
  602. static void mtk_wake_queue(struct mtk_eth *eth)
  603. {
  604. int i;
  605. for (i = 0; i < MTK_MAC_COUNT; i++) {
  606. if (!eth->netdev[i])
  607. continue;
  608. netif_wake_queue(eth->netdev[i]);
  609. }
  610. }
  611. static void mtk_stop_queue(struct mtk_eth *eth)
  612. {
  613. int i;
  614. for (i = 0; i < MTK_MAC_COUNT; i++) {
  615. if (!eth->netdev[i])
  616. continue;
  617. netif_stop_queue(eth->netdev[i]);
  618. }
  619. }
  620. static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  621. {
  622. struct mtk_mac *mac = netdev_priv(dev);
  623. struct mtk_eth *eth = mac->hw;
  624. struct mtk_tx_ring *ring = &eth->tx_ring;
  625. struct net_device_stats *stats = &dev->stats;
  626. unsigned long flags;
  627. bool gso = false;
  628. int tx_num;
  629. /* normally we can rely on the stack not calling this more than once,
  630. * however we have 2 queues running on the same ring so we need to lock
  631. * the ring access
  632. */
  633. spin_lock_irqsave(&eth->page_lock, flags);
  634. tx_num = mtk_cal_txd_req(skb);
  635. if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
  636. mtk_stop_queue(eth);
  637. netif_err(eth, tx_queued, dev,
  638. "Tx Ring full when queue awake!\n");
  639. spin_unlock_irqrestore(&eth->page_lock, flags);
  640. return NETDEV_TX_BUSY;
  641. }
  642. /* TSO: fill MSS info in tcp checksum field */
  643. if (skb_is_gso(skb)) {
  644. if (skb_cow_head(skb, 0)) {
  645. netif_warn(eth, tx_err, dev,
  646. "GSO expand head fail.\n");
  647. goto drop;
  648. }
  649. if (skb_shinfo(skb)->gso_type &
  650. (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
  651. gso = true;
  652. tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
  653. }
  654. }
  655. if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
  656. goto drop;
  657. if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
  658. mtk_stop_queue(eth);
  659. spin_unlock_irqrestore(&eth->page_lock, flags);
  660. return NETDEV_TX_OK;
  661. drop:
  662. spin_unlock_irqrestore(&eth->page_lock, flags);
  663. stats->tx_dropped++;
  664. dev_kfree_skb(skb);
  665. return NETDEV_TX_OK;
  666. }
  667. static int mtk_poll_rx(struct napi_struct *napi, int budget,
  668. struct mtk_eth *eth)
  669. {
  670. struct mtk_rx_ring *ring = &eth->rx_ring;
  671. int idx = ring->calc_idx;
  672. struct sk_buff *skb;
  673. u8 *data, *new_data;
  674. struct mtk_rx_dma *rxd, trxd;
  675. int done = 0;
  676. while (done < budget) {
  677. struct net_device *netdev;
  678. unsigned int pktlen;
  679. dma_addr_t dma_addr;
  680. int mac = 0;
  681. idx = NEXT_RX_DESP_IDX(idx);
  682. rxd = &ring->dma[idx];
  683. data = ring->data[idx];
  684. mtk_rx_get_desc(&trxd, rxd);
  685. if (!(trxd.rxd2 & RX_DMA_DONE))
  686. break;
  687. /* find out which mac the packet come from. values start at 1 */
  688. mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
  689. RX_DMA_FPORT_MASK;
  690. mac--;
  691. netdev = eth->netdev[mac];
  692. /* alloc new buffer */
  693. new_data = napi_alloc_frag(ring->frag_size);
  694. if (unlikely(!new_data)) {
  695. netdev->stats.rx_dropped++;
  696. goto release_desc;
  697. }
  698. dma_addr = dma_map_single(eth->dev,
  699. new_data + NET_SKB_PAD,
  700. ring->buf_size,
  701. DMA_FROM_DEVICE);
  702. if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
  703. skb_free_frag(new_data);
  704. netdev->stats.rx_dropped++;
  705. goto release_desc;
  706. }
  707. /* receive data */
  708. skb = build_skb(data, ring->frag_size);
  709. if (unlikely(!skb)) {
  710. put_page(virt_to_head_page(new_data));
  711. netdev->stats.rx_dropped++;
  712. goto release_desc;
  713. }
  714. skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
  715. dma_unmap_single(eth->dev, trxd.rxd1,
  716. ring->buf_size, DMA_FROM_DEVICE);
  717. pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
  718. skb->dev = netdev;
  719. skb_put(skb, pktlen);
  720. if (trxd.rxd4 & RX_DMA_L4_VALID)
  721. skb->ip_summed = CHECKSUM_UNNECESSARY;
  722. else
  723. skb_checksum_none_assert(skb);
  724. skb->protocol = eth_type_trans(skb, netdev);
  725. if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
  726. RX_DMA_VID(trxd.rxd3))
  727. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  728. RX_DMA_VID(trxd.rxd3));
  729. napi_gro_receive(napi, skb);
  730. ring->data[idx] = new_data;
  731. rxd->rxd1 = (unsigned int)dma_addr;
  732. release_desc:
  733. rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
  734. ring->calc_idx = idx;
  735. /* make sure that all changes to the dma ring are flushed before
  736. * we continue
  737. */
  738. wmb();
  739. mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
  740. done++;
  741. }
  742. if (done < budget)
  743. mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
  744. return done;
  745. }
  746. static int mtk_poll_tx(struct mtk_eth *eth, int budget)
  747. {
  748. struct mtk_tx_ring *ring = &eth->tx_ring;
  749. struct mtk_tx_dma *desc;
  750. struct sk_buff *skb;
  751. struct mtk_tx_buf *tx_buf;
  752. unsigned int done[MTK_MAX_DEVS];
  753. unsigned int bytes[MTK_MAX_DEVS];
  754. u32 cpu, dma;
  755. static int condition;
  756. int total = 0, i;
  757. memset(done, 0, sizeof(done));
  758. memset(bytes, 0, sizeof(bytes));
  759. cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
  760. dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
  761. desc = mtk_qdma_phys_to_virt(ring, cpu);
  762. while ((cpu != dma) && budget) {
  763. u32 next_cpu = desc->txd2;
  764. int mac;
  765. desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
  766. if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
  767. break;
  768. mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
  769. TX_DMA_FPORT_MASK;
  770. mac--;
  771. tx_buf = mtk_desc_to_tx_buf(ring, desc);
  772. skb = tx_buf->skb;
  773. if (!skb) {
  774. condition = 1;
  775. break;
  776. }
  777. if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
  778. bytes[mac] += skb->len;
  779. done[mac]++;
  780. budget--;
  781. }
  782. mtk_tx_unmap(eth, tx_buf);
  783. ring->last_free = desc;
  784. atomic_inc(&ring->free_count);
  785. cpu = next_cpu;
  786. }
  787. mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
  788. for (i = 0; i < MTK_MAC_COUNT; i++) {
  789. if (!eth->netdev[i] || !done[i])
  790. continue;
  791. netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
  792. total += done[i];
  793. }
  794. if (mtk_queue_stopped(eth) &&
  795. (atomic_read(&ring->free_count) > ring->thresh))
  796. mtk_wake_queue(eth);
  797. return total;
  798. }
  799. static void mtk_handle_status_irq(struct mtk_eth *eth)
  800. {
  801. u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
  802. if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
  803. mtk_stats_update(eth);
  804. mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
  805. MTK_INT_STATUS2);
  806. }
  807. }
  808. static int mtk_napi_tx(struct napi_struct *napi, int budget)
  809. {
  810. struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
  811. u32 status, mask;
  812. int tx_done = 0;
  813. mtk_handle_status_irq(eth);
  814. mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
  815. tx_done = mtk_poll_tx(eth, budget);
  816. if (unlikely(netif_msg_intr(eth))) {
  817. status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
  818. mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
  819. dev_info(eth->dev,
  820. "done tx %d, intr 0x%08x/0x%x\n",
  821. tx_done, status, mask);
  822. }
  823. if (tx_done == budget)
  824. return budget;
  825. status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
  826. if (status & MTK_TX_DONE_INT)
  827. return budget;
  828. napi_complete(napi);
  829. mtk_irq_enable(eth, MTK_TX_DONE_INT);
  830. return tx_done;
  831. }
  832. static int mtk_napi_rx(struct napi_struct *napi, int budget)
  833. {
  834. struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
  835. u32 status, mask;
  836. int rx_done = 0;
  837. mtk_handle_status_irq(eth);
  838. mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
  839. rx_done = mtk_poll_rx(napi, budget, eth);
  840. if (unlikely(netif_msg_intr(eth))) {
  841. status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
  842. mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
  843. dev_info(eth->dev,
  844. "done rx %d, intr 0x%08x/0x%x\n",
  845. rx_done, status, mask);
  846. }
  847. if (rx_done == budget)
  848. return budget;
  849. status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
  850. if (status & MTK_RX_DONE_INT)
  851. return budget;
  852. napi_complete(napi);
  853. mtk_irq_enable(eth, MTK_RX_DONE_INT);
  854. return rx_done;
  855. }
  856. static int mtk_tx_alloc(struct mtk_eth *eth)
  857. {
  858. struct mtk_tx_ring *ring = &eth->tx_ring;
  859. int i, sz = sizeof(*ring->dma);
  860. ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
  861. GFP_KERNEL);
  862. if (!ring->buf)
  863. goto no_tx_mem;
  864. ring->dma = dma_alloc_coherent(eth->dev,
  865. MTK_DMA_SIZE * sz,
  866. &ring->phys,
  867. GFP_ATOMIC | __GFP_ZERO);
  868. if (!ring->dma)
  869. goto no_tx_mem;
  870. memset(ring->dma, 0, MTK_DMA_SIZE * sz);
  871. for (i = 0; i < MTK_DMA_SIZE; i++) {
  872. int next = (i + 1) % MTK_DMA_SIZE;
  873. u32 next_ptr = ring->phys + next * sz;
  874. ring->dma[i].txd2 = next_ptr;
  875. ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
  876. }
  877. atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
  878. ring->next_free = &ring->dma[0];
  879. ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
  880. ring->thresh = MAX_SKB_FRAGS;
  881. /* make sure that all changes to the dma ring are flushed before we
  882. * continue
  883. */
  884. wmb();
  885. mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
  886. mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
  887. mtk_w32(eth,
  888. ring->phys + ((MTK_DMA_SIZE - 1) * sz),
  889. MTK_QTX_CRX_PTR);
  890. mtk_w32(eth,
  891. ring->phys + ((MTK_DMA_SIZE - 1) * sz),
  892. MTK_QTX_DRX_PTR);
  893. return 0;
  894. no_tx_mem:
  895. return -ENOMEM;
  896. }
  897. static void mtk_tx_clean(struct mtk_eth *eth)
  898. {
  899. struct mtk_tx_ring *ring = &eth->tx_ring;
  900. int i;
  901. if (ring->buf) {
  902. for (i = 0; i < MTK_DMA_SIZE; i++)
  903. mtk_tx_unmap(eth, &ring->buf[i]);
  904. kfree(ring->buf);
  905. ring->buf = NULL;
  906. }
  907. if (ring->dma) {
  908. dma_free_coherent(eth->dev,
  909. MTK_DMA_SIZE * sizeof(*ring->dma),
  910. ring->dma,
  911. ring->phys);
  912. ring->dma = NULL;
  913. }
  914. }
  915. static int mtk_rx_alloc(struct mtk_eth *eth)
  916. {
  917. struct mtk_rx_ring *ring = &eth->rx_ring;
  918. int i;
  919. ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
  920. ring->buf_size = mtk_max_buf_size(ring->frag_size);
  921. ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
  922. GFP_KERNEL);
  923. if (!ring->data)
  924. return -ENOMEM;
  925. for (i = 0; i < MTK_DMA_SIZE; i++) {
  926. ring->data[i] = netdev_alloc_frag(ring->frag_size);
  927. if (!ring->data[i])
  928. return -ENOMEM;
  929. }
  930. ring->dma = dma_alloc_coherent(eth->dev,
  931. MTK_DMA_SIZE * sizeof(*ring->dma),
  932. &ring->phys,
  933. GFP_ATOMIC | __GFP_ZERO);
  934. if (!ring->dma)
  935. return -ENOMEM;
  936. for (i = 0; i < MTK_DMA_SIZE; i++) {
  937. dma_addr_t dma_addr = dma_map_single(eth->dev,
  938. ring->data[i] + NET_SKB_PAD,
  939. ring->buf_size,
  940. DMA_FROM_DEVICE);
  941. if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
  942. return -ENOMEM;
  943. ring->dma[i].rxd1 = (unsigned int)dma_addr;
  944. ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
  945. }
  946. ring->calc_idx = MTK_DMA_SIZE - 1;
  947. /* make sure that all changes to the dma ring are flushed before we
  948. * continue
  949. */
  950. wmb();
  951. mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
  952. mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
  953. mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
  954. mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
  955. mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
  956. return 0;
  957. }
  958. static void mtk_rx_clean(struct mtk_eth *eth)
  959. {
  960. struct mtk_rx_ring *ring = &eth->rx_ring;
  961. int i;
  962. if (ring->data && ring->dma) {
  963. for (i = 0; i < MTK_DMA_SIZE; i++) {
  964. if (!ring->data[i])
  965. continue;
  966. if (!ring->dma[i].rxd1)
  967. continue;
  968. dma_unmap_single(eth->dev,
  969. ring->dma[i].rxd1,
  970. ring->buf_size,
  971. DMA_FROM_DEVICE);
  972. skb_free_frag(ring->data[i]);
  973. }
  974. kfree(ring->data);
  975. ring->data = NULL;
  976. }
  977. if (ring->dma) {
  978. dma_free_coherent(eth->dev,
  979. MTK_DMA_SIZE * sizeof(*ring->dma),
  980. ring->dma,
  981. ring->phys);
  982. ring->dma = NULL;
  983. }
  984. }
  985. /* wait for DMA to finish whatever it is doing before we start using it again */
  986. static int mtk_dma_busy_wait(struct mtk_eth *eth)
  987. {
  988. unsigned long t_start = jiffies;
  989. while (1) {
  990. if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
  991. (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
  992. return 0;
  993. if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
  994. break;
  995. }
  996. dev_err(eth->dev, "DMA init timeout\n");
  997. return -1;
  998. }
  999. static int mtk_dma_init(struct mtk_eth *eth)
  1000. {
  1001. int err;
  1002. if (mtk_dma_busy_wait(eth))
  1003. return -EBUSY;
  1004. /* QDMA needs scratch memory for internal reordering of the
  1005. * descriptors
  1006. */
  1007. err = mtk_init_fq_dma(eth);
  1008. if (err)
  1009. return err;
  1010. err = mtk_tx_alloc(eth);
  1011. if (err)
  1012. return err;
  1013. err = mtk_rx_alloc(eth);
  1014. if (err)
  1015. return err;
  1016. /* Enable random early drop and set drop threshold automatically */
  1017. mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
  1018. MTK_QDMA_FC_THRES);
  1019. mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
  1020. return 0;
  1021. }
  1022. static void mtk_dma_free(struct mtk_eth *eth)
  1023. {
  1024. int i;
  1025. for (i = 0; i < MTK_MAC_COUNT; i++)
  1026. if (eth->netdev[i])
  1027. netdev_reset_queue(eth->netdev[i]);
  1028. if (eth->scratch_ring) {
  1029. dma_free_coherent(eth->dev,
  1030. MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
  1031. eth->scratch_ring,
  1032. eth->phy_scratch_ring);
  1033. eth->scratch_ring = NULL;
  1034. eth->phy_scratch_ring = 0;
  1035. }
  1036. mtk_tx_clean(eth);
  1037. mtk_rx_clean(eth);
  1038. kfree(eth->scratch_head);
  1039. }
  1040. static void mtk_tx_timeout(struct net_device *dev)
  1041. {
  1042. struct mtk_mac *mac = netdev_priv(dev);
  1043. struct mtk_eth *eth = mac->hw;
  1044. eth->netdev[mac->id]->stats.tx_errors++;
  1045. netif_err(eth, tx_err, dev,
  1046. "transmit timed out\n");
  1047. schedule_work(&eth->pending_work);
  1048. }
  1049. static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
  1050. {
  1051. struct mtk_eth *eth = _eth;
  1052. if (likely(napi_schedule_prep(&eth->rx_napi))) {
  1053. __napi_schedule(&eth->rx_napi);
  1054. mtk_irq_disable(eth, MTK_RX_DONE_INT);
  1055. }
  1056. return IRQ_HANDLED;
  1057. }
  1058. static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
  1059. {
  1060. struct mtk_eth *eth = _eth;
  1061. if (likely(napi_schedule_prep(&eth->tx_napi))) {
  1062. __napi_schedule(&eth->tx_napi);
  1063. mtk_irq_disable(eth, MTK_TX_DONE_INT);
  1064. }
  1065. return IRQ_HANDLED;
  1066. }
  1067. #ifdef CONFIG_NET_POLL_CONTROLLER
  1068. static void mtk_poll_controller(struct net_device *dev)
  1069. {
  1070. struct mtk_mac *mac = netdev_priv(dev);
  1071. struct mtk_eth *eth = mac->hw;
  1072. u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
  1073. mtk_irq_disable(eth, int_mask);
  1074. mtk_handle_irq_rx(eth->irq[2], dev);
  1075. mtk_irq_enable(eth, int_mask);
  1076. }
  1077. #endif
  1078. static int mtk_start_dma(struct mtk_eth *eth)
  1079. {
  1080. int err;
  1081. err = mtk_dma_init(eth);
  1082. if (err) {
  1083. mtk_dma_free(eth);
  1084. return err;
  1085. }
  1086. mtk_w32(eth,
  1087. MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
  1088. MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
  1089. MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
  1090. MTK_QDMA_GLO_CFG);
  1091. return 0;
  1092. }
  1093. static int mtk_open(struct net_device *dev)
  1094. {
  1095. struct mtk_mac *mac = netdev_priv(dev);
  1096. struct mtk_eth *eth = mac->hw;
  1097. /* we run 2 netdevs on the same dma ring so we only bring it up once */
  1098. if (!atomic_read(&eth->dma_refcnt)) {
  1099. int err = mtk_start_dma(eth);
  1100. if (err)
  1101. return err;
  1102. napi_enable(&eth->tx_napi);
  1103. napi_enable(&eth->rx_napi);
  1104. mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
  1105. }
  1106. atomic_inc(&eth->dma_refcnt);
  1107. phy_start(mac->phy_dev);
  1108. netif_start_queue(dev);
  1109. return 0;
  1110. }
  1111. static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
  1112. {
  1113. unsigned long flags;
  1114. u32 val;
  1115. int i;
  1116. /* stop the dma engine */
  1117. spin_lock_irqsave(&eth->page_lock, flags);
  1118. val = mtk_r32(eth, glo_cfg);
  1119. mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
  1120. glo_cfg);
  1121. spin_unlock_irqrestore(&eth->page_lock, flags);
  1122. /* wait for dma stop */
  1123. for (i = 0; i < 10; i++) {
  1124. val = mtk_r32(eth, glo_cfg);
  1125. if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
  1126. msleep(20);
  1127. continue;
  1128. }
  1129. break;
  1130. }
  1131. }
  1132. static int mtk_stop(struct net_device *dev)
  1133. {
  1134. struct mtk_mac *mac = netdev_priv(dev);
  1135. struct mtk_eth *eth = mac->hw;
  1136. netif_tx_disable(dev);
  1137. phy_stop(mac->phy_dev);
  1138. /* only shutdown DMA if this is the last user */
  1139. if (!atomic_dec_and_test(&eth->dma_refcnt))
  1140. return 0;
  1141. mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
  1142. napi_disable(&eth->tx_napi);
  1143. napi_disable(&eth->rx_napi);
  1144. mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
  1145. mtk_dma_free(eth);
  1146. return 0;
  1147. }
  1148. static int __init mtk_hw_init(struct mtk_eth *eth)
  1149. {
  1150. int err, i;
  1151. /* reset the frame engine */
  1152. reset_control_assert(eth->rstc);
  1153. usleep_range(10, 20);
  1154. reset_control_deassert(eth->rstc);
  1155. usleep_range(10, 20);
  1156. /* Set GE2 driving and slew rate */
  1157. regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
  1158. /* set GE2 TDSEL */
  1159. regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
  1160. /* set GE2 TUNE */
  1161. regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
  1162. /* GE1, Force 1000M/FD, FC ON */
  1163. mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
  1164. /* GE2, Force 1000M/FD, FC ON */
  1165. mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
  1166. /* Enable RX VLan Offloading */
  1167. mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
  1168. err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
  1169. dev_name(eth->dev), eth);
  1170. if (err)
  1171. return err;
  1172. err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
  1173. dev_name(eth->dev), eth);
  1174. if (err)
  1175. return err;
  1176. err = mtk_mdio_init(eth);
  1177. if (err)
  1178. return err;
  1179. /* disable delay and normal interrupt */
  1180. mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
  1181. mtk_irq_disable(eth, ~0);
  1182. mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
  1183. mtk_w32(eth, 0, MTK_RST_GL);
  1184. /* FE int grouping */
  1185. mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
  1186. mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
  1187. mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
  1188. mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
  1189. mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  1190. for (i = 0; i < 2; i++) {
  1191. u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
  1192. /* setup the forward port to send frame to QDMA */
  1193. val &= ~0xffff;
  1194. val |= 0x5555;
  1195. /* Enable RX checksum */
  1196. val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
  1197. /* setup the mac dma */
  1198. mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
  1199. }
  1200. return 0;
  1201. }
  1202. static int __init mtk_init(struct net_device *dev)
  1203. {
  1204. struct mtk_mac *mac = netdev_priv(dev);
  1205. struct mtk_eth *eth = mac->hw;
  1206. const char *mac_addr;
  1207. mac_addr = of_get_mac_address(mac->of_node);
  1208. if (mac_addr)
  1209. ether_addr_copy(dev->dev_addr, mac_addr);
  1210. /* If the mac address is invalid, use random mac address */
  1211. if (!is_valid_ether_addr(dev->dev_addr)) {
  1212. random_ether_addr(dev->dev_addr);
  1213. dev_err(eth->dev, "generated random MAC address %pM\n",
  1214. dev->dev_addr);
  1215. dev->addr_assign_type = NET_ADDR_RANDOM;
  1216. }
  1217. return mtk_phy_connect(mac);
  1218. }
  1219. static void mtk_uninit(struct net_device *dev)
  1220. {
  1221. struct mtk_mac *mac = netdev_priv(dev);
  1222. struct mtk_eth *eth = mac->hw;
  1223. phy_disconnect(mac->phy_dev);
  1224. mtk_mdio_cleanup(eth);
  1225. mtk_irq_disable(eth, ~0);
  1226. free_irq(eth->irq[1], dev);
  1227. free_irq(eth->irq[2], dev);
  1228. }
  1229. static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1230. {
  1231. struct mtk_mac *mac = netdev_priv(dev);
  1232. switch (cmd) {
  1233. case SIOCGMIIPHY:
  1234. case SIOCGMIIREG:
  1235. case SIOCSMIIREG:
  1236. return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
  1237. default:
  1238. break;
  1239. }
  1240. return -EOPNOTSUPP;
  1241. }
  1242. static void mtk_pending_work(struct work_struct *work)
  1243. {
  1244. struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
  1245. int err, i;
  1246. unsigned long restart = 0;
  1247. rtnl_lock();
  1248. /* stop all devices to make sure that dma is properly shut down */
  1249. for (i = 0; i < MTK_MAC_COUNT; i++) {
  1250. if (!eth->netdev[i])
  1251. continue;
  1252. mtk_stop(eth->netdev[i]);
  1253. __set_bit(i, &restart);
  1254. }
  1255. /* restart DMA and enable IRQs */
  1256. for (i = 0; i < MTK_MAC_COUNT; i++) {
  1257. if (!test_bit(i, &restart))
  1258. continue;
  1259. err = mtk_open(eth->netdev[i]);
  1260. if (err) {
  1261. netif_alert(eth, ifup, eth->netdev[i],
  1262. "Driver up/down cycle failed, closing device.\n");
  1263. dev_close(eth->netdev[i]);
  1264. }
  1265. }
  1266. rtnl_unlock();
  1267. }
  1268. static int mtk_cleanup(struct mtk_eth *eth)
  1269. {
  1270. int i;
  1271. for (i = 0; i < MTK_MAC_COUNT; i++) {
  1272. if (!eth->netdev[i])
  1273. continue;
  1274. unregister_netdev(eth->netdev[i]);
  1275. free_netdev(eth->netdev[i]);
  1276. }
  1277. cancel_work_sync(&eth->pending_work);
  1278. return 0;
  1279. }
  1280. static int mtk_get_settings(struct net_device *dev,
  1281. struct ethtool_cmd *cmd)
  1282. {
  1283. struct mtk_mac *mac = netdev_priv(dev);
  1284. int err;
  1285. err = phy_read_status(mac->phy_dev);
  1286. if (err)
  1287. return -ENODEV;
  1288. return phy_ethtool_gset(mac->phy_dev, cmd);
  1289. }
  1290. static int mtk_set_settings(struct net_device *dev,
  1291. struct ethtool_cmd *cmd)
  1292. {
  1293. struct mtk_mac *mac = netdev_priv(dev);
  1294. if (cmd->phy_address != mac->phy_dev->mdio.addr) {
  1295. mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
  1296. cmd->phy_address);
  1297. if (!mac->phy_dev)
  1298. return -ENODEV;
  1299. }
  1300. return phy_ethtool_sset(mac->phy_dev, cmd);
  1301. }
  1302. static void mtk_get_drvinfo(struct net_device *dev,
  1303. struct ethtool_drvinfo *info)
  1304. {
  1305. struct mtk_mac *mac = netdev_priv(dev);
  1306. strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
  1307. strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
  1308. info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
  1309. }
  1310. static u32 mtk_get_msglevel(struct net_device *dev)
  1311. {
  1312. struct mtk_mac *mac = netdev_priv(dev);
  1313. return mac->hw->msg_enable;
  1314. }
  1315. static void mtk_set_msglevel(struct net_device *dev, u32 value)
  1316. {
  1317. struct mtk_mac *mac = netdev_priv(dev);
  1318. mac->hw->msg_enable = value;
  1319. }
  1320. static int mtk_nway_reset(struct net_device *dev)
  1321. {
  1322. struct mtk_mac *mac = netdev_priv(dev);
  1323. return genphy_restart_aneg(mac->phy_dev);
  1324. }
  1325. static u32 mtk_get_link(struct net_device *dev)
  1326. {
  1327. struct mtk_mac *mac = netdev_priv(dev);
  1328. int err;
  1329. err = genphy_update_link(mac->phy_dev);
  1330. if (err)
  1331. return ethtool_op_get_link(dev);
  1332. return mac->phy_dev->link;
  1333. }
  1334. static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  1335. {
  1336. int i;
  1337. switch (stringset) {
  1338. case ETH_SS_STATS:
  1339. for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
  1340. memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
  1341. data += ETH_GSTRING_LEN;
  1342. }
  1343. break;
  1344. }
  1345. }
  1346. static int mtk_get_sset_count(struct net_device *dev, int sset)
  1347. {
  1348. switch (sset) {
  1349. case ETH_SS_STATS:
  1350. return ARRAY_SIZE(mtk_ethtool_stats);
  1351. default:
  1352. return -EOPNOTSUPP;
  1353. }
  1354. }
  1355. static void mtk_get_ethtool_stats(struct net_device *dev,
  1356. struct ethtool_stats *stats, u64 *data)
  1357. {
  1358. struct mtk_mac *mac = netdev_priv(dev);
  1359. struct mtk_hw_stats *hwstats = mac->hw_stats;
  1360. u64 *data_src, *data_dst;
  1361. unsigned int start;
  1362. int i;
  1363. if (netif_running(dev) && netif_device_present(dev)) {
  1364. if (spin_trylock(&hwstats->stats_lock)) {
  1365. mtk_stats_update_mac(mac);
  1366. spin_unlock(&hwstats->stats_lock);
  1367. }
  1368. }
  1369. do {
  1370. data_src = (u64*)hwstats;
  1371. data_dst = data;
  1372. start = u64_stats_fetch_begin_irq(&hwstats->syncp);
  1373. for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
  1374. *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
  1375. } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
  1376. }
  1377. static struct ethtool_ops mtk_ethtool_ops = {
  1378. .get_settings = mtk_get_settings,
  1379. .set_settings = mtk_set_settings,
  1380. .get_drvinfo = mtk_get_drvinfo,
  1381. .get_msglevel = mtk_get_msglevel,
  1382. .set_msglevel = mtk_set_msglevel,
  1383. .nway_reset = mtk_nway_reset,
  1384. .get_link = mtk_get_link,
  1385. .get_strings = mtk_get_strings,
  1386. .get_sset_count = mtk_get_sset_count,
  1387. .get_ethtool_stats = mtk_get_ethtool_stats,
  1388. };
  1389. static const struct net_device_ops mtk_netdev_ops = {
  1390. .ndo_init = mtk_init,
  1391. .ndo_uninit = mtk_uninit,
  1392. .ndo_open = mtk_open,
  1393. .ndo_stop = mtk_stop,
  1394. .ndo_start_xmit = mtk_start_xmit,
  1395. .ndo_set_mac_address = mtk_set_mac_address,
  1396. .ndo_validate_addr = eth_validate_addr,
  1397. .ndo_do_ioctl = mtk_do_ioctl,
  1398. .ndo_change_mtu = eth_change_mtu,
  1399. .ndo_tx_timeout = mtk_tx_timeout,
  1400. .ndo_get_stats64 = mtk_get_stats64,
  1401. #ifdef CONFIG_NET_POLL_CONTROLLER
  1402. .ndo_poll_controller = mtk_poll_controller,
  1403. #endif
  1404. };
  1405. static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  1406. {
  1407. struct mtk_mac *mac;
  1408. const __be32 *_id = of_get_property(np, "reg", NULL);
  1409. int id, err;
  1410. if (!_id) {
  1411. dev_err(eth->dev, "missing mac id\n");
  1412. return -EINVAL;
  1413. }
  1414. id = be32_to_cpup(_id);
  1415. if (id >= MTK_MAC_COUNT) {
  1416. dev_err(eth->dev, "%d is not a valid mac id\n", id);
  1417. return -EINVAL;
  1418. }
  1419. if (eth->netdev[id]) {
  1420. dev_err(eth->dev, "duplicate mac id found: %d\n", id);
  1421. return -EINVAL;
  1422. }
  1423. eth->netdev[id] = alloc_etherdev(sizeof(*mac));
  1424. if (!eth->netdev[id]) {
  1425. dev_err(eth->dev, "alloc_etherdev failed\n");
  1426. return -ENOMEM;
  1427. }
  1428. mac = netdev_priv(eth->netdev[id]);
  1429. eth->mac[id] = mac;
  1430. mac->id = id;
  1431. mac->hw = eth;
  1432. mac->of_node = np;
  1433. mac->hw_stats = devm_kzalloc(eth->dev,
  1434. sizeof(*mac->hw_stats),
  1435. GFP_KERNEL);
  1436. if (!mac->hw_stats) {
  1437. dev_err(eth->dev, "failed to allocate counter memory\n");
  1438. err = -ENOMEM;
  1439. goto free_netdev;
  1440. }
  1441. spin_lock_init(&mac->hw_stats->stats_lock);
  1442. u64_stats_init(&mac->hw_stats->syncp);
  1443. mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
  1444. SET_NETDEV_DEV(eth->netdev[id], eth->dev);
  1445. eth->netdev[id]->watchdog_timeo = 5 * HZ;
  1446. eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
  1447. eth->netdev[id]->base_addr = (unsigned long)eth->base;
  1448. eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
  1449. ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
  1450. eth->netdev[id]->features |= MTK_HW_FEATURES;
  1451. eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
  1452. err = register_netdev(eth->netdev[id]);
  1453. if (err) {
  1454. dev_err(eth->dev, "error bringing up device\n");
  1455. goto free_netdev;
  1456. }
  1457. eth->netdev[id]->irq = eth->irq[0];
  1458. netif_info(eth, probe, eth->netdev[id],
  1459. "mediatek frame engine at 0x%08lx, irq %d\n",
  1460. eth->netdev[id]->base_addr, eth->irq[0]);
  1461. return 0;
  1462. free_netdev:
  1463. free_netdev(eth->netdev[id]);
  1464. return err;
  1465. }
  1466. static int mtk_probe(struct platform_device *pdev)
  1467. {
  1468. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1469. struct device_node *mac_np;
  1470. const struct of_device_id *match;
  1471. struct mtk_soc_data *soc;
  1472. struct mtk_eth *eth;
  1473. int err;
  1474. int i;
  1475. match = of_match_device(of_mtk_match, &pdev->dev);
  1476. soc = (struct mtk_soc_data *)match->data;
  1477. eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
  1478. if (!eth)
  1479. return -ENOMEM;
  1480. eth->base = devm_ioremap_resource(&pdev->dev, res);
  1481. if (IS_ERR(eth->base))
  1482. return PTR_ERR(eth->base);
  1483. spin_lock_init(&eth->page_lock);
  1484. spin_lock_init(&eth->irq_lock);
  1485. eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  1486. "mediatek,ethsys");
  1487. if (IS_ERR(eth->ethsys)) {
  1488. dev_err(&pdev->dev, "no ethsys regmap found\n");
  1489. return PTR_ERR(eth->ethsys);
  1490. }
  1491. eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  1492. "mediatek,pctl");
  1493. if (IS_ERR(eth->pctl)) {
  1494. dev_err(&pdev->dev, "no pctl regmap found\n");
  1495. return PTR_ERR(eth->pctl);
  1496. }
  1497. eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
  1498. if (IS_ERR(eth->rstc)) {
  1499. dev_err(&pdev->dev, "no eth reset found\n");
  1500. return PTR_ERR(eth->rstc);
  1501. }
  1502. for (i = 0; i < 3; i++) {
  1503. eth->irq[i] = platform_get_irq(pdev, i);
  1504. if (eth->irq[i] < 0) {
  1505. dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
  1506. return -ENXIO;
  1507. }
  1508. }
  1509. eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
  1510. eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
  1511. eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
  1512. eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
  1513. if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
  1514. IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
  1515. return -ENODEV;
  1516. clk_prepare_enable(eth->clk_ethif);
  1517. clk_prepare_enable(eth->clk_esw);
  1518. clk_prepare_enable(eth->clk_gp1);
  1519. clk_prepare_enable(eth->clk_gp2);
  1520. eth->dev = &pdev->dev;
  1521. eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
  1522. INIT_WORK(&eth->pending_work, mtk_pending_work);
  1523. err = mtk_hw_init(eth);
  1524. if (err)
  1525. return err;
  1526. for_each_child_of_node(pdev->dev.of_node, mac_np) {
  1527. if (!of_device_is_compatible(mac_np,
  1528. "mediatek,eth-mac"))
  1529. continue;
  1530. if (!of_device_is_available(mac_np))
  1531. continue;
  1532. err = mtk_add_mac(eth, mac_np);
  1533. if (err)
  1534. goto err_free_dev;
  1535. }
  1536. /* we run 2 devices on the same DMA ring so we need a dummy device
  1537. * for NAPI to work
  1538. */
  1539. init_dummy_netdev(&eth->dummy_dev);
  1540. netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
  1541. MTK_NAPI_WEIGHT);
  1542. netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
  1543. MTK_NAPI_WEIGHT);
  1544. platform_set_drvdata(pdev, eth);
  1545. return 0;
  1546. err_free_dev:
  1547. mtk_cleanup(eth);
  1548. return err;
  1549. }
  1550. static int mtk_remove(struct platform_device *pdev)
  1551. {
  1552. struct mtk_eth *eth = platform_get_drvdata(pdev);
  1553. clk_disable_unprepare(eth->clk_ethif);
  1554. clk_disable_unprepare(eth->clk_esw);
  1555. clk_disable_unprepare(eth->clk_gp1);
  1556. clk_disable_unprepare(eth->clk_gp2);
  1557. netif_napi_del(&eth->tx_napi);
  1558. netif_napi_del(&eth->rx_napi);
  1559. mtk_cleanup(eth);
  1560. platform_set_drvdata(pdev, NULL);
  1561. return 0;
  1562. }
  1563. const struct of_device_id of_mtk_match[] = {
  1564. { .compatible = "mediatek,mt7623-eth" },
  1565. {},
  1566. };
  1567. static struct platform_driver mtk_driver = {
  1568. .probe = mtk_probe,
  1569. .remove = mtk_remove,
  1570. .driver = {
  1571. .name = "mtk_soc_eth",
  1572. .of_match_table = of_mtk_match,
  1573. },
  1574. };
  1575. module_platform_driver(mtk_driver);
  1576. MODULE_LICENSE("GPL");
  1577. MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
  1578. MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");