adv7180.c 38 KB

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  1. /*
  2. * adv7180.c Analog Devices ADV7180 video decoder driver
  3. * Copyright (c) 2009 Intel Corporation
  4. * Copyright (C) 2013 Cogent Embedded, Inc.
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/errno.h>
  23. #include <linux/kernel.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/i2c.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <linux/videodev2.h>
  29. #include <media/v4l2-ioctl.h>
  30. #include <media/v4l2-event.h>
  31. #include <media/v4l2-device.h>
  32. #include <media/v4l2-ctrls.h>
  33. #include <linux/mutex.h>
  34. #include <linux/delay.h>
  35. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
  36. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
  37. #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
  38. #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
  39. #define ADV7180_STD_NTSC_J 0x4
  40. #define ADV7180_STD_NTSC_M 0x5
  41. #define ADV7180_STD_PAL60 0x6
  42. #define ADV7180_STD_NTSC_443 0x7
  43. #define ADV7180_STD_PAL_BG 0x8
  44. #define ADV7180_STD_PAL_N 0x9
  45. #define ADV7180_STD_PAL_M 0xa
  46. #define ADV7180_STD_PAL_M_PED 0xb
  47. #define ADV7180_STD_PAL_COMB_N 0xc
  48. #define ADV7180_STD_PAL_COMB_N_PED 0xd
  49. #define ADV7180_STD_PAL_SECAM 0xe
  50. #define ADV7180_STD_PAL_SECAM_PED 0xf
  51. #define ADV7180_REG_INPUT_CONTROL 0x0000
  52. #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
  53. #define ADV7182_REG_INPUT_VIDSEL 0x0002
  54. #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
  55. #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
  56. #define ADV7180_REG_AUTODETECT_ENABLE 0x07
  57. #define ADV7180_AUTODETECT_DEFAULT 0x7f
  58. /* Contrast */
  59. #define ADV7180_REG_CON 0x0008 /*Unsigned */
  60. #define ADV7180_CON_MIN 0
  61. #define ADV7180_CON_DEF 128
  62. #define ADV7180_CON_MAX 255
  63. /* Brightness*/
  64. #define ADV7180_REG_BRI 0x000a /*Signed */
  65. #define ADV7180_BRI_MIN -128
  66. #define ADV7180_BRI_DEF 0
  67. #define ADV7180_BRI_MAX 127
  68. /* Hue */
  69. #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
  70. #define ADV7180_HUE_MIN -127
  71. #define ADV7180_HUE_DEF 0
  72. #define ADV7180_HUE_MAX 128
  73. #define ADV7180_REG_CTRL 0x000e
  74. #define ADV7180_CTRL_IRQ_SPACE 0x20
  75. #define ADV7180_REG_PWR_MAN 0x0f
  76. #define ADV7180_PWR_MAN_ON 0x04
  77. #define ADV7180_PWR_MAN_OFF 0x24
  78. #define ADV7180_PWR_MAN_RES 0x80
  79. #define ADV7180_REG_STATUS1 0x0010
  80. #define ADV7180_STATUS1_IN_LOCK 0x01
  81. #define ADV7180_STATUS1_AUTOD_MASK 0x70
  82. #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
  83. #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  84. #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
  85. #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
  86. #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
  87. #define ADV7180_STATUS1_AUTOD_SECAM 0x50
  88. #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
  89. #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
  90. #define ADV7180_REG_IDENT 0x0011
  91. #define ADV7180_ID_7180 0x18
  92. #define ADV7180_REG_ICONF1 0x2040
  93. #define ADV7180_ICONF1_ACTIVE_LOW 0x01
  94. #define ADV7180_ICONF1_PSYNC_ONLY 0x10
  95. #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
  96. /* Saturation */
  97. #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
  98. #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
  99. #define ADV7180_SAT_MIN 0
  100. #define ADV7180_SAT_DEF 128
  101. #define ADV7180_SAT_MAX 255
  102. #define ADV7180_IRQ1_LOCK 0x01
  103. #define ADV7180_IRQ1_UNLOCK 0x02
  104. #define ADV7180_REG_ISR1 0x2042
  105. #define ADV7180_REG_ICR1 0x2043
  106. #define ADV7180_REG_IMR1 0x2044
  107. #define ADV7180_REG_IMR2 0x2048
  108. #define ADV7180_IRQ3_AD_CHANGE 0x08
  109. #define ADV7180_REG_ISR3 0x204A
  110. #define ADV7180_REG_ICR3 0x204B
  111. #define ADV7180_REG_IMR3 0x204C
  112. #define ADV7180_REG_IMR4 0x2050
  113. #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
  114. #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
  115. #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
  116. #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
  117. #define ADV7180_REG_FLCONTROL 0x40e0
  118. #define ADV7180_FLCONTROL_FL_ENABLE 0x1
  119. #define ADV7180_CSI_REG_PWRDN 0x00
  120. #define ADV7180_CSI_PWRDN 0x80
  121. #define ADV7180_INPUT_CVBS_AIN1 0x00
  122. #define ADV7180_INPUT_CVBS_AIN2 0x01
  123. #define ADV7180_INPUT_CVBS_AIN3 0x02
  124. #define ADV7180_INPUT_CVBS_AIN4 0x03
  125. #define ADV7180_INPUT_CVBS_AIN5 0x04
  126. #define ADV7180_INPUT_CVBS_AIN6 0x05
  127. #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
  128. #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
  129. #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
  130. #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
  131. #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
  132. #define ADV7182_INPUT_CVBS_AIN1 0x00
  133. #define ADV7182_INPUT_CVBS_AIN2 0x01
  134. #define ADV7182_INPUT_CVBS_AIN3 0x02
  135. #define ADV7182_INPUT_CVBS_AIN4 0x03
  136. #define ADV7182_INPUT_CVBS_AIN5 0x04
  137. #define ADV7182_INPUT_CVBS_AIN6 0x05
  138. #define ADV7182_INPUT_CVBS_AIN7 0x06
  139. #define ADV7182_INPUT_CVBS_AIN8 0x07
  140. #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
  141. #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
  142. #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
  143. #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
  144. #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
  145. #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
  146. #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
  147. #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
  148. #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
  149. #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
  150. #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
  151. #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
  152. #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
  153. struct adv7180_state;
  154. #define ADV7180_FLAG_RESET_POWERED BIT(0)
  155. #define ADV7180_FLAG_V2 BIT(1)
  156. #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
  157. #define ADV7180_FLAG_I2P BIT(3)
  158. struct adv7180_chip_info {
  159. unsigned int flags;
  160. unsigned int valid_input_mask;
  161. int (*set_std)(struct adv7180_state *st, unsigned int std);
  162. int (*select_input)(struct adv7180_state *st, unsigned int input);
  163. int (*init)(struct adv7180_state *state);
  164. };
  165. struct adv7180_state {
  166. struct v4l2_ctrl_handler ctrl_hdl;
  167. struct v4l2_subdev sd;
  168. struct media_pad pad;
  169. struct mutex mutex; /* mutual excl. when accessing chip */
  170. int irq;
  171. v4l2_std_id curr_norm;
  172. bool powered;
  173. bool streaming;
  174. u8 input;
  175. struct i2c_client *client;
  176. unsigned int register_page;
  177. struct i2c_client *csi_client;
  178. struct i2c_client *vpp_client;
  179. const struct adv7180_chip_info *chip_info;
  180. enum v4l2_field field;
  181. };
  182. #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
  183. struct adv7180_state, \
  184. ctrl_hdl)->sd)
  185. static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
  186. {
  187. if (state->register_page != page) {
  188. i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
  189. page);
  190. state->register_page = page;
  191. }
  192. return 0;
  193. }
  194. static int adv7180_write(struct adv7180_state *state, unsigned int reg,
  195. unsigned int value)
  196. {
  197. lockdep_assert_held(&state->mutex);
  198. adv7180_select_page(state, reg >> 8);
  199. return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
  200. }
  201. static int adv7180_read(struct adv7180_state *state, unsigned int reg)
  202. {
  203. lockdep_assert_held(&state->mutex);
  204. adv7180_select_page(state, reg >> 8);
  205. return i2c_smbus_read_byte_data(state->client, reg & 0xff);
  206. }
  207. static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
  208. unsigned int value)
  209. {
  210. return i2c_smbus_write_byte_data(state->csi_client, reg, value);
  211. }
  212. static int adv7180_set_video_standard(struct adv7180_state *state,
  213. unsigned int std)
  214. {
  215. return state->chip_info->set_std(state, std);
  216. }
  217. static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
  218. unsigned int value)
  219. {
  220. return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
  221. }
  222. static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
  223. {
  224. /* in case V4L2_IN_ST_NO_SIGNAL */
  225. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  226. return V4L2_STD_UNKNOWN;
  227. switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
  228. case ADV7180_STATUS1_AUTOD_NTSM_M_J:
  229. return V4L2_STD_NTSC;
  230. case ADV7180_STATUS1_AUTOD_NTSC_4_43:
  231. return V4L2_STD_NTSC_443;
  232. case ADV7180_STATUS1_AUTOD_PAL_M:
  233. return V4L2_STD_PAL_M;
  234. case ADV7180_STATUS1_AUTOD_PAL_60:
  235. return V4L2_STD_PAL_60;
  236. case ADV7180_STATUS1_AUTOD_PAL_B_G:
  237. return V4L2_STD_PAL;
  238. case ADV7180_STATUS1_AUTOD_SECAM:
  239. return V4L2_STD_SECAM;
  240. case ADV7180_STATUS1_AUTOD_PAL_COMB:
  241. return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
  242. case ADV7180_STATUS1_AUTOD_SECAM_525:
  243. return V4L2_STD_SECAM;
  244. default:
  245. return V4L2_STD_UNKNOWN;
  246. }
  247. }
  248. static int v4l2_std_to_adv7180(v4l2_std_id std)
  249. {
  250. if (std == V4L2_STD_PAL_60)
  251. return ADV7180_STD_PAL60;
  252. if (std == V4L2_STD_NTSC_443)
  253. return ADV7180_STD_NTSC_443;
  254. if (std == V4L2_STD_PAL_N)
  255. return ADV7180_STD_PAL_N;
  256. if (std == V4L2_STD_PAL_M)
  257. return ADV7180_STD_PAL_M;
  258. if (std == V4L2_STD_PAL_Nc)
  259. return ADV7180_STD_PAL_COMB_N;
  260. if (std & V4L2_STD_PAL)
  261. return ADV7180_STD_PAL_BG;
  262. if (std & V4L2_STD_NTSC)
  263. return ADV7180_STD_NTSC_M;
  264. if (std & V4L2_STD_SECAM)
  265. return ADV7180_STD_PAL_SECAM;
  266. return -EINVAL;
  267. }
  268. static u32 adv7180_status_to_v4l2(u8 status1)
  269. {
  270. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  271. return V4L2_IN_ST_NO_SIGNAL;
  272. return 0;
  273. }
  274. static int __adv7180_status(struct adv7180_state *state, u32 *status,
  275. v4l2_std_id *std)
  276. {
  277. int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
  278. if (status1 < 0)
  279. return status1;
  280. if (status)
  281. *status = adv7180_status_to_v4l2(status1);
  282. if (std)
  283. *std = adv7180_std_to_v4l2(status1);
  284. return 0;
  285. }
  286. static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
  287. {
  288. return container_of(sd, struct adv7180_state, sd);
  289. }
  290. static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  291. {
  292. struct adv7180_state *state = to_state(sd);
  293. int err = mutex_lock_interruptible(&state->mutex);
  294. if (err)
  295. return err;
  296. if (state->streaming) {
  297. err = -EBUSY;
  298. goto unlock;
  299. }
  300. err = adv7180_set_video_standard(state,
  301. ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
  302. if (err)
  303. goto unlock;
  304. msleep(100);
  305. __adv7180_status(state, NULL, std);
  306. err = v4l2_std_to_adv7180(state->curr_norm);
  307. if (err < 0)
  308. goto unlock;
  309. err = adv7180_set_video_standard(state, err);
  310. unlock:
  311. mutex_unlock(&state->mutex);
  312. return err;
  313. }
  314. static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
  315. u32 output, u32 config)
  316. {
  317. struct adv7180_state *state = to_state(sd);
  318. int ret = mutex_lock_interruptible(&state->mutex);
  319. if (ret)
  320. return ret;
  321. if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
  322. ret = -EINVAL;
  323. goto out;
  324. }
  325. ret = state->chip_info->select_input(state, input);
  326. if (ret == 0)
  327. state->input = input;
  328. out:
  329. mutex_unlock(&state->mutex);
  330. return ret;
  331. }
  332. static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
  333. {
  334. struct adv7180_state *state = to_state(sd);
  335. int ret = mutex_lock_interruptible(&state->mutex);
  336. if (ret)
  337. return ret;
  338. ret = __adv7180_status(state, status, NULL);
  339. mutex_unlock(&state->mutex);
  340. return ret;
  341. }
  342. static int adv7180_program_std(struct adv7180_state *state)
  343. {
  344. int ret;
  345. ret = v4l2_std_to_adv7180(state->curr_norm);
  346. if (ret < 0)
  347. return ret;
  348. ret = adv7180_set_video_standard(state, ret);
  349. if (ret < 0)
  350. return ret;
  351. return 0;
  352. }
  353. static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  354. {
  355. struct adv7180_state *state = to_state(sd);
  356. int ret = mutex_lock_interruptible(&state->mutex);
  357. if (ret)
  358. return ret;
  359. /* Make sure we can support this std */
  360. ret = v4l2_std_to_adv7180(std);
  361. if (ret < 0)
  362. goto out;
  363. state->curr_norm = std;
  364. ret = adv7180_program_std(state);
  365. out:
  366. mutex_unlock(&state->mutex);
  367. return ret;
  368. }
  369. static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  370. {
  371. struct adv7180_state *state = to_state(sd);
  372. *norm = state->curr_norm;
  373. return 0;
  374. }
  375. static int adv7180_set_power(struct adv7180_state *state, bool on)
  376. {
  377. u8 val;
  378. int ret;
  379. if (on)
  380. val = ADV7180_PWR_MAN_ON;
  381. else
  382. val = ADV7180_PWR_MAN_OFF;
  383. ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
  384. if (ret)
  385. return ret;
  386. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  387. if (on) {
  388. adv7180_csi_write(state, 0xDE, 0x02);
  389. adv7180_csi_write(state, 0xD2, 0xF7);
  390. adv7180_csi_write(state, 0xD8, 0x65);
  391. adv7180_csi_write(state, 0xE0, 0x09);
  392. adv7180_csi_write(state, 0x2C, 0x00);
  393. if (state->field == V4L2_FIELD_NONE)
  394. adv7180_csi_write(state, 0x1D, 0x80);
  395. adv7180_csi_write(state, 0x00, 0x00);
  396. } else {
  397. adv7180_csi_write(state, 0x00, 0x80);
  398. }
  399. }
  400. return 0;
  401. }
  402. static int adv7180_s_power(struct v4l2_subdev *sd, int on)
  403. {
  404. struct adv7180_state *state = to_state(sd);
  405. int ret;
  406. ret = mutex_lock_interruptible(&state->mutex);
  407. if (ret)
  408. return ret;
  409. ret = adv7180_set_power(state, on);
  410. if (ret == 0)
  411. state->powered = on;
  412. mutex_unlock(&state->mutex);
  413. return ret;
  414. }
  415. static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
  416. {
  417. struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
  418. struct adv7180_state *state = to_state(sd);
  419. int ret = mutex_lock_interruptible(&state->mutex);
  420. int val;
  421. if (ret)
  422. return ret;
  423. val = ctrl->val;
  424. switch (ctrl->id) {
  425. case V4L2_CID_BRIGHTNESS:
  426. ret = adv7180_write(state, ADV7180_REG_BRI, val);
  427. break;
  428. case V4L2_CID_HUE:
  429. /*Hue is inverted according to HSL chart */
  430. ret = adv7180_write(state, ADV7180_REG_HUE, -val);
  431. break;
  432. case V4L2_CID_CONTRAST:
  433. ret = adv7180_write(state, ADV7180_REG_CON, val);
  434. break;
  435. case V4L2_CID_SATURATION:
  436. /*
  437. *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
  438. *Let's not confuse the user, everybody understands saturation
  439. */
  440. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
  441. if (ret < 0)
  442. break;
  443. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
  444. break;
  445. case V4L2_CID_ADV_FAST_SWITCH:
  446. if (ctrl->val) {
  447. /* ADI required write */
  448. adv7180_write(state, 0x80d9, 0x44);
  449. adv7180_write(state, ADV7180_REG_FLCONTROL,
  450. ADV7180_FLCONTROL_FL_ENABLE);
  451. } else {
  452. /* ADI required write */
  453. adv7180_write(state, 0x80d9, 0xc4);
  454. adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
  455. }
  456. break;
  457. default:
  458. ret = -EINVAL;
  459. }
  460. mutex_unlock(&state->mutex);
  461. return ret;
  462. }
  463. static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
  464. .s_ctrl = adv7180_s_ctrl,
  465. };
  466. static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
  467. .ops = &adv7180_ctrl_ops,
  468. .id = V4L2_CID_ADV_FAST_SWITCH,
  469. .name = "Fast Switching",
  470. .type = V4L2_CTRL_TYPE_BOOLEAN,
  471. .min = 0,
  472. .max = 1,
  473. .step = 1,
  474. };
  475. static int adv7180_init_controls(struct adv7180_state *state)
  476. {
  477. v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
  478. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  479. V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
  480. ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
  481. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  482. V4L2_CID_CONTRAST, ADV7180_CON_MIN,
  483. ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
  484. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  485. V4L2_CID_SATURATION, ADV7180_SAT_MIN,
  486. ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
  487. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  488. V4L2_CID_HUE, ADV7180_HUE_MIN,
  489. ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
  490. v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
  491. state->sd.ctrl_handler = &state->ctrl_hdl;
  492. if (state->ctrl_hdl.error) {
  493. int err = state->ctrl_hdl.error;
  494. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  495. return err;
  496. }
  497. v4l2_ctrl_handler_setup(&state->ctrl_hdl);
  498. return 0;
  499. }
  500. static void adv7180_exit_controls(struct adv7180_state *state)
  501. {
  502. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  503. }
  504. static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
  505. struct v4l2_subdev_pad_config *cfg,
  506. struct v4l2_subdev_mbus_code_enum *code)
  507. {
  508. if (code->index != 0)
  509. return -EINVAL;
  510. code->code = MEDIA_BUS_FMT_YUYV8_2X8;
  511. return 0;
  512. }
  513. static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
  514. struct v4l2_mbus_framefmt *fmt)
  515. {
  516. struct adv7180_state *state = to_state(sd);
  517. fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
  518. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  519. fmt->width = 720;
  520. fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
  521. return 0;
  522. }
  523. static int adv7180_set_field_mode(struct adv7180_state *state)
  524. {
  525. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  526. return 0;
  527. if (state->field == V4L2_FIELD_NONE) {
  528. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  529. adv7180_csi_write(state, 0x01, 0x20);
  530. adv7180_csi_write(state, 0x02, 0x28);
  531. adv7180_csi_write(state, 0x03, 0x38);
  532. adv7180_csi_write(state, 0x04, 0x30);
  533. adv7180_csi_write(state, 0x05, 0x30);
  534. adv7180_csi_write(state, 0x06, 0x80);
  535. adv7180_csi_write(state, 0x07, 0x70);
  536. adv7180_csi_write(state, 0x08, 0x50);
  537. }
  538. adv7180_vpp_write(state, 0xa3, 0x00);
  539. adv7180_vpp_write(state, 0x5b, 0x00);
  540. adv7180_vpp_write(state, 0x55, 0x80);
  541. } else {
  542. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  543. adv7180_csi_write(state, 0x01, 0x18);
  544. adv7180_csi_write(state, 0x02, 0x18);
  545. adv7180_csi_write(state, 0x03, 0x30);
  546. adv7180_csi_write(state, 0x04, 0x20);
  547. adv7180_csi_write(state, 0x05, 0x28);
  548. adv7180_csi_write(state, 0x06, 0x40);
  549. adv7180_csi_write(state, 0x07, 0x58);
  550. adv7180_csi_write(state, 0x08, 0x30);
  551. }
  552. adv7180_vpp_write(state, 0xa3, 0x70);
  553. adv7180_vpp_write(state, 0x5b, 0x80);
  554. adv7180_vpp_write(state, 0x55, 0x00);
  555. }
  556. return 0;
  557. }
  558. static int adv7180_get_pad_format(struct v4l2_subdev *sd,
  559. struct v4l2_subdev_pad_config *cfg,
  560. struct v4l2_subdev_format *format)
  561. {
  562. struct adv7180_state *state = to_state(sd);
  563. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  564. format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
  565. } else {
  566. adv7180_mbus_fmt(sd, &format->format);
  567. format->format.field = state->field;
  568. }
  569. return 0;
  570. }
  571. static int adv7180_set_pad_format(struct v4l2_subdev *sd,
  572. struct v4l2_subdev_pad_config *cfg,
  573. struct v4l2_subdev_format *format)
  574. {
  575. struct adv7180_state *state = to_state(sd);
  576. struct v4l2_mbus_framefmt *framefmt;
  577. switch (format->format.field) {
  578. case V4L2_FIELD_NONE:
  579. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  580. format->format.field = V4L2_FIELD_INTERLACED;
  581. break;
  582. default:
  583. format->format.field = V4L2_FIELD_INTERLACED;
  584. break;
  585. }
  586. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  587. framefmt = &format->format;
  588. if (state->field != format->format.field) {
  589. state->field = format->format.field;
  590. adv7180_set_power(state, false);
  591. adv7180_set_field_mode(state);
  592. adv7180_set_power(state, true);
  593. }
  594. } else {
  595. framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
  596. *framefmt = format->format;
  597. }
  598. return adv7180_mbus_fmt(sd, framefmt);
  599. }
  600. static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
  601. struct v4l2_mbus_config *cfg)
  602. {
  603. struct adv7180_state *state = to_state(sd);
  604. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  605. cfg->type = V4L2_MBUS_CSI2;
  606. cfg->flags = V4L2_MBUS_CSI2_1_LANE |
  607. V4L2_MBUS_CSI2_CHANNEL_0 |
  608. V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
  609. } else {
  610. /*
  611. * The ADV7180 sensor supports BT.601/656 output modes.
  612. * The BT.656 is default and not yet configurable by s/w.
  613. */
  614. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  615. V4L2_MBUS_DATA_ACTIVE_HIGH;
  616. cfg->type = V4L2_MBUS_BT656;
  617. }
  618. return 0;
  619. }
  620. static int adv7180_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *cropcap)
  621. {
  622. struct adv7180_state *state = to_state(sd);
  623. if (state->curr_norm & V4L2_STD_525_60) {
  624. cropcap->pixelaspect.numerator = 11;
  625. cropcap->pixelaspect.denominator = 10;
  626. } else {
  627. cropcap->pixelaspect.numerator = 54;
  628. cropcap->pixelaspect.denominator = 59;
  629. }
  630. return 0;
  631. }
  632. static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
  633. {
  634. *norm = V4L2_STD_ALL;
  635. return 0;
  636. }
  637. static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
  638. {
  639. struct adv7180_state *state = to_state(sd);
  640. int ret;
  641. /* It's always safe to stop streaming, no need to take the lock */
  642. if (!enable) {
  643. state->streaming = enable;
  644. return 0;
  645. }
  646. /* Must wait until querystd released the lock */
  647. ret = mutex_lock_interruptible(&state->mutex);
  648. if (ret)
  649. return ret;
  650. state->streaming = enable;
  651. mutex_unlock(&state->mutex);
  652. return 0;
  653. }
  654. static int adv7180_subscribe_event(struct v4l2_subdev *sd,
  655. struct v4l2_fh *fh,
  656. struct v4l2_event_subscription *sub)
  657. {
  658. switch (sub->type) {
  659. case V4L2_EVENT_SOURCE_CHANGE:
  660. return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
  661. case V4L2_EVENT_CTRL:
  662. return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
  663. default:
  664. return -EINVAL;
  665. }
  666. }
  667. static const struct v4l2_subdev_video_ops adv7180_video_ops = {
  668. .s_std = adv7180_s_std,
  669. .g_std = adv7180_g_std,
  670. .querystd = adv7180_querystd,
  671. .g_input_status = adv7180_g_input_status,
  672. .s_routing = adv7180_s_routing,
  673. .g_mbus_config = adv7180_g_mbus_config,
  674. .cropcap = adv7180_cropcap,
  675. .g_tvnorms = adv7180_g_tvnorms,
  676. .s_stream = adv7180_s_stream,
  677. };
  678. static const struct v4l2_subdev_core_ops adv7180_core_ops = {
  679. .s_power = adv7180_s_power,
  680. .subscribe_event = adv7180_subscribe_event,
  681. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  682. };
  683. static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
  684. .enum_mbus_code = adv7180_enum_mbus_code,
  685. .set_fmt = adv7180_set_pad_format,
  686. .get_fmt = adv7180_get_pad_format,
  687. };
  688. static const struct v4l2_subdev_ops adv7180_ops = {
  689. .core = &adv7180_core_ops,
  690. .video = &adv7180_video_ops,
  691. .pad = &adv7180_pad_ops,
  692. };
  693. static irqreturn_t adv7180_irq(int irq, void *devid)
  694. {
  695. struct adv7180_state *state = devid;
  696. u8 isr3;
  697. mutex_lock(&state->mutex);
  698. isr3 = adv7180_read(state, ADV7180_REG_ISR3);
  699. /* clear */
  700. adv7180_write(state, ADV7180_REG_ICR3, isr3);
  701. if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
  702. static const struct v4l2_event src_ch = {
  703. .type = V4L2_EVENT_SOURCE_CHANGE,
  704. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  705. };
  706. v4l2_subdev_notify_event(&state->sd, &src_ch);
  707. }
  708. mutex_unlock(&state->mutex);
  709. return IRQ_HANDLED;
  710. }
  711. static int adv7180_init(struct adv7180_state *state)
  712. {
  713. int ret;
  714. /* ITU-R BT.656-4 compatible */
  715. ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  716. ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
  717. if (ret < 0)
  718. return ret;
  719. /* Manually set V bit end position in NTSC mode */
  720. return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
  721. ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
  722. }
  723. static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
  724. {
  725. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
  726. (std << 4) | state->input);
  727. }
  728. static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
  729. {
  730. int ret;
  731. ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
  732. if (ret < 0)
  733. return ret;
  734. ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
  735. ret |= input;
  736. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
  737. }
  738. static int adv7182_init(struct adv7180_state *state)
  739. {
  740. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  741. adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
  742. ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
  743. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  744. adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
  745. ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
  746. if (state->chip_info->flags & ADV7180_FLAG_V2) {
  747. /* ADI recommended writes for improved video quality */
  748. adv7180_write(state, 0x0080, 0x51);
  749. adv7180_write(state, 0x0081, 0x51);
  750. adv7180_write(state, 0x0082, 0x68);
  751. }
  752. /* ADI required writes */
  753. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  754. adv7180_write(state, 0x0003, 0x4e);
  755. adv7180_write(state, 0x0004, 0x57);
  756. adv7180_write(state, 0x001d, 0xc0);
  757. } else {
  758. if (state->chip_info->flags & ADV7180_FLAG_V2)
  759. adv7180_write(state, 0x0004, 0x17);
  760. else
  761. adv7180_write(state, 0x0004, 0x07);
  762. adv7180_write(state, 0x0003, 0x0c);
  763. adv7180_write(state, 0x001d, 0x40);
  764. }
  765. adv7180_write(state, 0x0013, 0x00);
  766. return 0;
  767. }
  768. static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
  769. {
  770. return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
  771. }
  772. enum adv7182_input_type {
  773. ADV7182_INPUT_TYPE_CVBS,
  774. ADV7182_INPUT_TYPE_DIFF_CVBS,
  775. ADV7182_INPUT_TYPE_SVIDEO,
  776. ADV7182_INPUT_TYPE_YPBPR,
  777. };
  778. static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
  779. {
  780. switch (input) {
  781. case ADV7182_INPUT_CVBS_AIN1:
  782. case ADV7182_INPUT_CVBS_AIN2:
  783. case ADV7182_INPUT_CVBS_AIN3:
  784. case ADV7182_INPUT_CVBS_AIN4:
  785. case ADV7182_INPUT_CVBS_AIN5:
  786. case ADV7182_INPUT_CVBS_AIN6:
  787. case ADV7182_INPUT_CVBS_AIN7:
  788. case ADV7182_INPUT_CVBS_AIN8:
  789. return ADV7182_INPUT_TYPE_CVBS;
  790. case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
  791. case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
  792. case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
  793. case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
  794. return ADV7182_INPUT_TYPE_SVIDEO;
  795. case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
  796. case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
  797. return ADV7182_INPUT_TYPE_YPBPR;
  798. case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
  799. case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
  800. case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
  801. case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
  802. return ADV7182_INPUT_TYPE_DIFF_CVBS;
  803. default: /* Will never happen */
  804. return 0;
  805. }
  806. }
  807. /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
  808. static unsigned int adv7182_lbias_settings[][3] = {
  809. [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
  810. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  811. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  812. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  813. };
  814. static unsigned int adv7280_lbias_settings[][3] = {
  815. [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
  816. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  817. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  818. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  819. };
  820. static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
  821. {
  822. enum adv7182_input_type input_type;
  823. unsigned int *lbias;
  824. unsigned int i;
  825. int ret;
  826. ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
  827. if (ret)
  828. return ret;
  829. /* Reset clamp circuitry - ADI recommended writes */
  830. adv7180_write(state, 0x809c, 0x00);
  831. adv7180_write(state, 0x809c, 0xff);
  832. input_type = adv7182_get_input_type(input);
  833. switch (input_type) {
  834. case ADV7182_INPUT_TYPE_CVBS:
  835. case ADV7182_INPUT_TYPE_DIFF_CVBS:
  836. /* ADI recommends to use the SH1 filter */
  837. adv7180_write(state, 0x0017, 0x41);
  838. break;
  839. default:
  840. adv7180_write(state, 0x0017, 0x01);
  841. break;
  842. }
  843. if (state->chip_info->flags & ADV7180_FLAG_V2)
  844. lbias = adv7280_lbias_settings[input_type];
  845. else
  846. lbias = adv7182_lbias_settings[input_type];
  847. for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
  848. adv7180_write(state, 0x0052 + i, lbias[i]);
  849. if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
  850. /* ADI required writes to make differential CVBS work */
  851. adv7180_write(state, 0x005f, 0xa8);
  852. adv7180_write(state, 0x005a, 0x90);
  853. adv7180_write(state, 0x0060, 0xb0);
  854. adv7180_write(state, 0x80b6, 0x08);
  855. adv7180_write(state, 0x80c0, 0xa0);
  856. } else {
  857. adv7180_write(state, 0x005f, 0xf0);
  858. adv7180_write(state, 0x005a, 0xd0);
  859. adv7180_write(state, 0x0060, 0x10);
  860. adv7180_write(state, 0x80b6, 0x9c);
  861. adv7180_write(state, 0x80c0, 0x00);
  862. }
  863. return 0;
  864. }
  865. static const struct adv7180_chip_info adv7180_info = {
  866. .flags = ADV7180_FLAG_RESET_POWERED,
  867. /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
  868. * all inputs and let the card driver take care of validation
  869. */
  870. .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
  871. BIT(ADV7180_INPUT_CVBS_AIN2) |
  872. BIT(ADV7180_INPUT_CVBS_AIN3) |
  873. BIT(ADV7180_INPUT_CVBS_AIN4) |
  874. BIT(ADV7180_INPUT_CVBS_AIN5) |
  875. BIT(ADV7180_INPUT_CVBS_AIN6) |
  876. BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
  877. BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
  878. BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
  879. BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  880. BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
  881. .init = adv7180_init,
  882. .set_std = adv7180_set_std,
  883. .select_input = adv7180_select_input,
  884. };
  885. static const struct adv7180_chip_info adv7182_info = {
  886. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  887. BIT(ADV7182_INPUT_CVBS_AIN2) |
  888. BIT(ADV7182_INPUT_CVBS_AIN3) |
  889. BIT(ADV7182_INPUT_CVBS_AIN4) |
  890. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  891. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  892. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  893. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  894. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
  895. .init = adv7182_init,
  896. .set_std = adv7182_set_std,
  897. .select_input = adv7182_select_input,
  898. };
  899. static const struct adv7180_chip_info adv7280_info = {
  900. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  901. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  902. BIT(ADV7182_INPUT_CVBS_AIN2) |
  903. BIT(ADV7182_INPUT_CVBS_AIN3) |
  904. BIT(ADV7182_INPUT_CVBS_AIN4) |
  905. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  906. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  907. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
  908. .init = adv7182_init,
  909. .set_std = adv7182_set_std,
  910. .select_input = adv7182_select_input,
  911. };
  912. static const struct adv7180_chip_info adv7280_m_info = {
  913. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  914. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  915. BIT(ADV7182_INPUT_CVBS_AIN2) |
  916. BIT(ADV7182_INPUT_CVBS_AIN3) |
  917. BIT(ADV7182_INPUT_CVBS_AIN4) |
  918. BIT(ADV7182_INPUT_CVBS_AIN5) |
  919. BIT(ADV7182_INPUT_CVBS_AIN6) |
  920. BIT(ADV7182_INPUT_CVBS_AIN7) |
  921. BIT(ADV7182_INPUT_CVBS_AIN8) |
  922. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  923. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  924. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  925. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  926. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  927. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
  928. .init = adv7182_init,
  929. .set_std = adv7182_set_std,
  930. .select_input = adv7182_select_input,
  931. };
  932. static const struct adv7180_chip_info adv7281_info = {
  933. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  934. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  935. BIT(ADV7182_INPUT_CVBS_AIN2) |
  936. BIT(ADV7182_INPUT_CVBS_AIN7) |
  937. BIT(ADV7182_INPUT_CVBS_AIN8) |
  938. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  939. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  940. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  941. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  942. .init = adv7182_init,
  943. .set_std = adv7182_set_std,
  944. .select_input = adv7182_select_input,
  945. };
  946. static const struct adv7180_chip_info adv7281_m_info = {
  947. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  948. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  949. BIT(ADV7182_INPUT_CVBS_AIN2) |
  950. BIT(ADV7182_INPUT_CVBS_AIN3) |
  951. BIT(ADV7182_INPUT_CVBS_AIN4) |
  952. BIT(ADV7182_INPUT_CVBS_AIN7) |
  953. BIT(ADV7182_INPUT_CVBS_AIN8) |
  954. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  955. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  956. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  957. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  958. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  959. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  960. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  961. .init = adv7182_init,
  962. .set_std = adv7182_set_std,
  963. .select_input = adv7182_select_input,
  964. };
  965. static const struct adv7180_chip_info adv7281_ma_info = {
  966. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  967. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  968. BIT(ADV7182_INPUT_CVBS_AIN2) |
  969. BIT(ADV7182_INPUT_CVBS_AIN3) |
  970. BIT(ADV7182_INPUT_CVBS_AIN4) |
  971. BIT(ADV7182_INPUT_CVBS_AIN5) |
  972. BIT(ADV7182_INPUT_CVBS_AIN6) |
  973. BIT(ADV7182_INPUT_CVBS_AIN7) |
  974. BIT(ADV7182_INPUT_CVBS_AIN8) |
  975. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  976. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  977. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  978. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  979. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  980. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
  981. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  982. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  983. BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
  984. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  985. .init = adv7182_init,
  986. .set_std = adv7182_set_std,
  987. .select_input = adv7182_select_input,
  988. };
  989. static const struct adv7180_chip_info adv7282_info = {
  990. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  991. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  992. BIT(ADV7182_INPUT_CVBS_AIN2) |
  993. BIT(ADV7182_INPUT_CVBS_AIN7) |
  994. BIT(ADV7182_INPUT_CVBS_AIN8) |
  995. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  996. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  997. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  998. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  999. .init = adv7182_init,
  1000. .set_std = adv7182_set_std,
  1001. .select_input = adv7182_select_input,
  1002. };
  1003. static const struct adv7180_chip_info adv7282_m_info = {
  1004. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  1005. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1006. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1007. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1008. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1009. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1010. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1011. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1012. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1013. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1014. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1015. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1016. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1017. .init = adv7182_init,
  1018. .set_std = adv7182_set_std,
  1019. .select_input = adv7182_select_input,
  1020. };
  1021. static int init_device(struct adv7180_state *state)
  1022. {
  1023. int ret;
  1024. mutex_lock(&state->mutex);
  1025. adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
  1026. usleep_range(5000, 10000);
  1027. ret = state->chip_info->init(state);
  1028. if (ret)
  1029. goto out_unlock;
  1030. ret = adv7180_program_std(state);
  1031. if (ret)
  1032. goto out_unlock;
  1033. adv7180_set_field_mode(state);
  1034. /* register for interrupts */
  1035. if (state->irq > 0) {
  1036. /* config the Interrupt pin to be active low */
  1037. ret = adv7180_write(state, ADV7180_REG_ICONF1,
  1038. ADV7180_ICONF1_ACTIVE_LOW |
  1039. ADV7180_ICONF1_PSYNC_ONLY);
  1040. if (ret < 0)
  1041. goto out_unlock;
  1042. ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
  1043. if (ret < 0)
  1044. goto out_unlock;
  1045. ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
  1046. if (ret < 0)
  1047. goto out_unlock;
  1048. /* enable AD change interrupts interrupts */
  1049. ret = adv7180_write(state, ADV7180_REG_IMR3,
  1050. ADV7180_IRQ3_AD_CHANGE);
  1051. if (ret < 0)
  1052. goto out_unlock;
  1053. ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
  1054. if (ret < 0)
  1055. goto out_unlock;
  1056. }
  1057. out_unlock:
  1058. mutex_unlock(&state->mutex);
  1059. return ret;
  1060. }
  1061. static int adv7180_probe(struct i2c_client *client,
  1062. const struct i2c_device_id *id)
  1063. {
  1064. struct adv7180_state *state;
  1065. struct v4l2_subdev *sd;
  1066. int ret;
  1067. /* Check if the adapter supports the needed features */
  1068. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  1069. return -EIO;
  1070. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1071. client->addr, client->adapter->name);
  1072. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  1073. if (state == NULL)
  1074. return -ENOMEM;
  1075. state->client = client;
  1076. state->field = V4L2_FIELD_INTERLACED;
  1077. state->chip_info = (struct adv7180_chip_info *)id->driver_data;
  1078. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  1079. state->csi_client = i2c_new_dummy(client->adapter,
  1080. ADV7180_DEFAULT_CSI_I2C_ADDR);
  1081. if (!state->csi_client)
  1082. return -ENOMEM;
  1083. }
  1084. if (state->chip_info->flags & ADV7180_FLAG_I2P) {
  1085. state->vpp_client = i2c_new_dummy(client->adapter,
  1086. ADV7180_DEFAULT_VPP_I2C_ADDR);
  1087. if (!state->vpp_client) {
  1088. ret = -ENOMEM;
  1089. goto err_unregister_csi_client;
  1090. }
  1091. }
  1092. state->irq = client->irq;
  1093. mutex_init(&state->mutex);
  1094. state->curr_norm = V4L2_STD_NTSC;
  1095. if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
  1096. state->powered = true;
  1097. else
  1098. state->powered = false;
  1099. state->input = 0;
  1100. sd = &state->sd;
  1101. v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
  1102. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
  1103. ret = adv7180_init_controls(state);
  1104. if (ret)
  1105. goto err_unregister_vpp_client;
  1106. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  1107. sd->entity.flags |= MEDIA_ENT_F_ATV_DECODER;
  1108. ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
  1109. if (ret)
  1110. goto err_free_ctrl;
  1111. ret = init_device(state);
  1112. if (ret)
  1113. goto err_media_entity_cleanup;
  1114. if (state->irq) {
  1115. ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
  1116. IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
  1117. KBUILD_MODNAME, state);
  1118. if (ret)
  1119. goto err_media_entity_cleanup;
  1120. }
  1121. ret = v4l2_async_register_subdev(sd);
  1122. if (ret)
  1123. goto err_free_irq;
  1124. return 0;
  1125. err_free_irq:
  1126. if (state->irq > 0)
  1127. free_irq(client->irq, state);
  1128. err_media_entity_cleanup:
  1129. media_entity_cleanup(&sd->entity);
  1130. err_free_ctrl:
  1131. adv7180_exit_controls(state);
  1132. err_unregister_vpp_client:
  1133. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1134. i2c_unregister_device(state->vpp_client);
  1135. err_unregister_csi_client:
  1136. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1137. i2c_unregister_device(state->csi_client);
  1138. mutex_destroy(&state->mutex);
  1139. return ret;
  1140. }
  1141. static int adv7180_remove(struct i2c_client *client)
  1142. {
  1143. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1144. struct adv7180_state *state = to_state(sd);
  1145. v4l2_async_unregister_subdev(sd);
  1146. if (state->irq > 0)
  1147. free_irq(client->irq, state);
  1148. media_entity_cleanup(&sd->entity);
  1149. adv7180_exit_controls(state);
  1150. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1151. i2c_unregister_device(state->vpp_client);
  1152. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1153. i2c_unregister_device(state->csi_client);
  1154. mutex_destroy(&state->mutex);
  1155. return 0;
  1156. }
  1157. static const struct i2c_device_id adv7180_id[] = {
  1158. { "adv7180", (kernel_ulong_t)&adv7180_info },
  1159. { "adv7182", (kernel_ulong_t)&adv7182_info },
  1160. { "adv7280", (kernel_ulong_t)&adv7280_info },
  1161. { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
  1162. { "adv7281", (kernel_ulong_t)&adv7281_info },
  1163. { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
  1164. { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
  1165. { "adv7282", (kernel_ulong_t)&adv7282_info },
  1166. { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
  1167. {},
  1168. };
  1169. MODULE_DEVICE_TABLE(i2c, adv7180_id);
  1170. #ifdef CONFIG_PM_SLEEP
  1171. static int adv7180_suspend(struct device *dev)
  1172. {
  1173. struct i2c_client *client = to_i2c_client(dev);
  1174. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1175. struct adv7180_state *state = to_state(sd);
  1176. return adv7180_set_power(state, false);
  1177. }
  1178. static int adv7180_resume(struct device *dev)
  1179. {
  1180. struct i2c_client *client = to_i2c_client(dev);
  1181. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1182. struct adv7180_state *state = to_state(sd);
  1183. int ret;
  1184. ret = init_device(state);
  1185. if (ret < 0)
  1186. return ret;
  1187. ret = adv7180_set_power(state, state->powered);
  1188. if (ret)
  1189. return ret;
  1190. return 0;
  1191. }
  1192. static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
  1193. #define ADV7180_PM_OPS (&adv7180_pm_ops)
  1194. #else
  1195. #define ADV7180_PM_OPS NULL
  1196. #endif
  1197. #ifdef CONFIG_OF
  1198. static const struct of_device_id adv7180_of_id[] = {
  1199. { .compatible = "adi,adv7180", },
  1200. { .compatible = "adi,adv7182", },
  1201. { .compatible = "adi,adv7280", },
  1202. { .compatible = "adi,adv7280-m", },
  1203. { .compatible = "adi,adv7281", },
  1204. { .compatible = "adi,adv7281-m", },
  1205. { .compatible = "adi,adv7281-ma", },
  1206. { .compatible = "adi,adv7282", },
  1207. { .compatible = "adi,adv7282-m", },
  1208. { },
  1209. };
  1210. MODULE_DEVICE_TABLE(of, adv7180_of_id);
  1211. #endif
  1212. static struct i2c_driver adv7180_driver = {
  1213. .driver = {
  1214. .name = KBUILD_MODNAME,
  1215. .pm = ADV7180_PM_OPS,
  1216. .of_match_table = of_match_ptr(adv7180_of_id),
  1217. },
  1218. .probe = adv7180_probe,
  1219. .remove = adv7180_remove,
  1220. .id_table = adv7180_id,
  1221. };
  1222. module_i2c_driver(adv7180_driver);
  1223. MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
  1224. MODULE_AUTHOR("Mocean Laboratories");
  1225. MODULE_LICENSE("GPL v2");