main.c 87 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/rtnetlink.h>
  40. #include <linux/if_vlan.h>
  41. #include <net/ipv6.h>
  42. #include <net/addrconf.h>
  43. #include <net/devlink.h>
  44. #include <rdma/ib_smi.h>
  45. #include <rdma/ib_user_verbs.h>
  46. #include <rdma/ib_addr.h>
  47. #include <rdma/ib_cache.h>
  48. #include <net/bonding.h>
  49. #include <linux/mlx4/driver.h>
  50. #include <linux/mlx4/cmd.h>
  51. #include <linux/mlx4/qp.h>
  52. #include "mlx4_ib.h"
  53. #include "user.h"
  54. #define DRV_NAME MLX4_IB_DRV_NAME
  55. #define DRV_VERSION "2.2-1"
  56. #define DRV_RELDATE "Feb 2014"
  57. #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
  58. #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
  59. #define MLX4_IB_CARD_REV_A0 0xA0
  60. MODULE_AUTHOR("Roland Dreier");
  61. MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
  62. MODULE_LICENSE("Dual BSD/GPL");
  63. MODULE_VERSION(DRV_VERSION);
  64. int mlx4_ib_sm_guid_assign = 0;
  65. module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
  66. MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
  67. static const char mlx4_ib_version[] =
  68. DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
  69. DRV_VERSION " (" DRV_RELDATE ")\n";
  70. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
  71. static struct workqueue_struct *wq;
  72. static void init_query_mad(struct ib_smp *mad)
  73. {
  74. mad->base_version = 1;
  75. mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
  76. mad->class_version = 1;
  77. mad->method = IB_MGMT_METHOD_GET;
  78. }
  79. static int check_flow_steering_support(struct mlx4_dev *dev)
  80. {
  81. int eth_num_ports = 0;
  82. int ib_num_ports = 0;
  83. int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
  84. if (dmfs) {
  85. int i;
  86. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
  87. eth_num_ports++;
  88. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  89. ib_num_ports++;
  90. dmfs &= (!ib_num_ports ||
  91. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
  92. (!eth_num_ports ||
  93. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
  94. if (ib_num_ports && mlx4_is_mfunc(dev)) {
  95. pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
  96. dmfs = 0;
  97. }
  98. }
  99. return dmfs;
  100. }
  101. static int num_ib_ports(struct mlx4_dev *dev)
  102. {
  103. int ib_ports = 0;
  104. int i;
  105. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  106. ib_ports++;
  107. return ib_ports;
  108. }
  109. static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
  110. {
  111. struct mlx4_ib_dev *ibdev = to_mdev(device);
  112. struct net_device *dev;
  113. rcu_read_lock();
  114. dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
  115. if (dev) {
  116. if (mlx4_is_bonded(ibdev->dev)) {
  117. struct net_device *upper = NULL;
  118. upper = netdev_master_upper_dev_get_rcu(dev);
  119. if (upper) {
  120. struct net_device *active;
  121. active = bond_option_active_slave_get_rcu(netdev_priv(upper));
  122. if (active)
  123. dev = active;
  124. }
  125. }
  126. }
  127. if (dev)
  128. dev_hold(dev);
  129. rcu_read_unlock();
  130. return dev;
  131. }
  132. static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
  133. struct mlx4_ib_dev *ibdev,
  134. u8 port_num)
  135. {
  136. struct mlx4_cmd_mailbox *mailbox;
  137. int err;
  138. struct mlx4_dev *dev = ibdev->dev;
  139. int i;
  140. union ib_gid *gid_tbl;
  141. mailbox = mlx4_alloc_cmd_mailbox(dev);
  142. if (IS_ERR(mailbox))
  143. return -ENOMEM;
  144. gid_tbl = mailbox->buf;
  145. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  146. memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
  147. err = mlx4_cmd(dev, mailbox->dma,
  148. MLX4_SET_PORT_GID_TABLE << 8 | port_num,
  149. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  150. MLX4_CMD_WRAPPED);
  151. if (mlx4_is_bonded(dev))
  152. err += mlx4_cmd(dev, mailbox->dma,
  153. MLX4_SET_PORT_GID_TABLE << 8 | 2,
  154. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  155. MLX4_CMD_WRAPPED);
  156. mlx4_free_cmd_mailbox(dev, mailbox);
  157. return err;
  158. }
  159. static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
  160. struct mlx4_ib_dev *ibdev,
  161. u8 port_num)
  162. {
  163. struct mlx4_cmd_mailbox *mailbox;
  164. int err;
  165. struct mlx4_dev *dev = ibdev->dev;
  166. int i;
  167. struct {
  168. union ib_gid gid;
  169. __be32 rsrvd1[2];
  170. __be16 rsrvd2;
  171. u8 type;
  172. u8 version;
  173. __be32 rsrvd3;
  174. } *gid_tbl;
  175. mailbox = mlx4_alloc_cmd_mailbox(dev);
  176. if (IS_ERR(mailbox))
  177. return -ENOMEM;
  178. gid_tbl = mailbox->buf;
  179. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  180. memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
  181. if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
  182. gid_tbl[i].version = 2;
  183. if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
  184. gid_tbl[i].type = 1;
  185. else
  186. memset(&gid_tbl[i].gid, 0, 12);
  187. }
  188. }
  189. err = mlx4_cmd(dev, mailbox->dma,
  190. MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
  191. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  192. MLX4_CMD_WRAPPED);
  193. if (mlx4_is_bonded(dev))
  194. err += mlx4_cmd(dev, mailbox->dma,
  195. MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
  196. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  197. MLX4_CMD_WRAPPED);
  198. mlx4_free_cmd_mailbox(dev, mailbox);
  199. return err;
  200. }
  201. static int mlx4_ib_update_gids(struct gid_entry *gids,
  202. struct mlx4_ib_dev *ibdev,
  203. u8 port_num)
  204. {
  205. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  206. return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
  207. return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
  208. }
  209. static int mlx4_ib_add_gid(struct ib_device *device,
  210. u8 port_num,
  211. unsigned int index,
  212. const union ib_gid *gid,
  213. const struct ib_gid_attr *attr,
  214. void **context)
  215. {
  216. struct mlx4_ib_dev *ibdev = to_mdev(device);
  217. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  218. struct mlx4_port_gid_table *port_gid_table;
  219. int free = -1, found = -1;
  220. int ret = 0;
  221. int hw_update = 0;
  222. int i;
  223. struct gid_entry *gids = NULL;
  224. if (!rdma_cap_roce_gid_table(device, port_num))
  225. return -EINVAL;
  226. if (port_num > MLX4_MAX_PORTS)
  227. return -EINVAL;
  228. if (!context)
  229. return -EINVAL;
  230. port_gid_table = &iboe->gids[port_num - 1];
  231. spin_lock_bh(&iboe->lock);
  232. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  233. if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
  234. (port_gid_table->gids[i].gid_type == attr->gid_type)) {
  235. found = i;
  236. break;
  237. }
  238. if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
  239. free = i; /* HW has space */
  240. }
  241. if (found < 0) {
  242. if (free < 0) {
  243. ret = -ENOSPC;
  244. } else {
  245. port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
  246. if (!port_gid_table->gids[free].ctx) {
  247. ret = -ENOMEM;
  248. } else {
  249. *context = port_gid_table->gids[free].ctx;
  250. memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
  251. port_gid_table->gids[free].gid_type = attr->gid_type;
  252. port_gid_table->gids[free].ctx->real_index = free;
  253. port_gid_table->gids[free].ctx->refcount = 1;
  254. hw_update = 1;
  255. }
  256. }
  257. } else {
  258. struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
  259. *context = ctx;
  260. ctx->refcount++;
  261. }
  262. if (!ret && hw_update) {
  263. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  264. if (!gids) {
  265. ret = -ENOMEM;
  266. } else {
  267. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
  268. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  269. gids[i].gid_type = port_gid_table->gids[i].gid_type;
  270. }
  271. }
  272. }
  273. spin_unlock_bh(&iboe->lock);
  274. if (!ret && hw_update) {
  275. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  276. kfree(gids);
  277. }
  278. return ret;
  279. }
  280. static int mlx4_ib_del_gid(struct ib_device *device,
  281. u8 port_num,
  282. unsigned int index,
  283. void **context)
  284. {
  285. struct gid_cache_context *ctx = *context;
  286. struct mlx4_ib_dev *ibdev = to_mdev(device);
  287. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  288. struct mlx4_port_gid_table *port_gid_table;
  289. int ret = 0;
  290. int hw_update = 0;
  291. struct gid_entry *gids = NULL;
  292. if (!rdma_cap_roce_gid_table(device, port_num))
  293. return -EINVAL;
  294. if (port_num > MLX4_MAX_PORTS)
  295. return -EINVAL;
  296. port_gid_table = &iboe->gids[port_num - 1];
  297. spin_lock_bh(&iboe->lock);
  298. if (ctx) {
  299. ctx->refcount--;
  300. if (!ctx->refcount) {
  301. unsigned int real_index = ctx->real_index;
  302. memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
  303. kfree(port_gid_table->gids[real_index].ctx);
  304. port_gid_table->gids[real_index].ctx = NULL;
  305. hw_update = 1;
  306. }
  307. }
  308. if (!ret && hw_update) {
  309. int i;
  310. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  311. if (!gids) {
  312. ret = -ENOMEM;
  313. } else {
  314. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
  315. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  316. }
  317. }
  318. spin_unlock_bh(&iboe->lock);
  319. if (!ret && hw_update) {
  320. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  321. kfree(gids);
  322. }
  323. return ret;
  324. }
  325. int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
  326. u8 port_num, int index)
  327. {
  328. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  329. struct gid_cache_context *ctx = NULL;
  330. union ib_gid gid;
  331. struct mlx4_port_gid_table *port_gid_table;
  332. int real_index = -EINVAL;
  333. int i;
  334. int ret;
  335. unsigned long flags;
  336. struct ib_gid_attr attr;
  337. if (port_num > MLX4_MAX_PORTS)
  338. return -EINVAL;
  339. if (mlx4_is_bonded(ibdev->dev))
  340. port_num = 1;
  341. if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
  342. return index;
  343. ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
  344. if (ret)
  345. return ret;
  346. if (attr.ndev)
  347. dev_put(attr.ndev);
  348. if (!memcmp(&gid, &zgid, sizeof(gid)))
  349. return -EINVAL;
  350. spin_lock_irqsave(&iboe->lock, flags);
  351. port_gid_table = &iboe->gids[port_num - 1];
  352. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  353. if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
  354. attr.gid_type == port_gid_table->gids[i].gid_type) {
  355. ctx = port_gid_table->gids[i].ctx;
  356. break;
  357. }
  358. if (ctx)
  359. real_index = ctx->real_index;
  360. spin_unlock_irqrestore(&iboe->lock, flags);
  361. return real_index;
  362. }
  363. static int mlx4_ib_query_device(struct ib_device *ibdev,
  364. struct ib_device_attr *props,
  365. struct ib_udata *uhw)
  366. {
  367. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  368. struct ib_smp *in_mad = NULL;
  369. struct ib_smp *out_mad = NULL;
  370. int err = -ENOMEM;
  371. int have_ib_ports;
  372. struct mlx4_uverbs_ex_query_device cmd;
  373. struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
  374. struct mlx4_clock_params clock_params;
  375. if (uhw->inlen) {
  376. if (uhw->inlen < sizeof(cmd))
  377. return -EINVAL;
  378. err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
  379. if (err)
  380. return err;
  381. if (cmd.comp_mask)
  382. return -EINVAL;
  383. if (cmd.reserved)
  384. return -EINVAL;
  385. }
  386. resp.response_length = offsetof(typeof(resp), response_length) +
  387. sizeof(resp.response_length);
  388. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  389. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  390. if (!in_mad || !out_mad)
  391. goto out;
  392. init_query_mad(in_mad);
  393. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  394. err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
  395. 1, NULL, NULL, in_mad, out_mad);
  396. if (err)
  397. goto out;
  398. memset(props, 0, sizeof *props);
  399. have_ib_ports = num_ib_ports(dev->dev);
  400. props->fw_ver = dev->dev->caps.fw_ver;
  401. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  402. IB_DEVICE_PORT_ACTIVE_EVENT |
  403. IB_DEVICE_SYS_IMAGE_GUID |
  404. IB_DEVICE_RC_RNR_NAK_GEN |
  405. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  406. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  407. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  408. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  409. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  410. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
  411. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  412. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
  413. props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  414. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  415. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  416. if (dev->dev->caps.max_gso_sz &&
  417. (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
  418. (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
  419. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  420. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
  421. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  422. if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
  423. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
  424. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
  425. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  426. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
  427. props->device_cap_flags |= IB_DEVICE_XRC;
  428. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
  429. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
  430. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  431. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
  432. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
  433. else
  434. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
  435. }
  436. if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  437. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  438. props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
  439. props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
  440. 0xffffff;
  441. props->vendor_part_id = dev->dev->persist->pdev->device;
  442. props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
  443. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  444. props->max_mr_size = ~0ull;
  445. props->page_size_cap = dev->dev->caps.page_size_cap;
  446. props->max_qp = dev->dev->quotas.qp;
  447. props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
  448. props->max_sge = min(dev->dev->caps.max_sq_sg,
  449. dev->dev->caps.max_rq_sg);
  450. props->max_sge_rd = MLX4_MAX_SGE_RD;
  451. props->max_cq = dev->dev->quotas.cq;
  452. props->max_cqe = dev->dev->caps.max_cqes;
  453. props->max_mr = dev->dev->quotas.mpt;
  454. props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
  455. props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
  456. props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
  457. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  458. props->max_srq = dev->dev->quotas.srq;
  459. props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
  460. props->max_srq_sge = dev->dev->caps.max_srq_sge;
  461. props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
  462. props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
  463. props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
  464. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  465. props->masked_atomic_cap = props->atomic_cap;
  466. props->max_pkeys = dev->dev->caps.pkey_table_len[1];
  467. props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
  468. props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
  469. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  470. props->max_mcast_grp;
  471. props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
  472. props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
  473. props->timestamp_mask = 0xFFFFFFFFFFFFULL;
  474. if (!mlx4_is_slave(dev->dev))
  475. err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
  476. if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
  477. resp.response_length += sizeof(resp.hca_core_clock_offset);
  478. if (!err && !mlx4_is_slave(dev->dev)) {
  479. resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
  480. resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
  481. }
  482. }
  483. if (uhw->outlen) {
  484. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  485. if (err)
  486. goto out;
  487. }
  488. out:
  489. kfree(in_mad);
  490. kfree(out_mad);
  491. return err;
  492. }
  493. static enum rdma_link_layer
  494. mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
  495. {
  496. struct mlx4_dev *dev = to_mdev(device)->dev;
  497. return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
  498. IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
  499. }
  500. static int ib_link_query_port(struct ib_device *ibdev, u8 port,
  501. struct ib_port_attr *props, int netw_view)
  502. {
  503. struct ib_smp *in_mad = NULL;
  504. struct ib_smp *out_mad = NULL;
  505. int ext_active_speed;
  506. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  507. int err = -ENOMEM;
  508. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  509. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  510. if (!in_mad || !out_mad)
  511. goto out;
  512. init_query_mad(in_mad);
  513. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  514. in_mad->attr_mod = cpu_to_be32(port);
  515. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  516. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  517. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  518. in_mad, out_mad);
  519. if (err)
  520. goto out;
  521. props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
  522. props->lmc = out_mad->data[34] & 0x7;
  523. props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
  524. props->sm_sl = out_mad->data[36] & 0xf;
  525. props->state = out_mad->data[32] & 0xf;
  526. props->phys_state = out_mad->data[33] >> 4;
  527. props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
  528. if (netw_view)
  529. props->gid_tbl_len = out_mad->data[50];
  530. else
  531. props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
  532. props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
  533. props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
  534. props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
  535. props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
  536. props->active_width = out_mad->data[31] & 0xf;
  537. props->active_speed = out_mad->data[35] >> 4;
  538. props->max_mtu = out_mad->data[41] & 0xf;
  539. props->active_mtu = out_mad->data[36] >> 4;
  540. props->subnet_timeout = out_mad->data[51] & 0x1f;
  541. props->max_vl_num = out_mad->data[37] >> 4;
  542. props->init_type_reply = out_mad->data[41] >> 4;
  543. /* Check if extended speeds (EDR/FDR/...) are supported */
  544. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  545. ext_active_speed = out_mad->data[62] >> 4;
  546. switch (ext_active_speed) {
  547. case 1:
  548. props->active_speed = IB_SPEED_FDR;
  549. break;
  550. case 2:
  551. props->active_speed = IB_SPEED_EDR;
  552. break;
  553. }
  554. }
  555. /* If reported active speed is QDR, check if is FDR-10 */
  556. if (props->active_speed == IB_SPEED_QDR) {
  557. init_query_mad(in_mad);
  558. in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
  559. in_mad->attr_mod = cpu_to_be32(port);
  560. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
  561. NULL, NULL, in_mad, out_mad);
  562. if (err)
  563. goto out;
  564. /* Checking LinkSpeedActive for FDR-10 */
  565. if (out_mad->data[15] & 0x1)
  566. props->active_speed = IB_SPEED_FDR10;
  567. }
  568. /* Avoid wrong speed value returned by FW if the IB link is down. */
  569. if (props->state == IB_PORT_DOWN)
  570. props->active_speed = IB_SPEED_SDR;
  571. out:
  572. kfree(in_mad);
  573. kfree(out_mad);
  574. return err;
  575. }
  576. static u8 state_to_phys_state(enum ib_port_state state)
  577. {
  578. return state == IB_PORT_ACTIVE ? 5 : 3;
  579. }
  580. static int eth_link_query_port(struct ib_device *ibdev, u8 port,
  581. struct ib_port_attr *props, int netw_view)
  582. {
  583. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  584. struct mlx4_ib_iboe *iboe = &mdev->iboe;
  585. struct net_device *ndev;
  586. enum ib_mtu tmp;
  587. struct mlx4_cmd_mailbox *mailbox;
  588. int err = 0;
  589. int is_bonded = mlx4_is_bonded(mdev->dev);
  590. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  591. if (IS_ERR(mailbox))
  592. return PTR_ERR(mailbox);
  593. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  594. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  595. MLX4_CMD_WRAPPED);
  596. if (err)
  597. goto out;
  598. props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ?
  599. IB_WIDTH_4X : IB_WIDTH_1X;
  600. props->active_speed = IB_SPEED_QDR;
  601. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
  602. props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
  603. props->max_msg_sz = mdev->dev->caps.max_msg_sz;
  604. props->pkey_tbl_len = 1;
  605. props->max_mtu = IB_MTU_4096;
  606. props->max_vl_num = 2;
  607. props->state = IB_PORT_DOWN;
  608. props->phys_state = state_to_phys_state(props->state);
  609. props->active_mtu = IB_MTU_256;
  610. spin_lock_bh(&iboe->lock);
  611. ndev = iboe->netdevs[port - 1];
  612. if (ndev && is_bonded) {
  613. rcu_read_lock(); /* required to get upper dev */
  614. ndev = netdev_master_upper_dev_get_rcu(ndev);
  615. rcu_read_unlock();
  616. }
  617. if (!ndev)
  618. goto out_unlock;
  619. tmp = iboe_get_mtu(ndev->mtu);
  620. props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
  621. props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
  622. IB_PORT_ACTIVE : IB_PORT_DOWN;
  623. props->phys_state = state_to_phys_state(props->state);
  624. out_unlock:
  625. spin_unlock_bh(&iboe->lock);
  626. out:
  627. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  628. return err;
  629. }
  630. int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  631. struct ib_port_attr *props, int netw_view)
  632. {
  633. int err;
  634. memset(props, 0, sizeof *props);
  635. err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
  636. ib_link_query_port(ibdev, port, props, netw_view) :
  637. eth_link_query_port(ibdev, port, props, netw_view);
  638. return err;
  639. }
  640. static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  641. struct ib_port_attr *props)
  642. {
  643. /* returns host view */
  644. return __mlx4_ib_query_port(ibdev, port, props, 0);
  645. }
  646. int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  647. union ib_gid *gid, int netw_view)
  648. {
  649. struct ib_smp *in_mad = NULL;
  650. struct ib_smp *out_mad = NULL;
  651. int err = -ENOMEM;
  652. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  653. int clear = 0;
  654. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  655. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  656. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  657. if (!in_mad || !out_mad)
  658. goto out;
  659. init_query_mad(in_mad);
  660. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  661. in_mad->attr_mod = cpu_to_be32(port);
  662. if (mlx4_is_mfunc(dev->dev) && netw_view)
  663. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  664. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
  665. if (err)
  666. goto out;
  667. memcpy(gid->raw, out_mad->data + 8, 8);
  668. if (mlx4_is_mfunc(dev->dev) && !netw_view) {
  669. if (index) {
  670. /* For any index > 0, return the null guid */
  671. err = 0;
  672. clear = 1;
  673. goto out;
  674. }
  675. }
  676. init_query_mad(in_mad);
  677. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  678. in_mad->attr_mod = cpu_to_be32(index / 8);
  679. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
  680. NULL, NULL, in_mad, out_mad);
  681. if (err)
  682. goto out;
  683. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  684. out:
  685. if (clear)
  686. memset(gid->raw + 8, 0, 8);
  687. kfree(in_mad);
  688. kfree(out_mad);
  689. return err;
  690. }
  691. static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  692. union ib_gid *gid)
  693. {
  694. int ret;
  695. if (rdma_protocol_ib(ibdev, port))
  696. return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
  697. if (!rdma_protocol_roce(ibdev, port))
  698. return -ENODEV;
  699. if (!rdma_cap_roce_gid_table(ibdev, port))
  700. return -ENODEV;
  701. ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
  702. if (ret == -EAGAIN) {
  703. memcpy(gid, &zgid, sizeof(*gid));
  704. return 0;
  705. }
  706. return ret;
  707. }
  708. int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  709. u16 *pkey, int netw_view)
  710. {
  711. struct ib_smp *in_mad = NULL;
  712. struct ib_smp *out_mad = NULL;
  713. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  714. int err = -ENOMEM;
  715. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  716. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  717. if (!in_mad || !out_mad)
  718. goto out;
  719. init_query_mad(in_mad);
  720. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  721. in_mad->attr_mod = cpu_to_be32(index / 32);
  722. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  723. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  724. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  725. in_mad, out_mad);
  726. if (err)
  727. goto out;
  728. *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
  729. out:
  730. kfree(in_mad);
  731. kfree(out_mad);
  732. return err;
  733. }
  734. static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  735. {
  736. return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
  737. }
  738. static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
  739. struct ib_device_modify *props)
  740. {
  741. struct mlx4_cmd_mailbox *mailbox;
  742. unsigned long flags;
  743. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  744. return -EOPNOTSUPP;
  745. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  746. return 0;
  747. if (mlx4_is_slave(to_mdev(ibdev)->dev))
  748. return -EOPNOTSUPP;
  749. spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
  750. memcpy(ibdev->node_desc, props->node_desc, 64);
  751. spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
  752. /*
  753. * If possible, pass node desc to FW, so it can generate
  754. * a 144 trap. If cmd fails, just ignore.
  755. */
  756. mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
  757. if (IS_ERR(mailbox))
  758. return 0;
  759. memcpy(mailbox->buf, props->node_desc, 64);
  760. mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
  761. MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  762. mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
  763. return 0;
  764. }
  765. static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
  766. u32 cap_mask)
  767. {
  768. struct mlx4_cmd_mailbox *mailbox;
  769. int err;
  770. mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
  771. if (IS_ERR(mailbox))
  772. return PTR_ERR(mailbox);
  773. if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  774. *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
  775. ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
  776. } else {
  777. ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
  778. ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
  779. }
  780. err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
  781. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  782. MLX4_CMD_WRAPPED);
  783. mlx4_free_cmd_mailbox(dev->dev, mailbox);
  784. return err;
  785. }
  786. static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  787. struct ib_port_modify *props)
  788. {
  789. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  790. u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
  791. struct ib_port_attr attr;
  792. u32 cap_mask;
  793. int err;
  794. /* return OK if this is RoCE. CM calls ib_modify_port() regardless
  795. * of whether port link layer is ETH or IB. For ETH ports, qkey
  796. * violations and port capabilities are not meaningful.
  797. */
  798. if (is_eth)
  799. return 0;
  800. mutex_lock(&mdev->cap_mask_mutex);
  801. err = mlx4_ib_query_port(ibdev, port, &attr);
  802. if (err)
  803. goto out;
  804. cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
  805. ~props->clr_port_cap_mask;
  806. err = mlx4_ib_SET_PORT(mdev, port,
  807. !!(mask & IB_PORT_RESET_QKEY_CNTR),
  808. cap_mask);
  809. out:
  810. mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
  811. return err;
  812. }
  813. static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
  814. struct ib_udata *udata)
  815. {
  816. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  817. struct mlx4_ib_ucontext *context;
  818. struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
  819. struct mlx4_ib_alloc_ucontext_resp resp;
  820. int err;
  821. if (!dev->ib_active)
  822. return ERR_PTR(-EAGAIN);
  823. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
  824. resp_v3.qp_tab_size = dev->dev->caps.num_qps;
  825. resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
  826. resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  827. } else {
  828. resp.dev_caps = dev->dev->caps.userspace_caps;
  829. resp.qp_tab_size = dev->dev->caps.num_qps;
  830. resp.bf_reg_size = dev->dev->caps.bf_reg_size;
  831. resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  832. resp.cqe_size = dev->dev->caps.cqe_size;
  833. }
  834. context = kzalloc(sizeof(*context), GFP_KERNEL);
  835. if (!context)
  836. return ERR_PTR(-ENOMEM);
  837. err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
  838. if (err) {
  839. kfree(context);
  840. return ERR_PTR(err);
  841. }
  842. INIT_LIST_HEAD(&context->db_page_list);
  843. mutex_init(&context->db_page_mutex);
  844. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
  845. err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
  846. else
  847. err = ib_copy_to_udata(udata, &resp, sizeof(resp));
  848. if (err) {
  849. mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
  850. kfree(context);
  851. return ERR_PTR(-EFAULT);
  852. }
  853. return &context->ibucontext;
  854. }
  855. static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  856. {
  857. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  858. mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
  859. kfree(context);
  860. return 0;
  861. }
  862. static void mlx4_ib_vma_open(struct vm_area_struct *area)
  863. {
  864. /* vma_open is called when a new VMA is created on top of our VMA.
  865. * This is done through either mremap flow or split_vma (usually due
  866. * to mlock, madvise, munmap, etc.). We do not support a clone of the
  867. * vma, as this VMA is strongly hardware related. Therefore we set the
  868. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  869. * calling us again and trying to do incorrect actions. We assume that
  870. * the original vma size is exactly a single page that there will be no
  871. * "splitting" operations on.
  872. */
  873. area->vm_ops = NULL;
  874. }
  875. static void mlx4_ib_vma_close(struct vm_area_struct *area)
  876. {
  877. struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
  878. /* It's guaranteed that all VMAs opened on a FD are closed before the
  879. * file itself is closed, therefore no sync is needed with the regular
  880. * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
  881. * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
  882. * The close operation is usually called under mm->mmap_sem except when
  883. * process is exiting. The exiting case is handled explicitly as part
  884. * of mlx4_ib_disassociate_ucontext.
  885. */
  886. mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
  887. area->vm_private_data;
  888. /* set the vma context pointer to null in the mlx4_ib driver's private
  889. * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
  890. */
  891. mlx4_ib_vma_priv_data->vma = NULL;
  892. }
  893. static const struct vm_operations_struct mlx4_ib_vm_ops = {
  894. .open = mlx4_ib_vma_open,
  895. .close = mlx4_ib_vma_close
  896. };
  897. static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  898. {
  899. int i;
  900. int ret = 0;
  901. struct vm_area_struct *vma;
  902. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  903. struct task_struct *owning_process = NULL;
  904. struct mm_struct *owning_mm = NULL;
  905. owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
  906. if (!owning_process)
  907. return;
  908. owning_mm = get_task_mm(owning_process);
  909. if (!owning_mm) {
  910. pr_info("no mm, disassociate ucontext is pending task termination\n");
  911. while (1) {
  912. /* make sure that task is dead before returning, it may
  913. * prevent a rare case of module down in parallel to a
  914. * call to mlx4_ib_vma_close.
  915. */
  916. put_task_struct(owning_process);
  917. msleep(1);
  918. owning_process = get_pid_task(ibcontext->tgid,
  919. PIDTYPE_PID);
  920. if (!owning_process ||
  921. owning_process->state == TASK_DEAD) {
  922. pr_info("disassociate ucontext done, task was terminated\n");
  923. /* in case task was dead need to release the task struct */
  924. if (owning_process)
  925. put_task_struct(owning_process);
  926. return;
  927. }
  928. }
  929. }
  930. /* need to protect from a race on closing the vma as part of
  931. * mlx4_ib_vma_close().
  932. */
  933. down_read(&owning_mm->mmap_sem);
  934. for (i = 0; i < HW_BAR_COUNT; i++) {
  935. vma = context->hw_bar_info[i].vma;
  936. if (!vma)
  937. continue;
  938. ret = zap_vma_ptes(context->hw_bar_info[i].vma,
  939. context->hw_bar_info[i].vma->vm_start,
  940. PAGE_SIZE);
  941. if (ret) {
  942. pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
  943. BUG_ON(1);
  944. }
  945. /* context going to be destroyed, should not access ops any more */
  946. context->hw_bar_info[i].vma->vm_ops = NULL;
  947. }
  948. up_read(&owning_mm->mmap_sem);
  949. mmput(owning_mm);
  950. put_task_struct(owning_process);
  951. }
  952. static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
  953. struct mlx4_ib_vma_private_data *vma_private_data)
  954. {
  955. vma_private_data->vma = vma;
  956. vma->vm_private_data = vma_private_data;
  957. vma->vm_ops = &mlx4_ib_vm_ops;
  958. }
  959. static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  960. {
  961. struct mlx4_ib_dev *dev = to_mdev(context->device);
  962. struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
  963. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  964. return -EINVAL;
  965. if (vma->vm_pgoff == 0) {
  966. /* We prevent double mmaping on same context */
  967. if (mucontext->hw_bar_info[HW_BAR_DB].vma)
  968. return -EINVAL;
  969. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  970. if (io_remap_pfn_range(vma, vma->vm_start,
  971. to_mucontext(context)->uar.pfn,
  972. PAGE_SIZE, vma->vm_page_prot))
  973. return -EAGAIN;
  974. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
  975. } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
  976. /* We prevent double mmaping on same context */
  977. if (mucontext->hw_bar_info[HW_BAR_BF].vma)
  978. return -EINVAL;
  979. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  980. if (io_remap_pfn_range(vma, vma->vm_start,
  981. to_mucontext(context)->uar.pfn +
  982. dev->dev->caps.num_uars,
  983. PAGE_SIZE, vma->vm_page_prot))
  984. return -EAGAIN;
  985. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
  986. } else if (vma->vm_pgoff == 3) {
  987. struct mlx4_clock_params params;
  988. int ret;
  989. /* We prevent double mmaping on same context */
  990. if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
  991. return -EINVAL;
  992. ret = mlx4_get_internal_clock_params(dev->dev, &params);
  993. if (ret)
  994. return ret;
  995. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  996. if (io_remap_pfn_range(vma, vma->vm_start,
  997. (pci_resource_start(dev->dev->persist->pdev,
  998. params.bar) +
  999. params.offset)
  1000. >> PAGE_SHIFT,
  1001. PAGE_SIZE, vma->vm_page_prot))
  1002. return -EAGAIN;
  1003. mlx4_ib_set_vma_data(vma,
  1004. &mucontext->hw_bar_info[HW_BAR_CLOCK]);
  1005. } else {
  1006. return -EINVAL;
  1007. }
  1008. return 0;
  1009. }
  1010. static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
  1011. struct ib_ucontext *context,
  1012. struct ib_udata *udata)
  1013. {
  1014. struct mlx4_ib_pd *pd;
  1015. int err;
  1016. pd = kmalloc(sizeof *pd, GFP_KERNEL);
  1017. if (!pd)
  1018. return ERR_PTR(-ENOMEM);
  1019. err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
  1020. if (err) {
  1021. kfree(pd);
  1022. return ERR_PTR(err);
  1023. }
  1024. if (context)
  1025. if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
  1026. mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
  1027. kfree(pd);
  1028. return ERR_PTR(-EFAULT);
  1029. }
  1030. return &pd->ibpd;
  1031. }
  1032. static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
  1033. {
  1034. mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
  1035. kfree(pd);
  1036. return 0;
  1037. }
  1038. static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
  1039. struct ib_ucontext *context,
  1040. struct ib_udata *udata)
  1041. {
  1042. struct mlx4_ib_xrcd *xrcd;
  1043. struct ib_cq_init_attr cq_attr = {};
  1044. int err;
  1045. if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
  1046. return ERR_PTR(-ENOSYS);
  1047. xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
  1048. if (!xrcd)
  1049. return ERR_PTR(-ENOMEM);
  1050. err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
  1051. if (err)
  1052. goto err1;
  1053. xrcd->pd = ib_alloc_pd(ibdev);
  1054. if (IS_ERR(xrcd->pd)) {
  1055. err = PTR_ERR(xrcd->pd);
  1056. goto err2;
  1057. }
  1058. cq_attr.cqe = 1;
  1059. xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
  1060. if (IS_ERR(xrcd->cq)) {
  1061. err = PTR_ERR(xrcd->cq);
  1062. goto err3;
  1063. }
  1064. return &xrcd->ibxrcd;
  1065. err3:
  1066. ib_dealloc_pd(xrcd->pd);
  1067. err2:
  1068. mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
  1069. err1:
  1070. kfree(xrcd);
  1071. return ERR_PTR(err);
  1072. }
  1073. static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
  1074. {
  1075. ib_destroy_cq(to_mxrcd(xrcd)->cq);
  1076. ib_dealloc_pd(to_mxrcd(xrcd)->pd);
  1077. mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
  1078. kfree(xrcd);
  1079. return 0;
  1080. }
  1081. static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
  1082. {
  1083. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1084. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1085. struct mlx4_ib_gid_entry *ge;
  1086. ge = kzalloc(sizeof *ge, GFP_KERNEL);
  1087. if (!ge)
  1088. return -ENOMEM;
  1089. ge->gid = *gid;
  1090. if (mlx4_ib_add_mc(mdev, mqp, gid)) {
  1091. ge->port = mqp->port;
  1092. ge->added = 1;
  1093. }
  1094. mutex_lock(&mqp->mutex);
  1095. list_add_tail(&ge->list, &mqp->gid_list);
  1096. mutex_unlock(&mqp->mutex);
  1097. return 0;
  1098. }
  1099. static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
  1100. struct mlx4_ib_counters *ctr_table)
  1101. {
  1102. struct counter_index *counter, *tmp_count;
  1103. mutex_lock(&ctr_table->mutex);
  1104. list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
  1105. list) {
  1106. if (counter->allocated)
  1107. mlx4_counter_free(ibdev->dev, counter->index);
  1108. list_del(&counter->list);
  1109. kfree(counter);
  1110. }
  1111. mutex_unlock(&ctr_table->mutex);
  1112. }
  1113. int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  1114. union ib_gid *gid)
  1115. {
  1116. struct net_device *ndev;
  1117. int ret = 0;
  1118. if (!mqp->port)
  1119. return 0;
  1120. spin_lock_bh(&mdev->iboe.lock);
  1121. ndev = mdev->iboe.netdevs[mqp->port - 1];
  1122. if (ndev)
  1123. dev_hold(ndev);
  1124. spin_unlock_bh(&mdev->iboe.lock);
  1125. if (ndev) {
  1126. ret = 1;
  1127. dev_put(ndev);
  1128. }
  1129. return ret;
  1130. }
  1131. struct mlx4_ib_steering {
  1132. struct list_head list;
  1133. struct mlx4_flow_reg_id reg_id;
  1134. union ib_gid gid;
  1135. };
  1136. static int parse_flow_attr(struct mlx4_dev *dev,
  1137. u32 qp_num,
  1138. union ib_flow_spec *ib_spec,
  1139. struct _rule_hw *mlx4_spec)
  1140. {
  1141. enum mlx4_net_trans_rule_id type;
  1142. switch (ib_spec->type) {
  1143. case IB_FLOW_SPEC_ETH:
  1144. type = MLX4_NET_TRANS_RULE_ID_ETH;
  1145. memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
  1146. ETH_ALEN);
  1147. memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
  1148. ETH_ALEN);
  1149. mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
  1150. mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
  1151. break;
  1152. case IB_FLOW_SPEC_IB:
  1153. type = MLX4_NET_TRANS_RULE_ID_IB;
  1154. mlx4_spec->ib.l3_qpn =
  1155. cpu_to_be32(qp_num);
  1156. mlx4_spec->ib.qpn_mask =
  1157. cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
  1158. break;
  1159. case IB_FLOW_SPEC_IPV4:
  1160. type = MLX4_NET_TRANS_RULE_ID_IPV4;
  1161. mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
  1162. mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
  1163. mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
  1164. mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
  1165. break;
  1166. case IB_FLOW_SPEC_TCP:
  1167. case IB_FLOW_SPEC_UDP:
  1168. type = ib_spec->type == IB_FLOW_SPEC_TCP ?
  1169. MLX4_NET_TRANS_RULE_ID_TCP :
  1170. MLX4_NET_TRANS_RULE_ID_UDP;
  1171. mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
  1172. mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
  1173. mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
  1174. mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
  1175. break;
  1176. default:
  1177. return -EINVAL;
  1178. }
  1179. if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
  1180. mlx4_hw_rule_sz(dev, type) < 0)
  1181. return -EINVAL;
  1182. mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
  1183. mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
  1184. return mlx4_hw_rule_sz(dev, type);
  1185. }
  1186. struct default_rules {
  1187. __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1188. __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1189. __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1190. __u8 link_layer;
  1191. };
  1192. static const struct default_rules default_table[] = {
  1193. {
  1194. .mandatory_fields = {IB_FLOW_SPEC_IPV4},
  1195. .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
  1196. .rules_create_list = {IB_FLOW_SPEC_IB},
  1197. .link_layer = IB_LINK_LAYER_INFINIBAND
  1198. }
  1199. };
  1200. static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
  1201. struct ib_flow_attr *flow_attr)
  1202. {
  1203. int i, j, k;
  1204. void *ib_flow;
  1205. const struct default_rules *pdefault_rules = default_table;
  1206. u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
  1207. for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
  1208. __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1209. memset(&field_types, 0, sizeof(field_types));
  1210. if (link_layer != pdefault_rules->link_layer)
  1211. continue;
  1212. ib_flow = flow_attr + 1;
  1213. /* we assume the specs are sorted */
  1214. for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
  1215. j < flow_attr->num_of_specs; k++) {
  1216. union ib_flow_spec *current_flow =
  1217. (union ib_flow_spec *)ib_flow;
  1218. /* same layer but different type */
  1219. if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
  1220. (pdefault_rules->mandatory_fields[k] &
  1221. IB_FLOW_SPEC_LAYER_MASK)) &&
  1222. (current_flow->type !=
  1223. pdefault_rules->mandatory_fields[k]))
  1224. goto out;
  1225. /* same layer, try match next one */
  1226. if (current_flow->type ==
  1227. pdefault_rules->mandatory_fields[k]) {
  1228. j++;
  1229. ib_flow +=
  1230. ((union ib_flow_spec *)ib_flow)->size;
  1231. }
  1232. }
  1233. ib_flow = flow_attr + 1;
  1234. for (j = 0; j < flow_attr->num_of_specs;
  1235. j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
  1236. for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
  1237. /* same layer and same type */
  1238. if (((union ib_flow_spec *)ib_flow)->type ==
  1239. pdefault_rules->mandatory_not_fields[k])
  1240. goto out;
  1241. return i;
  1242. }
  1243. out:
  1244. return -1;
  1245. }
  1246. static int __mlx4_ib_create_default_rules(
  1247. struct mlx4_ib_dev *mdev,
  1248. struct ib_qp *qp,
  1249. const struct default_rules *pdefault_rules,
  1250. struct _rule_hw *mlx4_spec) {
  1251. int size = 0;
  1252. int i;
  1253. for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
  1254. int ret;
  1255. union ib_flow_spec ib_spec;
  1256. switch (pdefault_rules->rules_create_list[i]) {
  1257. case 0:
  1258. /* no rule */
  1259. continue;
  1260. case IB_FLOW_SPEC_IB:
  1261. ib_spec.type = IB_FLOW_SPEC_IB;
  1262. ib_spec.size = sizeof(struct ib_flow_spec_ib);
  1263. break;
  1264. default:
  1265. /* invalid rule */
  1266. return -EINVAL;
  1267. }
  1268. /* We must put empty rule, qpn is being ignored */
  1269. ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
  1270. mlx4_spec);
  1271. if (ret < 0) {
  1272. pr_info("invalid parsing\n");
  1273. return -EINVAL;
  1274. }
  1275. mlx4_spec = (void *)mlx4_spec + ret;
  1276. size += ret;
  1277. }
  1278. return size;
  1279. }
  1280. static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1281. int domain,
  1282. enum mlx4_net_trans_promisc_mode flow_type,
  1283. u64 *reg_id)
  1284. {
  1285. int ret, i;
  1286. int size = 0;
  1287. void *ib_flow;
  1288. struct mlx4_ib_dev *mdev = to_mdev(qp->device);
  1289. struct mlx4_cmd_mailbox *mailbox;
  1290. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  1291. int default_flow;
  1292. static const u16 __mlx4_domain[] = {
  1293. [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
  1294. [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
  1295. [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
  1296. [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
  1297. };
  1298. if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
  1299. pr_err("Invalid priority value %d\n", flow_attr->priority);
  1300. return -EINVAL;
  1301. }
  1302. if (domain >= IB_FLOW_DOMAIN_NUM) {
  1303. pr_err("Invalid domain value %d\n", domain);
  1304. return -EINVAL;
  1305. }
  1306. if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
  1307. return -EINVAL;
  1308. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  1309. if (IS_ERR(mailbox))
  1310. return PTR_ERR(mailbox);
  1311. ctrl = mailbox->buf;
  1312. ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
  1313. flow_attr->priority);
  1314. ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
  1315. ctrl->port = flow_attr->port;
  1316. ctrl->qpn = cpu_to_be32(qp->qp_num);
  1317. ib_flow = flow_attr + 1;
  1318. size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  1319. /* Add default flows */
  1320. default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
  1321. if (default_flow >= 0) {
  1322. ret = __mlx4_ib_create_default_rules(
  1323. mdev, qp, default_table + default_flow,
  1324. mailbox->buf + size);
  1325. if (ret < 0) {
  1326. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1327. return -EINVAL;
  1328. }
  1329. size += ret;
  1330. }
  1331. for (i = 0; i < flow_attr->num_of_specs; i++) {
  1332. ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
  1333. mailbox->buf + size);
  1334. if (ret < 0) {
  1335. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1336. return -EINVAL;
  1337. }
  1338. ib_flow += ((union ib_flow_spec *) ib_flow)->size;
  1339. size += ret;
  1340. }
  1341. ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
  1342. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  1343. MLX4_CMD_WRAPPED);
  1344. if (ret == -ENOMEM)
  1345. pr_err("mcg table is full. Fail to register network rule.\n");
  1346. else if (ret == -ENXIO)
  1347. pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
  1348. else if (ret)
  1349. pr_err("Invalid argument. Fail to register network rule.\n");
  1350. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1351. return ret;
  1352. }
  1353. static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
  1354. {
  1355. int err;
  1356. err = mlx4_cmd(dev, reg_id, 0, 0,
  1357. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  1358. MLX4_CMD_WRAPPED);
  1359. if (err)
  1360. pr_err("Fail to detach network rule. registration id = 0x%llx\n",
  1361. reg_id);
  1362. return err;
  1363. }
  1364. static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1365. u64 *reg_id)
  1366. {
  1367. void *ib_flow;
  1368. union ib_flow_spec *ib_spec;
  1369. struct mlx4_dev *dev = to_mdev(qp->device)->dev;
  1370. int err = 0;
  1371. if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
  1372. dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
  1373. return 0; /* do nothing */
  1374. ib_flow = flow_attr + 1;
  1375. ib_spec = (union ib_flow_spec *)ib_flow;
  1376. if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
  1377. return 0; /* do nothing */
  1378. err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
  1379. flow_attr->port, qp->qp_num,
  1380. MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
  1381. reg_id);
  1382. return err;
  1383. }
  1384. static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
  1385. struct ib_flow_attr *flow_attr,
  1386. enum mlx4_net_trans_promisc_mode *type)
  1387. {
  1388. int err = 0;
  1389. if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
  1390. (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
  1391. (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
  1392. return -EOPNOTSUPP;
  1393. }
  1394. if (flow_attr->num_of_specs == 0) {
  1395. type[0] = MLX4_FS_MC_SNIFFER;
  1396. type[1] = MLX4_FS_UC_SNIFFER;
  1397. } else {
  1398. union ib_flow_spec *ib_spec;
  1399. ib_spec = (union ib_flow_spec *)(flow_attr + 1);
  1400. if (ib_spec->type != IB_FLOW_SPEC_ETH)
  1401. return -EINVAL;
  1402. /* if all is zero than MC and UC */
  1403. if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
  1404. type[0] = MLX4_FS_MC_SNIFFER;
  1405. type[1] = MLX4_FS_UC_SNIFFER;
  1406. } else {
  1407. u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
  1408. ib_spec->eth.mask.dst_mac[1],
  1409. ib_spec->eth.mask.dst_mac[2],
  1410. ib_spec->eth.mask.dst_mac[3],
  1411. ib_spec->eth.mask.dst_mac[4],
  1412. ib_spec->eth.mask.dst_mac[5]};
  1413. /* Above xor was only on MC bit, non empty mask is valid
  1414. * only if this bit is set and rest are zero.
  1415. */
  1416. if (!is_zero_ether_addr(&mac[0]))
  1417. return -EINVAL;
  1418. if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
  1419. type[0] = MLX4_FS_MC_SNIFFER;
  1420. else
  1421. type[0] = MLX4_FS_UC_SNIFFER;
  1422. }
  1423. }
  1424. return err;
  1425. }
  1426. static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
  1427. struct ib_flow_attr *flow_attr,
  1428. int domain)
  1429. {
  1430. int err = 0, i = 0, j = 0;
  1431. struct mlx4_ib_flow *mflow;
  1432. enum mlx4_net_trans_promisc_mode type[2];
  1433. struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
  1434. int is_bonded = mlx4_is_bonded(dev);
  1435. if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
  1436. return ERR_PTR(-EINVAL);
  1437. if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
  1438. (flow_attr->type != IB_FLOW_ATTR_NORMAL))
  1439. return ERR_PTR(-EOPNOTSUPP);
  1440. memset(type, 0, sizeof(type));
  1441. mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
  1442. if (!mflow) {
  1443. err = -ENOMEM;
  1444. goto err_free;
  1445. }
  1446. switch (flow_attr->type) {
  1447. case IB_FLOW_ATTR_NORMAL:
  1448. /* If dont trap flag (continue match) is set, under specific
  1449. * condition traffic be replicated to given qp,
  1450. * without stealing it
  1451. */
  1452. if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
  1453. err = mlx4_ib_add_dont_trap_rule(dev,
  1454. flow_attr,
  1455. type);
  1456. if (err)
  1457. goto err_free;
  1458. } else {
  1459. type[0] = MLX4_FS_REGULAR;
  1460. }
  1461. break;
  1462. case IB_FLOW_ATTR_ALL_DEFAULT:
  1463. type[0] = MLX4_FS_ALL_DEFAULT;
  1464. break;
  1465. case IB_FLOW_ATTR_MC_DEFAULT:
  1466. type[0] = MLX4_FS_MC_DEFAULT;
  1467. break;
  1468. case IB_FLOW_ATTR_SNIFFER:
  1469. type[0] = MLX4_FS_MIRROR_RX_PORT;
  1470. type[1] = MLX4_FS_MIRROR_SX_PORT;
  1471. break;
  1472. default:
  1473. err = -EINVAL;
  1474. goto err_free;
  1475. }
  1476. while (i < ARRAY_SIZE(type) && type[i]) {
  1477. err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
  1478. &mflow->reg_id[i].id);
  1479. if (err)
  1480. goto err_create_flow;
  1481. if (is_bonded) {
  1482. /* Application always sees one port so the mirror rule
  1483. * must be on port #2
  1484. */
  1485. flow_attr->port = 2;
  1486. err = __mlx4_ib_create_flow(qp, flow_attr,
  1487. domain, type[j],
  1488. &mflow->reg_id[j].mirror);
  1489. flow_attr->port = 1;
  1490. if (err)
  1491. goto err_create_flow;
  1492. j++;
  1493. }
  1494. i++;
  1495. }
  1496. if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  1497. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1498. &mflow->reg_id[i].id);
  1499. if (err)
  1500. goto err_create_flow;
  1501. if (is_bonded) {
  1502. flow_attr->port = 2;
  1503. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1504. &mflow->reg_id[j].mirror);
  1505. flow_attr->port = 1;
  1506. if (err)
  1507. goto err_create_flow;
  1508. j++;
  1509. }
  1510. /* function to create mirror rule */
  1511. i++;
  1512. }
  1513. return &mflow->ibflow;
  1514. err_create_flow:
  1515. while (i) {
  1516. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1517. mflow->reg_id[i].id);
  1518. i--;
  1519. }
  1520. while (j) {
  1521. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1522. mflow->reg_id[j].mirror);
  1523. j--;
  1524. }
  1525. err_free:
  1526. kfree(mflow);
  1527. return ERR_PTR(err);
  1528. }
  1529. static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
  1530. {
  1531. int err, ret = 0;
  1532. int i = 0;
  1533. struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
  1534. struct mlx4_ib_flow *mflow = to_mflow(flow_id);
  1535. while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
  1536. err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
  1537. if (err)
  1538. ret = err;
  1539. if (mflow->reg_id[i].mirror) {
  1540. err = __mlx4_ib_destroy_flow(mdev->dev,
  1541. mflow->reg_id[i].mirror);
  1542. if (err)
  1543. ret = err;
  1544. }
  1545. i++;
  1546. }
  1547. kfree(mflow);
  1548. return ret;
  1549. }
  1550. static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1551. {
  1552. int err;
  1553. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1554. struct mlx4_dev *dev = mdev->dev;
  1555. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1556. struct mlx4_ib_steering *ib_steering = NULL;
  1557. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1558. struct mlx4_flow_reg_id reg_id;
  1559. if (mdev->dev->caps.steering_mode ==
  1560. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1561. ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
  1562. if (!ib_steering)
  1563. return -ENOMEM;
  1564. }
  1565. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
  1566. !!(mqp->flags &
  1567. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1568. prot, &reg_id.id);
  1569. if (err) {
  1570. pr_err("multicast attach op failed, err %d\n", err);
  1571. goto err_malloc;
  1572. }
  1573. reg_id.mirror = 0;
  1574. if (mlx4_is_bonded(dev)) {
  1575. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
  1576. (mqp->port == 1) ? 2 : 1,
  1577. !!(mqp->flags &
  1578. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1579. prot, &reg_id.mirror);
  1580. if (err)
  1581. goto err_add;
  1582. }
  1583. err = add_gid_entry(ibqp, gid);
  1584. if (err)
  1585. goto err_add;
  1586. if (ib_steering) {
  1587. memcpy(ib_steering->gid.raw, gid->raw, 16);
  1588. ib_steering->reg_id = reg_id;
  1589. mutex_lock(&mqp->mutex);
  1590. list_add(&ib_steering->list, &mqp->steering_rules);
  1591. mutex_unlock(&mqp->mutex);
  1592. }
  1593. return 0;
  1594. err_add:
  1595. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1596. prot, reg_id.id);
  1597. if (reg_id.mirror)
  1598. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1599. prot, reg_id.mirror);
  1600. err_malloc:
  1601. kfree(ib_steering);
  1602. return err;
  1603. }
  1604. static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
  1605. {
  1606. struct mlx4_ib_gid_entry *ge;
  1607. struct mlx4_ib_gid_entry *tmp;
  1608. struct mlx4_ib_gid_entry *ret = NULL;
  1609. list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
  1610. if (!memcmp(raw, ge->gid.raw, 16)) {
  1611. ret = ge;
  1612. break;
  1613. }
  1614. }
  1615. return ret;
  1616. }
  1617. static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1618. {
  1619. int err;
  1620. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1621. struct mlx4_dev *dev = mdev->dev;
  1622. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1623. struct net_device *ndev;
  1624. struct mlx4_ib_gid_entry *ge;
  1625. struct mlx4_flow_reg_id reg_id = {0, 0};
  1626. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1627. if (mdev->dev->caps.steering_mode ==
  1628. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1629. struct mlx4_ib_steering *ib_steering;
  1630. mutex_lock(&mqp->mutex);
  1631. list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
  1632. if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
  1633. list_del(&ib_steering->list);
  1634. break;
  1635. }
  1636. }
  1637. mutex_unlock(&mqp->mutex);
  1638. if (&ib_steering->list == &mqp->steering_rules) {
  1639. pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
  1640. return -EINVAL;
  1641. }
  1642. reg_id = ib_steering->reg_id;
  1643. kfree(ib_steering);
  1644. }
  1645. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1646. prot, reg_id.id);
  1647. if (err)
  1648. return err;
  1649. if (mlx4_is_bonded(dev)) {
  1650. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1651. prot, reg_id.mirror);
  1652. if (err)
  1653. return err;
  1654. }
  1655. mutex_lock(&mqp->mutex);
  1656. ge = find_gid_entry(mqp, gid->raw);
  1657. if (ge) {
  1658. spin_lock_bh(&mdev->iboe.lock);
  1659. ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
  1660. if (ndev)
  1661. dev_hold(ndev);
  1662. spin_unlock_bh(&mdev->iboe.lock);
  1663. if (ndev)
  1664. dev_put(ndev);
  1665. list_del(&ge->list);
  1666. kfree(ge);
  1667. } else
  1668. pr_warn("could not find mgid entry\n");
  1669. mutex_unlock(&mqp->mutex);
  1670. return 0;
  1671. }
  1672. static int init_node_data(struct mlx4_ib_dev *dev)
  1673. {
  1674. struct ib_smp *in_mad = NULL;
  1675. struct ib_smp *out_mad = NULL;
  1676. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  1677. int err = -ENOMEM;
  1678. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  1679. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  1680. if (!in_mad || !out_mad)
  1681. goto out;
  1682. init_query_mad(in_mad);
  1683. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  1684. if (mlx4_is_master(dev->dev))
  1685. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  1686. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1687. if (err)
  1688. goto out;
  1689. memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
  1690. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  1691. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1692. if (err)
  1693. goto out;
  1694. dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
  1695. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  1696. out:
  1697. kfree(in_mad);
  1698. kfree(out_mad);
  1699. return err;
  1700. }
  1701. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  1702. char *buf)
  1703. {
  1704. struct mlx4_ib_dev *dev =
  1705. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1706. return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
  1707. }
  1708. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  1709. char *buf)
  1710. {
  1711. struct mlx4_ib_dev *dev =
  1712. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1713. return sprintf(buf, "%x\n", dev->dev->rev_id);
  1714. }
  1715. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  1716. char *buf)
  1717. {
  1718. struct mlx4_ib_dev *dev =
  1719. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1720. return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
  1721. dev->dev->board_id);
  1722. }
  1723. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1724. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1725. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  1726. static struct device_attribute *mlx4_class_attributes[] = {
  1727. &dev_attr_hw_rev,
  1728. &dev_attr_hca_type,
  1729. &dev_attr_board_id
  1730. };
  1731. struct diag_counter {
  1732. const char *name;
  1733. u32 offset;
  1734. };
  1735. #define DIAG_COUNTER(_name, _offset) \
  1736. { .name = #_name, .offset = _offset }
  1737. static const struct diag_counter diag_basic[] = {
  1738. DIAG_COUNTER(rq_num_lle, 0x00),
  1739. DIAG_COUNTER(sq_num_lle, 0x04),
  1740. DIAG_COUNTER(rq_num_lqpoe, 0x08),
  1741. DIAG_COUNTER(sq_num_lqpoe, 0x0C),
  1742. DIAG_COUNTER(rq_num_lpe, 0x18),
  1743. DIAG_COUNTER(sq_num_lpe, 0x1C),
  1744. DIAG_COUNTER(rq_num_wrfe, 0x20),
  1745. DIAG_COUNTER(sq_num_wrfe, 0x24),
  1746. DIAG_COUNTER(sq_num_mwbe, 0x2C),
  1747. DIAG_COUNTER(sq_num_bre, 0x34),
  1748. DIAG_COUNTER(sq_num_rire, 0x44),
  1749. DIAG_COUNTER(rq_num_rire, 0x48),
  1750. DIAG_COUNTER(sq_num_rae, 0x4C),
  1751. DIAG_COUNTER(rq_num_rae, 0x50),
  1752. DIAG_COUNTER(sq_num_roe, 0x54),
  1753. DIAG_COUNTER(sq_num_tree, 0x5C),
  1754. DIAG_COUNTER(sq_num_rree, 0x64),
  1755. DIAG_COUNTER(rq_num_rnr, 0x68),
  1756. DIAG_COUNTER(sq_num_rnr, 0x6C),
  1757. DIAG_COUNTER(rq_num_oos, 0x100),
  1758. DIAG_COUNTER(sq_num_oos, 0x104),
  1759. };
  1760. static const struct diag_counter diag_ext[] = {
  1761. DIAG_COUNTER(rq_num_dup, 0x130),
  1762. DIAG_COUNTER(sq_num_to, 0x134),
  1763. };
  1764. static const struct diag_counter diag_device_only[] = {
  1765. DIAG_COUNTER(num_cqovf, 0x1A0),
  1766. DIAG_COUNTER(rq_num_udsdprd, 0x118),
  1767. };
  1768. static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
  1769. u8 port_num)
  1770. {
  1771. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1772. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1773. if (!diag[!!port_num].name)
  1774. return NULL;
  1775. return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
  1776. diag[!!port_num].num_counters,
  1777. RDMA_HW_STATS_DEFAULT_LIFESPAN);
  1778. }
  1779. static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
  1780. struct rdma_hw_stats *stats,
  1781. u8 port, int index)
  1782. {
  1783. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1784. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1785. u32 hw_value[ARRAY_SIZE(diag_device_only) +
  1786. ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
  1787. int ret;
  1788. int i;
  1789. ret = mlx4_query_diag_counters(dev->dev,
  1790. MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
  1791. diag[!!port].offset, hw_value,
  1792. diag[!!port].num_counters, port);
  1793. if (ret)
  1794. return ret;
  1795. for (i = 0; i < diag[!!port].num_counters; i++)
  1796. stats->value[i] = hw_value[i];
  1797. return diag[!!port].num_counters;
  1798. }
  1799. static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
  1800. const char ***name,
  1801. u32 **offset,
  1802. u32 *num,
  1803. bool port)
  1804. {
  1805. u32 num_counters;
  1806. num_counters = ARRAY_SIZE(diag_basic);
  1807. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
  1808. num_counters += ARRAY_SIZE(diag_ext);
  1809. if (!port)
  1810. num_counters += ARRAY_SIZE(diag_device_only);
  1811. *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
  1812. if (!*name)
  1813. return -ENOMEM;
  1814. *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
  1815. if (!*offset)
  1816. goto err_name;
  1817. *num = num_counters;
  1818. return 0;
  1819. err_name:
  1820. kfree(*name);
  1821. return -ENOMEM;
  1822. }
  1823. static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
  1824. const char **name,
  1825. u32 *offset,
  1826. bool port)
  1827. {
  1828. int i;
  1829. int j;
  1830. for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
  1831. name[i] = diag_basic[i].name;
  1832. offset[i] = diag_basic[i].offset;
  1833. }
  1834. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
  1835. for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
  1836. name[j] = diag_ext[i].name;
  1837. offset[j] = diag_ext[i].offset;
  1838. }
  1839. }
  1840. if (!port) {
  1841. for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
  1842. name[j] = diag_device_only[i].name;
  1843. offset[j] = diag_device_only[i].offset;
  1844. }
  1845. }
  1846. }
  1847. static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
  1848. {
  1849. struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
  1850. int i;
  1851. int ret;
  1852. bool per_port = !!(ibdev->dev->caps.flags2 &
  1853. MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
  1854. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1855. /* i == 1 means we are building port counters */
  1856. if (i && !per_port)
  1857. continue;
  1858. ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
  1859. &diag[i].offset,
  1860. &diag[i].num_counters, i);
  1861. if (ret)
  1862. goto err_alloc;
  1863. mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
  1864. diag[i].offset, i);
  1865. }
  1866. ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
  1867. ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
  1868. return 0;
  1869. err_alloc:
  1870. if (i) {
  1871. kfree(diag[i - 1].name);
  1872. kfree(diag[i - 1].offset);
  1873. }
  1874. return ret;
  1875. }
  1876. static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
  1877. {
  1878. int i;
  1879. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1880. kfree(ibdev->diag_counters[i].offset);
  1881. kfree(ibdev->diag_counters[i].name);
  1882. }
  1883. }
  1884. #define MLX4_IB_INVALID_MAC ((u64)-1)
  1885. static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
  1886. struct net_device *dev,
  1887. int port)
  1888. {
  1889. u64 new_smac = 0;
  1890. u64 release_mac = MLX4_IB_INVALID_MAC;
  1891. struct mlx4_ib_qp *qp;
  1892. read_lock(&dev_base_lock);
  1893. new_smac = mlx4_mac_to_u64(dev->dev_addr);
  1894. read_unlock(&dev_base_lock);
  1895. atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
  1896. /* no need for update QP1 and mac registration in non-SRIOV */
  1897. if (!mlx4_is_mfunc(ibdev->dev))
  1898. return;
  1899. mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
  1900. qp = ibdev->qp1_proxy[port - 1];
  1901. if (qp) {
  1902. int new_smac_index;
  1903. u64 old_smac;
  1904. struct mlx4_update_qp_params update_params;
  1905. mutex_lock(&qp->mutex);
  1906. old_smac = qp->pri.smac;
  1907. if (new_smac == old_smac)
  1908. goto unlock;
  1909. new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
  1910. if (new_smac_index < 0)
  1911. goto unlock;
  1912. update_params.smac_index = new_smac_index;
  1913. if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
  1914. &update_params)) {
  1915. release_mac = new_smac;
  1916. goto unlock;
  1917. }
  1918. /* if old port was zero, no mac was yet registered for this QP */
  1919. if (qp->pri.smac_port)
  1920. release_mac = old_smac;
  1921. qp->pri.smac = new_smac;
  1922. qp->pri.smac_port = port;
  1923. qp->pri.smac_index = new_smac_index;
  1924. }
  1925. unlock:
  1926. if (release_mac != MLX4_IB_INVALID_MAC)
  1927. mlx4_unregister_mac(ibdev->dev, port, release_mac);
  1928. if (qp)
  1929. mutex_unlock(&qp->mutex);
  1930. mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
  1931. }
  1932. static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
  1933. struct net_device *dev,
  1934. unsigned long event)
  1935. {
  1936. struct mlx4_ib_iboe *iboe;
  1937. int update_qps_port = -1;
  1938. int port;
  1939. ASSERT_RTNL();
  1940. iboe = &ibdev->iboe;
  1941. spin_lock_bh(&iboe->lock);
  1942. mlx4_foreach_ib_transport_port(port, ibdev->dev) {
  1943. iboe->netdevs[port - 1] =
  1944. mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
  1945. if (dev == iboe->netdevs[port - 1] &&
  1946. (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
  1947. event == NETDEV_UP || event == NETDEV_CHANGE))
  1948. update_qps_port = port;
  1949. }
  1950. spin_unlock_bh(&iboe->lock);
  1951. if (update_qps_port > 0)
  1952. mlx4_ib_update_qps(ibdev, dev, update_qps_port);
  1953. }
  1954. static int mlx4_ib_netdev_event(struct notifier_block *this,
  1955. unsigned long event, void *ptr)
  1956. {
  1957. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  1958. struct mlx4_ib_dev *ibdev;
  1959. if (!net_eq(dev_net(dev), &init_net))
  1960. return NOTIFY_DONE;
  1961. ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
  1962. mlx4_ib_scan_netdevs(ibdev, dev, event);
  1963. return NOTIFY_DONE;
  1964. }
  1965. static void init_pkeys(struct mlx4_ib_dev *ibdev)
  1966. {
  1967. int port;
  1968. int slave;
  1969. int i;
  1970. if (mlx4_is_master(ibdev->dev)) {
  1971. for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
  1972. ++slave) {
  1973. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  1974. for (i = 0;
  1975. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  1976. ++i) {
  1977. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
  1978. /* master has the identity virt2phys pkey mapping */
  1979. (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
  1980. ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
  1981. mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
  1982. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
  1983. }
  1984. }
  1985. }
  1986. /* initialize pkey cache */
  1987. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  1988. for (i = 0;
  1989. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  1990. ++i)
  1991. ibdev->pkeys.phys_pkey_cache[port-1][i] =
  1992. (i) ? 0 : 0xFFFF;
  1993. }
  1994. }
  1995. }
  1996. static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  1997. {
  1998. int i, j, eq = 0, total_eqs = 0;
  1999. ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
  2000. sizeof(ibdev->eq_table[0]), GFP_KERNEL);
  2001. if (!ibdev->eq_table)
  2002. return;
  2003. for (i = 1; i <= dev->caps.num_ports; i++) {
  2004. for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
  2005. j++, total_eqs++) {
  2006. if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
  2007. continue;
  2008. ibdev->eq_table[eq] = total_eqs;
  2009. if (!mlx4_assign_eq(dev, i,
  2010. &ibdev->eq_table[eq]))
  2011. eq++;
  2012. else
  2013. ibdev->eq_table[eq] = -1;
  2014. }
  2015. }
  2016. for (i = eq; i < dev->caps.num_comp_vectors;
  2017. ibdev->eq_table[i++] = -1)
  2018. ;
  2019. /* Advertise the new number of EQs to clients */
  2020. ibdev->ib_dev.num_comp_vectors = eq;
  2021. }
  2022. static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2023. {
  2024. int i;
  2025. int total_eqs = ibdev->ib_dev.num_comp_vectors;
  2026. /* no eqs were allocated */
  2027. if (!ibdev->eq_table)
  2028. return;
  2029. /* Reset the advertised EQ number */
  2030. ibdev->ib_dev.num_comp_vectors = 0;
  2031. for (i = 0; i < total_eqs; i++)
  2032. mlx4_release_eq(dev, ibdev->eq_table[i]);
  2033. kfree(ibdev->eq_table);
  2034. ibdev->eq_table = NULL;
  2035. }
  2036. static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
  2037. struct ib_port_immutable *immutable)
  2038. {
  2039. struct ib_port_attr attr;
  2040. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  2041. int err;
  2042. err = mlx4_ib_query_port(ibdev, port_num, &attr);
  2043. if (err)
  2044. return err;
  2045. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2046. immutable->gid_tbl_len = attr.gid_tbl_len;
  2047. if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
  2048. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  2049. } else {
  2050. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
  2051. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  2052. if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  2053. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
  2054. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  2055. }
  2056. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2057. return 0;
  2058. }
  2059. static void get_fw_ver_str(struct ib_device *device, char *str,
  2060. size_t str_len)
  2061. {
  2062. struct mlx4_ib_dev *dev =
  2063. container_of(device, struct mlx4_ib_dev, ib_dev);
  2064. snprintf(str, str_len, "%d.%d.%d",
  2065. (int) (dev->dev->caps.fw_ver >> 32),
  2066. (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
  2067. (int) dev->dev->caps.fw_ver & 0xffff);
  2068. }
  2069. static void *mlx4_ib_add(struct mlx4_dev *dev)
  2070. {
  2071. struct mlx4_ib_dev *ibdev;
  2072. int num_ports = 0;
  2073. int i, j;
  2074. int err;
  2075. struct mlx4_ib_iboe *iboe;
  2076. int ib_num_ports = 0;
  2077. int num_req_counters;
  2078. int allocated;
  2079. u32 counter_index;
  2080. struct counter_index *new_counter_index = NULL;
  2081. pr_info_once("%s", mlx4_ib_version);
  2082. num_ports = 0;
  2083. mlx4_foreach_ib_transport_port(i, dev)
  2084. num_ports++;
  2085. /* No point in registering a device with no ports... */
  2086. if (num_ports == 0)
  2087. return NULL;
  2088. ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
  2089. if (!ibdev) {
  2090. dev_err(&dev->persist->pdev->dev,
  2091. "Device struct alloc failed\n");
  2092. return NULL;
  2093. }
  2094. iboe = &ibdev->iboe;
  2095. if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
  2096. goto err_dealloc;
  2097. if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
  2098. goto err_pd;
  2099. ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
  2100. PAGE_SIZE);
  2101. if (!ibdev->uar_map)
  2102. goto err_uar;
  2103. MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
  2104. ibdev->dev = dev;
  2105. ibdev->bond_next_port = 0;
  2106. strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
  2107. ibdev->ib_dev.owner = THIS_MODULE;
  2108. ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
  2109. ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
  2110. ibdev->num_ports = num_ports;
  2111. ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
  2112. 1 : ibdev->num_ports;
  2113. ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
  2114. ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
  2115. ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
  2116. ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
  2117. ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
  2118. if (dev->caps.userspace_caps)
  2119. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
  2120. else
  2121. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
  2122. ibdev->ib_dev.uverbs_cmd_mask =
  2123. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2124. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2125. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2126. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2127. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2128. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2129. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  2130. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2131. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2132. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2133. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  2134. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2135. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2136. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2137. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2138. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2139. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  2140. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  2141. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  2142. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  2143. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  2144. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  2145. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  2146. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  2147. ibdev->ib_dev.query_device = mlx4_ib_query_device;
  2148. ibdev->ib_dev.query_port = mlx4_ib_query_port;
  2149. ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
  2150. ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
  2151. ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
  2152. ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
  2153. ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
  2154. ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
  2155. ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
  2156. ibdev->ib_dev.mmap = mlx4_ib_mmap;
  2157. ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
  2158. ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
  2159. ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
  2160. ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
  2161. ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
  2162. ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
  2163. ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
  2164. ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
  2165. ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
  2166. ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
  2167. ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
  2168. ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
  2169. ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
  2170. ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
  2171. ibdev->ib_dev.post_send = mlx4_ib_post_send;
  2172. ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
  2173. ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
  2174. ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
  2175. ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
  2176. ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
  2177. ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
  2178. ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
  2179. ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
  2180. ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
  2181. ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
  2182. ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
  2183. ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
  2184. ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
  2185. ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
  2186. ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
  2187. ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
  2188. ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
  2189. ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
  2190. ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
  2191. if (!mlx4_is_slave(ibdev->dev)) {
  2192. ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
  2193. ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
  2194. ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
  2195. ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
  2196. }
  2197. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
  2198. dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  2199. ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
  2200. ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
  2201. ibdev->ib_dev.uverbs_cmd_mask |=
  2202. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  2203. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  2204. }
  2205. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
  2206. ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
  2207. ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
  2208. ibdev->ib_dev.uverbs_cmd_mask |=
  2209. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  2210. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  2211. }
  2212. if (check_flow_steering_support(dev)) {
  2213. ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
  2214. ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
  2215. ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
  2216. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2217. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  2218. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  2219. }
  2220. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2221. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  2222. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
  2223. (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
  2224. mlx4_ib_alloc_eqs(dev, ibdev);
  2225. spin_lock_init(&iboe->lock);
  2226. if (init_node_data(ibdev))
  2227. goto err_map;
  2228. for (i = 0; i < ibdev->num_ports; ++i) {
  2229. mutex_init(&ibdev->counters_table[i].mutex);
  2230. INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
  2231. }
  2232. num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
  2233. for (i = 0; i < num_req_counters; ++i) {
  2234. mutex_init(&ibdev->qp1_proxy_lock[i]);
  2235. allocated = 0;
  2236. if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
  2237. IB_LINK_LAYER_ETHERNET) {
  2238. err = mlx4_counter_alloc(ibdev->dev, &counter_index);
  2239. /* if failed to allocate a new counter, use default */
  2240. if (err)
  2241. counter_index =
  2242. mlx4_get_default_counter_index(dev,
  2243. i + 1);
  2244. else
  2245. allocated = 1;
  2246. } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
  2247. counter_index = mlx4_get_default_counter_index(dev,
  2248. i + 1);
  2249. }
  2250. new_counter_index = kmalloc(sizeof(*new_counter_index),
  2251. GFP_KERNEL);
  2252. if (!new_counter_index) {
  2253. if (allocated)
  2254. mlx4_counter_free(ibdev->dev, counter_index);
  2255. goto err_counter;
  2256. }
  2257. new_counter_index->index = counter_index;
  2258. new_counter_index->allocated = allocated;
  2259. list_add_tail(&new_counter_index->list,
  2260. &ibdev->counters_table[i].counters_list);
  2261. ibdev->counters_table[i].default_counter = counter_index;
  2262. pr_info("counter index %d for port %d allocated %d\n",
  2263. counter_index, i + 1, allocated);
  2264. }
  2265. if (mlx4_is_bonded(dev))
  2266. for (i = 1; i < ibdev->num_ports ; ++i) {
  2267. new_counter_index =
  2268. kmalloc(sizeof(struct counter_index),
  2269. GFP_KERNEL);
  2270. if (!new_counter_index)
  2271. goto err_counter;
  2272. new_counter_index->index = counter_index;
  2273. new_counter_index->allocated = 0;
  2274. list_add_tail(&new_counter_index->list,
  2275. &ibdev->counters_table[i].counters_list);
  2276. ibdev->counters_table[i].default_counter =
  2277. counter_index;
  2278. }
  2279. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2280. ib_num_ports++;
  2281. spin_lock_init(&ibdev->sm_lock);
  2282. mutex_init(&ibdev->cap_mask_mutex);
  2283. INIT_LIST_HEAD(&ibdev->qp_list);
  2284. spin_lock_init(&ibdev->reset_flow_resource_lock);
  2285. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
  2286. ib_num_ports) {
  2287. ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
  2288. err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
  2289. MLX4_IB_UC_STEER_QPN_ALIGN,
  2290. &ibdev->steer_qpn_base, 0);
  2291. if (err)
  2292. goto err_counter;
  2293. ibdev->ib_uc_qpns_bitmap =
  2294. kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
  2295. sizeof(long),
  2296. GFP_KERNEL);
  2297. if (!ibdev->ib_uc_qpns_bitmap) {
  2298. dev_err(&dev->persist->pdev->dev,
  2299. "bit map alloc failed\n");
  2300. goto err_steer_qp_release;
  2301. }
  2302. bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
  2303. err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
  2304. dev, ibdev->steer_qpn_base,
  2305. ibdev->steer_qpn_base +
  2306. ibdev->steer_qpn_count - 1);
  2307. if (err)
  2308. goto err_steer_free_bitmap;
  2309. }
  2310. for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
  2311. atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
  2312. if (mlx4_ib_alloc_diag_counters(ibdev))
  2313. goto err_steer_free_bitmap;
  2314. if (ib_register_device(&ibdev->ib_dev, NULL))
  2315. goto err_diag_counters;
  2316. if (mlx4_ib_mad_init(ibdev))
  2317. goto err_reg;
  2318. if (mlx4_ib_init_sriov(ibdev))
  2319. goto err_mad;
  2320. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE ||
  2321. dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
  2322. if (!iboe->nb.notifier_call) {
  2323. iboe->nb.notifier_call = mlx4_ib_netdev_event;
  2324. err = register_netdevice_notifier(&iboe->nb);
  2325. if (err) {
  2326. iboe->nb.notifier_call = NULL;
  2327. goto err_notif;
  2328. }
  2329. }
  2330. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
  2331. err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
  2332. if (err) {
  2333. goto err_notif;
  2334. }
  2335. }
  2336. }
  2337. for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
  2338. if (device_create_file(&ibdev->ib_dev.dev,
  2339. mlx4_class_attributes[j]))
  2340. goto err_notif;
  2341. }
  2342. ibdev->ib_active = true;
  2343. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2344. devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
  2345. &ibdev->ib_dev);
  2346. if (mlx4_is_mfunc(ibdev->dev))
  2347. init_pkeys(ibdev);
  2348. /* create paravirt contexts for any VFs which are active */
  2349. if (mlx4_is_master(ibdev->dev)) {
  2350. for (j = 0; j < MLX4_MFUNC_MAX; j++) {
  2351. if (j == mlx4_master_func_num(ibdev->dev))
  2352. continue;
  2353. if (mlx4_is_slave_active(ibdev->dev, j))
  2354. do_slave_init(ibdev, j, 1);
  2355. }
  2356. }
  2357. return ibdev;
  2358. err_notif:
  2359. if (ibdev->iboe.nb.notifier_call) {
  2360. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2361. pr_warn("failure unregistering notifier\n");
  2362. ibdev->iboe.nb.notifier_call = NULL;
  2363. }
  2364. flush_workqueue(wq);
  2365. mlx4_ib_close_sriov(ibdev);
  2366. err_mad:
  2367. mlx4_ib_mad_cleanup(ibdev);
  2368. err_reg:
  2369. ib_unregister_device(&ibdev->ib_dev);
  2370. err_diag_counters:
  2371. mlx4_ib_diag_cleanup(ibdev);
  2372. err_steer_free_bitmap:
  2373. kfree(ibdev->ib_uc_qpns_bitmap);
  2374. err_steer_qp_release:
  2375. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  2376. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2377. ibdev->steer_qpn_count);
  2378. err_counter:
  2379. for (i = 0; i < ibdev->num_ports; ++i)
  2380. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
  2381. err_map:
  2382. iounmap(ibdev->uar_map);
  2383. err_uar:
  2384. mlx4_uar_free(dev, &ibdev->priv_uar);
  2385. err_pd:
  2386. mlx4_pd_free(dev, ibdev->priv_pdn);
  2387. err_dealloc:
  2388. ib_dealloc_device(&ibdev->ib_dev);
  2389. return NULL;
  2390. }
  2391. int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
  2392. {
  2393. int offset;
  2394. WARN_ON(!dev->ib_uc_qpns_bitmap);
  2395. offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
  2396. dev->steer_qpn_count,
  2397. get_count_order(count));
  2398. if (offset < 0)
  2399. return offset;
  2400. *qpn = dev->steer_qpn_base + offset;
  2401. return 0;
  2402. }
  2403. void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
  2404. {
  2405. if (!qpn ||
  2406. dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
  2407. return;
  2408. BUG_ON(qpn < dev->steer_qpn_base);
  2409. bitmap_release_region(dev->ib_uc_qpns_bitmap,
  2410. qpn - dev->steer_qpn_base,
  2411. get_count_order(count));
  2412. }
  2413. int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  2414. int is_attach)
  2415. {
  2416. int err;
  2417. size_t flow_size;
  2418. struct ib_flow_attr *flow = NULL;
  2419. struct ib_flow_spec_ib *ib_spec;
  2420. if (is_attach) {
  2421. flow_size = sizeof(struct ib_flow_attr) +
  2422. sizeof(struct ib_flow_spec_ib);
  2423. flow = kzalloc(flow_size, GFP_KERNEL);
  2424. if (!flow)
  2425. return -ENOMEM;
  2426. flow->port = mqp->port;
  2427. flow->num_of_specs = 1;
  2428. flow->size = flow_size;
  2429. ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
  2430. ib_spec->type = IB_FLOW_SPEC_IB;
  2431. ib_spec->size = sizeof(struct ib_flow_spec_ib);
  2432. /* Add an empty rule for IB L2 */
  2433. memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
  2434. err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
  2435. IB_FLOW_DOMAIN_NIC,
  2436. MLX4_FS_REGULAR,
  2437. &mqp->reg_id);
  2438. } else {
  2439. err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
  2440. }
  2441. kfree(flow);
  2442. return err;
  2443. }
  2444. static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
  2445. {
  2446. struct mlx4_ib_dev *ibdev = ibdev_ptr;
  2447. int p;
  2448. int i;
  2449. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2450. devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
  2451. ibdev->ib_active = false;
  2452. flush_workqueue(wq);
  2453. mlx4_ib_close_sriov(ibdev);
  2454. mlx4_ib_mad_cleanup(ibdev);
  2455. ib_unregister_device(&ibdev->ib_dev);
  2456. mlx4_ib_diag_cleanup(ibdev);
  2457. if (ibdev->iboe.nb.notifier_call) {
  2458. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2459. pr_warn("failure unregistering notifier\n");
  2460. ibdev->iboe.nb.notifier_call = NULL;
  2461. }
  2462. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
  2463. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2464. ibdev->steer_qpn_count);
  2465. kfree(ibdev->ib_uc_qpns_bitmap);
  2466. }
  2467. iounmap(ibdev->uar_map);
  2468. for (p = 0; p < ibdev->num_ports; ++p)
  2469. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
  2470. mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
  2471. mlx4_CLOSE_PORT(dev, p);
  2472. mlx4_ib_free_eqs(dev, ibdev);
  2473. mlx4_uar_free(dev, &ibdev->priv_uar);
  2474. mlx4_pd_free(dev, ibdev->priv_pdn);
  2475. ib_dealloc_device(&ibdev->ib_dev);
  2476. }
  2477. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
  2478. {
  2479. struct mlx4_ib_demux_work **dm = NULL;
  2480. struct mlx4_dev *dev = ibdev->dev;
  2481. int i;
  2482. unsigned long flags;
  2483. struct mlx4_active_ports actv_ports;
  2484. unsigned int ports;
  2485. unsigned int first_port;
  2486. if (!mlx4_is_master(dev))
  2487. return;
  2488. actv_ports = mlx4_get_active_ports(dev, slave);
  2489. ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
  2490. first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
  2491. dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
  2492. if (!dm) {
  2493. pr_err("failed to allocate memory for tunneling qp update\n");
  2494. return;
  2495. }
  2496. for (i = 0; i < ports; i++) {
  2497. dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
  2498. if (!dm[i]) {
  2499. pr_err("failed to allocate memory for tunneling qp update work struct\n");
  2500. while (--i >= 0)
  2501. kfree(dm[i]);
  2502. goto out;
  2503. }
  2504. INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
  2505. dm[i]->port = first_port + i + 1;
  2506. dm[i]->slave = slave;
  2507. dm[i]->do_init = do_init;
  2508. dm[i]->dev = ibdev;
  2509. }
  2510. /* initialize or tear down tunnel QPs for the slave */
  2511. spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
  2512. if (!ibdev->sriov.is_going_down) {
  2513. for (i = 0; i < ports; i++)
  2514. queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
  2515. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2516. } else {
  2517. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2518. for (i = 0; i < ports; i++)
  2519. kfree(dm[i]);
  2520. }
  2521. out:
  2522. kfree(dm);
  2523. return;
  2524. }
  2525. static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
  2526. {
  2527. struct mlx4_ib_qp *mqp;
  2528. unsigned long flags_qp;
  2529. unsigned long flags_cq;
  2530. struct mlx4_ib_cq *send_mcq, *recv_mcq;
  2531. struct list_head cq_notify_list;
  2532. struct mlx4_cq *mcq;
  2533. unsigned long flags;
  2534. pr_warn("mlx4_ib_handle_catas_error was started\n");
  2535. INIT_LIST_HEAD(&cq_notify_list);
  2536. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  2537. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  2538. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  2539. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  2540. if (mqp->sq.tail != mqp->sq.head) {
  2541. send_mcq = to_mcq(mqp->ibqp.send_cq);
  2542. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  2543. if (send_mcq->mcq.comp &&
  2544. mqp->ibqp.send_cq->comp_handler) {
  2545. if (!send_mcq->mcq.reset_notify_added) {
  2546. send_mcq->mcq.reset_notify_added = 1;
  2547. list_add_tail(&send_mcq->mcq.reset_notify,
  2548. &cq_notify_list);
  2549. }
  2550. }
  2551. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  2552. }
  2553. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  2554. /* Now, handle the QP's receive queue */
  2555. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  2556. /* no handling is needed for SRQ */
  2557. if (!mqp->ibqp.srq) {
  2558. if (mqp->rq.tail != mqp->rq.head) {
  2559. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  2560. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  2561. if (recv_mcq->mcq.comp &&
  2562. mqp->ibqp.recv_cq->comp_handler) {
  2563. if (!recv_mcq->mcq.reset_notify_added) {
  2564. recv_mcq->mcq.reset_notify_added = 1;
  2565. list_add_tail(&recv_mcq->mcq.reset_notify,
  2566. &cq_notify_list);
  2567. }
  2568. }
  2569. spin_unlock_irqrestore(&recv_mcq->lock,
  2570. flags_cq);
  2571. }
  2572. }
  2573. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  2574. }
  2575. list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
  2576. mcq->comp(mcq);
  2577. }
  2578. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  2579. pr_warn("mlx4_ib_handle_catas_error ended\n");
  2580. }
  2581. static void handle_bonded_port_state_event(struct work_struct *work)
  2582. {
  2583. struct ib_event_work *ew =
  2584. container_of(work, struct ib_event_work, work);
  2585. struct mlx4_ib_dev *ibdev = ew->ib_dev;
  2586. enum ib_port_state bonded_port_state = IB_PORT_NOP;
  2587. int i;
  2588. struct ib_event ibev;
  2589. kfree(ew);
  2590. spin_lock_bh(&ibdev->iboe.lock);
  2591. for (i = 0; i < MLX4_MAX_PORTS; ++i) {
  2592. struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
  2593. enum ib_port_state curr_port_state;
  2594. if (!curr_netdev)
  2595. continue;
  2596. curr_port_state =
  2597. (netif_running(curr_netdev) &&
  2598. netif_carrier_ok(curr_netdev)) ?
  2599. IB_PORT_ACTIVE : IB_PORT_DOWN;
  2600. bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
  2601. curr_port_state : IB_PORT_ACTIVE;
  2602. }
  2603. spin_unlock_bh(&ibdev->iboe.lock);
  2604. ibev.device = &ibdev->ib_dev;
  2605. ibev.element.port_num = 1;
  2606. ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
  2607. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2608. ib_dispatch_event(&ibev);
  2609. }
  2610. static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
  2611. enum mlx4_dev_event event, unsigned long param)
  2612. {
  2613. struct ib_event ibev;
  2614. struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
  2615. struct mlx4_eqe *eqe = NULL;
  2616. struct ib_event_work *ew;
  2617. int p = 0;
  2618. if (mlx4_is_bonded(dev) &&
  2619. ((event == MLX4_DEV_EVENT_PORT_UP) ||
  2620. (event == MLX4_DEV_EVENT_PORT_DOWN))) {
  2621. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2622. if (!ew)
  2623. return;
  2624. INIT_WORK(&ew->work, handle_bonded_port_state_event);
  2625. ew->ib_dev = ibdev;
  2626. queue_work(wq, &ew->work);
  2627. return;
  2628. }
  2629. if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
  2630. eqe = (struct mlx4_eqe *)param;
  2631. else
  2632. p = (int) param;
  2633. switch (event) {
  2634. case MLX4_DEV_EVENT_PORT_UP:
  2635. if (p > ibdev->num_ports)
  2636. return;
  2637. if (mlx4_is_master(dev) &&
  2638. rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
  2639. IB_LINK_LAYER_INFINIBAND) {
  2640. mlx4_ib_invalidate_all_guid_record(ibdev, p);
  2641. }
  2642. ibev.event = IB_EVENT_PORT_ACTIVE;
  2643. break;
  2644. case MLX4_DEV_EVENT_PORT_DOWN:
  2645. if (p > ibdev->num_ports)
  2646. return;
  2647. ibev.event = IB_EVENT_PORT_ERR;
  2648. break;
  2649. case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
  2650. ibdev->ib_active = false;
  2651. ibev.event = IB_EVENT_DEVICE_FATAL;
  2652. mlx4_ib_handle_catas_error(ibdev);
  2653. break;
  2654. case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
  2655. ew = kmalloc(sizeof *ew, GFP_ATOMIC);
  2656. if (!ew) {
  2657. pr_err("failed to allocate memory for events work\n");
  2658. break;
  2659. }
  2660. INIT_WORK(&ew->work, handle_port_mgmt_change_event);
  2661. memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
  2662. ew->ib_dev = ibdev;
  2663. /* need to queue only for port owner, which uses GEN_EQE */
  2664. if (mlx4_is_master(dev))
  2665. queue_work(wq, &ew->work);
  2666. else
  2667. handle_port_mgmt_change_event(&ew->work);
  2668. return;
  2669. case MLX4_DEV_EVENT_SLAVE_INIT:
  2670. /* here, p is the slave id */
  2671. do_slave_init(ibdev, p, 1);
  2672. if (mlx4_is_master(dev)) {
  2673. int i;
  2674. for (i = 1; i <= ibdev->num_ports; i++) {
  2675. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2676. == IB_LINK_LAYER_INFINIBAND)
  2677. mlx4_ib_slave_alias_guid_event(ibdev,
  2678. p, i,
  2679. 1);
  2680. }
  2681. }
  2682. return;
  2683. case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
  2684. if (mlx4_is_master(dev)) {
  2685. int i;
  2686. for (i = 1; i <= ibdev->num_ports; i++) {
  2687. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2688. == IB_LINK_LAYER_INFINIBAND)
  2689. mlx4_ib_slave_alias_guid_event(ibdev,
  2690. p, i,
  2691. 0);
  2692. }
  2693. }
  2694. /* here, p is the slave id */
  2695. do_slave_init(ibdev, p, 0);
  2696. return;
  2697. default:
  2698. return;
  2699. }
  2700. ibev.device = ibdev_ptr;
  2701. ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
  2702. ib_dispatch_event(&ibev);
  2703. }
  2704. static struct mlx4_interface mlx4_ib_interface = {
  2705. .add = mlx4_ib_add,
  2706. .remove = mlx4_ib_remove,
  2707. .event = mlx4_ib_event,
  2708. .protocol = MLX4_PROT_IB_IPV6,
  2709. .flags = MLX4_INTFF_BONDING
  2710. };
  2711. static int __init mlx4_ib_init(void)
  2712. {
  2713. int err;
  2714. wq = create_singlethread_workqueue("mlx4_ib");
  2715. if (!wq)
  2716. return -ENOMEM;
  2717. err = mlx4_ib_mcg_init();
  2718. if (err)
  2719. goto clean_wq;
  2720. err = mlx4_register_interface(&mlx4_ib_interface);
  2721. if (err)
  2722. goto clean_mcg;
  2723. return 0;
  2724. clean_mcg:
  2725. mlx4_ib_mcg_destroy();
  2726. clean_wq:
  2727. destroy_workqueue(wq);
  2728. return err;
  2729. }
  2730. static void __exit mlx4_ib_cleanup(void)
  2731. {
  2732. mlx4_unregister_interface(&mlx4_ib_interface);
  2733. mlx4_ib_mcg_destroy();
  2734. destroy_workqueue(wq);
  2735. }
  2736. module_init(mlx4_ib_init);
  2737. module_exit(mlx4_ib_cleanup);