i40iw_verbs.c 75 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/random.h>
  37. #include <linux/highmem.h>
  38. #include <linux/time.h>
  39. #include <asm/byteorder.h>
  40. #include <net/ip.h>
  41. #include <rdma/ib_verbs.h>
  42. #include <rdma/iw_cm.h>
  43. #include <rdma/ib_user_verbs.h>
  44. #include <rdma/ib_umem.h>
  45. #include "i40iw.h"
  46. /**
  47. * i40iw_query_device - get device attributes
  48. * @ibdev: device pointer from stack
  49. * @props: returning device attributes
  50. * @udata: user data
  51. */
  52. static int i40iw_query_device(struct ib_device *ibdev,
  53. struct ib_device_attr *props,
  54. struct ib_udata *udata)
  55. {
  56. struct i40iw_device *iwdev = to_iwdev(ibdev);
  57. if (udata->inlen || udata->outlen)
  58. return -EINVAL;
  59. memset(props, 0, sizeof(*props));
  60. ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
  61. props->fw_ver = I40IW_FW_VERSION;
  62. props->device_cap_flags = iwdev->device_cap_flags;
  63. props->vendor_id = iwdev->ldev->pcidev->vendor;
  64. props->vendor_part_id = iwdev->ldev->pcidev->device;
  65. props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
  66. props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  67. props->max_qp = iwdev->max_qp;
  68. props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1;
  69. props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  70. props->max_cq = iwdev->max_cq;
  71. props->max_cqe = iwdev->max_cqe;
  72. props->max_mr = iwdev->max_mr;
  73. props->max_pd = iwdev->max_pd;
  74. props->max_sge_rd = I40IW_MAX_SGE_RD;
  75. props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
  76. props->max_qp_init_rd_atom = props->max_qp_rd_atom;
  77. props->atomic_cap = IB_ATOMIC_NONE;
  78. props->max_map_per_fmr = 1;
  79. props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
  80. return 0;
  81. }
  82. /**
  83. * i40iw_query_port - get port attrubutes
  84. * @ibdev: device pointer from stack
  85. * @port: port number for query
  86. * @props: returning device attributes
  87. */
  88. static int i40iw_query_port(struct ib_device *ibdev,
  89. u8 port,
  90. struct ib_port_attr *props)
  91. {
  92. struct i40iw_device *iwdev = to_iwdev(ibdev);
  93. struct net_device *netdev = iwdev->netdev;
  94. memset(props, 0, sizeof(*props));
  95. props->max_mtu = IB_MTU_4096;
  96. if (netdev->mtu >= 4096)
  97. props->active_mtu = IB_MTU_4096;
  98. else if (netdev->mtu >= 2048)
  99. props->active_mtu = IB_MTU_2048;
  100. else if (netdev->mtu >= 1024)
  101. props->active_mtu = IB_MTU_1024;
  102. else if (netdev->mtu >= 512)
  103. props->active_mtu = IB_MTU_512;
  104. else
  105. props->active_mtu = IB_MTU_256;
  106. props->lid = 1;
  107. if (netif_carrier_ok(iwdev->netdev))
  108. props->state = IB_PORT_ACTIVE;
  109. else
  110. props->state = IB_PORT_DOWN;
  111. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  112. IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
  113. props->gid_tbl_len = 1;
  114. props->pkey_tbl_len = 1;
  115. props->active_width = IB_WIDTH_4X;
  116. props->active_speed = 1;
  117. props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  118. return 0;
  119. }
  120. /**
  121. * i40iw_alloc_ucontext - Allocate the user context data structure
  122. * @ibdev: device pointer from stack
  123. * @udata: user data
  124. *
  125. * This keeps track of all objects associated with a particular
  126. * user-mode client.
  127. */
  128. static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
  129. struct ib_udata *udata)
  130. {
  131. struct i40iw_device *iwdev = to_iwdev(ibdev);
  132. struct i40iw_alloc_ucontext_req req;
  133. struct i40iw_alloc_ucontext_resp uresp;
  134. struct i40iw_ucontext *ucontext;
  135. if (ib_copy_from_udata(&req, udata, sizeof(req)))
  136. return ERR_PTR(-EINVAL);
  137. if (req.userspace_ver != I40IW_ABI_USERSPACE_VER) {
  138. i40iw_pr_err("Invalid userspace driver version detected. Detected version %d, should be %d\n",
  139. req.userspace_ver, I40IW_ABI_USERSPACE_VER);
  140. return ERR_PTR(-EINVAL);
  141. }
  142. memset(&uresp, 0, sizeof(uresp));
  143. uresp.max_qps = iwdev->max_qp;
  144. uresp.max_pds = iwdev->max_pd;
  145. uresp.wq_size = iwdev->max_qp_wr * 2;
  146. uresp.kernel_ver = I40IW_ABI_KERNEL_VER;
  147. ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
  148. if (!ucontext)
  149. return ERR_PTR(-ENOMEM);
  150. ucontext->iwdev = iwdev;
  151. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  152. kfree(ucontext);
  153. return ERR_PTR(-EFAULT);
  154. }
  155. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  156. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  157. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  158. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  159. return &ucontext->ibucontext;
  160. }
  161. /**
  162. * i40iw_dealloc_ucontext - deallocate the user context data structure
  163. * @context: user context created during alloc
  164. */
  165. static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
  166. {
  167. struct i40iw_ucontext *ucontext = to_ucontext(context);
  168. unsigned long flags;
  169. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  170. if (!list_empty(&ucontext->cq_reg_mem_list)) {
  171. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  172. return -EBUSY;
  173. }
  174. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  175. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  176. if (!list_empty(&ucontext->qp_reg_mem_list)) {
  177. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  178. return -EBUSY;
  179. }
  180. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  181. kfree(ucontext);
  182. return 0;
  183. }
  184. /**
  185. * i40iw_mmap - user memory map
  186. * @context: context created during alloc
  187. * @vma: kernel info for user memory map
  188. */
  189. static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  190. {
  191. struct i40iw_ucontext *ucontext;
  192. u64 db_addr_offset;
  193. u64 push_offset;
  194. ucontext = to_ucontext(context);
  195. if (ucontext->iwdev->sc_dev.is_pf) {
  196. db_addr_offset = I40IW_DB_ADDR_OFFSET;
  197. push_offset = I40IW_PUSH_OFFSET;
  198. if (vma->vm_pgoff)
  199. vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1;
  200. } else {
  201. db_addr_offset = I40IW_VF_DB_ADDR_OFFSET;
  202. push_offset = I40IW_VF_PUSH_OFFSET;
  203. if (vma->vm_pgoff)
  204. vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1;
  205. }
  206. vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT;
  207. if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) {
  208. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  209. vma->vm_private_data = ucontext;
  210. } else {
  211. if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2)
  212. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  213. else
  214. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  215. }
  216. if (io_remap_pfn_range(vma, vma->vm_start,
  217. vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT),
  218. PAGE_SIZE, vma->vm_page_prot))
  219. return -EAGAIN;
  220. return 0;
  221. }
  222. /**
  223. * i40iw_alloc_push_page - allocate a push page for qp
  224. * @iwdev: iwarp device
  225. * @qp: hardware control qp
  226. */
  227. static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  228. {
  229. struct i40iw_cqp_request *cqp_request;
  230. struct cqp_commands_info *cqp_info;
  231. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  232. enum i40iw_status_code status;
  233. if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
  234. return;
  235. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  236. if (!cqp_request)
  237. return;
  238. atomic_inc(&cqp_request->refcount);
  239. cqp_info = &cqp_request->info;
  240. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  241. cqp_info->post_sq = 1;
  242. cqp_info->in.u.manage_push_page.info.qs_handle = dev->qs_handle;
  243. cqp_info->in.u.manage_push_page.info.free_page = 0;
  244. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  245. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  246. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  247. if (!status)
  248. qp->push_idx = cqp_request->compl_info.op_ret_val;
  249. else
  250. i40iw_pr_err("CQP-OP Push page fail");
  251. i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
  252. }
  253. /**
  254. * i40iw_dealloc_push_page - free a push page for qp
  255. * @iwdev: iwarp device
  256. * @qp: hardware control qp
  257. */
  258. static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  259. {
  260. struct i40iw_cqp_request *cqp_request;
  261. struct cqp_commands_info *cqp_info;
  262. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  263. enum i40iw_status_code status;
  264. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
  265. return;
  266. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
  267. if (!cqp_request)
  268. return;
  269. cqp_info = &cqp_request->info;
  270. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  271. cqp_info->post_sq = 1;
  272. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  273. cqp_info->in.u.manage_push_page.info.qs_handle = dev->qs_handle;
  274. cqp_info->in.u.manage_push_page.info.free_page = 1;
  275. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  276. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  277. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  278. if (!status)
  279. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  280. else
  281. i40iw_pr_err("CQP-OP Push page fail");
  282. }
  283. /**
  284. * i40iw_alloc_pd - allocate protection domain
  285. * @ibdev: device pointer from stack
  286. * @context: user context created during alloc
  287. * @udata: user data
  288. */
  289. static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
  290. struct ib_ucontext *context,
  291. struct ib_udata *udata)
  292. {
  293. struct i40iw_pd *iwpd;
  294. struct i40iw_device *iwdev = to_iwdev(ibdev);
  295. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  296. struct i40iw_alloc_pd_resp uresp;
  297. struct i40iw_sc_pd *sc_pd;
  298. u32 pd_id = 0;
  299. int err;
  300. err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
  301. iwdev->max_pd, &pd_id, &iwdev->next_pd);
  302. if (err) {
  303. i40iw_pr_err("alloc resource failed\n");
  304. return ERR_PTR(err);
  305. }
  306. iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
  307. if (!iwpd) {
  308. err = -ENOMEM;
  309. goto free_res;
  310. }
  311. sc_pd = &iwpd->sc_pd;
  312. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id);
  313. if (context) {
  314. memset(&uresp, 0, sizeof(uresp));
  315. uresp.pd_id = pd_id;
  316. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  317. err = -EFAULT;
  318. goto error;
  319. }
  320. }
  321. i40iw_add_pdusecount(iwpd);
  322. return &iwpd->ibpd;
  323. error:
  324. kfree(iwpd);
  325. free_res:
  326. i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
  327. return ERR_PTR(err);
  328. }
  329. /**
  330. * i40iw_dealloc_pd - deallocate pd
  331. * @ibpd: ptr of pd to be deallocated
  332. */
  333. static int i40iw_dealloc_pd(struct ib_pd *ibpd)
  334. {
  335. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  336. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  337. i40iw_rem_pdusecount(iwpd, iwdev);
  338. return 0;
  339. }
  340. /**
  341. * i40iw_qp_roundup - return round up qp ring size
  342. * @wr_ring_size: ring size to round up
  343. */
  344. static int i40iw_qp_roundup(u32 wr_ring_size)
  345. {
  346. int scount = 1;
  347. if (wr_ring_size < I40IWQP_SW_MIN_WQSIZE)
  348. wr_ring_size = I40IWQP_SW_MIN_WQSIZE;
  349. for (wr_ring_size--; scount <= 16; scount *= 2)
  350. wr_ring_size |= wr_ring_size >> scount;
  351. return ++wr_ring_size;
  352. }
  353. /**
  354. * i40iw_get_pbl - Retrieve pbl from a list given a virtual
  355. * address
  356. * @va: user virtual address
  357. * @pbl_list: pbl list to search in (QP's or CQ's)
  358. */
  359. static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
  360. struct list_head *pbl_list)
  361. {
  362. struct i40iw_pbl *iwpbl;
  363. list_for_each_entry(iwpbl, pbl_list, list) {
  364. if (iwpbl->user_base == va) {
  365. list_del(&iwpbl->list);
  366. return iwpbl;
  367. }
  368. }
  369. return NULL;
  370. }
  371. /**
  372. * i40iw_free_qp_resources - free up memory resources for qp
  373. * @iwdev: iwarp device
  374. * @iwqp: qp ptr (user or kernel)
  375. * @qp_num: qp number assigned
  376. */
  377. void i40iw_free_qp_resources(struct i40iw_device *iwdev,
  378. struct i40iw_qp *iwqp,
  379. u32 qp_num)
  380. {
  381. i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
  382. if (qp_num)
  383. i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
  384. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
  385. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
  386. kfree(iwqp->kqp.wrid_mem);
  387. iwqp->kqp.wrid_mem = NULL;
  388. kfree(iwqp->allocated_buffer);
  389. }
  390. /**
  391. * i40iw_clean_cqes - clean cq entries for qp
  392. * @iwqp: qp ptr (user or kernel)
  393. * @iwcq: cq ptr
  394. */
  395. static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
  396. {
  397. struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  398. ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
  399. }
  400. /**
  401. * i40iw_destroy_qp - destroy qp
  402. * @ibqp: qp's ib pointer also to get to device's qp address
  403. */
  404. static int i40iw_destroy_qp(struct ib_qp *ibqp)
  405. {
  406. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  407. iwqp->destroyed = 1;
  408. if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
  409. i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
  410. if (!iwqp->user_mode) {
  411. if (iwqp->iwscq) {
  412. i40iw_clean_cqes(iwqp, iwqp->iwscq);
  413. if (iwqp->iwrcq != iwqp->iwscq)
  414. i40iw_clean_cqes(iwqp, iwqp->iwrcq);
  415. }
  416. }
  417. i40iw_rem_ref(&iwqp->ibqp);
  418. return 0;
  419. }
  420. /**
  421. * i40iw_setup_virt_qp - setup for allocation of virtual qp
  422. * @dev: iwarp device
  423. * @qp: qp ptr
  424. * @init_info: initialize info to return
  425. */
  426. static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
  427. struct i40iw_qp *iwqp,
  428. struct i40iw_qp_init_info *init_info)
  429. {
  430. struct i40iw_pbl *iwpbl = iwqp->iwpbl;
  431. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  432. iwqp->page = qpmr->sq_page;
  433. init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
  434. if (iwpbl->pbl_allocated) {
  435. init_info->virtual_map = true;
  436. init_info->sq_pa = qpmr->sq_pbl.idx;
  437. init_info->rq_pa = qpmr->rq_pbl.idx;
  438. } else {
  439. init_info->sq_pa = qpmr->sq_pbl.addr;
  440. init_info->rq_pa = qpmr->rq_pbl.addr;
  441. }
  442. return 0;
  443. }
  444. /**
  445. * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
  446. * @iwdev: iwarp device
  447. * @iwqp: qp ptr (user or kernel)
  448. * @info: initialize info to return
  449. */
  450. static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
  451. struct i40iw_qp *iwqp,
  452. struct i40iw_qp_init_info *info)
  453. {
  454. struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
  455. u32 sqdepth, rqdepth;
  456. u32 sq_size, rq_size;
  457. u8 sqshift, rqshift;
  458. u32 size;
  459. enum i40iw_status_code status;
  460. struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  461. sq_size = i40iw_qp_roundup(ukinfo->sq_size + 1);
  462. rq_size = i40iw_qp_roundup(ukinfo->rq_size + 1);
  463. status = i40iw_get_wqe_shift(sq_size, ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
  464. if (!status)
  465. status = i40iw_get_wqe_shift(rq_size, ukinfo->max_rq_frag_cnt, 0, &rqshift);
  466. if (status)
  467. return -ENOMEM;
  468. sqdepth = sq_size << sqshift;
  469. rqdepth = rq_size << rqshift;
  470. size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
  471. iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
  472. ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
  473. if (!ukinfo->sq_wrtrk_array)
  474. return -ENOMEM;
  475. ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
  476. size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
  477. size += (I40IW_SHADOW_AREA_SIZE << 3);
  478. status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
  479. if (status) {
  480. kfree(ukinfo->sq_wrtrk_array);
  481. ukinfo->sq_wrtrk_array = NULL;
  482. return -ENOMEM;
  483. }
  484. ukinfo->sq = mem->va;
  485. info->sq_pa = mem->pa;
  486. ukinfo->rq = &ukinfo->sq[sqdepth];
  487. info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
  488. ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
  489. info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
  490. ukinfo->sq_size = sq_size;
  491. ukinfo->rq_size = rq_size;
  492. ukinfo->qp_id = iwqp->ibqp.qp_num;
  493. return 0;
  494. }
  495. /**
  496. * i40iw_create_qp - create qp
  497. * @ibpd: ptr of pd
  498. * @init_attr: attributes for qp
  499. * @udata: user data for create qp
  500. */
  501. static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
  502. struct ib_qp_init_attr *init_attr,
  503. struct ib_udata *udata)
  504. {
  505. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  506. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  507. struct i40iw_cqp *iwcqp = &iwdev->cqp;
  508. struct i40iw_qp *iwqp;
  509. struct i40iw_ucontext *ucontext;
  510. struct i40iw_create_qp_req req;
  511. struct i40iw_create_qp_resp uresp;
  512. u32 qp_num = 0;
  513. void *mem;
  514. enum i40iw_status_code ret;
  515. int err_code;
  516. int sq_size;
  517. int rq_size;
  518. struct i40iw_sc_qp *qp;
  519. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  520. struct i40iw_qp_init_info init_info;
  521. struct i40iw_create_qp_info *qp_info;
  522. struct i40iw_cqp_request *cqp_request;
  523. struct cqp_commands_info *cqp_info;
  524. struct i40iw_qp_host_ctx_info *ctx_info;
  525. struct i40iwarp_offload_info *iwarp_info;
  526. unsigned long flags;
  527. if (init_attr->create_flags)
  528. return ERR_PTR(-EINVAL);
  529. if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
  530. init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  531. if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  532. init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  533. memset(&init_info, 0, sizeof(init_info));
  534. sq_size = init_attr->cap.max_send_wr;
  535. rq_size = init_attr->cap.max_recv_wr;
  536. init_info.qp_uk_init_info.sq_size = sq_size;
  537. init_info.qp_uk_init_info.rq_size = rq_size;
  538. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  539. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  540. init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
  541. mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
  542. if (!mem)
  543. return ERR_PTR(-ENOMEM);
  544. iwqp = (struct i40iw_qp *)mem;
  545. qp = &iwqp->sc_qp;
  546. qp->back_qp = (void *)iwqp;
  547. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  548. iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
  549. if (i40iw_allocate_dma_mem(dev->hw,
  550. &iwqp->q2_ctx_mem,
  551. I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
  552. 256)) {
  553. i40iw_pr_err("dma_mem failed\n");
  554. err_code = -ENOMEM;
  555. goto error;
  556. }
  557. init_info.q2 = iwqp->q2_ctx_mem.va;
  558. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  559. init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
  560. init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
  561. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
  562. &qp_num, &iwdev->next_qp);
  563. if (err_code) {
  564. i40iw_pr_err("qp resource\n");
  565. goto error;
  566. }
  567. iwqp->allocated_buffer = mem;
  568. iwqp->iwdev = iwdev;
  569. iwqp->iwpd = iwpd;
  570. iwqp->ibqp.qp_num = qp_num;
  571. qp = &iwqp->sc_qp;
  572. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  573. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  574. iwqp->host_ctx.va = init_info.host_ctx;
  575. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  576. iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
  577. init_info.pd = &iwpd->sc_pd;
  578. init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
  579. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  580. if (init_attr->qp_type != IB_QPT_RC) {
  581. err_code = -EINVAL;
  582. goto error;
  583. }
  584. if (iwdev->push_mode)
  585. i40iw_alloc_push_page(iwdev, qp);
  586. if (udata) {
  587. err_code = ib_copy_from_udata(&req, udata, sizeof(req));
  588. if (err_code) {
  589. i40iw_pr_err("ib_copy_from_data\n");
  590. goto error;
  591. }
  592. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  593. if (ibpd->uobject && ibpd->uobject->context) {
  594. iwqp->user_mode = 1;
  595. ucontext = to_ucontext(ibpd->uobject->context);
  596. if (req.user_wqe_buffers) {
  597. spin_lock_irqsave(
  598. &ucontext->qp_reg_mem_list_lock, flags);
  599. iwqp->iwpbl = i40iw_get_pbl(
  600. (unsigned long)req.user_wqe_buffers,
  601. &ucontext->qp_reg_mem_list);
  602. spin_unlock_irqrestore(
  603. &ucontext->qp_reg_mem_list_lock, flags);
  604. if (!iwqp->iwpbl) {
  605. err_code = -ENODATA;
  606. i40iw_pr_err("no pbl info\n");
  607. goto error;
  608. }
  609. }
  610. }
  611. err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
  612. } else {
  613. err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
  614. }
  615. if (err_code) {
  616. i40iw_pr_err("setup qp failed\n");
  617. goto error;
  618. }
  619. init_info.type = I40IW_QP_TYPE_IWARP;
  620. ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
  621. if (ret) {
  622. err_code = -EPROTO;
  623. i40iw_pr_err("qp_init fail\n");
  624. goto error;
  625. }
  626. ctx_info = &iwqp->ctx_info;
  627. iwarp_info = &iwqp->iwarp_info;
  628. iwarp_info->rd_enable = true;
  629. iwarp_info->wr_rdresp_en = true;
  630. if (!iwqp->user_mode) {
  631. iwarp_info->fast_reg_en = true;
  632. iwarp_info->priv_mode_en = true;
  633. }
  634. iwarp_info->ddp_ver = 1;
  635. iwarp_info->rdmap_ver = 1;
  636. ctx_info->iwarp_info_valid = true;
  637. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  638. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  639. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
  640. ctx_info->push_mode_en = false;
  641. } else {
  642. ctx_info->push_mode_en = true;
  643. ctx_info->push_idx = qp->push_idx;
  644. }
  645. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  646. (u64 *)iwqp->host_ctx.va,
  647. ctx_info);
  648. ctx_info->iwarp_info_valid = false;
  649. cqp_request = i40iw_get_cqp_request(iwcqp, true);
  650. if (!cqp_request) {
  651. err_code = -ENOMEM;
  652. goto error;
  653. }
  654. cqp_info = &cqp_request->info;
  655. qp_info = &cqp_request->info.in.u.qp_create.info;
  656. memset(qp_info, 0, sizeof(*qp_info));
  657. qp_info->cq_num_valid = true;
  658. qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
  659. cqp_info->cqp_cmd = OP_QP_CREATE;
  660. cqp_info->post_sq = 1;
  661. cqp_info->in.u.qp_create.qp = qp;
  662. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  663. ret = i40iw_handle_cqp_op(iwdev, cqp_request);
  664. if (ret) {
  665. i40iw_pr_err("CQP-OP QP create fail");
  666. err_code = -EACCES;
  667. goto error;
  668. }
  669. i40iw_add_ref(&iwqp->ibqp);
  670. spin_lock_init(&iwqp->lock);
  671. iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
  672. iwdev->qp_table[qp_num] = iwqp;
  673. i40iw_add_pdusecount(iwqp->iwpd);
  674. if (ibpd->uobject && udata) {
  675. memset(&uresp, 0, sizeof(uresp));
  676. uresp.actual_sq_size = sq_size;
  677. uresp.actual_rq_size = rq_size;
  678. uresp.qp_id = qp_num;
  679. uresp.push_idx = qp->push_idx;
  680. err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  681. if (err_code) {
  682. i40iw_pr_err("copy_to_udata failed\n");
  683. i40iw_destroy_qp(&iwqp->ibqp);
  684. /* let the completion of the qp destroy free the qp */
  685. return ERR_PTR(err_code);
  686. }
  687. }
  688. init_completion(&iwqp->sq_drained);
  689. init_completion(&iwqp->rq_drained);
  690. return &iwqp->ibqp;
  691. error:
  692. i40iw_free_qp_resources(iwdev, iwqp, qp_num);
  693. return ERR_PTR(err_code);
  694. }
  695. /**
  696. * i40iw_query - query qp attributes
  697. * @ibqp: qp pointer
  698. * @attr: attributes pointer
  699. * @attr_mask: Not used
  700. * @init_attr: qp attributes to return
  701. */
  702. static int i40iw_query_qp(struct ib_qp *ibqp,
  703. struct ib_qp_attr *attr,
  704. int attr_mask,
  705. struct ib_qp_init_attr *init_attr)
  706. {
  707. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  708. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  709. attr->qp_access_flags = 0;
  710. attr->cap.max_send_wr = qp->qp_uk.sq_size;
  711. attr->cap.max_recv_wr = qp->qp_uk.rq_size;
  712. attr->cap.max_recv_sge = 1;
  713. attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  714. init_attr->event_handler = iwqp->ibqp.event_handler;
  715. init_attr->qp_context = iwqp->ibqp.qp_context;
  716. init_attr->send_cq = iwqp->ibqp.send_cq;
  717. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  718. init_attr->srq = iwqp->ibqp.srq;
  719. init_attr->cap = attr->cap;
  720. return 0;
  721. }
  722. /**
  723. * i40iw_hw_modify_qp - setup cqp for modify qp
  724. * @iwdev: iwarp device
  725. * @iwqp: qp ptr (user or kernel)
  726. * @info: info for modify qp
  727. * @wait: flag to wait or not for modify qp completion
  728. */
  729. void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
  730. struct i40iw_modify_qp_info *info, bool wait)
  731. {
  732. enum i40iw_status_code status;
  733. struct i40iw_cqp_request *cqp_request;
  734. struct cqp_commands_info *cqp_info;
  735. struct i40iw_modify_qp_info *m_info;
  736. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
  737. if (!cqp_request)
  738. return;
  739. cqp_info = &cqp_request->info;
  740. m_info = &cqp_info->in.u.qp_modify.info;
  741. memcpy(m_info, info, sizeof(*m_info));
  742. cqp_info->cqp_cmd = OP_QP_MODIFY;
  743. cqp_info->post_sq = 1;
  744. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  745. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  746. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  747. if (status)
  748. i40iw_pr_err("CQP-OP Modify QP fail");
  749. }
  750. /**
  751. * i40iw_modify_qp - modify qp request
  752. * @ibqp: qp's pointer for modify
  753. * @attr: access attributes
  754. * @attr_mask: state mask
  755. * @udata: user data
  756. */
  757. int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  758. int attr_mask, struct ib_udata *udata)
  759. {
  760. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  761. struct i40iw_device *iwdev = iwqp->iwdev;
  762. struct i40iw_qp_host_ctx_info *ctx_info;
  763. struct i40iwarp_offload_info *iwarp_info;
  764. struct i40iw_modify_qp_info info;
  765. u8 issue_modify_qp = 0;
  766. u8 dont_wait = 0;
  767. u32 err;
  768. unsigned long flags;
  769. memset(&info, 0, sizeof(info));
  770. ctx_info = &iwqp->ctx_info;
  771. iwarp_info = &iwqp->iwarp_info;
  772. spin_lock_irqsave(&iwqp->lock, flags);
  773. if (attr_mask & IB_QP_STATE) {
  774. switch (attr->qp_state) {
  775. case IB_QPS_INIT:
  776. case IB_QPS_RTR:
  777. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
  778. err = -EINVAL;
  779. goto exit;
  780. }
  781. if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
  782. info.next_iwarp_state = I40IW_QP_STATE_IDLE;
  783. issue_modify_qp = 1;
  784. }
  785. break;
  786. case IB_QPS_RTS:
  787. if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
  788. (!iwqp->cm_id)) {
  789. err = -EINVAL;
  790. goto exit;
  791. }
  792. issue_modify_qp = 1;
  793. iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
  794. iwqp->hte_added = 1;
  795. info.next_iwarp_state = I40IW_QP_STATE_RTS;
  796. info.tcp_ctx_valid = true;
  797. info.ord_valid = true;
  798. info.arp_cache_idx_valid = true;
  799. info.cq_num_valid = true;
  800. break;
  801. case IB_QPS_SQD:
  802. if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
  803. err = 0;
  804. goto exit;
  805. }
  806. if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
  807. (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
  808. err = 0;
  809. goto exit;
  810. }
  811. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
  812. err = -EINVAL;
  813. goto exit;
  814. }
  815. info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
  816. issue_modify_qp = 1;
  817. break;
  818. case IB_QPS_SQE:
  819. if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
  820. err = -EINVAL;
  821. goto exit;
  822. }
  823. info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
  824. issue_modify_qp = 1;
  825. break;
  826. case IB_QPS_ERR:
  827. case IB_QPS_RESET:
  828. if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
  829. err = -EINVAL;
  830. goto exit;
  831. }
  832. if (iwqp->sc_qp.term_flags)
  833. del_timer(&iwqp->terminate_timer);
  834. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  835. if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
  836. iwdev->iw_status &&
  837. (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
  838. info.reset_tcp_conn = true;
  839. else
  840. dont_wait = 1;
  841. issue_modify_qp = 1;
  842. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  843. break;
  844. default:
  845. err = -EINVAL;
  846. goto exit;
  847. }
  848. iwqp->ibqp_state = attr->qp_state;
  849. if (issue_modify_qp)
  850. iwqp->iwarp_state = info.next_iwarp_state;
  851. else
  852. info.next_iwarp_state = iwqp->iwarp_state;
  853. }
  854. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  855. ctx_info->iwarp_info_valid = true;
  856. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  857. iwarp_info->wr_rdresp_en = true;
  858. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  859. iwarp_info->wr_rdresp_en = true;
  860. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  861. iwarp_info->rd_enable = true;
  862. if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
  863. iwarp_info->bind_en = true;
  864. if (iwqp->user_mode) {
  865. iwarp_info->rd_enable = true;
  866. iwarp_info->wr_rdresp_en = true;
  867. iwarp_info->priv_mode_en = false;
  868. }
  869. }
  870. if (ctx_info->iwarp_info_valid) {
  871. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  872. int ret;
  873. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  874. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  875. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  876. (u64 *)iwqp->host_ctx.va,
  877. ctx_info);
  878. if (ret) {
  879. i40iw_pr_err("setting QP context\n");
  880. err = -EINVAL;
  881. goto exit;
  882. }
  883. }
  884. spin_unlock_irqrestore(&iwqp->lock, flags);
  885. if (issue_modify_qp)
  886. i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
  887. if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
  888. if (dont_wait) {
  889. if (iwqp->cm_id && iwqp->hw_tcp_state) {
  890. spin_lock_irqsave(&iwqp->lock, flags);
  891. iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
  892. iwqp->last_aeq = I40IW_AE_RESET_SENT;
  893. spin_unlock_irqrestore(&iwqp->lock, flags);
  894. }
  895. }
  896. }
  897. return 0;
  898. exit:
  899. spin_unlock_irqrestore(&iwqp->lock, flags);
  900. return err;
  901. }
  902. /**
  903. * cq_free_resources - free up recources for cq
  904. * @iwdev: iwarp device
  905. * @iwcq: cq ptr
  906. */
  907. static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
  908. {
  909. struct i40iw_sc_cq *cq = &iwcq->sc_cq;
  910. if (!iwcq->user_mode)
  911. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
  912. i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
  913. }
  914. /**
  915. * cq_wq_destroy - send cq destroy cqp
  916. * @iwdev: iwarp device
  917. * @cq: hardware control cq
  918. */
  919. static void cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
  920. {
  921. enum i40iw_status_code status;
  922. struct i40iw_cqp_request *cqp_request;
  923. struct cqp_commands_info *cqp_info;
  924. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  925. if (!cqp_request)
  926. return;
  927. cqp_info = &cqp_request->info;
  928. cqp_info->cqp_cmd = OP_CQ_DESTROY;
  929. cqp_info->post_sq = 1;
  930. cqp_info->in.u.cq_destroy.cq = cq;
  931. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  932. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  933. if (status)
  934. i40iw_pr_err("CQP-OP Destroy QP fail");
  935. }
  936. /**
  937. * i40iw_destroy_cq - destroy cq
  938. * @ib_cq: cq pointer
  939. */
  940. static int i40iw_destroy_cq(struct ib_cq *ib_cq)
  941. {
  942. struct i40iw_cq *iwcq;
  943. struct i40iw_device *iwdev;
  944. struct i40iw_sc_cq *cq;
  945. if (!ib_cq) {
  946. i40iw_pr_err("ib_cq == NULL\n");
  947. return 0;
  948. }
  949. iwcq = to_iwcq(ib_cq);
  950. iwdev = to_iwdev(ib_cq->device);
  951. cq = &iwcq->sc_cq;
  952. cq_wq_destroy(iwdev, cq);
  953. cq_free_resources(iwdev, iwcq);
  954. kfree(iwcq);
  955. return 0;
  956. }
  957. /**
  958. * i40iw_create_cq - create cq
  959. * @ibdev: device pointer from stack
  960. * @attr: attributes for cq
  961. * @context: user context created during alloc
  962. * @udata: user data
  963. */
  964. static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
  965. const struct ib_cq_init_attr *attr,
  966. struct ib_ucontext *context,
  967. struct ib_udata *udata)
  968. {
  969. struct i40iw_device *iwdev = to_iwdev(ibdev);
  970. struct i40iw_cq *iwcq;
  971. struct i40iw_pbl *iwpbl;
  972. u32 cq_num = 0;
  973. struct i40iw_sc_cq *cq;
  974. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  975. struct i40iw_cq_init_info info;
  976. enum i40iw_status_code status;
  977. struct i40iw_cqp_request *cqp_request;
  978. struct cqp_commands_info *cqp_info;
  979. struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  980. unsigned long flags;
  981. int err_code;
  982. int entries = attr->cqe;
  983. if (entries > iwdev->max_cqe)
  984. return ERR_PTR(-EINVAL);
  985. iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
  986. if (!iwcq)
  987. return ERR_PTR(-ENOMEM);
  988. memset(&info, 0, sizeof(info));
  989. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
  990. iwdev->max_cq, &cq_num,
  991. &iwdev->next_cq);
  992. if (err_code)
  993. goto error;
  994. cq = &iwcq->sc_cq;
  995. cq->back_cq = (void *)iwcq;
  996. spin_lock_init(&iwcq->lock);
  997. info.dev = dev;
  998. ukinfo->cq_size = max(entries, 4);
  999. ukinfo->cq_id = cq_num;
  1000. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  1001. info.ceqe_mask = 0;
  1002. info.ceq_id = 0;
  1003. info.ceq_id_valid = true;
  1004. info.ceqe_mask = 1;
  1005. info.type = I40IW_CQ_TYPE_IWARP;
  1006. if (context) {
  1007. struct i40iw_ucontext *ucontext;
  1008. struct i40iw_create_cq_req req;
  1009. struct i40iw_cq_mr *cqmr;
  1010. memset(&req, 0, sizeof(req));
  1011. iwcq->user_mode = true;
  1012. ucontext = to_ucontext(context);
  1013. if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req)))
  1014. goto cq_free_resources;
  1015. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1016. iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
  1017. &ucontext->cq_reg_mem_list);
  1018. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1019. if (!iwpbl) {
  1020. err_code = -EPROTO;
  1021. goto cq_free_resources;
  1022. }
  1023. iwcq->iwpbl = iwpbl;
  1024. iwcq->cq_mem_size = 0;
  1025. cqmr = &iwpbl->cq_mr;
  1026. info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
  1027. if (iwpbl->pbl_allocated) {
  1028. info.virtual_map = true;
  1029. info.pbl_chunk_size = 1;
  1030. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1031. } else {
  1032. info.cq_base_pa = cqmr->cq_pbl.addr;
  1033. }
  1034. } else {
  1035. /* Kmode allocations */
  1036. int rsize;
  1037. int shadow;
  1038. rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
  1039. rsize = round_up(rsize, 256);
  1040. shadow = I40IW_SHADOW_AREA_SIZE << 3;
  1041. status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
  1042. rsize + shadow, 256);
  1043. if (status) {
  1044. err_code = -ENOMEM;
  1045. goto cq_free_resources;
  1046. }
  1047. ukinfo->cq_base = iwcq->kmem.va;
  1048. info.cq_base_pa = iwcq->kmem.pa;
  1049. info.shadow_area_pa = info.cq_base_pa + rsize;
  1050. ukinfo->shadow_area = iwcq->kmem.va + rsize;
  1051. }
  1052. if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
  1053. i40iw_pr_err("init cq fail\n");
  1054. err_code = -EPROTO;
  1055. goto cq_free_resources;
  1056. }
  1057. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1058. if (!cqp_request) {
  1059. err_code = -ENOMEM;
  1060. goto cq_free_resources;
  1061. }
  1062. cqp_info = &cqp_request->info;
  1063. cqp_info->cqp_cmd = OP_CQ_CREATE;
  1064. cqp_info->post_sq = 1;
  1065. cqp_info->in.u.cq_create.cq = cq;
  1066. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1067. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1068. if (status) {
  1069. i40iw_pr_err("CQP-OP Create QP fail");
  1070. err_code = -EPROTO;
  1071. goto cq_free_resources;
  1072. }
  1073. if (context) {
  1074. struct i40iw_create_cq_resp resp;
  1075. memset(&resp, 0, sizeof(resp));
  1076. resp.cq_id = info.cq_uk_init_info.cq_id;
  1077. resp.cq_size = info.cq_uk_init_info.cq_size;
  1078. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  1079. i40iw_pr_err("copy to user data\n");
  1080. err_code = -EPROTO;
  1081. goto cq_destroy;
  1082. }
  1083. }
  1084. return (struct ib_cq *)iwcq;
  1085. cq_destroy:
  1086. cq_wq_destroy(iwdev, cq);
  1087. cq_free_resources:
  1088. cq_free_resources(iwdev, iwcq);
  1089. error:
  1090. kfree(iwcq);
  1091. return ERR_PTR(err_code);
  1092. }
  1093. /**
  1094. * i40iw_get_user_access - get hw access from IB access
  1095. * @acc: IB access to return hw access
  1096. */
  1097. static inline u16 i40iw_get_user_access(int acc)
  1098. {
  1099. u16 access = 0;
  1100. access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
  1101. access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
  1102. access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
  1103. access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
  1104. return access;
  1105. }
  1106. /**
  1107. * i40iw_free_stag - free stag resource
  1108. * @iwdev: iwarp device
  1109. * @stag: stag to free
  1110. */
  1111. static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
  1112. {
  1113. u32 stag_idx;
  1114. stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1115. i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
  1116. }
  1117. /**
  1118. * i40iw_create_stag - create random stag
  1119. * @iwdev: iwarp device
  1120. */
  1121. static u32 i40iw_create_stag(struct i40iw_device *iwdev)
  1122. {
  1123. u32 stag = 0;
  1124. u32 stag_index = 0;
  1125. u32 next_stag_index;
  1126. u32 driver_key;
  1127. u32 random;
  1128. u8 consumer_key;
  1129. int ret;
  1130. get_random_bytes(&random, sizeof(random));
  1131. consumer_key = (u8)random;
  1132. driver_key = random & ~iwdev->mr_stagmask;
  1133. next_stag_index = (random & iwdev->mr_stagmask) >> 8;
  1134. next_stag_index %= iwdev->max_mr;
  1135. ret = i40iw_alloc_resource(iwdev,
  1136. iwdev->allocated_mrs, iwdev->max_mr,
  1137. &stag_index, &next_stag_index);
  1138. if (!ret) {
  1139. stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
  1140. stag |= driver_key;
  1141. stag += (u32)consumer_key;
  1142. }
  1143. return stag;
  1144. }
  1145. /**
  1146. * i40iw_next_pbl_addr - Get next pbl address
  1147. * @palloc: Poiner to allocated pbles
  1148. * @pbl: pointer to a pble
  1149. * @pinfo: info pointer
  1150. * @idx: index
  1151. */
  1152. static inline u64 *i40iw_next_pbl_addr(struct i40iw_pble_alloc *palloc,
  1153. u64 *pbl,
  1154. struct i40iw_pble_info **pinfo,
  1155. u32 *idx)
  1156. {
  1157. *idx += 1;
  1158. if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
  1159. return ++pbl;
  1160. *idx = 0;
  1161. (*pinfo)++;
  1162. return (u64 *)(*pinfo)->addr;
  1163. }
  1164. /**
  1165. * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
  1166. * @iwmr: iwmr for IB's user page addresses
  1167. * @pbl: ple pointer to save 1 level or 0 level pble
  1168. * @level: indicated level 0, 1 or 2
  1169. */
  1170. static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
  1171. u64 *pbl,
  1172. enum i40iw_pble_level level)
  1173. {
  1174. struct ib_umem *region = iwmr->region;
  1175. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1176. int chunk_pages, entry, pg_shift, i;
  1177. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1178. struct i40iw_pble_info *pinfo;
  1179. struct scatterlist *sg;
  1180. u32 idx = 0;
  1181. pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
  1182. pg_shift = ffs(region->page_size) - 1;
  1183. for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
  1184. chunk_pages = sg_dma_len(sg) >> pg_shift;
  1185. if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
  1186. !iwpbl->qp_mr.sq_page)
  1187. iwpbl->qp_mr.sq_page = sg_page(sg);
  1188. for (i = 0; i < chunk_pages; i++) {
  1189. *pbl = cpu_to_le64(sg_dma_address(sg) + region->page_size * i);
  1190. pbl = i40iw_next_pbl_addr(palloc, pbl, &pinfo, &idx);
  1191. }
  1192. }
  1193. }
  1194. /**
  1195. * i40iw_setup_pbles - copy user pg address to pble's
  1196. * @iwdev: iwarp device
  1197. * @iwmr: mr pointer for this memory registration
  1198. * @use_pbles: flag if to use pble's or memory (level 0)
  1199. */
  1200. static int i40iw_setup_pbles(struct i40iw_device *iwdev,
  1201. struct i40iw_mr *iwmr,
  1202. bool use_pbles)
  1203. {
  1204. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1205. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1206. struct i40iw_pble_info *pinfo;
  1207. u64 *pbl;
  1208. enum i40iw_status_code status;
  1209. enum i40iw_pble_level level = I40IW_LEVEL_1;
  1210. if (!use_pbles && (iwmr->page_cnt > MAX_SAVE_PAGE_ADDRS))
  1211. return -ENOMEM;
  1212. if (use_pbles) {
  1213. mutex_lock(&iwdev->pbl_mutex);
  1214. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1215. mutex_unlock(&iwdev->pbl_mutex);
  1216. if (status)
  1217. return -ENOMEM;
  1218. iwpbl->pbl_allocated = true;
  1219. level = palloc->level;
  1220. pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
  1221. pbl = (u64 *)pinfo->addr;
  1222. } else {
  1223. pbl = iwmr->pgaddrmem;
  1224. }
  1225. i40iw_copy_user_pgaddrs(iwmr, pbl, level);
  1226. return 0;
  1227. }
  1228. /**
  1229. * i40iw_handle_q_mem - handle memory for qp and cq
  1230. * @iwdev: iwarp device
  1231. * @req: information for q memory management
  1232. * @iwpbl: pble struct
  1233. * @use_pbles: flag to use pble
  1234. */
  1235. static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
  1236. struct i40iw_mem_reg_req *req,
  1237. struct i40iw_pbl *iwpbl,
  1238. bool use_pbles)
  1239. {
  1240. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1241. struct i40iw_mr *iwmr = iwpbl->iwmr;
  1242. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  1243. struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
  1244. struct i40iw_hmc_pble *hmc_p;
  1245. u64 *arr = iwmr->pgaddrmem;
  1246. int err;
  1247. int total;
  1248. total = req->sq_pages + req->rq_pages + req->cq_pages;
  1249. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1250. if (err)
  1251. return err;
  1252. if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
  1253. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1254. iwpbl->pbl_allocated = false;
  1255. return -ENOMEM;
  1256. }
  1257. if (use_pbles)
  1258. arr = (u64 *)palloc->level1.addr;
  1259. if (req->reg_type == IW_MEMREG_TYPE_QP) {
  1260. hmc_p = &qpmr->sq_pbl;
  1261. qpmr->shadow = (dma_addr_t)arr[total];
  1262. if (use_pbles) {
  1263. hmc_p->idx = palloc->level1.idx;
  1264. hmc_p = &qpmr->rq_pbl;
  1265. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  1266. } else {
  1267. hmc_p->addr = arr[0];
  1268. hmc_p = &qpmr->rq_pbl;
  1269. hmc_p->addr = arr[1];
  1270. }
  1271. } else { /* CQ */
  1272. hmc_p = &cqmr->cq_pbl;
  1273. cqmr->shadow = (dma_addr_t)arr[total];
  1274. if (use_pbles)
  1275. hmc_p->idx = palloc->level1.idx;
  1276. else
  1277. hmc_p->addr = arr[0];
  1278. }
  1279. return err;
  1280. }
  1281. /**
  1282. * i40iw_hw_alloc_stag - cqp command to allocate stag
  1283. * @iwdev: iwarp device
  1284. * @iwmr: iwarp mr pointer
  1285. */
  1286. static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
  1287. {
  1288. struct i40iw_allocate_stag_info *info;
  1289. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1290. enum i40iw_status_code status;
  1291. int err = 0;
  1292. struct i40iw_cqp_request *cqp_request;
  1293. struct cqp_commands_info *cqp_info;
  1294. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1295. if (!cqp_request)
  1296. return -ENOMEM;
  1297. cqp_info = &cqp_request->info;
  1298. info = &cqp_info->in.u.alloc_stag.info;
  1299. memset(info, 0, sizeof(*info));
  1300. info->page_size = PAGE_SIZE;
  1301. info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1302. info->pd_id = iwpd->sc_pd.pd_id;
  1303. info->total_len = iwmr->length;
  1304. info->remote_access = true;
  1305. cqp_info->cqp_cmd = OP_ALLOC_STAG;
  1306. cqp_info->post_sq = 1;
  1307. cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
  1308. cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
  1309. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1310. if (status) {
  1311. err = -ENOMEM;
  1312. i40iw_pr_err("CQP-OP MR Reg fail");
  1313. }
  1314. return err;
  1315. }
  1316. /**
  1317. * i40iw_alloc_mr - register stag for fast memory registration
  1318. * @pd: ibpd pointer
  1319. * @mr_type: memory for stag registrion
  1320. * @max_num_sg: man number of pages
  1321. */
  1322. static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
  1323. enum ib_mr_type mr_type,
  1324. u32 max_num_sg)
  1325. {
  1326. struct i40iw_pd *iwpd = to_iwpd(pd);
  1327. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1328. struct i40iw_pble_alloc *palloc;
  1329. struct i40iw_pbl *iwpbl;
  1330. struct i40iw_mr *iwmr;
  1331. enum i40iw_status_code status;
  1332. u32 stag;
  1333. int err_code = -ENOMEM;
  1334. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1335. if (!iwmr)
  1336. return ERR_PTR(-ENOMEM);
  1337. stag = i40iw_create_stag(iwdev);
  1338. if (!stag) {
  1339. err_code = -EOVERFLOW;
  1340. goto err;
  1341. }
  1342. iwmr->stag = stag;
  1343. iwmr->ibmr.rkey = stag;
  1344. iwmr->ibmr.lkey = stag;
  1345. iwmr->ibmr.pd = pd;
  1346. iwmr->ibmr.device = pd->device;
  1347. iwpbl = &iwmr->iwpbl;
  1348. iwpbl->iwmr = iwmr;
  1349. iwmr->type = IW_MEMREG_TYPE_MEM;
  1350. palloc = &iwpbl->pble_alloc;
  1351. iwmr->page_cnt = max_num_sg;
  1352. mutex_lock(&iwdev->pbl_mutex);
  1353. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1354. mutex_unlock(&iwdev->pbl_mutex);
  1355. if (status)
  1356. goto err1;
  1357. if (palloc->level != I40IW_LEVEL_1)
  1358. goto err2;
  1359. err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
  1360. if (err_code)
  1361. goto err2;
  1362. iwpbl->pbl_allocated = true;
  1363. i40iw_add_pdusecount(iwpd);
  1364. return &iwmr->ibmr;
  1365. err2:
  1366. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1367. err1:
  1368. i40iw_free_stag(iwdev, stag);
  1369. err:
  1370. kfree(iwmr);
  1371. return ERR_PTR(err_code);
  1372. }
  1373. /**
  1374. * i40iw_set_page - populate pbl list for fmr
  1375. * @ibmr: ib mem to access iwarp mr pointer
  1376. * @addr: page dma address fro pbl list
  1377. */
  1378. static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
  1379. {
  1380. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1381. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1382. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1383. u64 *pbl;
  1384. if (unlikely(iwmr->npages == iwmr->page_cnt))
  1385. return -ENOMEM;
  1386. pbl = (u64 *)palloc->level1.addr;
  1387. pbl[iwmr->npages++] = cpu_to_le64(addr);
  1388. return 0;
  1389. }
  1390. /**
  1391. * i40iw_map_mr_sg - map of sg list for fmr
  1392. * @ibmr: ib mem to access iwarp mr pointer
  1393. * @sg: scatter gather list for fmr
  1394. * @sg_nents: number of sg pages
  1395. */
  1396. static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
  1397. int sg_nents, unsigned int *sg_offset)
  1398. {
  1399. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1400. iwmr->npages = 0;
  1401. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
  1402. }
  1403. /**
  1404. * i40iw_drain_sq - drain the send queue
  1405. * @ibqp: ib qp pointer
  1406. */
  1407. static void i40iw_drain_sq(struct ib_qp *ibqp)
  1408. {
  1409. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1410. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1411. if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  1412. wait_for_completion(&iwqp->sq_drained);
  1413. }
  1414. /**
  1415. * i40iw_drain_rq - drain the receive queue
  1416. * @ibqp: ib qp pointer
  1417. */
  1418. static void i40iw_drain_rq(struct ib_qp *ibqp)
  1419. {
  1420. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1421. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1422. if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  1423. wait_for_completion(&iwqp->rq_drained);
  1424. }
  1425. /**
  1426. * i40iw_hwreg_mr - send cqp command for memory registration
  1427. * @iwdev: iwarp device
  1428. * @iwmr: iwarp mr pointer
  1429. * @access: access for MR
  1430. */
  1431. static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
  1432. struct i40iw_mr *iwmr,
  1433. u16 access)
  1434. {
  1435. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1436. struct i40iw_reg_ns_stag_info *stag_info;
  1437. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1438. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1439. enum i40iw_status_code status;
  1440. int err = 0;
  1441. struct i40iw_cqp_request *cqp_request;
  1442. struct cqp_commands_info *cqp_info;
  1443. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1444. if (!cqp_request)
  1445. return -ENOMEM;
  1446. cqp_info = &cqp_request->info;
  1447. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  1448. memset(stag_info, 0, sizeof(*stag_info));
  1449. stag_info->va = (void *)(unsigned long)iwpbl->user_base;
  1450. stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1451. stag_info->stag_key = (u8)iwmr->stag;
  1452. stag_info->total_len = iwmr->length;
  1453. stag_info->access_rights = access;
  1454. stag_info->pd_id = iwpd->sc_pd.pd_id;
  1455. stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
  1456. if (iwmr->page_cnt > 1) {
  1457. if (palloc->level == I40IW_LEVEL_1) {
  1458. stag_info->first_pm_pbl_index = palloc->level1.idx;
  1459. stag_info->chunk_size = 1;
  1460. } else {
  1461. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  1462. stag_info->chunk_size = 3;
  1463. }
  1464. } else {
  1465. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  1466. }
  1467. cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
  1468. cqp_info->post_sq = 1;
  1469. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
  1470. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  1471. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1472. if (status) {
  1473. err = -ENOMEM;
  1474. i40iw_pr_err("CQP-OP MR Reg fail");
  1475. }
  1476. return err;
  1477. }
  1478. /**
  1479. * i40iw_reg_user_mr - Register a user memory region
  1480. * @pd: ptr of pd
  1481. * @start: virtual start address
  1482. * @length: length of mr
  1483. * @virt: virtual address
  1484. * @acc: access of mr
  1485. * @udata: user data
  1486. */
  1487. static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
  1488. u64 start,
  1489. u64 length,
  1490. u64 virt,
  1491. int acc,
  1492. struct ib_udata *udata)
  1493. {
  1494. struct i40iw_pd *iwpd = to_iwpd(pd);
  1495. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1496. struct i40iw_ucontext *ucontext;
  1497. struct i40iw_pble_alloc *palloc;
  1498. struct i40iw_pbl *iwpbl;
  1499. struct i40iw_mr *iwmr;
  1500. struct ib_umem *region;
  1501. struct i40iw_mem_reg_req req;
  1502. u64 pbl_depth = 0;
  1503. u32 stag = 0;
  1504. u16 access;
  1505. u64 region_length;
  1506. bool use_pbles = false;
  1507. unsigned long flags;
  1508. int err = -ENOSYS;
  1509. if (length > I40IW_MAX_MR_SIZE)
  1510. return ERR_PTR(-EINVAL);
  1511. region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
  1512. if (IS_ERR(region))
  1513. return (struct ib_mr *)region;
  1514. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  1515. ib_umem_release(region);
  1516. return ERR_PTR(-EFAULT);
  1517. }
  1518. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1519. if (!iwmr) {
  1520. ib_umem_release(region);
  1521. return ERR_PTR(-ENOMEM);
  1522. }
  1523. iwpbl = &iwmr->iwpbl;
  1524. iwpbl->iwmr = iwmr;
  1525. iwmr->region = region;
  1526. iwmr->ibmr.pd = pd;
  1527. iwmr->ibmr.device = pd->device;
  1528. ucontext = to_ucontext(pd->uobject->context);
  1529. region_length = region->length + (start & 0xfff);
  1530. pbl_depth = region_length >> 12;
  1531. pbl_depth += (region_length & (4096 - 1)) ? 1 : 0;
  1532. iwmr->length = region->length;
  1533. iwpbl->user_base = virt;
  1534. palloc = &iwpbl->pble_alloc;
  1535. iwmr->type = req.reg_type;
  1536. iwmr->page_cnt = (u32)pbl_depth;
  1537. switch (req.reg_type) {
  1538. case IW_MEMREG_TYPE_QP:
  1539. use_pbles = ((req.sq_pages + req.rq_pages) > 2);
  1540. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1541. if (err)
  1542. goto error;
  1543. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1544. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  1545. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1546. break;
  1547. case IW_MEMREG_TYPE_CQ:
  1548. use_pbles = (req.cq_pages > 1);
  1549. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1550. if (err)
  1551. goto error;
  1552. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1553. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  1554. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1555. break;
  1556. case IW_MEMREG_TYPE_MEM:
  1557. access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1558. use_pbles = (iwmr->page_cnt != 1);
  1559. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1560. if (err)
  1561. goto error;
  1562. access |= i40iw_get_user_access(acc);
  1563. stag = i40iw_create_stag(iwdev);
  1564. if (!stag) {
  1565. err = -ENOMEM;
  1566. goto error;
  1567. }
  1568. iwmr->stag = stag;
  1569. iwmr->ibmr.rkey = stag;
  1570. iwmr->ibmr.lkey = stag;
  1571. err = i40iw_hwreg_mr(iwdev, iwmr, access);
  1572. if (err) {
  1573. i40iw_free_stag(iwdev, stag);
  1574. goto error;
  1575. }
  1576. break;
  1577. default:
  1578. goto error;
  1579. }
  1580. iwmr->type = req.reg_type;
  1581. if (req.reg_type == IW_MEMREG_TYPE_MEM)
  1582. i40iw_add_pdusecount(iwpd);
  1583. return &iwmr->ibmr;
  1584. error:
  1585. if (palloc->level != I40IW_LEVEL_0)
  1586. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1587. ib_umem_release(region);
  1588. kfree(iwmr);
  1589. return ERR_PTR(err);
  1590. }
  1591. /**
  1592. * i40iw_reg_phys_mr - register kernel physical memory
  1593. * @pd: ibpd pointer
  1594. * @addr: physical address of memory to register
  1595. * @size: size of memory to register
  1596. * @acc: Access rights
  1597. * @iova_start: start of virtual address for physical buffers
  1598. */
  1599. struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
  1600. u64 addr,
  1601. u64 size,
  1602. int acc,
  1603. u64 *iova_start)
  1604. {
  1605. struct i40iw_pd *iwpd = to_iwpd(pd);
  1606. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1607. struct i40iw_pbl *iwpbl;
  1608. struct i40iw_mr *iwmr;
  1609. enum i40iw_status_code status;
  1610. u32 stag;
  1611. u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1612. int ret;
  1613. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1614. if (!iwmr)
  1615. return ERR_PTR(-ENOMEM);
  1616. iwmr->ibmr.pd = pd;
  1617. iwmr->ibmr.device = pd->device;
  1618. iwpbl = &iwmr->iwpbl;
  1619. iwpbl->iwmr = iwmr;
  1620. iwmr->type = IW_MEMREG_TYPE_MEM;
  1621. iwpbl->user_base = *iova_start;
  1622. stag = i40iw_create_stag(iwdev);
  1623. if (!stag) {
  1624. ret = -EOVERFLOW;
  1625. goto err;
  1626. }
  1627. access |= i40iw_get_user_access(acc);
  1628. iwmr->stag = stag;
  1629. iwmr->ibmr.rkey = stag;
  1630. iwmr->ibmr.lkey = stag;
  1631. iwmr->page_cnt = 1;
  1632. iwmr->pgaddrmem[0] = addr;
  1633. iwmr->length = size;
  1634. status = i40iw_hwreg_mr(iwdev, iwmr, access);
  1635. if (status) {
  1636. i40iw_free_stag(iwdev, stag);
  1637. ret = -ENOMEM;
  1638. goto err;
  1639. }
  1640. i40iw_add_pdusecount(iwpd);
  1641. return &iwmr->ibmr;
  1642. err:
  1643. kfree(iwmr);
  1644. return ERR_PTR(ret);
  1645. }
  1646. /**
  1647. * i40iw_get_dma_mr - register physical mem
  1648. * @pd: ptr of pd
  1649. * @acc: access for memory
  1650. */
  1651. static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
  1652. {
  1653. u64 kva = 0;
  1654. return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
  1655. }
  1656. /**
  1657. * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
  1658. * @iwmr: iwmr for IB's user page addresses
  1659. * @ucontext: ptr to user context
  1660. */
  1661. static void i40iw_del_memlist(struct i40iw_mr *iwmr,
  1662. struct i40iw_ucontext *ucontext)
  1663. {
  1664. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1665. unsigned long flags;
  1666. switch (iwmr->type) {
  1667. case IW_MEMREG_TYPE_CQ:
  1668. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1669. if (!list_empty(&ucontext->cq_reg_mem_list))
  1670. list_del(&iwpbl->list);
  1671. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1672. break;
  1673. case IW_MEMREG_TYPE_QP:
  1674. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1675. if (!list_empty(&ucontext->qp_reg_mem_list))
  1676. list_del(&iwpbl->list);
  1677. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1678. break;
  1679. default:
  1680. break;
  1681. }
  1682. }
  1683. /**
  1684. * i40iw_dereg_mr - deregister mr
  1685. * @ib_mr: mr ptr for dereg
  1686. */
  1687. static int i40iw_dereg_mr(struct ib_mr *ib_mr)
  1688. {
  1689. struct ib_pd *ibpd = ib_mr->pd;
  1690. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  1691. struct i40iw_mr *iwmr = to_iwmr(ib_mr);
  1692. struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
  1693. enum i40iw_status_code status;
  1694. struct i40iw_dealloc_stag_info *info;
  1695. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1696. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1697. struct i40iw_cqp_request *cqp_request;
  1698. struct cqp_commands_info *cqp_info;
  1699. u32 stag_idx;
  1700. if (iwmr->region)
  1701. ib_umem_release(iwmr->region);
  1702. if (iwmr->type != IW_MEMREG_TYPE_MEM) {
  1703. if (ibpd->uobject) {
  1704. struct i40iw_ucontext *ucontext;
  1705. ucontext = to_ucontext(ibpd->uobject->context);
  1706. i40iw_del_memlist(iwmr, ucontext);
  1707. }
  1708. if (iwpbl->pbl_allocated)
  1709. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1710. kfree(iwmr);
  1711. return 0;
  1712. }
  1713. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1714. if (!cqp_request)
  1715. return -ENOMEM;
  1716. cqp_info = &cqp_request->info;
  1717. info = &cqp_info->in.u.dealloc_stag.info;
  1718. memset(info, 0, sizeof(*info));
  1719. info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
  1720. info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
  1721. stag_idx = info->stag_idx;
  1722. info->mr = true;
  1723. if (iwpbl->pbl_allocated)
  1724. info->dealloc_pbl = true;
  1725. cqp_info->cqp_cmd = OP_DEALLOC_STAG;
  1726. cqp_info->post_sq = 1;
  1727. cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
  1728. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  1729. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1730. if (status)
  1731. i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
  1732. i40iw_rem_pdusecount(iwpd, iwdev);
  1733. i40iw_free_stag(iwdev, iwmr->stag);
  1734. if (iwpbl->pbl_allocated)
  1735. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1736. kfree(iwmr);
  1737. return 0;
  1738. }
  1739. /**
  1740. * i40iw_show_rev
  1741. */
  1742. static ssize_t i40iw_show_rev(struct device *dev,
  1743. struct device_attribute *attr, char *buf)
  1744. {
  1745. struct i40iw_ib_device *iwibdev = container_of(dev,
  1746. struct i40iw_ib_device,
  1747. ibdev.dev);
  1748. u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
  1749. return sprintf(buf, "%x\n", hw_rev);
  1750. }
  1751. /**
  1752. * i40iw_show_hca
  1753. */
  1754. static ssize_t i40iw_show_hca(struct device *dev,
  1755. struct device_attribute *attr, char *buf)
  1756. {
  1757. return sprintf(buf, "I40IW\n");
  1758. }
  1759. /**
  1760. * i40iw_show_board
  1761. */
  1762. static ssize_t i40iw_show_board(struct device *dev,
  1763. struct device_attribute *attr,
  1764. char *buf)
  1765. {
  1766. return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
  1767. }
  1768. static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
  1769. static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
  1770. static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
  1771. static struct device_attribute *i40iw_dev_attributes[] = {
  1772. &dev_attr_hw_rev,
  1773. &dev_attr_hca_type,
  1774. &dev_attr_board_id
  1775. };
  1776. /**
  1777. * i40iw_copy_sg_list - copy sg list for qp
  1778. * @sg_list: copied into sg_list
  1779. * @sgl: copy from sgl
  1780. * @num_sges: count of sg entries
  1781. */
  1782. static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
  1783. {
  1784. unsigned int i;
  1785. for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
  1786. sg_list[i].tag_off = sgl[i].addr;
  1787. sg_list[i].len = sgl[i].length;
  1788. sg_list[i].stag = sgl[i].lkey;
  1789. }
  1790. }
  1791. /**
  1792. * i40iw_post_send - kernel application wr
  1793. * @ibqp: qp ptr for wr
  1794. * @ib_wr: work request ptr
  1795. * @bad_wr: return of bad wr if err
  1796. */
  1797. static int i40iw_post_send(struct ib_qp *ibqp,
  1798. struct ib_send_wr *ib_wr,
  1799. struct ib_send_wr **bad_wr)
  1800. {
  1801. struct i40iw_qp *iwqp;
  1802. struct i40iw_qp_uk *ukqp;
  1803. struct i40iw_post_sq_info info;
  1804. enum i40iw_status_code ret;
  1805. int err = 0;
  1806. unsigned long flags;
  1807. bool inv_stag;
  1808. iwqp = (struct i40iw_qp *)ibqp;
  1809. ukqp = &iwqp->sc_qp.qp_uk;
  1810. spin_lock_irqsave(&iwqp->lock, flags);
  1811. while (ib_wr) {
  1812. inv_stag = false;
  1813. memset(&info, 0, sizeof(info));
  1814. info.wr_id = (u64)(ib_wr->wr_id);
  1815. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  1816. info.signaled = true;
  1817. if (ib_wr->send_flags & IB_SEND_FENCE)
  1818. info.read_fence = true;
  1819. switch (ib_wr->opcode) {
  1820. case IB_WR_SEND:
  1821. /* fall-through */
  1822. case IB_WR_SEND_WITH_INV:
  1823. if (ib_wr->opcode == IB_WR_SEND) {
  1824. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1825. info.op_type = I40IW_OP_TYPE_SEND_SOL;
  1826. else
  1827. info.op_type = I40IW_OP_TYPE_SEND;
  1828. } else {
  1829. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1830. info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
  1831. else
  1832. info.op_type = I40IW_OP_TYPE_SEND_INV;
  1833. }
  1834. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1835. info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1836. info.op.inline_send.len = ib_wr->sg_list[0].length;
  1837. ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1838. } else {
  1839. info.op.send.num_sges = ib_wr->num_sge;
  1840. info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
  1841. ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1842. }
  1843. if (ret) {
  1844. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1845. err = -ENOMEM;
  1846. else
  1847. err = -EINVAL;
  1848. }
  1849. break;
  1850. case IB_WR_RDMA_WRITE:
  1851. info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
  1852. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1853. info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1854. info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
  1855. info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1856. info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1857. info.op.inline_rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1858. ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
  1859. } else {
  1860. info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
  1861. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  1862. info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1863. info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1864. info.op.rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1865. ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
  1866. }
  1867. if (ret) {
  1868. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1869. err = -ENOMEM;
  1870. else
  1871. err = -EINVAL;
  1872. }
  1873. break;
  1874. case IB_WR_RDMA_READ_WITH_INV:
  1875. inv_stag = true;
  1876. /* fall-through*/
  1877. case IB_WR_RDMA_READ:
  1878. if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
  1879. err = -EINVAL;
  1880. break;
  1881. }
  1882. info.op_type = I40IW_OP_TYPE_RDMA_READ;
  1883. info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1884. info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1885. info.op.rdma_read.rem_addr.len = ib_wr->sg_list->length;
  1886. info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
  1887. info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
  1888. info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
  1889. ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
  1890. if (ret) {
  1891. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1892. err = -ENOMEM;
  1893. else
  1894. err = -EINVAL;
  1895. }
  1896. break;
  1897. case IB_WR_LOCAL_INV:
  1898. info.op_type = I40IW_OP_TYPE_INV_STAG;
  1899. info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
  1900. ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
  1901. if (ret)
  1902. err = -ENOMEM;
  1903. break;
  1904. case IB_WR_REG_MR:
  1905. {
  1906. struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
  1907. int page_shift = ilog2(reg_wr(ib_wr)->mr->page_size);
  1908. int flags = reg_wr(ib_wr)->access;
  1909. struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
  1910. struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
  1911. struct i40iw_fast_reg_stag_info info;
  1912. memset(&info, 0, sizeof(info));
  1913. info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
  1914. info.access_rights |= i40iw_get_user_access(flags);
  1915. info.stag_key = reg_wr(ib_wr)->key & 0xff;
  1916. info.stag_idx = reg_wr(ib_wr)->key >> 8;
  1917. info.wr_id = ib_wr->wr_id;
  1918. info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
  1919. info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
  1920. info.total_len = iwmr->ibmr.length;
  1921. info.reg_addr_pa = *(u64 *)palloc->level1.addr;
  1922. info.first_pm_pbl_index = palloc->level1.idx;
  1923. info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
  1924. info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
  1925. if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
  1926. info.chunk_size = 1;
  1927. if (page_shift == 21)
  1928. info.page_size = 1; /* 2M page */
  1929. ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
  1930. if (ret)
  1931. err = -ENOMEM;
  1932. break;
  1933. }
  1934. default:
  1935. err = -EINVAL;
  1936. i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
  1937. ib_wr->opcode);
  1938. break;
  1939. }
  1940. if (err)
  1941. break;
  1942. ib_wr = ib_wr->next;
  1943. }
  1944. if (err)
  1945. *bad_wr = ib_wr;
  1946. else
  1947. ukqp->ops.iw_qp_post_wr(ukqp);
  1948. spin_unlock_irqrestore(&iwqp->lock, flags);
  1949. return err;
  1950. }
  1951. /**
  1952. * i40iw_post_recv - post receive wr for kernel application
  1953. * @ibqp: ib qp pointer
  1954. * @ib_wr: work request for receive
  1955. * @bad_wr: bad wr caused an error
  1956. */
  1957. static int i40iw_post_recv(struct ib_qp *ibqp,
  1958. struct ib_recv_wr *ib_wr,
  1959. struct ib_recv_wr **bad_wr)
  1960. {
  1961. struct i40iw_qp *iwqp;
  1962. struct i40iw_qp_uk *ukqp;
  1963. struct i40iw_post_rq_info post_recv;
  1964. struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
  1965. enum i40iw_status_code ret = 0;
  1966. unsigned long flags;
  1967. int err = 0;
  1968. iwqp = (struct i40iw_qp *)ibqp;
  1969. ukqp = &iwqp->sc_qp.qp_uk;
  1970. memset(&post_recv, 0, sizeof(post_recv));
  1971. spin_lock_irqsave(&iwqp->lock, flags);
  1972. while (ib_wr) {
  1973. post_recv.num_sges = ib_wr->num_sge;
  1974. post_recv.wr_id = ib_wr->wr_id;
  1975. i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
  1976. post_recv.sg_list = sg_list;
  1977. ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
  1978. if (ret) {
  1979. i40iw_pr_err(" post_recv err %d\n", ret);
  1980. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1981. err = -ENOMEM;
  1982. else
  1983. err = -EINVAL;
  1984. *bad_wr = ib_wr;
  1985. goto out;
  1986. }
  1987. ib_wr = ib_wr->next;
  1988. }
  1989. out:
  1990. spin_unlock_irqrestore(&iwqp->lock, flags);
  1991. return err;
  1992. }
  1993. /**
  1994. * i40iw_poll_cq - poll cq for completion (kernel apps)
  1995. * @ibcq: cq to poll
  1996. * @num_entries: number of entries to poll
  1997. * @entry: wr of entry completed
  1998. */
  1999. static int i40iw_poll_cq(struct ib_cq *ibcq,
  2000. int num_entries,
  2001. struct ib_wc *entry)
  2002. {
  2003. struct i40iw_cq *iwcq;
  2004. int cqe_count = 0;
  2005. struct i40iw_cq_poll_info cq_poll_info;
  2006. enum i40iw_status_code ret;
  2007. struct i40iw_cq_uk *ukcq;
  2008. struct i40iw_sc_qp *qp;
  2009. struct i40iw_qp *iwqp;
  2010. unsigned long flags;
  2011. iwcq = (struct i40iw_cq *)ibcq;
  2012. ukcq = &iwcq->sc_cq.cq_uk;
  2013. spin_lock_irqsave(&iwcq->lock, flags);
  2014. while (cqe_count < num_entries) {
  2015. ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
  2016. if (ret == I40IW_ERR_QUEUE_EMPTY) {
  2017. break;
  2018. } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
  2019. continue;
  2020. } else if (ret) {
  2021. if (!cqe_count)
  2022. cqe_count = -1;
  2023. break;
  2024. }
  2025. entry->wc_flags = 0;
  2026. entry->wr_id = cq_poll_info.wr_id;
  2027. if (cq_poll_info.error) {
  2028. entry->status = IB_WC_WR_FLUSH_ERR;
  2029. entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
  2030. } else {
  2031. entry->status = IB_WC_SUCCESS;
  2032. }
  2033. switch (cq_poll_info.op_type) {
  2034. case I40IW_OP_TYPE_RDMA_WRITE:
  2035. entry->opcode = IB_WC_RDMA_WRITE;
  2036. break;
  2037. case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
  2038. case I40IW_OP_TYPE_RDMA_READ:
  2039. entry->opcode = IB_WC_RDMA_READ;
  2040. break;
  2041. case I40IW_OP_TYPE_SEND_SOL:
  2042. case I40IW_OP_TYPE_SEND_SOL_INV:
  2043. case I40IW_OP_TYPE_SEND_INV:
  2044. case I40IW_OP_TYPE_SEND:
  2045. entry->opcode = IB_WC_SEND;
  2046. break;
  2047. case I40IW_OP_TYPE_REC:
  2048. entry->opcode = IB_WC_RECV;
  2049. break;
  2050. default:
  2051. entry->opcode = IB_WC_RECV;
  2052. break;
  2053. }
  2054. entry->ex.imm_data = 0;
  2055. qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
  2056. entry->qp = (struct ib_qp *)qp->back_qp;
  2057. entry->src_qp = cq_poll_info.qp_id;
  2058. iwqp = (struct i40iw_qp *)qp->back_qp;
  2059. if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
  2060. if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  2061. complete(&iwqp->sq_drained);
  2062. if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  2063. complete(&iwqp->rq_drained);
  2064. }
  2065. entry->byte_len = cq_poll_info.bytes_xfered;
  2066. entry++;
  2067. cqe_count++;
  2068. }
  2069. spin_unlock_irqrestore(&iwcq->lock, flags);
  2070. return cqe_count;
  2071. }
  2072. /**
  2073. * i40iw_req_notify_cq - arm cq kernel application
  2074. * @ibcq: cq to arm
  2075. * @notify_flags: notofication flags
  2076. */
  2077. static int i40iw_req_notify_cq(struct ib_cq *ibcq,
  2078. enum ib_cq_notify_flags notify_flags)
  2079. {
  2080. struct i40iw_cq *iwcq;
  2081. struct i40iw_cq_uk *ukcq;
  2082. unsigned long flags;
  2083. enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
  2084. iwcq = (struct i40iw_cq *)ibcq;
  2085. ukcq = &iwcq->sc_cq.cq_uk;
  2086. if (notify_flags == IB_CQ_SOLICITED)
  2087. cq_notify = IW_CQ_COMPL_SOLICITED;
  2088. spin_lock_irqsave(&iwcq->lock, flags);
  2089. ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
  2090. spin_unlock_irqrestore(&iwcq->lock, flags);
  2091. return 0;
  2092. }
  2093. /**
  2094. * i40iw_port_immutable - return port's immutable data
  2095. * @ibdev: ib dev struct
  2096. * @port_num: port number
  2097. * @immutable: immutable data for the port return
  2098. */
  2099. static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
  2100. struct ib_port_immutable *immutable)
  2101. {
  2102. struct ib_port_attr attr;
  2103. int err;
  2104. err = i40iw_query_port(ibdev, port_num, &attr);
  2105. if (err)
  2106. return err;
  2107. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2108. immutable->gid_tbl_len = attr.gid_tbl_len;
  2109. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  2110. return 0;
  2111. }
  2112. static const char * const i40iw_hw_stat_names[] = {
  2113. // 32bit names
  2114. [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
  2115. [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
  2116. [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
  2117. [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
  2118. [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
  2119. [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
  2120. [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
  2121. [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
  2122. [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
  2123. // 64bit names
  2124. [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2125. "ip4InOctets",
  2126. [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2127. "ip4InPkts",
  2128. [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2129. "ip4InReasmRqd",
  2130. [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2131. "ip4InMcastPkts",
  2132. [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2133. "ip4OutOctets",
  2134. [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2135. "ip4OutPkts",
  2136. [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2137. "ip4OutSegRqd",
  2138. [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2139. "ip4OutMcastPkts",
  2140. [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2141. "ip6InOctets",
  2142. [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2143. "ip6InPkts",
  2144. [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2145. "ip6InReasmRqd",
  2146. [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2147. "ip6InMcastPkts",
  2148. [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2149. "ip6OutOctets",
  2150. [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2151. "ip6OutPkts",
  2152. [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2153. "ip6OutSegRqd",
  2154. [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2155. "ip6OutMcastPkts",
  2156. [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2157. "tcpInSegs",
  2158. [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
  2159. "tcpOutSegs",
  2160. [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2161. "iwInRdmaReads",
  2162. [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2163. "iwInRdmaSends",
  2164. [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2165. "iwInRdmaWrites",
  2166. [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2167. "iwOutRdmaReads",
  2168. [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2169. "iwOutRdmaSends",
  2170. [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2171. "iwOutRdmaWrites",
  2172. [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
  2173. "iwRdmaBnd",
  2174. [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
  2175. "iwRdmaInv"
  2176. };
  2177. static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str,
  2178. size_t str_len)
  2179. {
  2180. u32 firmware_version = I40IW_FW_VERSION;
  2181. snprintf(str, str_len, "%u.%u", firmware_version,
  2182. (firmware_version & 0x000000ff));
  2183. }
  2184. /**
  2185. * i40iw_alloc_hw_stats - Allocate a hw stats structure
  2186. * @ibdev: device pointer from stack
  2187. * @port_num: port number
  2188. */
  2189. static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
  2190. u8 port_num)
  2191. {
  2192. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2193. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2194. int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
  2195. I40IW_HW_STAT_INDEX_MAX_64;
  2196. unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
  2197. BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
  2198. (I40IW_HW_STAT_INDEX_MAX_32 +
  2199. I40IW_HW_STAT_INDEX_MAX_64));
  2200. /*
  2201. * PFs get the default update lifespan, but VFs only update once
  2202. * per second
  2203. */
  2204. if (!dev->is_pf)
  2205. lifespan = 1000;
  2206. return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
  2207. lifespan);
  2208. }
  2209. /**
  2210. * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
  2211. * @ibdev: device pointer from stack
  2212. * @stats: stats pointer from stack
  2213. * @port_num: port number
  2214. * @index: which hw counter the stack is requesting we update
  2215. */
  2216. static int i40iw_get_hw_stats(struct ib_device *ibdev,
  2217. struct rdma_hw_stats *stats,
  2218. u8 port_num, int index)
  2219. {
  2220. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2221. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2222. struct i40iw_dev_pestat *devstat = &dev->dev_pestat;
  2223. struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
  2224. unsigned long flags;
  2225. if (dev->is_pf) {
  2226. spin_lock_irqsave(&devstat->stats_lock, flags);
  2227. devstat->ops.iw_hw_stat_read_all(devstat,
  2228. &devstat->hw_stats);
  2229. spin_unlock_irqrestore(&devstat->stats_lock, flags);
  2230. } else {
  2231. if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
  2232. return -ENOSYS;
  2233. }
  2234. memcpy(&stats->value[0], &hw_stats, sizeof(*hw_stats));
  2235. return stats->num_counters;
  2236. }
  2237. /**
  2238. * i40iw_query_gid - Query port GID
  2239. * @ibdev: device pointer from stack
  2240. * @port: port number
  2241. * @index: Entry index
  2242. * @gid: Global ID
  2243. */
  2244. static int i40iw_query_gid(struct ib_device *ibdev,
  2245. u8 port,
  2246. int index,
  2247. union ib_gid *gid)
  2248. {
  2249. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2250. memset(gid->raw, 0, sizeof(gid->raw));
  2251. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  2252. return 0;
  2253. }
  2254. /**
  2255. * i40iw_modify_port Modify port properties
  2256. * @ibdev: device pointer from stack
  2257. * @port: port number
  2258. * @port_modify_mask: mask for port modifications
  2259. * @props: port properties
  2260. */
  2261. static int i40iw_modify_port(struct ib_device *ibdev,
  2262. u8 port,
  2263. int port_modify_mask,
  2264. struct ib_port_modify *props)
  2265. {
  2266. return -ENOSYS;
  2267. }
  2268. /**
  2269. * i40iw_query_pkey - Query partition key
  2270. * @ibdev: device pointer from stack
  2271. * @port: port number
  2272. * @index: index of pkey
  2273. * @pkey: pointer to store the pkey
  2274. */
  2275. static int i40iw_query_pkey(struct ib_device *ibdev,
  2276. u8 port,
  2277. u16 index,
  2278. u16 *pkey)
  2279. {
  2280. *pkey = 0;
  2281. return 0;
  2282. }
  2283. /**
  2284. * i40iw_create_ah - create address handle
  2285. * @ibpd: ptr of pd
  2286. * @ah_attr: address handle attributes
  2287. */
  2288. static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
  2289. struct ib_ah_attr *attr)
  2290. {
  2291. return ERR_PTR(-ENOSYS);
  2292. }
  2293. /**
  2294. * i40iw_destroy_ah - Destroy address handle
  2295. * @ah: pointer to address handle
  2296. */
  2297. static int i40iw_destroy_ah(struct ib_ah *ah)
  2298. {
  2299. return -ENOSYS;
  2300. }
  2301. /**
  2302. * i40iw_init_rdma_device - initialization of iwarp device
  2303. * @iwdev: iwarp device
  2304. */
  2305. static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
  2306. {
  2307. struct i40iw_ib_device *iwibdev;
  2308. struct net_device *netdev = iwdev->netdev;
  2309. struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
  2310. iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
  2311. if (!iwibdev) {
  2312. i40iw_pr_err("iwdev == NULL\n");
  2313. return NULL;
  2314. }
  2315. strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
  2316. iwibdev->ibdev.owner = THIS_MODULE;
  2317. iwdev->iwibdev = iwibdev;
  2318. iwibdev->iwdev = iwdev;
  2319. iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
  2320. ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
  2321. iwibdev->ibdev.uverbs_cmd_mask =
  2322. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2323. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2324. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2325. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2326. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2327. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2328. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2329. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2330. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2331. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2332. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  2333. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2334. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2335. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2336. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  2337. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  2338. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  2339. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2340. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  2341. (1ull << IB_USER_VERBS_CMD_POST_SEND);
  2342. iwibdev->ibdev.phys_port_cnt = 1;
  2343. iwibdev->ibdev.num_comp_vectors = 1;
  2344. iwibdev->ibdev.dma_device = &pcidev->dev;
  2345. iwibdev->ibdev.dev.parent = &pcidev->dev;
  2346. iwibdev->ibdev.query_port = i40iw_query_port;
  2347. iwibdev->ibdev.modify_port = i40iw_modify_port;
  2348. iwibdev->ibdev.query_pkey = i40iw_query_pkey;
  2349. iwibdev->ibdev.query_gid = i40iw_query_gid;
  2350. iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
  2351. iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
  2352. iwibdev->ibdev.mmap = i40iw_mmap;
  2353. iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
  2354. iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
  2355. iwibdev->ibdev.create_qp = i40iw_create_qp;
  2356. iwibdev->ibdev.modify_qp = i40iw_modify_qp;
  2357. iwibdev->ibdev.query_qp = i40iw_query_qp;
  2358. iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
  2359. iwibdev->ibdev.create_cq = i40iw_create_cq;
  2360. iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
  2361. iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
  2362. iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
  2363. iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
  2364. iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
  2365. iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
  2366. iwibdev->ibdev.query_device = i40iw_query_device;
  2367. iwibdev->ibdev.create_ah = i40iw_create_ah;
  2368. iwibdev->ibdev.destroy_ah = i40iw_destroy_ah;
  2369. iwibdev->ibdev.drain_sq = i40iw_drain_sq;
  2370. iwibdev->ibdev.drain_rq = i40iw_drain_rq;
  2371. iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
  2372. iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
  2373. iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
  2374. if (!iwibdev->ibdev.iwcm) {
  2375. ib_dealloc_device(&iwibdev->ibdev);
  2376. i40iw_pr_err("iwcm == NULL\n");
  2377. return NULL;
  2378. }
  2379. iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
  2380. iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
  2381. iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
  2382. iwibdev->ibdev.iwcm->connect = i40iw_connect;
  2383. iwibdev->ibdev.iwcm->accept = i40iw_accept;
  2384. iwibdev->ibdev.iwcm->reject = i40iw_reject;
  2385. iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
  2386. iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
  2387. memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
  2388. sizeof(iwibdev->ibdev.iwcm->ifname));
  2389. iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
  2390. iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
  2391. iwibdev->ibdev.poll_cq = i40iw_poll_cq;
  2392. iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
  2393. iwibdev->ibdev.post_send = i40iw_post_send;
  2394. iwibdev->ibdev.post_recv = i40iw_post_recv;
  2395. return iwibdev;
  2396. }
  2397. /**
  2398. * i40iw_port_ibevent - indicate port event
  2399. * @iwdev: iwarp device
  2400. */
  2401. void i40iw_port_ibevent(struct i40iw_device *iwdev)
  2402. {
  2403. struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
  2404. struct ib_event event;
  2405. event.device = &iwibdev->ibdev;
  2406. event.element.port_num = 1;
  2407. event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2408. ib_dispatch_event(&event);
  2409. }
  2410. /**
  2411. * i40iw_unregister_rdma_device - unregister of iwarp from IB
  2412. * @iwibdev: rdma device ptr
  2413. */
  2414. static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
  2415. {
  2416. int i;
  2417. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
  2418. device_remove_file(&iwibdev->ibdev.dev,
  2419. i40iw_dev_attributes[i]);
  2420. ib_unregister_device(&iwibdev->ibdev);
  2421. }
  2422. /**
  2423. * i40iw_destroy_rdma_device - destroy rdma device and free resources
  2424. * @iwibdev: IB device ptr
  2425. */
  2426. void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
  2427. {
  2428. if (!iwibdev)
  2429. return;
  2430. i40iw_unregister_rdma_device(iwibdev);
  2431. kfree(iwibdev->ibdev.iwcm);
  2432. iwibdev->ibdev.iwcm = NULL;
  2433. ib_dealloc_device(&iwibdev->ibdev);
  2434. }
  2435. /**
  2436. * i40iw_register_rdma_device - register iwarp device to IB
  2437. * @iwdev: iwarp device
  2438. */
  2439. int i40iw_register_rdma_device(struct i40iw_device *iwdev)
  2440. {
  2441. int i, ret;
  2442. struct i40iw_ib_device *iwibdev;
  2443. iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
  2444. if (!iwdev->iwibdev)
  2445. return -ENOMEM;
  2446. iwibdev = iwdev->iwibdev;
  2447. ret = ib_register_device(&iwibdev->ibdev, NULL);
  2448. if (ret)
  2449. goto error;
  2450. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
  2451. ret =
  2452. device_create_file(&iwibdev->ibdev.dev,
  2453. i40iw_dev_attributes[i]);
  2454. if (ret) {
  2455. while (i > 0) {
  2456. i--;
  2457. device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
  2458. }
  2459. ib_unregister_device(&iwibdev->ibdev);
  2460. goto error;
  2461. }
  2462. }
  2463. return 0;
  2464. error:
  2465. kfree(iwdev->iwibdev->ibdev.iwcm);
  2466. iwdev->iwibdev->ibdev.iwcm = NULL;
  2467. ib_dealloc_device(&iwdev->iwibdev->ibdev);
  2468. return ret;
  2469. }