init.c 49 KB

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  1. /*
  2. * Copyright(c) 2015, 2016 Intel Corporation.
  3. *
  4. * This file is provided under a dual BSD/GPLv2 license. When using or
  5. * redistributing this file, you may do so under either license.
  6. *
  7. * GPL LICENSE SUMMARY
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of version 2 of the GNU General Public License as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * BSD LICENSE
  19. *
  20. * Redistribution and use in source and binary forms, with or without
  21. * modification, are permitted provided that the following conditions
  22. * are met:
  23. *
  24. * - Redistributions of source code must retain the above copyright
  25. * notice, this list of conditions and the following disclaimer.
  26. * - Redistributions in binary form must reproduce the above copyright
  27. * notice, this list of conditions and the following disclaimer in
  28. * the documentation and/or other materials provided with the
  29. * distribution.
  30. * - Neither the name of Intel Corporation nor the names of its
  31. * contributors may be used to endorse or promote products derived
  32. * from this software without specific prior written permission.
  33. *
  34. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45. *
  46. */
  47. #include <linux/pci.h>
  48. #include <linux/netdevice.h>
  49. #include <linux/vmalloc.h>
  50. #include <linux/delay.h>
  51. #include <linux/idr.h>
  52. #include <linux/module.h>
  53. #include <linux/printk.h>
  54. #include <linux/hrtimer.h>
  55. #include <rdma/rdma_vt.h>
  56. #include "hfi.h"
  57. #include "device.h"
  58. #include "common.h"
  59. #include "trace.h"
  60. #include "mad.h"
  61. #include "sdma.h"
  62. #include "debugfs.h"
  63. #include "verbs.h"
  64. #include "aspm.h"
  65. #include "affinity.h"
  66. #undef pr_fmt
  67. #define pr_fmt(fmt) DRIVER_NAME ": " fmt
  68. /*
  69. * min buffers we want to have per context, after driver
  70. */
  71. #define HFI1_MIN_USER_CTXT_BUFCNT 7
  72. #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
  73. #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
  74. #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
  75. #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
  76. /*
  77. * Number of user receive contexts we are configured to use (to allow for more
  78. * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
  79. */
  80. int num_user_contexts = -1;
  81. module_param_named(num_user_contexts, num_user_contexts, uint, S_IRUGO);
  82. MODULE_PARM_DESC(
  83. num_user_contexts, "Set max number of user contexts to use");
  84. uint krcvqs[RXE_NUM_DATA_VL];
  85. int krcvqsset;
  86. module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
  87. MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
  88. /* computed based on above array */
  89. unsigned n_krcvqs;
  90. static unsigned hfi1_rcvarr_split = 25;
  91. module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
  92. MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
  93. static uint eager_buffer_size = (2 << 20); /* 2MB */
  94. module_param(eager_buffer_size, uint, S_IRUGO);
  95. MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 2MB");
  96. static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
  97. module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
  98. MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
  99. static uint hfi1_hdrq_entsize = 32;
  100. module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO);
  101. MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
  102. unsigned int user_credit_return_threshold = 33; /* default is 33% */
  103. module_param(user_credit_return_threshold, uint, S_IRUGO);
  104. MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
  105. static inline u64 encode_rcv_header_entry_size(u16);
  106. static struct idr hfi1_unit_table;
  107. u32 hfi1_cpulist_count;
  108. unsigned long *hfi1_cpulist;
  109. /*
  110. * Common code for creating the receive context array.
  111. */
  112. int hfi1_create_ctxts(struct hfi1_devdata *dd)
  113. {
  114. unsigned i;
  115. int ret;
  116. /* Control context has to be always 0 */
  117. BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
  118. dd->rcd = kzalloc_node(dd->num_rcv_contexts * sizeof(*dd->rcd),
  119. GFP_KERNEL, dd->node);
  120. if (!dd->rcd)
  121. goto nomem;
  122. /* create one or more kernel contexts */
  123. for (i = 0; i < dd->first_user_ctxt; ++i) {
  124. struct hfi1_pportdata *ppd;
  125. struct hfi1_ctxtdata *rcd;
  126. ppd = dd->pport + (i % dd->num_pports);
  127. rcd = hfi1_create_ctxtdata(ppd, i, dd->node);
  128. if (!rcd) {
  129. dd_dev_err(dd,
  130. "Unable to allocate kernel receive context, failing\n");
  131. goto nomem;
  132. }
  133. /*
  134. * Set up the kernel context flags here and now because they
  135. * use default values for all receive side memories. User
  136. * contexts will be handled as they are created.
  137. */
  138. rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
  139. HFI1_CAP_KGET(NODROP_RHQ_FULL) |
  140. HFI1_CAP_KGET(NODROP_EGR_FULL) |
  141. HFI1_CAP_KGET(DMA_RTAIL);
  142. /* Control context must use DMA_RTAIL */
  143. if (rcd->ctxt == HFI1_CTRL_CTXT)
  144. rcd->flags |= HFI1_CAP_DMA_RTAIL;
  145. rcd->seq_cnt = 1;
  146. rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
  147. if (!rcd->sc) {
  148. dd_dev_err(dd,
  149. "Unable to allocate kernel send context, failing\n");
  150. dd->rcd[rcd->ctxt] = NULL;
  151. hfi1_free_ctxtdata(dd, rcd);
  152. goto nomem;
  153. }
  154. ret = hfi1_init_ctxt(rcd->sc);
  155. if (ret < 0) {
  156. dd_dev_err(dd,
  157. "Failed to setup kernel receive context, failing\n");
  158. sc_free(rcd->sc);
  159. dd->rcd[rcd->ctxt] = NULL;
  160. hfi1_free_ctxtdata(dd, rcd);
  161. ret = -EFAULT;
  162. goto bail;
  163. }
  164. }
  165. /*
  166. * Initialize aspm, to be done after gen3 transition and setting up
  167. * contexts and before enabling interrupts
  168. */
  169. aspm_init(dd);
  170. return 0;
  171. nomem:
  172. ret = -ENOMEM;
  173. bail:
  174. kfree(dd->rcd);
  175. dd->rcd = NULL;
  176. return ret;
  177. }
  178. /*
  179. * Common code for user and kernel context setup.
  180. */
  181. struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt,
  182. int numa)
  183. {
  184. struct hfi1_devdata *dd = ppd->dd;
  185. struct hfi1_ctxtdata *rcd;
  186. unsigned kctxt_ngroups = 0;
  187. u32 base;
  188. if (dd->rcv_entries.nctxt_extra >
  189. dd->num_rcv_contexts - dd->first_user_ctxt)
  190. kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
  191. (dd->num_rcv_contexts - dd->first_user_ctxt));
  192. rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);
  193. if (rcd) {
  194. u32 rcvtids, max_entries;
  195. hfi1_cdbg(PROC, "setting up context %u\n", ctxt);
  196. INIT_LIST_HEAD(&rcd->qp_wait_list);
  197. rcd->ppd = ppd;
  198. rcd->dd = dd;
  199. rcd->cnt = 1;
  200. rcd->ctxt = ctxt;
  201. dd->rcd[ctxt] = rcd;
  202. rcd->numa_id = numa;
  203. rcd->rcv_array_groups = dd->rcv_entries.ngroups;
  204. mutex_init(&rcd->exp_lock);
  205. /*
  206. * Calculate the context's RcvArray entry starting point.
  207. * We do this here because we have to take into account all
  208. * the RcvArray entries that previous context would have
  209. * taken and we have to account for any extra groups
  210. * assigned to the kernel or user contexts.
  211. */
  212. if (ctxt < dd->first_user_ctxt) {
  213. if (ctxt < kctxt_ngroups) {
  214. base = ctxt * (dd->rcv_entries.ngroups + 1);
  215. rcd->rcv_array_groups++;
  216. } else
  217. base = kctxt_ngroups +
  218. (ctxt * dd->rcv_entries.ngroups);
  219. } else {
  220. u16 ct = ctxt - dd->first_user_ctxt;
  221. base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
  222. kctxt_ngroups);
  223. if (ct < dd->rcv_entries.nctxt_extra) {
  224. base += ct * (dd->rcv_entries.ngroups + 1);
  225. rcd->rcv_array_groups++;
  226. } else
  227. base += dd->rcv_entries.nctxt_extra +
  228. (ct * dd->rcv_entries.ngroups);
  229. }
  230. rcd->eager_base = base * dd->rcv_entries.group_size;
  231. /* Validate and initialize Rcv Hdr Q variables */
  232. if (rcvhdrcnt % HDRQ_INCREMENT) {
  233. dd_dev_err(dd,
  234. "ctxt%u: header queue count %d must be divisible by %lu\n",
  235. rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT);
  236. goto bail;
  237. }
  238. rcd->rcvhdrq_cnt = rcvhdrcnt;
  239. rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
  240. /*
  241. * Simple Eager buffer allocation: we have already pre-allocated
  242. * the number of RcvArray entry groups. Each ctxtdata structure
  243. * holds the number of groups for that context.
  244. *
  245. * To follow CSR requirements and maintain cacheline alignment,
  246. * make sure all sizes and bases are multiples of group_size.
  247. *
  248. * The expected entry count is what is left after assigning
  249. * eager.
  250. */
  251. max_entries = rcd->rcv_array_groups *
  252. dd->rcv_entries.group_size;
  253. rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
  254. rcd->egrbufs.count = round_down(rcvtids,
  255. dd->rcv_entries.group_size);
  256. if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
  257. dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
  258. rcd->ctxt);
  259. rcd->egrbufs.count = MAX_EAGER_ENTRIES;
  260. }
  261. hfi1_cdbg(PROC,
  262. "ctxt%u: max Eager buffer RcvArray entries: %u\n",
  263. rcd->ctxt, rcd->egrbufs.count);
  264. /*
  265. * Allocate array that will hold the eager buffer accounting
  266. * data.
  267. * This will allocate the maximum possible buffer count based
  268. * on the value of the RcvArray split parameter.
  269. * The resulting value will be rounded down to the closest
  270. * multiple of dd->rcv_entries.group_size.
  271. */
  272. rcd->egrbufs.buffers = kcalloc(rcd->egrbufs.count,
  273. sizeof(*rcd->egrbufs.buffers),
  274. GFP_KERNEL);
  275. if (!rcd->egrbufs.buffers)
  276. goto bail;
  277. rcd->egrbufs.rcvtids = kcalloc(rcd->egrbufs.count,
  278. sizeof(*rcd->egrbufs.rcvtids),
  279. GFP_KERNEL);
  280. if (!rcd->egrbufs.rcvtids)
  281. goto bail;
  282. rcd->egrbufs.size = eager_buffer_size;
  283. /*
  284. * The size of the buffers programmed into the RcvArray
  285. * entries needs to be big enough to handle the highest
  286. * MTU supported.
  287. */
  288. if (rcd->egrbufs.size < hfi1_max_mtu) {
  289. rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
  290. hfi1_cdbg(PROC,
  291. "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
  292. rcd->ctxt, rcd->egrbufs.size);
  293. }
  294. rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
  295. if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */
  296. rcd->opstats = kzalloc(sizeof(*rcd->opstats),
  297. GFP_KERNEL);
  298. if (!rcd->opstats)
  299. goto bail;
  300. }
  301. }
  302. return rcd;
  303. bail:
  304. kfree(rcd->egrbufs.rcvtids);
  305. kfree(rcd->egrbufs.buffers);
  306. kfree(rcd);
  307. return NULL;
  308. }
  309. /*
  310. * Convert a receive header entry size that to the encoding used in the CSR.
  311. *
  312. * Return a zero if the given size is invalid.
  313. */
  314. static inline u64 encode_rcv_header_entry_size(u16 size)
  315. {
  316. /* there are only 3 valid receive header entry sizes */
  317. if (size == 2)
  318. return 1;
  319. if (size == 16)
  320. return 2;
  321. else if (size == 32)
  322. return 4;
  323. return 0; /* invalid */
  324. }
  325. /*
  326. * Select the largest ccti value over all SLs to determine the intra-
  327. * packet gap for the link.
  328. *
  329. * called with cca_timer_lock held (to protect access to cca_timer
  330. * array), and rcu_read_lock() (to protect access to cc_state).
  331. */
  332. void set_link_ipg(struct hfi1_pportdata *ppd)
  333. {
  334. struct hfi1_devdata *dd = ppd->dd;
  335. struct cc_state *cc_state;
  336. int i;
  337. u16 cce, ccti_limit, max_ccti = 0;
  338. u16 shift, mult;
  339. u64 src;
  340. u32 current_egress_rate; /* Mbits /sec */
  341. u32 max_pkt_time;
  342. /*
  343. * max_pkt_time is the maximum packet egress time in units
  344. * of the fabric clock period 1/(805 MHz).
  345. */
  346. cc_state = get_cc_state(ppd);
  347. if (!cc_state)
  348. /*
  349. * This should _never_ happen - rcu_read_lock() is held,
  350. * and set_link_ipg() should not be called if cc_state
  351. * is NULL.
  352. */
  353. return;
  354. for (i = 0; i < OPA_MAX_SLS; i++) {
  355. u16 ccti = ppd->cca_timer[i].ccti;
  356. if (ccti > max_ccti)
  357. max_ccti = ccti;
  358. }
  359. ccti_limit = cc_state->cct.ccti_limit;
  360. if (max_ccti > ccti_limit)
  361. max_ccti = ccti_limit;
  362. cce = cc_state->cct.entries[max_ccti].entry;
  363. shift = (cce & 0xc000) >> 14;
  364. mult = (cce & 0x3fff);
  365. current_egress_rate = active_egress_rate(ppd);
  366. max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
  367. src = (max_pkt_time >> shift) * mult;
  368. src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
  369. src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
  370. write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
  371. }
  372. static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
  373. {
  374. struct cca_timer *cca_timer;
  375. struct hfi1_pportdata *ppd;
  376. int sl;
  377. u16 ccti_timer, ccti_min;
  378. struct cc_state *cc_state;
  379. unsigned long flags;
  380. enum hrtimer_restart ret = HRTIMER_NORESTART;
  381. cca_timer = container_of(t, struct cca_timer, hrtimer);
  382. ppd = cca_timer->ppd;
  383. sl = cca_timer->sl;
  384. rcu_read_lock();
  385. cc_state = get_cc_state(ppd);
  386. if (!cc_state) {
  387. rcu_read_unlock();
  388. return HRTIMER_NORESTART;
  389. }
  390. /*
  391. * 1) decrement ccti for SL
  392. * 2) calculate IPG for link (set_link_ipg())
  393. * 3) restart timer, unless ccti is at min value
  394. */
  395. ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
  396. ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
  397. spin_lock_irqsave(&ppd->cca_timer_lock, flags);
  398. if (cca_timer->ccti > ccti_min) {
  399. cca_timer->ccti--;
  400. set_link_ipg(ppd);
  401. }
  402. if (cca_timer->ccti > ccti_min) {
  403. unsigned long nsec = 1024 * ccti_timer;
  404. /* ccti_timer is in units of 1.024 usec */
  405. hrtimer_forward_now(t, ns_to_ktime(nsec));
  406. ret = HRTIMER_RESTART;
  407. }
  408. spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
  409. rcu_read_unlock();
  410. return ret;
  411. }
  412. /*
  413. * Common code for initializing the physical port structure.
  414. */
  415. void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
  416. struct hfi1_devdata *dd, u8 hw_pidx, u8 port)
  417. {
  418. int i;
  419. uint default_pkey_idx;
  420. struct cc_state *cc_state;
  421. ppd->dd = dd;
  422. ppd->hw_pidx = hw_pidx;
  423. ppd->port = port; /* IB port number, not index */
  424. default_pkey_idx = 1;
  425. ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
  426. if (loopback) {
  427. hfi1_early_err(&pdev->dev,
  428. "Faking data partition 0x8001 in idx %u\n",
  429. !default_pkey_idx);
  430. ppd->pkeys[!default_pkey_idx] = 0x8001;
  431. }
  432. INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
  433. INIT_WORK(&ppd->link_up_work, handle_link_up);
  434. INIT_WORK(&ppd->link_down_work, handle_link_down);
  435. INIT_WORK(&ppd->freeze_work, handle_freeze);
  436. INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
  437. INIT_WORK(&ppd->sma_message_work, handle_sma_message);
  438. INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
  439. INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
  440. INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
  441. mutex_init(&ppd->hls_lock);
  442. spin_lock_init(&ppd->sdma_alllock);
  443. spin_lock_init(&ppd->qsfp_info.qsfp_lock);
  444. ppd->qsfp_info.ppd = ppd;
  445. ppd->sm_trap_qp = 0x0;
  446. ppd->sa_qp = 0x1;
  447. ppd->hfi1_wq = NULL;
  448. spin_lock_init(&ppd->cca_timer_lock);
  449. for (i = 0; i < OPA_MAX_SLS; i++) {
  450. hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
  451. HRTIMER_MODE_REL);
  452. ppd->cca_timer[i].ppd = ppd;
  453. ppd->cca_timer[i].sl = i;
  454. ppd->cca_timer[i].ccti = 0;
  455. ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
  456. }
  457. ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
  458. spin_lock_init(&ppd->cc_state_lock);
  459. spin_lock_init(&ppd->cc_log_lock);
  460. cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL);
  461. RCU_INIT_POINTER(ppd->cc_state, cc_state);
  462. if (!cc_state)
  463. goto bail;
  464. return;
  465. bail:
  466. hfi1_early_err(&pdev->dev,
  467. "Congestion Control Agent disabled for port %d\n", port);
  468. }
  469. /*
  470. * Do initialization for device that is only needed on
  471. * first detect, not on resets.
  472. */
  473. static int loadtime_init(struct hfi1_devdata *dd)
  474. {
  475. return 0;
  476. }
  477. /**
  478. * init_after_reset - re-initialize after a reset
  479. * @dd: the hfi1_ib device
  480. *
  481. * sanity check at least some of the values after reset, and
  482. * ensure no receive or transmit (explicitly, in case reset
  483. * failed
  484. */
  485. static int init_after_reset(struct hfi1_devdata *dd)
  486. {
  487. int i;
  488. /*
  489. * Ensure chip does no sends or receives, tail updates, or
  490. * pioavail updates while we re-initialize. This is mostly
  491. * for the driver data structures, not chip registers.
  492. */
  493. for (i = 0; i < dd->num_rcv_contexts; i++)
  494. hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
  495. HFI1_RCVCTRL_INTRAVAIL_DIS |
  496. HFI1_RCVCTRL_TAILUPD_DIS, i);
  497. pio_send_control(dd, PSC_GLOBAL_DISABLE);
  498. for (i = 0; i < dd->num_send_contexts; i++)
  499. sc_disable(dd->send_contexts[i].sc);
  500. return 0;
  501. }
  502. static void enable_chip(struct hfi1_devdata *dd)
  503. {
  504. u32 rcvmask;
  505. u32 i;
  506. /* enable PIO send */
  507. pio_send_control(dd, PSC_GLOBAL_ENABLE);
  508. /*
  509. * Enable kernel ctxts' receive and receive interrupt.
  510. * Other ctxts done as user opens and initializes them.
  511. */
  512. for (i = 0; i < dd->first_user_ctxt; ++i) {
  513. rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
  514. rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
  515. HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
  516. if (!HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, MULTI_PKT_EGR))
  517. rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
  518. if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_RHQ_FULL))
  519. rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
  520. if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_EGR_FULL))
  521. rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
  522. hfi1_rcvctrl(dd, rcvmask, i);
  523. sc_enable(dd->rcd[i]->sc);
  524. }
  525. }
  526. /**
  527. * create_workqueues - create per port workqueues
  528. * @dd: the hfi1_ib device
  529. */
  530. static int create_workqueues(struct hfi1_devdata *dd)
  531. {
  532. int pidx;
  533. struct hfi1_pportdata *ppd;
  534. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  535. ppd = dd->pport + pidx;
  536. if (!ppd->hfi1_wq) {
  537. ppd->hfi1_wq =
  538. alloc_workqueue(
  539. "hfi%d_%d",
  540. WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE,
  541. dd->num_sdma,
  542. dd->unit, pidx);
  543. if (!ppd->hfi1_wq)
  544. goto wq_error;
  545. }
  546. }
  547. return 0;
  548. wq_error:
  549. pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
  550. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  551. ppd = dd->pport + pidx;
  552. if (ppd->hfi1_wq) {
  553. destroy_workqueue(ppd->hfi1_wq);
  554. ppd->hfi1_wq = NULL;
  555. }
  556. }
  557. return -ENOMEM;
  558. }
  559. /**
  560. * hfi1_init - do the actual initialization sequence on the chip
  561. * @dd: the hfi1_ib device
  562. * @reinit: re-initializing, so don't allocate new memory
  563. *
  564. * Do the actual initialization sequence on the chip. This is done
  565. * both from the init routine called from the PCI infrastructure, and
  566. * when we reset the chip, or detect that it was reset internally,
  567. * or it's administratively re-enabled.
  568. *
  569. * Memory allocation here and in called routines is only done in
  570. * the first case (reinit == 0). We have to be careful, because even
  571. * without memory allocation, we need to re-write all the chip registers
  572. * TIDs, etc. after the reset or enable has completed.
  573. */
  574. int hfi1_init(struct hfi1_devdata *dd, int reinit)
  575. {
  576. int ret = 0, pidx, lastfail = 0;
  577. unsigned i, len;
  578. struct hfi1_ctxtdata *rcd;
  579. struct hfi1_pportdata *ppd;
  580. /* Set up recv low level handlers */
  581. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] =
  582. kdeth_process_expected;
  583. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] =
  584. kdeth_process_eager;
  585. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib;
  586. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] =
  587. process_receive_error;
  588. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] =
  589. process_receive_bypass;
  590. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] =
  591. process_receive_invalid;
  592. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] =
  593. process_receive_invalid;
  594. dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] =
  595. process_receive_invalid;
  596. dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions;
  597. /* Set up send low level handlers */
  598. dd->process_pio_send = hfi1_verbs_send_pio;
  599. dd->process_dma_send = hfi1_verbs_send_dma;
  600. dd->pio_inline_send = pio_copy;
  601. if (is_ax(dd)) {
  602. atomic_set(&dd->drop_packet, DROP_PACKET_ON);
  603. dd->do_drop = 1;
  604. } else {
  605. atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
  606. dd->do_drop = 0;
  607. }
  608. /* make sure the link is not "up" */
  609. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  610. ppd = dd->pport + pidx;
  611. ppd->linkup = 0;
  612. }
  613. if (reinit)
  614. ret = init_after_reset(dd);
  615. else
  616. ret = loadtime_init(dd);
  617. if (ret)
  618. goto done;
  619. /* allocate dummy tail memory for all receive contexts */
  620. dd->rcvhdrtail_dummy_kvaddr = dma_zalloc_coherent(
  621. &dd->pcidev->dev, sizeof(u64),
  622. &dd->rcvhdrtail_dummy_physaddr,
  623. GFP_KERNEL);
  624. if (!dd->rcvhdrtail_dummy_kvaddr) {
  625. dd_dev_err(dd, "cannot allocate dummy tail memory\n");
  626. ret = -ENOMEM;
  627. goto done;
  628. }
  629. /* dd->rcd can be NULL if early initialization failed */
  630. for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
  631. /*
  632. * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
  633. * re-init, the simplest way to handle this is to free
  634. * existing, and re-allocate.
  635. * Need to re-create rest of ctxt 0 ctxtdata as well.
  636. */
  637. rcd = dd->rcd[i];
  638. if (!rcd)
  639. continue;
  640. rcd->do_interrupt = &handle_receive_interrupt;
  641. lastfail = hfi1_create_rcvhdrq(dd, rcd);
  642. if (!lastfail)
  643. lastfail = hfi1_setup_eagerbufs(rcd);
  644. if (lastfail) {
  645. dd_dev_err(dd,
  646. "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
  647. ret = lastfail;
  648. }
  649. }
  650. /* Allocate enough memory for user event notification. */
  651. len = PAGE_ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS *
  652. sizeof(*dd->events));
  653. dd->events = vmalloc_user(len);
  654. if (!dd->events)
  655. dd_dev_err(dd, "Failed to allocate user events page\n");
  656. /*
  657. * Allocate a page for device and port status.
  658. * Page will be shared amongst all user processes.
  659. */
  660. dd->status = vmalloc_user(PAGE_SIZE);
  661. if (!dd->status)
  662. dd_dev_err(dd, "Failed to allocate dev status page\n");
  663. else
  664. dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) -
  665. sizeof(dd->status->freezemsg));
  666. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  667. ppd = dd->pport + pidx;
  668. if (dd->status)
  669. /* Currently, we only have one port */
  670. ppd->statusp = &dd->status->port;
  671. set_mtu(ppd);
  672. }
  673. /* enable chip even if we have an error, so we can debug cause */
  674. enable_chip(dd);
  675. done:
  676. /*
  677. * Set status even if port serdes is not initialized
  678. * so that diags will work.
  679. */
  680. if (dd->status)
  681. dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
  682. HFI1_STATUS_INITTED;
  683. if (!ret) {
  684. /* enable all interrupts from the chip */
  685. set_intr_state(dd, 1);
  686. /* chip is OK for user apps; mark it as initialized */
  687. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  688. ppd = dd->pport + pidx;
  689. /*
  690. * start the serdes - must be after interrupts are
  691. * enabled so we are notified when the link goes up
  692. */
  693. lastfail = bringup_serdes(ppd);
  694. if (lastfail)
  695. dd_dev_info(dd,
  696. "Failed to bring up port %u\n",
  697. ppd->port);
  698. /*
  699. * Set status even if port serdes is not initialized
  700. * so that diags will work.
  701. */
  702. if (ppd->statusp)
  703. *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
  704. HFI1_STATUS_INITTED;
  705. if (!ppd->link_speed_enabled)
  706. continue;
  707. }
  708. }
  709. /* if ret is non-zero, we probably should do some cleanup here... */
  710. return ret;
  711. }
  712. static inline struct hfi1_devdata *__hfi1_lookup(int unit)
  713. {
  714. return idr_find(&hfi1_unit_table, unit);
  715. }
  716. struct hfi1_devdata *hfi1_lookup(int unit)
  717. {
  718. struct hfi1_devdata *dd;
  719. unsigned long flags;
  720. spin_lock_irqsave(&hfi1_devs_lock, flags);
  721. dd = __hfi1_lookup(unit);
  722. spin_unlock_irqrestore(&hfi1_devs_lock, flags);
  723. return dd;
  724. }
  725. /*
  726. * Stop the timers during unit shutdown, or after an error late
  727. * in initialization.
  728. */
  729. static void stop_timers(struct hfi1_devdata *dd)
  730. {
  731. struct hfi1_pportdata *ppd;
  732. int pidx;
  733. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  734. ppd = dd->pport + pidx;
  735. if (ppd->led_override_timer.data) {
  736. del_timer_sync(&ppd->led_override_timer);
  737. atomic_set(&ppd->led_override_timer_active, 0);
  738. }
  739. }
  740. }
  741. /**
  742. * shutdown_device - shut down a device
  743. * @dd: the hfi1_ib device
  744. *
  745. * This is called to make the device quiet when we are about to
  746. * unload the driver, and also when the device is administratively
  747. * disabled. It does not free any data structures.
  748. * Everything it does has to be setup again by hfi1_init(dd, 1)
  749. */
  750. static void shutdown_device(struct hfi1_devdata *dd)
  751. {
  752. struct hfi1_pportdata *ppd;
  753. unsigned pidx;
  754. int i;
  755. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  756. ppd = dd->pport + pidx;
  757. ppd->linkup = 0;
  758. if (ppd->statusp)
  759. *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
  760. HFI1_STATUS_IB_READY);
  761. }
  762. dd->flags &= ~HFI1_INITTED;
  763. /* mask interrupts, but not errors */
  764. set_intr_state(dd, 0);
  765. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  766. ppd = dd->pport + pidx;
  767. for (i = 0; i < dd->num_rcv_contexts; i++)
  768. hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
  769. HFI1_RCVCTRL_CTXT_DIS |
  770. HFI1_RCVCTRL_INTRAVAIL_DIS |
  771. HFI1_RCVCTRL_PKEY_DIS |
  772. HFI1_RCVCTRL_ONE_PKT_EGR_DIS, i);
  773. /*
  774. * Gracefully stop all sends allowing any in progress to
  775. * trickle out first.
  776. */
  777. for (i = 0; i < dd->num_send_contexts; i++)
  778. sc_flush(dd->send_contexts[i].sc);
  779. }
  780. /*
  781. * Enough for anything that's going to trickle out to have actually
  782. * done so.
  783. */
  784. udelay(20);
  785. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  786. ppd = dd->pport + pidx;
  787. /* disable all contexts */
  788. for (i = 0; i < dd->num_send_contexts; i++)
  789. sc_disable(dd->send_contexts[i].sc);
  790. /* disable the send device */
  791. pio_send_control(dd, PSC_GLOBAL_DISABLE);
  792. shutdown_led_override(ppd);
  793. /*
  794. * Clear SerdesEnable.
  795. * We can't count on interrupts since we are stopping.
  796. */
  797. hfi1_quiet_serdes(ppd);
  798. if (ppd->hfi1_wq) {
  799. destroy_workqueue(ppd->hfi1_wq);
  800. ppd->hfi1_wq = NULL;
  801. }
  802. }
  803. sdma_exit(dd);
  804. }
  805. /**
  806. * hfi1_free_ctxtdata - free a context's allocated data
  807. * @dd: the hfi1_ib device
  808. * @rcd: the ctxtdata structure
  809. *
  810. * free up any allocated data for a context
  811. * This should not touch anything that would affect a simultaneous
  812. * re-allocation of context data, because it is called after hfi1_mutex
  813. * is released (and can be called from reinit as well).
  814. * It should never change any chip state, or global driver state.
  815. */
  816. void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
  817. {
  818. unsigned e;
  819. if (!rcd)
  820. return;
  821. if (rcd->rcvhdrq) {
  822. dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
  823. rcd->rcvhdrq, rcd->rcvhdrq_phys);
  824. rcd->rcvhdrq = NULL;
  825. if (rcd->rcvhdrtail_kvaddr) {
  826. dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
  827. (void *)rcd->rcvhdrtail_kvaddr,
  828. rcd->rcvhdrqtailaddr_phys);
  829. rcd->rcvhdrtail_kvaddr = NULL;
  830. }
  831. }
  832. /* all the RcvArray entries should have been cleared by now */
  833. kfree(rcd->egrbufs.rcvtids);
  834. for (e = 0; e < rcd->egrbufs.alloced; e++) {
  835. if (rcd->egrbufs.buffers[e].phys)
  836. dma_free_coherent(&dd->pcidev->dev,
  837. rcd->egrbufs.buffers[e].len,
  838. rcd->egrbufs.buffers[e].addr,
  839. rcd->egrbufs.buffers[e].phys);
  840. }
  841. kfree(rcd->egrbufs.buffers);
  842. sc_free(rcd->sc);
  843. vfree(rcd->user_event_mask);
  844. vfree(rcd->subctxt_uregbase);
  845. vfree(rcd->subctxt_rcvegrbuf);
  846. vfree(rcd->subctxt_rcvhdr_base);
  847. kfree(rcd->opstats);
  848. kfree(rcd);
  849. }
  850. /*
  851. * Release our hold on the shared asic data. If we are the last one,
  852. * return the structure to be finalized outside the lock. Must be
  853. * holding hfi1_devs_lock.
  854. */
  855. static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
  856. {
  857. struct hfi1_asic_data *ad;
  858. int other;
  859. if (!dd->asic_data)
  860. return NULL;
  861. dd->asic_data->dds[dd->hfi1_id] = NULL;
  862. other = dd->hfi1_id ? 0 : 1;
  863. ad = dd->asic_data;
  864. dd->asic_data = NULL;
  865. /* return NULL if the other dd still has a link */
  866. return ad->dds[other] ? NULL : ad;
  867. }
  868. static void finalize_asic_data(struct hfi1_devdata *dd,
  869. struct hfi1_asic_data *ad)
  870. {
  871. clean_up_i2c(dd, ad);
  872. kfree(ad);
  873. }
  874. static void __hfi1_free_devdata(struct kobject *kobj)
  875. {
  876. struct hfi1_devdata *dd =
  877. container_of(kobj, struct hfi1_devdata, kobj);
  878. struct hfi1_asic_data *ad;
  879. unsigned long flags;
  880. spin_lock_irqsave(&hfi1_devs_lock, flags);
  881. idr_remove(&hfi1_unit_table, dd->unit);
  882. list_del(&dd->list);
  883. ad = release_asic_data(dd);
  884. spin_unlock_irqrestore(&hfi1_devs_lock, flags);
  885. if (ad)
  886. finalize_asic_data(dd, ad);
  887. free_platform_config(dd);
  888. rcu_barrier(); /* wait for rcu callbacks to complete */
  889. free_percpu(dd->int_counter);
  890. free_percpu(dd->rcv_limit);
  891. free_percpu(dd->send_schedule);
  892. rvt_dealloc_device(&dd->verbs_dev.rdi);
  893. }
  894. static struct kobj_type hfi1_devdata_type = {
  895. .release = __hfi1_free_devdata,
  896. };
  897. void hfi1_free_devdata(struct hfi1_devdata *dd)
  898. {
  899. kobject_put(&dd->kobj);
  900. }
  901. /*
  902. * Allocate our primary per-unit data structure. Must be done via verbs
  903. * allocator, because the verbs cleanup process both does cleanup and
  904. * free of the data structure.
  905. * "extra" is for chip-specific data.
  906. *
  907. * Use the idr mechanism to get a unit number for this unit.
  908. */
  909. struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra)
  910. {
  911. unsigned long flags;
  912. struct hfi1_devdata *dd;
  913. int ret, nports;
  914. /* extra is * number of ports */
  915. nports = extra / sizeof(struct hfi1_pportdata);
  916. dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
  917. nports);
  918. if (!dd)
  919. return ERR_PTR(-ENOMEM);
  920. dd->num_pports = nports;
  921. dd->pport = (struct hfi1_pportdata *)(dd + 1);
  922. INIT_LIST_HEAD(&dd->list);
  923. idr_preload(GFP_KERNEL);
  924. spin_lock_irqsave(&hfi1_devs_lock, flags);
  925. ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT);
  926. if (ret >= 0) {
  927. dd->unit = ret;
  928. list_add(&dd->list, &hfi1_dev_list);
  929. }
  930. spin_unlock_irqrestore(&hfi1_devs_lock, flags);
  931. idr_preload_end();
  932. if (ret < 0) {
  933. hfi1_early_err(&pdev->dev,
  934. "Could not allocate unit ID: error %d\n", -ret);
  935. goto bail;
  936. }
  937. /*
  938. * Initialize all locks for the device. This needs to be as early as
  939. * possible so locks are usable.
  940. */
  941. spin_lock_init(&dd->sc_lock);
  942. spin_lock_init(&dd->sendctrl_lock);
  943. spin_lock_init(&dd->rcvctrl_lock);
  944. spin_lock_init(&dd->uctxt_lock);
  945. spin_lock_init(&dd->hfi1_diag_trans_lock);
  946. spin_lock_init(&dd->sc_init_lock);
  947. spin_lock_init(&dd->dc8051_lock);
  948. spin_lock_init(&dd->dc8051_memlock);
  949. seqlock_init(&dd->sc2vl_lock);
  950. spin_lock_init(&dd->sde_map_lock);
  951. spin_lock_init(&dd->pio_map_lock);
  952. init_waitqueue_head(&dd->event_queue);
  953. dd->int_counter = alloc_percpu(u64);
  954. if (!dd->int_counter) {
  955. ret = -ENOMEM;
  956. hfi1_early_err(&pdev->dev,
  957. "Could not allocate per-cpu int_counter\n");
  958. goto bail;
  959. }
  960. dd->rcv_limit = alloc_percpu(u64);
  961. if (!dd->rcv_limit) {
  962. ret = -ENOMEM;
  963. hfi1_early_err(&pdev->dev,
  964. "Could not allocate per-cpu rcv_limit\n");
  965. goto bail;
  966. }
  967. dd->send_schedule = alloc_percpu(u64);
  968. if (!dd->send_schedule) {
  969. ret = -ENOMEM;
  970. hfi1_early_err(&pdev->dev,
  971. "Could not allocate per-cpu int_counter\n");
  972. goto bail;
  973. }
  974. if (!hfi1_cpulist_count) {
  975. u32 count = num_online_cpus();
  976. hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long),
  977. GFP_KERNEL);
  978. if (hfi1_cpulist)
  979. hfi1_cpulist_count = count;
  980. else
  981. hfi1_early_err(
  982. &pdev->dev,
  983. "Could not alloc cpulist info, cpu affinity might be wrong\n");
  984. }
  985. kobject_init(&dd->kobj, &hfi1_devdata_type);
  986. return dd;
  987. bail:
  988. if (!list_empty(&dd->list))
  989. list_del_init(&dd->list);
  990. rvt_dealloc_device(&dd->verbs_dev.rdi);
  991. return ERR_PTR(ret);
  992. }
  993. /*
  994. * Called from freeze mode handlers, and from PCI error
  995. * reporting code. Should be paranoid about state of
  996. * system and data structures.
  997. */
  998. void hfi1_disable_after_error(struct hfi1_devdata *dd)
  999. {
  1000. if (dd->flags & HFI1_INITTED) {
  1001. u32 pidx;
  1002. dd->flags &= ~HFI1_INITTED;
  1003. if (dd->pport)
  1004. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  1005. struct hfi1_pportdata *ppd;
  1006. ppd = dd->pport + pidx;
  1007. if (dd->flags & HFI1_PRESENT)
  1008. set_link_state(ppd, HLS_DN_DISABLE);
  1009. if (ppd->statusp)
  1010. *ppd->statusp &= ~HFI1_STATUS_IB_READY;
  1011. }
  1012. }
  1013. /*
  1014. * Mark as having had an error for driver, and also
  1015. * for /sys and status word mapped to user programs.
  1016. * This marks unit as not usable, until reset.
  1017. */
  1018. if (dd->status)
  1019. dd->status->dev |= HFI1_STATUS_HWERROR;
  1020. }
  1021. static void remove_one(struct pci_dev *);
  1022. static int init_one(struct pci_dev *, const struct pci_device_id *);
  1023. #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
  1024. #define PFX DRIVER_NAME ": "
  1025. const struct pci_device_id hfi1_pci_tbl[] = {
  1026. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
  1027. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
  1028. { 0, }
  1029. };
  1030. MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
  1031. static struct pci_driver hfi1_pci_driver = {
  1032. .name = DRIVER_NAME,
  1033. .probe = init_one,
  1034. .remove = remove_one,
  1035. .id_table = hfi1_pci_tbl,
  1036. .err_handler = &hfi1_pci_err_handler,
  1037. };
  1038. static void __init compute_krcvqs(void)
  1039. {
  1040. int i;
  1041. for (i = 0; i < krcvqsset; i++)
  1042. n_krcvqs += krcvqs[i];
  1043. }
  1044. /*
  1045. * Do all the generic driver unit- and chip-independent memory
  1046. * allocation and initialization.
  1047. */
  1048. static int __init hfi1_mod_init(void)
  1049. {
  1050. int ret;
  1051. ret = dev_init();
  1052. if (ret)
  1053. goto bail;
  1054. ret = node_affinity_init();
  1055. if (ret)
  1056. goto bail;
  1057. /* validate max MTU before any devices start */
  1058. if (!valid_opa_max_mtu(hfi1_max_mtu)) {
  1059. pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
  1060. hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
  1061. hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
  1062. }
  1063. /* valid CUs run from 1-128 in powers of 2 */
  1064. if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
  1065. hfi1_cu = 1;
  1066. /* valid credit return threshold is 0-100, variable is unsigned */
  1067. if (user_credit_return_threshold > 100)
  1068. user_credit_return_threshold = 100;
  1069. compute_krcvqs();
  1070. /*
  1071. * sanitize receive interrupt count, time must wait until after
  1072. * the hardware type is known
  1073. */
  1074. if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
  1075. rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
  1076. /* reject invalid combinations */
  1077. if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
  1078. pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
  1079. rcv_intr_count = 1;
  1080. }
  1081. if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
  1082. /*
  1083. * Avoid indefinite packet delivery by requiring a timeout
  1084. * if count is > 1.
  1085. */
  1086. pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
  1087. rcv_intr_timeout = 1;
  1088. }
  1089. if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
  1090. /*
  1091. * The dynamic algorithm expects a non-zero timeout
  1092. * and a count > 1.
  1093. */
  1094. pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
  1095. rcv_intr_dynamic = 0;
  1096. }
  1097. /* sanitize link CRC options */
  1098. link_crc_mask &= SUPPORTED_CRCS;
  1099. /*
  1100. * These must be called before the driver is registered with
  1101. * the PCI subsystem.
  1102. */
  1103. idr_init(&hfi1_unit_table);
  1104. hfi1_dbg_init();
  1105. ret = hfi1_wss_init();
  1106. if (ret < 0)
  1107. goto bail_wss;
  1108. ret = pci_register_driver(&hfi1_pci_driver);
  1109. if (ret < 0) {
  1110. pr_err("Unable to register driver: error %d\n", -ret);
  1111. goto bail_dev;
  1112. }
  1113. goto bail; /* all OK */
  1114. bail_dev:
  1115. hfi1_wss_exit();
  1116. bail_wss:
  1117. hfi1_dbg_exit();
  1118. idr_destroy(&hfi1_unit_table);
  1119. dev_cleanup();
  1120. bail:
  1121. return ret;
  1122. }
  1123. module_init(hfi1_mod_init);
  1124. /*
  1125. * Do the non-unit driver cleanup, memory free, etc. at unload.
  1126. */
  1127. static void __exit hfi1_mod_cleanup(void)
  1128. {
  1129. pci_unregister_driver(&hfi1_pci_driver);
  1130. node_affinity_destroy();
  1131. hfi1_wss_exit();
  1132. hfi1_dbg_exit();
  1133. hfi1_cpulist_count = 0;
  1134. kfree(hfi1_cpulist);
  1135. idr_destroy(&hfi1_unit_table);
  1136. dispose_firmware(); /* asymmetric with obtain_firmware() */
  1137. dev_cleanup();
  1138. }
  1139. module_exit(hfi1_mod_cleanup);
  1140. /* this can only be called after a successful initialization */
  1141. static void cleanup_device_data(struct hfi1_devdata *dd)
  1142. {
  1143. int ctxt;
  1144. int pidx;
  1145. struct hfi1_ctxtdata **tmp;
  1146. unsigned long flags;
  1147. /* users can't do anything more with chip */
  1148. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  1149. struct hfi1_pportdata *ppd = &dd->pport[pidx];
  1150. struct cc_state *cc_state;
  1151. int i;
  1152. if (ppd->statusp)
  1153. *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
  1154. for (i = 0; i < OPA_MAX_SLS; i++)
  1155. hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
  1156. spin_lock(&ppd->cc_state_lock);
  1157. cc_state = get_cc_state_protected(ppd);
  1158. RCU_INIT_POINTER(ppd->cc_state, NULL);
  1159. spin_unlock(&ppd->cc_state_lock);
  1160. if (cc_state)
  1161. kfree_rcu(cc_state, rcu);
  1162. }
  1163. free_credit_return(dd);
  1164. /*
  1165. * Free any resources still in use (usually just kernel contexts)
  1166. * at unload; we do for ctxtcnt, because that's what we allocate.
  1167. * We acquire lock to be really paranoid that rcd isn't being
  1168. * accessed from some interrupt-related code (that should not happen,
  1169. * but best to be sure).
  1170. */
  1171. spin_lock_irqsave(&dd->uctxt_lock, flags);
  1172. tmp = dd->rcd;
  1173. dd->rcd = NULL;
  1174. spin_unlock_irqrestore(&dd->uctxt_lock, flags);
  1175. if (dd->rcvhdrtail_dummy_kvaddr) {
  1176. dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
  1177. (void *)dd->rcvhdrtail_dummy_kvaddr,
  1178. dd->rcvhdrtail_dummy_physaddr);
  1179. dd->rcvhdrtail_dummy_kvaddr = NULL;
  1180. }
  1181. for (ctxt = 0; tmp && ctxt < dd->num_rcv_contexts; ctxt++) {
  1182. struct hfi1_ctxtdata *rcd = tmp[ctxt];
  1183. tmp[ctxt] = NULL; /* debugging paranoia */
  1184. if (rcd) {
  1185. hfi1_clear_tids(rcd);
  1186. hfi1_free_ctxtdata(dd, rcd);
  1187. }
  1188. }
  1189. kfree(tmp);
  1190. free_pio_map(dd);
  1191. /* must follow rcv context free - need to remove rcv's hooks */
  1192. for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
  1193. sc_free(dd->send_contexts[ctxt].sc);
  1194. dd->num_send_contexts = 0;
  1195. kfree(dd->send_contexts);
  1196. dd->send_contexts = NULL;
  1197. kfree(dd->hw_to_sw);
  1198. dd->hw_to_sw = NULL;
  1199. kfree(dd->boardname);
  1200. vfree(dd->events);
  1201. vfree(dd->status);
  1202. }
  1203. /*
  1204. * Clean up on unit shutdown, or error during unit load after
  1205. * successful initialization.
  1206. */
  1207. static void postinit_cleanup(struct hfi1_devdata *dd)
  1208. {
  1209. hfi1_start_cleanup(dd);
  1210. hfi1_pcie_ddcleanup(dd);
  1211. hfi1_pcie_cleanup(dd->pcidev);
  1212. cleanup_device_data(dd);
  1213. hfi1_free_devdata(dd);
  1214. }
  1215. static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1216. {
  1217. int ret = 0, j, pidx, initfail;
  1218. struct hfi1_devdata *dd = ERR_PTR(-EINVAL);
  1219. struct hfi1_pportdata *ppd;
  1220. /* First, lock the non-writable module parameters */
  1221. HFI1_CAP_LOCK();
  1222. /* Validate some global module parameters */
  1223. if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {
  1224. hfi1_early_err(&pdev->dev, "Header queue count too small\n");
  1225. ret = -EINVAL;
  1226. goto bail;
  1227. }
  1228. if (rcvhdrcnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
  1229. hfi1_early_err(&pdev->dev,
  1230. "Receive header queue count cannot be greater than %u\n",
  1231. HFI1_MAX_HDRQ_EGRBUF_CNT);
  1232. ret = -EINVAL;
  1233. goto bail;
  1234. }
  1235. /* use the encoding function as a sanitization check */
  1236. if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
  1237. hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n",
  1238. hfi1_hdrq_entsize);
  1239. ret = -EINVAL;
  1240. goto bail;
  1241. }
  1242. /* The receive eager buffer size must be set before the receive
  1243. * contexts are created.
  1244. *
  1245. * Set the eager buffer size. Validate that it falls in a range
  1246. * allowed by the hardware - all powers of 2 between the min and
  1247. * max. The maximum valid MTU is within the eager buffer range
  1248. * so we do not need to cap the max_mtu by an eager buffer size
  1249. * setting.
  1250. */
  1251. if (eager_buffer_size) {
  1252. if (!is_power_of_2(eager_buffer_size))
  1253. eager_buffer_size =
  1254. roundup_pow_of_two(eager_buffer_size);
  1255. eager_buffer_size =
  1256. clamp_val(eager_buffer_size,
  1257. MIN_EAGER_BUFFER * 8,
  1258. MAX_EAGER_BUFFER_TOTAL);
  1259. hfi1_early_info(&pdev->dev, "Eager buffer size %u\n",
  1260. eager_buffer_size);
  1261. } else {
  1262. hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n");
  1263. ret = -EINVAL;
  1264. goto bail;
  1265. }
  1266. /* restrict value of hfi1_rcvarr_split */
  1267. hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
  1268. ret = hfi1_pcie_init(pdev, ent);
  1269. if (ret)
  1270. goto bail;
  1271. /*
  1272. * Do device-specific initialization, function table setup, dd
  1273. * allocation, etc.
  1274. */
  1275. switch (ent->device) {
  1276. case PCI_DEVICE_ID_INTEL0:
  1277. case PCI_DEVICE_ID_INTEL1:
  1278. dd = hfi1_init_dd(pdev, ent);
  1279. break;
  1280. default:
  1281. hfi1_early_err(&pdev->dev,
  1282. "Failing on unknown Intel deviceid 0x%x\n",
  1283. ent->device);
  1284. ret = -ENODEV;
  1285. }
  1286. if (IS_ERR(dd))
  1287. ret = PTR_ERR(dd);
  1288. if (ret)
  1289. goto clean_bail; /* error already printed */
  1290. ret = create_workqueues(dd);
  1291. if (ret)
  1292. goto clean_bail;
  1293. /* do the generic initialization */
  1294. initfail = hfi1_init(dd, 0);
  1295. ret = hfi1_register_ib_device(dd);
  1296. /*
  1297. * Now ready for use. this should be cleared whenever we
  1298. * detect a reset, or initiate one. If earlier failure,
  1299. * we still create devices, so diags, etc. can be used
  1300. * to determine cause of problem.
  1301. */
  1302. if (!initfail && !ret) {
  1303. dd->flags |= HFI1_INITTED;
  1304. /* create debufs files after init and ib register */
  1305. hfi1_dbg_ibdev_init(&dd->verbs_dev);
  1306. }
  1307. j = hfi1_device_create(dd);
  1308. if (j)
  1309. dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
  1310. if (initfail || ret) {
  1311. stop_timers(dd);
  1312. flush_workqueue(ib_wq);
  1313. for (pidx = 0; pidx < dd->num_pports; ++pidx) {
  1314. hfi1_quiet_serdes(dd->pport + pidx);
  1315. ppd = dd->pport + pidx;
  1316. if (ppd->hfi1_wq) {
  1317. destroy_workqueue(ppd->hfi1_wq);
  1318. ppd->hfi1_wq = NULL;
  1319. }
  1320. }
  1321. if (!j)
  1322. hfi1_device_remove(dd);
  1323. if (!ret)
  1324. hfi1_unregister_ib_device(dd);
  1325. postinit_cleanup(dd);
  1326. if (initfail)
  1327. ret = initfail;
  1328. goto bail; /* everything already cleaned */
  1329. }
  1330. sdma_start(dd);
  1331. return 0;
  1332. clean_bail:
  1333. hfi1_pcie_cleanup(pdev);
  1334. bail:
  1335. return ret;
  1336. }
  1337. static void remove_one(struct pci_dev *pdev)
  1338. {
  1339. struct hfi1_devdata *dd = pci_get_drvdata(pdev);
  1340. /* close debugfs files before ib unregister */
  1341. hfi1_dbg_ibdev_exit(&dd->verbs_dev);
  1342. /* unregister from IB core */
  1343. hfi1_unregister_ib_device(dd);
  1344. /*
  1345. * Disable the IB link, disable interrupts on the device,
  1346. * clear dma engines, etc.
  1347. */
  1348. shutdown_device(dd);
  1349. stop_timers(dd);
  1350. /* wait until all of our (qsfp) queue_work() calls complete */
  1351. flush_workqueue(ib_wq);
  1352. hfi1_device_remove(dd);
  1353. postinit_cleanup(dd);
  1354. }
  1355. /**
  1356. * hfi1_create_rcvhdrq - create a receive header queue
  1357. * @dd: the hfi1_ib device
  1358. * @rcd: the context data
  1359. *
  1360. * This must be contiguous memory (from an i/o perspective), and must be
  1361. * DMA'able (which means for some systems, it will go through an IOMMU,
  1362. * or be forced into a low address range).
  1363. */
  1364. int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
  1365. {
  1366. unsigned amt;
  1367. u64 reg;
  1368. if (!rcd->rcvhdrq) {
  1369. dma_addr_t phys_hdrqtail;
  1370. gfp_t gfp_flags;
  1371. /*
  1372. * rcvhdrqentsize is in DWs, so we have to convert to bytes
  1373. * (* sizeof(u32)).
  1374. */
  1375. amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize *
  1376. sizeof(u32));
  1377. gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
  1378. GFP_USER : GFP_KERNEL;
  1379. rcd->rcvhdrq = dma_zalloc_coherent(
  1380. &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
  1381. gfp_flags | __GFP_COMP);
  1382. if (!rcd->rcvhdrq) {
  1383. dd_dev_err(dd,
  1384. "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
  1385. amt, rcd->ctxt);
  1386. goto bail;
  1387. }
  1388. if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) {
  1389. rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent(
  1390. &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
  1391. gfp_flags);
  1392. if (!rcd->rcvhdrtail_kvaddr)
  1393. goto bail_free;
  1394. rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
  1395. }
  1396. rcd->rcvhdrq_size = amt;
  1397. }
  1398. /*
  1399. * These values are per-context:
  1400. * RcvHdrCnt
  1401. * RcvHdrEntSize
  1402. * RcvHdrSize
  1403. */
  1404. reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT)
  1405. & RCV_HDR_CNT_CNT_MASK)
  1406. << RCV_HDR_CNT_CNT_SHIFT;
  1407. write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg);
  1408. reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize)
  1409. & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK)
  1410. << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
  1411. write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg);
  1412. reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK)
  1413. << RCV_HDR_SIZE_HDR_SIZE_SHIFT;
  1414. write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg);
  1415. /*
  1416. * Program dummy tail address for every receive context
  1417. * before enabling any receive context
  1418. */
  1419. write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR,
  1420. dd->rcvhdrtail_dummy_physaddr);
  1421. return 0;
  1422. bail_free:
  1423. dd_dev_err(dd,
  1424. "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
  1425. rcd->ctxt);
  1426. vfree(rcd->user_event_mask);
  1427. rcd->user_event_mask = NULL;
  1428. dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
  1429. rcd->rcvhdrq_phys);
  1430. rcd->rcvhdrq = NULL;
  1431. bail:
  1432. return -ENOMEM;
  1433. }
  1434. /**
  1435. * allocate eager buffers, both kernel and user contexts.
  1436. * @rcd: the context we are setting up.
  1437. *
  1438. * Allocate the eager TID buffers and program them into hip.
  1439. * They are no longer completely contiguous, we do multiple allocation
  1440. * calls. Otherwise we get the OOM code involved, by asking for too
  1441. * much per call, with disastrous results on some kernels.
  1442. */
  1443. int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
  1444. {
  1445. struct hfi1_devdata *dd = rcd->dd;
  1446. u32 max_entries, egrtop, alloced_bytes = 0, idx = 0;
  1447. gfp_t gfp_flags;
  1448. u16 order;
  1449. int ret = 0;
  1450. u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
  1451. /*
  1452. * GFP_USER, but without GFP_FS, so buffer cache can be
  1453. * coalesced (we hope); otherwise, even at order 4,
  1454. * heavy filesystem activity makes these fail, and we can
  1455. * use compound pages.
  1456. */
  1457. gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
  1458. /*
  1459. * The minimum size of the eager buffers is a groups of MTU-sized
  1460. * buffers.
  1461. * The global eager_buffer_size parameter is checked against the
  1462. * theoretical lower limit of the value. Here, we check against the
  1463. * MTU.
  1464. */
  1465. if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
  1466. rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
  1467. /*
  1468. * If using one-pkt-per-egr-buffer, lower the eager buffer
  1469. * size to the max MTU (page-aligned).
  1470. */
  1471. if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
  1472. rcd->egrbufs.rcvtid_size = round_mtu;
  1473. /*
  1474. * Eager buffers sizes of 1MB or less require smaller TID sizes
  1475. * to satisfy the "multiple of 8 RcvArray entries" requirement.
  1476. */
  1477. if (rcd->egrbufs.size <= (1 << 20))
  1478. rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
  1479. rounddown_pow_of_two(rcd->egrbufs.size / 8));
  1480. while (alloced_bytes < rcd->egrbufs.size &&
  1481. rcd->egrbufs.alloced < rcd->egrbufs.count) {
  1482. rcd->egrbufs.buffers[idx].addr =
  1483. dma_zalloc_coherent(&dd->pcidev->dev,
  1484. rcd->egrbufs.rcvtid_size,
  1485. &rcd->egrbufs.buffers[idx].phys,
  1486. gfp_flags);
  1487. if (rcd->egrbufs.buffers[idx].addr) {
  1488. rcd->egrbufs.buffers[idx].len =
  1489. rcd->egrbufs.rcvtid_size;
  1490. rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
  1491. rcd->egrbufs.buffers[idx].addr;
  1492. rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].phys =
  1493. rcd->egrbufs.buffers[idx].phys;
  1494. rcd->egrbufs.alloced++;
  1495. alloced_bytes += rcd->egrbufs.rcvtid_size;
  1496. idx++;
  1497. } else {
  1498. u32 new_size, i, j;
  1499. u64 offset = 0;
  1500. /*
  1501. * Fail the eager buffer allocation if:
  1502. * - we are already using the lowest acceptable size
  1503. * - we are using one-pkt-per-egr-buffer (this implies
  1504. * that we are accepting only one size)
  1505. */
  1506. if (rcd->egrbufs.rcvtid_size == round_mtu ||
  1507. !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
  1508. dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
  1509. rcd->ctxt);
  1510. goto bail_rcvegrbuf_phys;
  1511. }
  1512. new_size = rcd->egrbufs.rcvtid_size / 2;
  1513. /*
  1514. * If the first attempt to allocate memory failed, don't
  1515. * fail everything but continue with the next lower
  1516. * size.
  1517. */
  1518. if (idx == 0) {
  1519. rcd->egrbufs.rcvtid_size = new_size;
  1520. continue;
  1521. }
  1522. /*
  1523. * Re-partition already allocated buffers to a smaller
  1524. * size.
  1525. */
  1526. rcd->egrbufs.alloced = 0;
  1527. for (i = 0, j = 0, offset = 0; j < idx; i++) {
  1528. if (i >= rcd->egrbufs.count)
  1529. break;
  1530. rcd->egrbufs.rcvtids[i].phys =
  1531. rcd->egrbufs.buffers[j].phys + offset;
  1532. rcd->egrbufs.rcvtids[i].addr =
  1533. rcd->egrbufs.buffers[j].addr + offset;
  1534. rcd->egrbufs.alloced++;
  1535. if ((rcd->egrbufs.buffers[j].phys + offset +
  1536. new_size) ==
  1537. (rcd->egrbufs.buffers[j].phys +
  1538. rcd->egrbufs.buffers[j].len)) {
  1539. j++;
  1540. offset = 0;
  1541. } else {
  1542. offset += new_size;
  1543. }
  1544. }
  1545. rcd->egrbufs.rcvtid_size = new_size;
  1546. }
  1547. }
  1548. rcd->egrbufs.numbufs = idx;
  1549. rcd->egrbufs.size = alloced_bytes;
  1550. hfi1_cdbg(PROC,
  1551. "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
  1552. rcd->ctxt, rcd->egrbufs.alloced,
  1553. rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024);
  1554. /*
  1555. * Set the contexts rcv array head update threshold to the closest
  1556. * power of 2 (so we can use a mask instead of modulo) below half
  1557. * the allocated entries.
  1558. */
  1559. rcd->egrbufs.threshold =
  1560. rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
  1561. /*
  1562. * Compute the expected RcvArray entry base. This is done after
  1563. * allocating the eager buffers in order to maximize the
  1564. * expected RcvArray entries for the context.
  1565. */
  1566. max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
  1567. egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
  1568. rcd->expected_count = max_entries - egrtop;
  1569. if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
  1570. rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
  1571. rcd->expected_base = rcd->eager_base + egrtop;
  1572. hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
  1573. rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
  1574. rcd->eager_base, rcd->expected_base);
  1575. if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
  1576. hfi1_cdbg(PROC,
  1577. "ctxt%u: current Eager buffer size is invalid %u\n",
  1578. rcd->ctxt, rcd->egrbufs.rcvtid_size);
  1579. ret = -EINVAL;
  1580. goto bail;
  1581. }
  1582. for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
  1583. hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
  1584. rcd->egrbufs.rcvtids[idx].phys, order);
  1585. cond_resched();
  1586. }
  1587. goto bail;
  1588. bail_rcvegrbuf_phys:
  1589. for (idx = 0; idx < rcd->egrbufs.alloced &&
  1590. rcd->egrbufs.buffers[idx].addr;
  1591. idx++) {
  1592. dma_free_coherent(&dd->pcidev->dev,
  1593. rcd->egrbufs.buffers[idx].len,
  1594. rcd->egrbufs.buffers[idx].addr,
  1595. rcd->egrbufs.buffers[idx].phys);
  1596. rcd->egrbufs.buffers[idx].addr = NULL;
  1597. rcd->egrbufs.buffers[idx].phys = 0;
  1598. rcd->egrbufs.buffers[idx].len = 0;
  1599. }
  1600. bail:
  1601. return ret;
  1602. }