sun4i_dotclock.c 4.1 KB

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  1. /*
  2. * Copyright (C) 2016 Free Electrons
  3. * Copyright (C) 2016 NextThing Co
  4. *
  5. * Maxime Ripard <maxime.ripard@free-electrons.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. */
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include "sun4i_tcon.h"
  15. struct sun4i_dclk {
  16. struct clk_hw hw;
  17. struct regmap *regmap;
  18. };
  19. static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
  20. {
  21. return container_of(hw, struct sun4i_dclk, hw);
  22. }
  23. static void sun4i_dclk_disable(struct clk_hw *hw)
  24. {
  25. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  26. regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  27. BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
  28. }
  29. static int sun4i_dclk_enable(struct clk_hw *hw)
  30. {
  31. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  32. return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  33. BIT(SUN4I_TCON0_DCLK_GATE_BIT),
  34. BIT(SUN4I_TCON0_DCLK_GATE_BIT));
  35. }
  36. static int sun4i_dclk_is_enabled(struct clk_hw *hw)
  37. {
  38. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  39. u32 val;
  40. regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
  41. return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
  42. }
  43. static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
  44. unsigned long parent_rate)
  45. {
  46. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  47. u32 val;
  48. regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
  49. val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
  50. val &= SUN4I_TCON0_DCLK_DIV_WIDTH;
  51. if (!val)
  52. val = 1;
  53. return parent_rate / val;
  54. }
  55. static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
  56. unsigned long *parent_rate)
  57. {
  58. unsigned long best_parent = 0;
  59. u8 best_div = 1;
  60. int i;
  61. for (i = 6; i < 127; i++) {
  62. unsigned long ideal = rate * i;
  63. unsigned long rounded;
  64. rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
  65. ideal);
  66. if (rounded == ideal) {
  67. best_parent = rounded;
  68. best_div = i;
  69. goto out;
  70. }
  71. if ((rounded < ideal) && (rounded > best_parent)) {
  72. best_parent = rounded;
  73. best_div = i;
  74. }
  75. }
  76. out:
  77. *parent_rate = best_parent;
  78. return best_parent / best_div;
  79. }
  80. static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
  81. unsigned long parent_rate)
  82. {
  83. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  84. u8 div = parent_rate / rate;
  85. return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  86. GENMASK(6, 0), div);
  87. }
  88. static int sun4i_dclk_get_phase(struct clk_hw *hw)
  89. {
  90. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  91. u32 val;
  92. regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
  93. val >>= 28;
  94. val &= 3;
  95. return val * 120;
  96. }
  97. static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
  98. {
  99. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  100. regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
  101. GENMASK(29, 28),
  102. degrees / 120);
  103. return 0;
  104. }
  105. static const struct clk_ops sun4i_dclk_ops = {
  106. .disable = sun4i_dclk_disable,
  107. .enable = sun4i_dclk_enable,
  108. .is_enabled = sun4i_dclk_is_enabled,
  109. .recalc_rate = sun4i_dclk_recalc_rate,
  110. .round_rate = sun4i_dclk_round_rate,
  111. .set_rate = sun4i_dclk_set_rate,
  112. .get_phase = sun4i_dclk_get_phase,
  113. .set_phase = sun4i_dclk_set_phase,
  114. };
  115. int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
  116. {
  117. const char *clk_name, *parent_name;
  118. struct clk_init_data init;
  119. struct sun4i_dclk *dclk;
  120. int ret;
  121. parent_name = __clk_get_name(tcon->sclk0);
  122. ret = of_property_read_string_index(dev->of_node,
  123. "clock-output-names", 0,
  124. &clk_name);
  125. if (ret)
  126. return ret;
  127. dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
  128. if (!dclk)
  129. return -ENOMEM;
  130. init.name = clk_name;
  131. init.ops = &sun4i_dclk_ops;
  132. init.parent_names = &parent_name;
  133. init.num_parents = 1;
  134. init.flags = CLK_SET_RATE_PARENT;
  135. dclk->regmap = tcon->regs;
  136. dclk->hw.init = &init;
  137. tcon->dclk = clk_register(dev, &dclk->hw);
  138. if (IS_ERR(tcon->dclk))
  139. return PTR_ERR(tcon->dclk);
  140. return 0;
  141. }
  142. EXPORT_SYMBOL(sun4i_dclk_create);
  143. int sun4i_dclk_free(struct sun4i_tcon *tcon)
  144. {
  145. clk_unregister(tcon->dclk);
  146. return 0;
  147. }
  148. EXPORT_SYMBOL(sun4i_dclk_free);