hdmi5.c 18 KB

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  1. /*
  2. * HDMI driver for OMAP5
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. *
  6. * Authors:
  7. * Yong Zhi
  8. * Mythri pk
  9. * Archit Taneja <archit@ti.com>
  10. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License version 2 as published by
  14. * the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program. If not, see <http://www.gnu.org/licenses/>.
  23. */
  24. #define DSS_SUBSYS_NAME "HDMI"
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/err.h>
  28. #include <linux/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/string.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/clk.h>
  36. #include <linux/gpio.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/component.h>
  39. #include <linux/of.h>
  40. #include <sound/omap-hdmi-audio.h>
  41. #include "omapdss.h"
  42. #include "hdmi5_core.h"
  43. #include "dss.h"
  44. #include "dss_features.h"
  45. static struct omap_hdmi hdmi;
  46. static int hdmi_runtime_get(void)
  47. {
  48. int r;
  49. DSSDBG("hdmi_runtime_get\n");
  50. r = pm_runtime_get_sync(&hdmi.pdev->dev);
  51. WARN_ON(r < 0);
  52. if (r < 0)
  53. return r;
  54. return 0;
  55. }
  56. static void hdmi_runtime_put(void)
  57. {
  58. int r;
  59. DSSDBG("hdmi_runtime_put\n");
  60. r = pm_runtime_put_sync(&hdmi.pdev->dev);
  61. WARN_ON(r < 0 && r != -ENOSYS);
  62. }
  63. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  64. {
  65. struct hdmi_wp_data *wp = data;
  66. u32 irqstatus;
  67. irqstatus = hdmi_wp_get_irqstatus(wp);
  68. hdmi_wp_set_irqstatus(wp, irqstatus);
  69. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  70. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  71. u32 v;
  72. /*
  73. * If we get both connect and disconnect interrupts at the same
  74. * time, turn off the PHY, clear interrupts, and restart, which
  75. * raises connect interrupt if a cable is connected, or nothing
  76. * if cable is not connected.
  77. */
  78. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  79. /*
  80. * We always get bogus CONNECT & DISCONNECT interrupts when
  81. * setting the PHY to LDOON. To ignore those, we force the RXDET
  82. * line to 0 until the PHY power state has been changed.
  83. */
  84. v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  85. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  86. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  87. hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  88. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  89. HDMI_IRQ_LINK_DISCONNECT);
  90. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  91. REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  92. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  93. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  94. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  95. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  96. }
  97. return IRQ_HANDLED;
  98. }
  99. static int hdmi_init_regulator(void)
  100. {
  101. struct regulator *reg;
  102. if (hdmi.vdda_reg != NULL)
  103. return 0;
  104. reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
  105. if (IS_ERR(reg)) {
  106. DSSERR("can't get VDDA regulator\n");
  107. return PTR_ERR(reg);
  108. }
  109. hdmi.vdda_reg = reg;
  110. return 0;
  111. }
  112. static int hdmi_power_on_core(struct omap_dss_device *dssdev)
  113. {
  114. int r;
  115. r = regulator_enable(hdmi.vdda_reg);
  116. if (r)
  117. return r;
  118. r = hdmi_runtime_get();
  119. if (r)
  120. goto err_runtime_get;
  121. /* Make selection of HDMI in DSS */
  122. dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
  123. hdmi.core_enabled = true;
  124. return 0;
  125. err_runtime_get:
  126. regulator_disable(hdmi.vdda_reg);
  127. return r;
  128. }
  129. static void hdmi_power_off_core(struct omap_dss_device *dssdev)
  130. {
  131. hdmi.core_enabled = false;
  132. hdmi_runtime_put();
  133. regulator_disable(hdmi.vdda_reg);
  134. }
  135. static int hdmi_power_on_full(struct omap_dss_device *dssdev)
  136. {
  137. int r;
  138. struct omap_video_timings *p;
  139. enum omap_channel channel = dssdev->dispc_channel;
  140. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  141. unsigned pc;
  142. r = hdmi_power_on_core(dssdev);
  143. if (r)
  144. return r;
  145. p = &hdmi.cfg.timings;
  146. DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
  147. pc = p->pixelclock;
  148. if (p->double_pixel)
  149. pc *= 2;
  150. /* DSS_HDMI_TCLK is bitclk / 10 */
  151. pc *= 10;
  152. dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin),
  153. pc, &hdmi_cinfo);
  154. /* disable and clear irqs */
  155. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  156. hdmi_wp_set_irqstatus(&hdmi.wp,
  157. hdmi_wp_get_irqstatus(&hdmi.wp));
  158. r = dss_pll_enable(&hdmi.pll.pll);
  159. if (r) {
  160. DSSERR("Failed to enable PLL\n");
  161. goto err_pll_enable;
  162. }
  163. r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
  164. if (r) {
  165. DSSERR("Failed to configure PLL\n");
  166. goto err_pll_cfg;
  167. }
  168. r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
  169. hdmi_cinfo.clkout[0]);
  170. if (r) {
  171. DSSDBG("Failed to start PHY\n");
  172. goto err_phy_cfg;
  173. }
  174. r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
  175. if (r)
  176. goto err_phy_pwr;
  177. hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
  178. /* tv size */
  179. dss_mgr_set_timings(channel, p);
  180. r = dss_mgr_enable(channel);
  181. if (r)
  182. goto err_mgr_enable;
  183. r = hdmi_wp_video_start(&hdmi.wp);
  184. if (r)
  185. goto err_vid_enable;
  186. hdmi_wp_set_irqenable(&hdmi.wp,
  187. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  188. return 0;
  189. err_vid_enable:
  190. dss_mgr_disable(channel);
  191. err_mgr_enable:
  192. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  193. err_phy_pwr:
  194. err_phy_cfg:
  195. err_pll_cfg:
  196. dss_pll_disable(&hdmi.pll.pll);
  197. err_pll_enable:
  198. hdmi_power_off_core(dssdev);
  199. return -EIO;
  200. }
  201. static void hdmi_power_off_full(struct omap_dss_device *dssdev)
  202. {
  203. enum omap_channel channel = dssdev->dispc_channel;
  204. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  205. hdmi_wp_video_stop(&hdmi.wp);
  206. dss_mgr_disable(channel);
  207. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  208. dss_pll_disable(&hdmi.pll.pll);
  209. hdmi_power_off_core(dssdev);
  210. }
  211. static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
  212. struct omap_video_timings *timings)
  213. {
  214. if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings))
  215. return -EINVAL;
  216. return 0;
  217. }
  218. static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
  219. struct omap_video_timings *timings)
  220. {
  221. mutex_lock(&hdmi.lock);
  222. hdmi.cfg.timings = *timings;
  223. dispc_set_tv_pclk(timings->pixelclock);
  224. mutex_unlock(&hdmi.lock);
  225. }
  226. static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
  227. struct omap_video_timings *timings)
  228. {
  229. *timings = hdmi.cfg.timings;
  230. }
  231. static void hdmi_dump_regs(struct seq_file *s)
  232. {
  233. mutex_lock(&hdmi.lock);
  234. if (hdmi_runtime_get()) {
  235. mutex_unlock(&hdmi.lock);
  236. return;
  237. }
  238. hdmi_wp_dump(&hdmi.wp, s);
  239. hdmi_pll_dump(&hdmi.pll, s);
  240. hdmi_phy_dump(&hdmi.phy, s);
  241. hdmi5_core_dump(&hdmi.core, s);
  242. hdmi_runtime_put();
  243. mutex_unlock(&hdmi.lock);
  244. }
  245. static int read_edid(u8 *buf, int len)
  246. {
  247. int r;
  248. int idlemode;
  249. mutex_lock(&hdmi.lock);
  250. r = hdmi_runtime_get();
  251. BUG_ON(r);
  252. idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  253. /* No-idle mode */
  254. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  255. r = hdmi5_read_edid(&hdmi.core, buf, len);
  256. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  257. hdmi_runtime_put();
  258. mutex_unlock(&hdmi.lock);
  259. return r;
  260. }
  261. static void hdmi_start_audio_stream(struct omap_hdmi *hd)
  262. {
  263. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  264. hdmi_wp_audio_enable(&hd->wp, true);
  265. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  266. }
  267. static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
  268. {
  269. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  270. hdmi_wp_audio_enable(&hd->wp, false);
  271. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  272. }
  273. static int hdmi_display_enable(struct omap_dss_device *dssdev)
  274. {
  275. struct omap_dss_device *out = &hdmi.output;
  276. unsigned long flags;
  277. int r = 0;
  278. DSSDBG("ENTER hdmi_display_enable\n");
  279. mutex_lock(&hdmi.lock);
  280. if (!out->dispc_channel_connected) {
  281. DSSERR("failed to enable display: no output/manager\n");
  282. r = -ENODEV;
  283. goto err0;
  284. }
  285. r = hdmi_power_on_full(dssdev);
  286. if (r) {
  287. DSSERR("failed to power on device\n");
  288. goto err0;
  289. }
  290. if (hdmi.audio_configured) {
  291. r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
  292. hdmi.cfg.timings.pixelclock);
  293. if (r) {
  294. DSSERR("Error restoring audio configuration: %d", r);
  295. hdmi.audio_abort_cb(&hdmi.pdev->dev);
  296. hdmi.audio_configured = false;
  297. }
  298. }
  299. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  300. if (hdmi.audio_configured && hdmi.audio_playing)
  301. hdmi_start_audio_stream(&hdmi);
  302. hdmi.display_enabled = true;
  303. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  304. mutex_unlock(&hdmi.lock);
  305. return 0;
  306. err0:
  307. mutex_unlock(&hdmi.lock);
  308. return r;
  309. }
  310. static void hdmi_display_disable(struct omap_dss_device *dssdev)
  311. {
  312. unsigned long flags;
  313. DSSDBG("Enter hdmi_display_disable\n");
  314. mutex_lock(&hdmi.lock);
  315. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  316. hdmi_stop_audio_stream(&hdmi);
  317. hdmi.display_enabled = false;
  318. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  319. hdmi_power_off_full(dssdev);
  320. mutex_unlock(&hdmi.lock);
  321. }
  322. static int hdmi_core_enable(struct omap_dss_device *dssdev)
  323. {
  324. int r = 0;
  325. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  326. mutex_lock(&hdmi.lock);
  327. r = hdmi_power_on_core(dssdev);
  328. if (r) {
  329. DSSERR("failed to power on device\n");
  330. goto err0;
  331. }
  332. mutex_unlock(&hdmi.lock);
  333. return 0;
  334. err0:
  335. mutex_unlock(&hdmi.lock);
  336. return r;
  337. }
  338. static void hdmi_core_disable(struct omap_dss_device *dssdev)
  339. {
  340. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  341. mutex_lock(&hdmi.lock);
  342. hdmi_power_off_core(dssdev);
  343. mutex_unlock(&hdmi.lock);
  344. }
  345. static int hdmi_connect(struct omap_dss_device *dssdev,
  346. struct omap_dss_device *dst)
  347. {
  348. enum omap_channel channel = dssdev->dispc_channel;
  349. int r;
  350. r = hdmi_init_regulator();
  351. if (r)
  352. return r;
  353. r = dss_mgr_connect(channel, dssdev);
  354. if (r)
  355. return r;
  356. r = omapdss_output_set_device(dssdev, dst);
  357. if (r) {
  358. DSSERR("failed to connect output to new device: %s\n",
  359. dst->name);
  360. dss_mgr_disconnect(channel, dssdev);
  361. return r;
  362. }
  363. return 0;
  364. }
  365. static void hdmi_disconnect(struct omap_dss_device *dssdev,
  366. struct omap_dss_device *dst)
  367. {
  368. enum omap_channel channel = dssdev->dispc_channel;
  369. WARN_ON(dst != dssdev->dst);
  370. if (dst != dssdev->dst)
  371. return;
  372. omapdss_output_unset_device(dssdev);
  373. dss_mgr_disconnect(channel, dssdev);
  374. }
  375. static int hdmi_read_edid(struct omap_dss_device *dssdev,
  376. u8 *edid, int len)
  377. {
  378. bool need_enable;
  379. int r;
  380. need_enable = hdmi.core_enabled == false;
  381. if (need_enable) {
  382. r = hdmi_core_enable(dssdev);
  383. if (r)
  384. return r;
  385. }
  386. r = read_edid(edid, len);
  387. if (need_enable)
  388. hdmi_core_disable(dssdev);
  389. return r;
  390. }
  391. static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
  392. const struct hdmi_avi_infoframe *avi)
  393. {
  394. hdmi.cfg.infoframe = *avi;
  395. return 0;
  396. }
  397. static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
  398. bool hdmi_mode)
  399. {
  400. hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
  401. return 0;
  402. }
  403. static const struct omapdss_hdmi_ops hdmi_ops = {
  404. .connect = hdmi_connect,
  405. .disconnect = hdmi_disconnect,
  406. .enable = hdmi_display_enable,
  407. .disable = hdmi_display_disable,
  408. .check_timings = hdmi_display_check_timing,
  409. .set_timings = hdmi_display_set_timing,
  410. .get_timings = hdmi_display_get_timings,
  411. .read_edid = hdmi_read_edid,
  412. .set_infoframe = hdmi_set_infoframe,
  413. .set_hdmi_mode = hdmi_set_hdmi_mode,
  414. };
  415. static void hdmi_init_output(struct platform_device *pdev)
  416. {
  417. struct omap_dss_device *out = &hdmi.output;
  418. out->dev = &pdev->dev;
  419. out->id = OMAP_DSS_OUTPUT_HDMI;
  420. out->output_type = OMAP_DISPLAY_TYPE_HDMI;
  421. out->name = "hdmi.0";
  422. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  423. out->ops.hdmi = &hdmi_ops;
  424. out->owner = THIS_MODULE;
  425. omapdss_register_output(out);
  426. }
  427. static void hdmi_uninit_output(struct platform_device *pdev)
  428. {
  429. struct omap_dss_device *out = &hdmi.output;
  430. omapdss_unregister_output(out);
  431. }
  432. static int hdmi_probe_of(struct platform_device *pdev)
  433. {
  434. struct device_node *node = pdev->dev.of_node;
  435. struct device_node *ep;
  436. int r;
  437. ep = omapdss_of_get_first_endpoint(node);
  438. if (!ep)
  439. return 0;
  440. r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
  441. if (r)
  442. goto err;
  443. of_node_put(ep);
  444. return 0;
  445. err:
  446. of_node_put(ep);
  447. return r;
  448. }
  449. /* Audio callbacks */
  450. static int hdmi_audio_startup(struct device *dev,
  451. void (*abort_cb)(struct device *dev))
  452. {
  453. struct omap_hdmi *hd = dev_get_drvdata(dev);
  454. int ret = 0;
  455. mutex_lock(&hd->lock);
  456. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  457. ret = -EPERM;
  458. goto out;
  459. }
  460. hd->audio_abort_cb = abort_cb;
  461. out:
  462. mutex_unlock(&hd->lock);
  463. return ret;
  464. }
  465. static int hdmi_audio_shutdown(struct device *dev)
  466. {
  467. struct omap_hdmi *hd = dev_get_drvdata(dev);
  468. mutex_lock(&hd->lock);
  469. hd->audio_abort_cb = NULL;
  470. hd->audio_configured = false;
  471. hd->audio_playing = false;
  472. mutex_unlock(&hd->lock);
  473. return 0;
  474. }
  475. static int hdmi_audio_start(struct device *dev)
  476. {
  477. struct omap_hdmi *hd = dev_get_drvdata(dev);
  478. unsigned long flags;
  479. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  480. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  481. if (hd->display_enabled)
  482. hdmi_start_audio_stream(hd);
  483. hd->audio_playing = true;
  484. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  485. return 0;
  486. }
  487. static void hdmi_audio_stop(struct device *dev)
  488. {
  489. struct omap_hdmi *hd = dev_get_drvdata(dev);
  490. unsigned long flags;
  491. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  492. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  493. if (hd->display_enabled)
  494. hdmi_stop_audio_stream(hd);
  495. hd->audio_playing = false;
  496. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  497. }
  498. static int hdmi_audio_config(struct device *dev,
  499. struct omap_dss_audio *dss_audio)
  500. {
  501. struct omap_hdmi *hd = dev_get_drvdata(dev);
  502. int ret;
  503. mutex_lock(&hd->lock);
  504. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  505. ret = -EPERM;
  506. goto out;
  507. }
  508. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  509. hd->cfg.timings.pixelclock);
  510. if (!ret) {
  511. hd->audio_configured = true;
  512. hd->audio_config = *dss_audio;
  513. }
  514. out:
  515. mutex_unlock(&hd->lock);
  516. return ret;
  517. }
  518. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  519. .audio_startup = hdmi_audio_startup,
  520. .audio_shutdown = hdmi_audio_shutdown,
  521. .audio_start = hdmi_audio_start,
  522. .audio_stop = hdmi_audio_stop,
  523. .audio_config = hdmi_audio_config,
  524. };
  525. static int hdmi_audio_register(struct device *dev)
  526. {
  527. struct omap_hdmi_audio_pdata pdata = {
  528. .dev = dev,
  529. .dss_version = omapdss_get_version(),
  530. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
  531. .ops = &hdmi_audio_ops,
  532. };
  533. hdmi.audio_pdev = platform_device_register_data(
  534. dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  535. &pdata, sizeof(pdata));
  536. if (IS_ERR(hdmi.audio_pdev))
  537. return PTR_ERR(hdmi.audio_pdev);
  538. hdmi_runtime_get();
  539. hdmi.wp_idlemode =
  540. REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  541. hdmi_runtime_put();
  542. return 0;
  543. }
  544. /* HDMI HW IP initialisation */
  545. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  546. {
  547. struct platform_device *pdev = to_platform_device(dev);
  548. int r;
  549. int irq;
  550. hdmi.pdev = pdev;
  551. dev_set_drvdata(&pdev->dev, &hdmi);
  552. mutex_init(&hdmi.lock);
  553. spin_lock_init(&hdmi.audio_playing_lock);
  554. if (pdev->dev.of_node) {
  555. r = hdmi_probe_of(pdev);
  556. if (r)
  557. return r;
  558. }
  559. r = hdmi_wp_init(pdev, &hdmi.wp);
  560. if (r)
  561. return r;
  562. r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
  563. if (r)
  564. return r;
  565. r = hdmi_phy_init(pdev, &hdmi.phy);
  566. if (r)
  567. goto err;
  568. r = hdmi5_core_init(pdev, &hdmi.core);
  569. if (r)
  570. goto err;
  571. irq = platform_get_irq(pdev, 0);
  572. if (irq < 0) {
  573. DSSERR("platform_get_irq failed\n");
  574. r = -ENODEV;
  575. goto err;
  576. }
  577. r = devm_request_threaded_irq(&pdev->dev, irq,
  578. NULL, hdmi_irq_handler,
  579. IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
  580. if (r) {
  581. DSSERR("HDMI IRQ request failed\n");
  582. goto err;
  583. }
  584. pm_runtime_enable(&pdev->dev);
  585. hdmi_init_output(pdev);
  586. r = hdmi_audio_register(&pdev->dev);
  587. if (r) {
  588. DSSERR("Registering HDMI audio failed %d\n", r);
  589. hdmi_uninit_output(pdev);
  590. pm_runtime_disable(&pdev->dev);
  591. return r;
  592. }
  593. dss_debugfs_create_file("hdmi", hdmi_dump_regs);
  594. return 0;
  595. err:
  596. hdmi_pll_uninit(&hdmi.pll);
  597. return r;
  598. }
  599. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  600. {
  601. struct platform_device *pdev = to_platform_device(dev);
  602. if (hdmi.audio_pdev)
  603. platform_device_unregister(hdmi.audio_pdev);
  604. hdmi_uninit_output(pdev);
  605. hdmi_pll_uninit(&hdmi.pll);
  606. pm_runtime_disable(&pdev->dev);
  607. }
  608. static const struct component_ops hdmi5_component_ops = {
  609. .bind = hdmi5_bind,
  610. .unbind = hdmi5_unbind,
  611. };
  612. static int hdmi5_probe(struct platform_device *pdev)
  613. {
  614. return component_add(&pdev->dev, &hdmi5_component_ops);
  615. }
  616. static int hdmi5_remove(struct platform_device *pdev)
  617. {
  618. component_del(&pdev->dev, &hdmi5_component_ops);
  619. return 0;
  620. }
  621. static int hdmi_runtime_suspend(struct device *dev)
  622. {
  623. dispc_runtime_put();
  624. return 0;
  625. }
  626. static int hdmi_runtime_resume(struct device *dev)
  627. {
  628. int r;
  629. r = dispc_runtime_get();
  630. if (r < 0)
  631. return r;
  632. return 0;
  633. }
  634. static const struct dev_pm_ops hdmi_pm_ops = {
  635. .runtime_suspend = hdmi_runtime_suspend,
  636. .runtime_resume = hdmi_runtime_resume,
  637. };
  638. static const struct of_device_id hdmi_of_match[] = {
  639. { .compatible = "ti,omap5-hdmi", },
  640. { .compatible = "ti,dra7-hdmi", },
  641. {},
  642. };
  643. static struct platform_driver omapdss_hdmihw_driver = {
  644. .probe = hdmi5_probe,
  645. .remove = hdmi5_remove,
  646. .driver = {
  647. .name = "omapdss_hdmi5",
  648. .pm = &hdmi_pm_ops,
  649. .of_match_table = hdmi_of_match,
  650. .suppress_bind_attrs = true,
  651. },
  652. };
  653. int __init hdmi5_init_platform_driver(void)
  654. {
  655. return platform_driver_register(&omapdss_hdmihw_driver);
  656. }
  657. void hdmi5_uninit_platform_driver(void)
  658. {
  659. platform_driver_unregister(&omapdss_hdmihw_driver);
  660. }