mtk_mt8173_hdmi_phy.c 15 KB

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  1. /*
  2. * Copyright (c) 2014 MediaTek Inc.
  3. * Author: Jie Qiu <jie.qiu@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/delay.h>
  17. #include <linux/io.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/module.h>
  20. #include <linux/phy/phy.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/types.h>
  23. #define HDMI_CON0 0x00
  24. #define RG_HDMITX_PLL_EN BIT(31)
  25. #define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
  26. #define PLL_FBKDIV_SHIFT 24
  27. #define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
  28. #define PLL_FBKSEL_SHIFT 22
  29. #define RG_HDMITX_PLL_PREDIV (0x3 << 20)
  30. #define PREDIV_SHIFT 20
  31. #define RG_HDMITX_PLL_POSDIV (0x3 << 18)
  32. #define POSDIV_SHIFT 18
  33. #define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
  34. #define RG_HDMITX_PLL_IR (0xf << 12)
  35. #define PLL_IR_SHIFT 12
  36. #define RG_HDMITX_PLL_IC (0xf << 8)
  37. #define PLL_IC_SHIFT 8
  38. #define RG_HDMITX_PLL_BP (0xf << 4)
  39. #define PLL_BP_SHIFT 4
  40. #define RG_HDMITX_PLL_BR (0x3 << 2)
  41. #define PLL_BR_SHIFT 2
  42. #define RG_HDMITX_PLL_BC (0x3 << 0)
  43. #define PLL_BC_SHIFT 0
  44. #define HDMI_CON1 0x04
  45. #define RG_HDMITX_PLL_DIVEN (0x7 << 29)
  46. #define PLL_DIVEN_SHIFT 29
  47. #define RG_HDMITX_PLL_AUTOK_EN BIT(28)
  48. #define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
  49. #define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
  50. #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
  51. #define RG_HDMITX_PLL_BAND (0x3f << 16)
  52. #define RG_HDMITX_PLL_REF_SEL BIT(15)
  53. #define RG_HDMITX_PLL_BIAS_EN BIT(14)
  54. #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
  55. #define RG_HDMITX_PLL_TXDIV_EN BIT(12)
  56. #define RG_HDMITX_PLL_TXDIV (0x3 << 10)
  57. #define PLL_TXDIV_SHIFT 10
  58. #define RG_HDMITX_PLL_LVROD_EN BIT(9)
  59. #define RG_HDMITX_PLL_MONVC_EN BIT(8)
  60. #define RG_HDMITX_PLL_MONCK_EN BIT(7)
  61. #define RG_HDMITX_PLL_MONREF_EN BIT(6)
  62. #define RG_HDMITX_PLL_TST_EN BIT(5)
  63. #define RG_HDMITX_PLL_TST_CK_EN BIT(4)
  64. #define RG_HDMITX_PLL_TST_SEL (0xf << 0)
  65. #define HDMI_CON2 0x08
  66. #define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
  67. #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
  68. #define RG_HDMITX_EN_TX_CKLDO BIT(0)
  69. #define HDMI_CON3 0x0c
  70. #define RG_HDMITX_SER_EN (0xf << 28)
  71. #define RG_HDMITX_PRD_EN (0xf << 24)
  72. #define RG_HDMITX_PRD_IMP_EN (0xf << 20)
  73. #define RG_HDMITX_DRV_EN (0xf << 16)
  74. #define RG_HDMITX_DRV_IMP_EN (0xf << 12)
  75. #define DRV_IMP_EN_SHIFT 12
  76. #define RG_HDMITX_MHLCK_FORCE BIT(10)
  77. #define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
  78. #define RG_HDMITX_MHLCK_EN BIT(8)
  79. #define RG_HDMITX_SER_DIN_SEL (0xf << 4)
  80. #define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
  81. #define RG_HDMITX_SER_BIST_TOG BIT(2)
  82. #define RG_HDMITX_SER_DIN_TOG BIT(1)
  83. #define RG_HDMITX_SER_CLKDIG_INV BIT(0)
  84. #define HDMI_CON4 0x10
  85. #define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
  86. #define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
  87. #define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
  88. #define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
  89. #define PRD_IBIAS_CLK_SHIFT 24
  90. #define PRD_IBIAS_D2_SHIFT 16
  91. #define PRD_IBIAS_D1_SHIFT 8
  92. #define PRD_IBIAS_D0_SHIFT 0
  93. #define HDMI_CON5 0x14
  94. #define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
  95. #define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
  96. #define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
  97. #define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
  98. #define DRV_IBIAS_CLK_SHIFT 24
  99. #define DRV_IBIAS_D2_SHIFT 16
  100. #define DRV_IBIAS_D1_SHIFT 8
  101. #define DRV_IBIAS_D0_SHIFT 0
  102. #define HDMI_CON6 0x18
  103. #define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
  104. #define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
  105. #define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
  106. #define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
  107. #define DRV_IMP_CLK_SHIFT 24
  108. #define DRV_IMP_D2_SHIFT 16
  109. #define DRV_IMP_D1_SHIFT 8
  110. #define DRV_IMP_D0_SHIFT 0
  111. #define HDMI_CON7 0x1c
  112. #define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
  113. #define RG_HDMITX_SER_DIN (0x3ff << 16)
  114. #define RG_HDMITX_CHLDC_TST (0xf << 12)
  115. #define RG_HDMITX_CHLCK_TST (0xf << 8)
  116. #define RG_HDMITX_RESERVE (0xff << 0)
  117. #define HDMI_CON8 0x20
  118. #define RGS_HDMITX_2T1_LEV (0xf << 16)
  119. #define RGS_HDMITX_2T1_EDG (0xf << 12)
  120. #define RGS_HDMITX_5T1_LEV (0xf << 8)
  121. #define RGS_HDMITX_5T1_EDG (0xf << 4)
  122. #define RGS_HDMITX_PLUG_TST BIT(0)
  123. struct mtk_hdmi_phy {
  124. void __iomem *regs;
  125. struct device *dev;
  126. struct clk *pll;
  127. struct clk_hw pll_hw;
  128. unsigned long pll_rate;
  129. u8 drv_imp_clk;
  130. u8 drv_imp_d2;
  131. u8 drv_imp_d1;
  132. u8 drv_imp_d0;
  133. u32 ibias;
  134. u32 ibias_up;
  135. };
  136. static const u8 PREDIV[3][4] = {
  137. {0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
  138. {0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
  139. {0x1, 0x1, 0x1, 0x1} /* 148Mhz */
  140. };
  141. static const u8 TXDIV[3][4] = {
  142. {0x3, 0x3, 0x3, 0x2}, /* 27Mhz */
  143. {0x2, 0x1, 0x1, 0x1}, /* 74Mhz */
  144. {0x1, 0x0, 0x0, 0x0} /* 148Mhz */
  145. };
  146. static const u8 FBKSEL[3][4] = {
  147. {0x1, 0x1, 0x1, 0x1}, /* 27Mhz */
  148. {0x1, 0x0, 0x1, 0x1}, /* 74Mhz */
  149. {0x1, 0x0, 0x1, 0x1} /* 148Mhz */
  150. };
  151. static const u8 FBKDIV[3][4] = {
  152. {19, 24, 29, 19}, /* 27Mhz */
  153. {19, 24, 14, 19}, /* 74Mhz */
  154. {19, 24, 14, 19} /* 148Mhz */
  155. };
  156. static const u8 DIVEN[3][4] = {
  157. {0x2, 0x1, 0x1, 0x2}, /* 27Mhz */
  158. {0x2, 0x2, 0x2, 0x2}, /* 74Mhz */
  159. {0x2, 0x2, 0x2, 0x2} /* 148Mhz */
  160. };
  161. static const u8 HTPLLBP[3][4] = {
  162. {0xc, 0xc, 0x8, 0xc}, /* 27Mhz */
  163. {0xc, 0xf, 0xf, 0xc}, /* 74Mhz */
  164. {0xc, 0xf, 0xf, 0xc} /* 148Mhz */
  165. };
  166. static const u8 HTPLLBC[3][4] = {
  167. {0x2, 0x3, 0x3, 0x2}, /* 27Mhz */
  168. {0x2, 0x3, 0x3, 0x2}, /* 74Mhz */
  169. {0x2, 0x3, 0x3, 0x2} /* 148Mhz */
  170. };
  171. static const u8 HTPLLBR[3][4] = {
  172. {0x1, 0x1, 0x0, 0x1}, /* 27Mhz */
  173. {0x1, 0x2, 0x2, 0x1}, /* 74Mhz */
  174. {0x1, 0x2, 0x2, 0x1} /* 148Mhz */
  175. };
  176. static void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  177. u32 bits)
  178. {
  179. void __iomem *reg = hdmi_phy->regs + offset;
  180. u32 tmp;
  181. tmp = readl(reg);
  182. tmp &= ~bits;
  183. writel(tmp, reg);
  184. }
  185. static void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  186. u32 bits)
  187. {
  188. void __iomem *reg = hdmi_phy->regs + offset;
  189. u32 tmp;
  190. tmp = readl(reg);
  191. tmp |= bits;
  192. writel(tmp, reg);
  193. }
  194. static void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
  195. u32 val, u32 mask)
  196. {
  197. void __iomem *reg = hdmi_phy->regs + offset;
  198. u32 tmp;
  199. tmp = readl(reg);
  200. tmp = (tmp & ~mask) | (val & mask);
  201. writel(tmp, reg);
  202. }
  203. static inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
  204. {
  205. return container_of(hw, struct mtk_hdmi_phy, pll_hw);
  206. }
  207. static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
  208. {
  209. struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  210. dev_dbg(hdmi_phy->dev, "%s\n", __func__);
  211. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
  212. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
  213. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
  214. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
  215. usleep_range(100, 150);
  216. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
  217. usleep_range(100, 150);
  218. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
  219. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
  220. return 0;
  221. }
  222. static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
  223. {
  224. struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  225. dev_dbg(hdmi_phy->dev, "%s\n", __func__);
  226. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
  227. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
  228. usleep_range(100, 150);
  229. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
  230. usleep_range(100, 150);
  231. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
  232. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
  233. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
  234. usleep_range(100, 150);
  235. }
  236. static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  237. unsigned long parent_rate)
  238. {
  239. struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  240. unsigned int pre_div;
  241. unsigned int div;
  242. dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
  243. rate, parent_rate);
  244. if (rate <= 27000000) {
  245. pre_div = 0;
  246. div = 3;
  247. } else if (rate <= 74250000) {
  248. pre_div = 1;
  249. div = 2;
  250. } else {
  251. pre_div = 1;
  252. div = 1;
  253. }
  254. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
  255. (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
  256. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
  257. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
  258. (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
  259. RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
  260. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
  261. (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
  262. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
  263. (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
  264. RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
  265. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
  266. (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
  267. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
  268. (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
  269. (0x1 << PLL_BR_SHIFT),
  270. RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
  271. RG_HDMITX_PLL_BR);
  272. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
  273. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
  274. (0x3 << PRD_IBIAS_CLK_SHIFT) |
  275. (0x3 << PRD_IBIAS_D2_SHIFT) |
  276. (0x3 << PRD_IBIAS_D1_SHIFT) |
  277. (0x3 << PRD_IBIAS_D0_SHIFT),
  278. RG_HDMITX_PRD_IBIAS_CLK |
  279. RG_HDMITX_PRD_IBIAS_D2 |
  280. RG_HDMITX_PRD_IBIAS_D1 |
  281. RG_HDMITX_PRD_IBIAS_D0);
  282. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
  283. (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
  284. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
  285. (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
  286. (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
  287. (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
  288. (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
  289. RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
  290. RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
  291. mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
  292. (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
  293. (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
  294. (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
  295. (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
  296. RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
  297. RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
  298. return 0;
  299. }
  300. static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  301. unsigned long *parent_rate)
  302. {
  303. struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  304. hdmi_phy->pll_rate = rate;
  305. if (rate <= 74250000)
  306. *parent_rate = rate;
  307. else
  308. *parent_rate = rate / 2;
  309. return rate;
  310. }
  311. static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
  312. unsigned long parent_rate)
  313. {
  314. struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
  315. return hdmi_phy->pll_rate;
  316. }
  317. static const struct clk_ops mtk_hdmi_pll_ops = {
  318. .prepare = mtk_hdmi_pll_prepare,
  319. .unprepare = mtk_hdmi_pll_unprepare,
  320. .set_rate = mtk_hdmi_pll_set_rate,
  321. .round_rate = mtk_hdmi_pll_round_rate,
  322. .recalc_rate = mtk_hdmi_pll_recalc_rate,
  323. };
  324. static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
  325. {
  326. mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
  327. RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
  328. RG_HDMITX_DRV_EN);
  329. usleep_range(100, 150);
  330. }
  331. static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
  332. {
  333. mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
  334. RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
  335. RG_HDMITX_SER_EN);
  336. }
  337. static int mtk_hdmi_phy_power_on(struct phy *phy)
  338. {
  339. struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
  340. int ret;
  341. ret = clk_prepare_enable(hdmi_phy->pll);
  342. if (ret < 0)
  343. return ret;
  344. mtk_hdmi_phy_enable_tmds(hdmi_phy);
  345. return 0;
  346. }
  347. static int mtk_hdmi_phy_power_off(struct phy *phy)
  348. {
  349. struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
  350. mtk_hdmi_phy_disable_tmds(hdmi_phy);
  351. clk_disable_unprepare(hdmi_phy->pll);
  352. return 0;
  353. }
  354. static const struct phy_ops mtk_hdmi_phy_ops = {
  355. .power_on = mtk_hdmi_phy_power_on,
  356. .power_off = mtk_hdmi_phy_power_off,
  357. .owner = THIS_MODULE,
  358. };
  359. static int mtk_hdmi_phy_probe(struct platform_device *pdev)
  360. {
  361. struct device *dev = &pdev->dev;
  362. struct mtk_hdmi_phy *hdmi_phy;
  363. struct resource *mem;
  364. struct clk *ref_clk;
  365. const char *ref_clk_name;
  366. struct clk_init_data clk_init = {
  367. .ops = &mtk_hdmi_pll_ops,
  368. .num_parents = 1,
  369. .parent_names = (const char * const *)&ref_clk_name,
  370. .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
  371. };
  372. struct phy *phy;
  373. struct phy_provider *phy_provider;
  374. int ret;
  375. hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
  376. if (!hdmi_phy)
  377. return -ENOMEM;
  378. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  379. hdmi_phy->regs = devm_ioremap_resource(dev, mem);
  380. if (IS_ERR(hdmi_phy->regs)) {
  381. ret = PTR_ERR(hdmi_phy->regs);
  382. dev_err(dev, "Failed to get memory resource: %d\n", ret);
  383. return ret;
  384. }
  385. ref_clk = devm_clk_get(dev, "pll_ref");
  386. if (IS_ERR(ref_clk)) {
  387. ret = PTR_ERR(ref_clk);
  388. dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
  389. ret);
  390. return ret;
  391. }
  392. ref_clk_name = __clk_get_name(ref_clk);
  393. ret = of_property_read_string(dev->of_node, "clock-output-names",
  394. &clk_init.name);
  395. if (ret < 0) {
  396. dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
  397. return ret;
  398. }
  399. hdmi_phy->pll_hw.init = &clk_init;
  400. hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
  401. if (IS_ERR(hdmi_phy->pll)) {
  402. ret = PTR_ERR(hdmi_phy->pll);
  403. dev_err(dev, "Failed to register PLL: %d\n", ret);
  404. return ret;
  405. }
  406. ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
  407. &hdmi_phy->ibias);
  408. if (ret < 0) {
  409. dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
  410. return ret;
  411. }
  412. ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
  413. &hdmi_phy->ibias_up);
  414. if (ret < 0) {
  415. dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
  416. return ret;
  417. }
  418. dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
  419. hdmi_phy->drv_imp_clk = 0x30;
  420. hdmi_phy->drv_imp_d2 = 0x30;
  421. hdmi_phy->drv_imp_d1 = 0x30;
  422. hdmi_phy->drv_imp_d0 = 0x30;
  423. phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
  424. if (IS_ERR(phy)) {
  425. dev_err(dev, "Failed to create HDMI PHY\n");
  426. return PTR_ERR(phy);
  427. }
  428. phy_set_drvdata(phy, hdmi_phy);
  429. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  430. if (IS_ERR(phy_provider))
  431. return PTR_ERR(phy_provider);
  432. hdmi_phy->dev = dev;
  433. return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
  434. hdmi_phy->pll);
  435. }
  436. static int mtk_hdmi_phy_remove(struct platform_device *pdev)
  437. {
  438. return 0;
  439. }
  440. static const struct of_device_id mtk_hdmi_phy_match[] = {
  441. { .compatible = "mediatek,mt8173-hdmi-phy", },
  442. {},
  443. };
  444. struct platform_driver mtk_hdmi_phy_driver = {
  445. .probe = mtk_hdmi_phy_probe,
  446. .remove = mtk_hdmi_phy_remove,
  447. .driver = {
  448. .name = "mediatek-hdmi-phy",
  449. .of_match_table = mtk_hdmi_phy_match,
  450. },
  451. };
  452. MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
  453. MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
  454. MODULE_LICENSE("GPL v2");