mtk_disp_ovl.c 8.1 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <drm/drmP.h>
  14. #include <linux/clk.h>
  15. #include <linux/component.h>
  16. #include <linux/of_device.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/platform_device.h>
  19. #include "mtk_drm_crtc.h"
  20. #include "mtk_drm_ddp_comp.h"
  21. #define DISP_REG_OVL_INTEN 0x0004
  22. #define OVL_FME_CPL_INT BIT(1)
  23. #define DISP_REG_OVL_INTSTA 0x0008
  24. #define DISP_REG_OVL_EN 0x000c
  25. #define DISP_REG_OVL_RST 0x0014
  26. #define DISP_REG_OVL_ROI_SIZE 0x0020
  27. #define DISP_REG_OVL_ROI_BGCLR 0x0028
  28. #define DISP_REG_OVL_SRC_CON 0x002c
  29. #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
  30. #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
  31. #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
  32. #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
  33. #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
  34. #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
  35. #define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * (n))
  36. #define OVL_RDMA_MEM_GMC 0x40402020
  37. #define OVL_CON_BYTE_SWAP BIT(24)
  38. #define OVL_CON_CLRFMT_RGB565 (0 << 12)
  39. #define OVL_CON_CLRFMT_RGB888 (1 << 12)
  40. #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
  41. #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
  42. #define OVL_CON_AEN BIT(8)
  43. #define OVL_CON_ALPHA 0xff
  44. /**
  45. * struct mtk_disp_ovl - DISP_OVL driver structure
  46. * @ddp_comp - structure containing type enum and hardware resources
  47. * @crtc - associated crtc to report vblank events to
  48. */
  49. struct mtk_disp_ovl {
  50. struct mtk_ddp_comp ddp_comp;
  51. struct drm_crtc *crtc;
  52. };
  53. static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
  54. {
  55. struct mtk_disp_ovl *priv = dev_id;
  56. struct mtk_ddp_comp *ovl = &priv->ddp_comp;
  57. /* Clear frame completion interrupt */
  58. writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
  59. if (!priv->crtc)
  60. return IRQ_NONE;
  61. mtk_crtc_ddp_irq(priv->crtc, ovl);
  62. return IRQ_HANDLED;
  63. }
  64. static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
  65. struct drm_crtc *crtc)
  66. {
  67. struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
  68. ddp_comp);
  69. priv->crtc = crtc;
  70. writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
  71. }
  72. static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
  73. {
  74. struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
  75. ddp_comp);
  76. priv->crtc = NULL;
  77. writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
  78. }
  79. static void mtk_ovl_start(struct mtk_ddp_comp *comp)
  80. {
  81. writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
  82. }
  83. static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
  84. {
  85. writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
  86. }
  87. static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
  88. unsigned int h, unsigned int vrefresh)
  89. {
  90. if (w != 0 && h != 0)
  91. writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
  92. writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
  93. writel(0x1, comp->regs + DISP_REG_OVL_RST);
  94. writel(0x0, comp->regs + DISP_REG_OVL_RST);
  95. }
  96. static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
  97. {
  98. unsigned int reg;
  99. writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
  100. writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
  101. reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
  102. reg = reg | BIT(idx);
  103. writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
  104. }
  105. static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
  106. {
  107. unsigned int reg;
  108. reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
  109. reg = reg & ~BIT(idx);
  110. writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
  111. writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
  112. }
  113. static unsigned int ovl_fmt_convert(unsigned int fmt)
  114. {
  115. switch (fmt) {
  116. default:
  117. case DRM_FORMAT_RGB565:
  118. return OVL_CON_CLRFMT_RGB565;
  119. case DRM_FORMAT_BGR565:
  120. return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
  121. case DRM_FORMAT_RGB888:
  122. return OVL_CON_CLRFMT_RGB888;
  123. case DRM_FORMAT_BGR888:
  124. return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
  125. case DRM_FORMAT_RGBX8888:
  126. case DRM_FORMAT_RGBA8888:
  127. return OVL_CON_CLRFMT_ARGB8888;
  128. case DRM_FORMAT_BGRX8888:
  129. case DRM_FORMAT_BGRA8888:
  130. return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
  131. case DRM_FORMAT_XRGB8888:
  132. case DRM_FORMAT_ARGB8888:
  133. return OVL_CON_CLRFMT_RGBA8888;
  134. case DRM_FORMAT_XBGR8888:
  135. case DRM_FORMAT_ABGR8888:
  136. return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
  137. }
  138. }
  139. static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
  140. struct mtk_plane_state *state)
  141. {
  142. struct mtk_plane_pending_state *pending = &state->pending;
  143. unsigned int addr = pending->addr;
  144. unsigned int pitch = pending->pitch & 0xffff;
  145. unsigned int fmt = pending->format;
  146. unsigned int offset = (pending->y << 16) | pending->x;
  147. unsigned int src_size = (pending->height << 16) | pending->width;
  148. unsigned int con;
  149. if (!pending->enable)
  150. mtk_ovl_layer_off(comp, idx);
  151. con = ovl_fmt_convert(fmt);
  152. if (idx != 0)
  153. con |= OVL_CON_AEN | OVL_CON_ALPHA;
  154. writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
  155. writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
  156. writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
  157. writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
  158. writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
  159. if (pending->enable)
  160. mtk_ovl_layer_on(comp, idx);
  161. }
  162. static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
  163. .config = mtk_ovl_config,
  164. .start = mtk_ovl_start,
  165. .stop = mtk_ovl_stop,
  166. .enable_vblank = mtk_ovl_enable_vblank,
  167. .disable_vblank = mtk_ovl_disable_vblank,
  168. .layer_on = mtk_ovl_layer_on,
  169. .layer_off = mtk_ovl_layer_off,
  170. .layer_config = mtk_ovl_layer_config,
  171. };
  172. static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
  173. void *data)
  174. {
  175. struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
  176. struct drm_device *drm_dev = data;
  177. int ret;
  178. ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
  179. if (ret < 0) {
  180. dev_err(dev, "Failed to register component %s: %d\n",
  181. dev->of_node->full_name, ret);
  182. return ret;
  183. }
  184. return 0;
  185. }
  186. static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
  187. void *data)
  188. {
  189. struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
  190. struct drm_device *drm_dev = data;
  191. mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
  192. }
  193. static const struct component_ops mtk_disp_ovl_component_ops = {
  194. .bind = mtk_disp_ovl_bind,
  195. .unbind = mtk_disp_ovl_unbind,
  196. };
  197. static int mtk_disp_ovl_probe(struct platform_device *pdev)
  198. {
  199. struct device *dev = &pdev->dev;
  200. struct mtk_disp_ovl *priv;
  201. int comp_id;
  202. int irq;
  203. int ret;
  204. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  205. if (!priv)
  206. return -ENOMEM;
  207. irq = platform_get_irq(pdev, 0);
  208. if (irq < 0)
  209. return irq;
  210. ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
  211. IRQF_TRIGGER_NONE, dev_name(dev), priv);
  212. if (ret < 0) {
  213. dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
  214. return ret;
  215. }
  216. comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
  217. if (comp_id < 0) {
  218. dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
  219. return comp_id;
  220. }
  221. ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
  222. &mtk_disp_ovl_funcs);
  223. if (ret) {
  224. dev_err(dev, "Failed to initialize component: %d\n", ret);
  225. return ret;
  226. }
  227. platform_set_drvdata(pdev, priv);
  228. ret = component_add(dev, &mtk_disp_ovl_component_ops);
  229. if (ret)
  230. dev_err(dev, "Failed to add component: %d\n", ret);
  231. return ret;
  232. }
  233. static int mtk_disp_ovl_remove(struct platform_device *pdev)
  234. {
  235. component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
  236. return 0;
  237. }
  238. static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
  239. { .compatible = "mediatek,mt8173-disp-ovl", },
  240. {},
  241. };
  242. MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
  243. struct platform_driver mtk_disp_ovl_driver = {
  244. .probe = mtk_disp_ovl_probe,
  245. .remove = mtk_disp_ovl_remove,
  246. .driver = {
  247. .name = "mediatek-disp-ovl",
  248. .owner = THIS_MODULE,
  249. .of_match_table = mtk_disp_ovl_driver_dt_match,
  250. },
  251. };