fsl_dcu_drm_drv.c 11 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * Freescale DCU drm device driver
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/console.h>
  14. #include <linux/io.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/mm.h>
  17. #include <linux/module.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <drm/drmP.h>
  24. #include <drm/drm_atomic_helper.h>
  25. #include <drm/drm_crtc_helper.h>
  26. #include <drm/drm_fb_cma_helper.h>
  27. #include <drm/drm_gem_cma_helper.h>
  28. #include "fsl_dcu_drm_crtc.h"
  29. #include "fsl_dcu_drm_drv.h"
  30. #include "fsl_tcon.h"
  31. static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
  32. {
  33. if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE)
  34. return true;
  35. return false;
  36. }
  37. static const struct regmap_config fsl_dcu_regmap_config = {
  38. .reg_bits = 32,
  39. .reg_stride = 4,
  40. .val_bits = 32,
  41. .volatile_reg = fsl_dcu_drm_is_volatile_reg,
  42. };
  43. static int fsl_dcu_drm_irq_init(struct drm_device *dev)
  44. {
  45. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  46. int ret;
  47. ret = drm_irq_install(dev, fsl_dev->irq);
  48. if (ret < 0)
  49. dev_err(dev->dev, "failed to install IRQ handler\n");
  50. regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
  51. regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
  52. regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  53. DCU_UPDATE_MODE_READREG);
  54. return ret;
  55. }
  56. static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
  57. {
  58. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  59. int ret;
  60. ret = fsl_dcu_drm_modeset_init(fsl_dev);
  61. if (ret < 0) {
  62. dev_err(dev->dev, "failed to initialize mode setting\n");
  63. return ret;
  64. }
  65. ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  66. if (ret < 0) {
  67. dev_err(dev->dev, "failed to initialize vblank\n");
  68. goto done;
  69. }
  70. ret = fsl_dcu_drm_irq_init(dev);
  71. if (ret < 0)
  72. goto done;
  73. dev->irq_enabled = true;
  74. fsl_dcu_fbdev_init(dev);
  75. return 0;
  76. done:
  77. drm_kms_helper_poll_fini(dev);
  78. if (fsl_dev->fbdev)
  79. drm_fbdev_cma_fini(fsl_dev->fbdev);
  80. drm_mode_config_cleanup(dev);
  81. drm_vblank_cleanup(dev);
  82. drm_irq_uninstall(dev);
  83. dev->dev_private = NULL;
  84. return ret;
  85. }
  86. static int fsl_dcu_unload(struct drm_device *dev)
  87. {
  88. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  89. drm_kms_helper_poll_fini(dev);
  90. if (fsl_dev->fbdev)
  91. drm_fbdev_cma_fini(fsl_dev->fbdev);
  92. drm_mode_config_cleanup(dev);
  93. drm_vblank_cleanup(dev);
  94. drm_irq_uninstall(dev);
  95. dev->dev_private = NULL;
  96. return 0;
  97. }
  98. static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
  99. {
  100. struct drm_device *dev = arg;
  101. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  102. unsigned int int_status;
  103. int ret;
  104. ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
  105. if (ret) {
  106. dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
  107. return IRQ_NONE;
  108. }
  109. if (int_status & DCU_INT_STATUS_VBLANK)
  110. drm_handle_vblank(dev, 0);
  111. regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
  112. regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  113. DCU_UPDATE_MODE_READREG);
  114. return IRQ_HANDLED;
  115. }
  116. static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe)
  117. {
  118. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  119. unsigned int value;
  120. regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
  121. value &= ~DCU_INT_MASK_VBLANK;
  122. regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
  123. return 0;
  124. }
  125. static void fsl_dcu_drm_disable_vblank(struct drm_device *dev,
  126. unsigned int pipe)
  127. {
  128. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  129. unsigned int value;
  130. regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
  131. value |= DCU_INT_MASK_VBLANK;
  132. regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
  133. }
  134. static void fsl_dcu_drm_lastclose(struct drm_device *dev)
  135. {
  136. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  137. drm_fbdev_cma_restore_mode(fsl_dev->fbdev);
  138. }
  139. static const struct file_operations fsl_dcu_drm_fops = {
  140. .owner = THIS_MODULE,
  141. .open = drm_open,
  142. .release = drm_release,
  143. .unlocked_ioctl = drm_ioctl,
  144. #ifdef CONFIG_COMPAT
  145. .compat_ioctl = drm_compat_ioctl,
  146. #endif
  147. .poll = drm_poll,
  148. .read = drm_read,
  149. .llseek = no_llseek,
  150. .mmap = drm_gem_cma_mmap,
  151. };
  152. static struct drm_driver fsl_dcu_drm_driver = {
  153. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
  154. | DRIVER_PRIME | DRIVER_ATOMIC,
  155. .lastclose = fsl_dcu_drm_lastclose,
  156. .load = fsl_dcu_load,
  157. .unload = fsl_dcu_unload,
  158. .irq_handler = fsl_dcu_drm_irq,
  159. .get_vblank_counter = drm_vblank_no_hw_counter,
  160. .enable_vblank = fsl_dcu_drm_enable_vblank,
  161. .disable_vblank = fsl_dcu_drm_disable_vblank,
  162. .gem_free_object_unlocked = drm_gem_cma_free_object,
  163. .gem_vm_ops = &drm_gem_cma_vm_ops,
  164. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  165. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  166. .gem_prime_import = drm_gem_prime_import,
  167. .gem_prime_export = drm_gem_prime_export,
  168. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  169. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  170. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  171. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  172. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  173. .dumb_create = drm_gem_cma_dumb_create,
  174. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  175. .dumb_destroy = drm_gem_dumb_destroy,
  176. .fops = &fsl_dcu_drm_fops,
  177. .name = "fsl-dcu-drm",
  178. .desc = "Freescale DCU DRM",
  179. .date = "20160425",
  180. .major = 1,
  181. .minor = 1,
  182. };
  183. #ifdef CONFIG_PM_SLEEP
  184. static int fsl_dcu_drm_pm_suspend(struct device *dev)
  185. {
  186. struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
  187. if (!fsl_dev)
  188. return 0;
  189. disable_irq(fsl_dev->irq);
  190. drm_kms_helper_poll_disable(fsl_dev->drm);
  191. console_lock();
  192. drm_fbdev_cma_set_suspend(fsl_dev->fbdev, 1);
  193. console_unlock();
  194. fsl_dev->state = drm_atomic_helper_suspend(fsl_dev->drm);
  195. if (IS_ERR(fsl_dev->state)) {
  196. console_lock();
  197. drm_fbdev_cma_set_suspend(fsl_dev->fbdev, 0);
  198. console_unlock();
  199. drm_kms_helper_poll_enable(fsl_dev->drm);
  200. enable_irq(fsl_dev->irq);
  201. return PTR_ERR(fsl_dev->state);
  202. }
  203. clk_disable_unprepare(fsl_dev->pix_clk);
  204. clk_disable_unprepare(fsl_dev->clk);
  205. return 0;
  206. }
  207. static int fsl_dcu_drm_pm_resume(struct device *dev)
  208. {
  209. struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
  210. int ret;
  211. if (!fsl_dev)
  212. return 0;
  213. ret = clk_prepare_enable(fsl_dev->clk);
  214. if (ret < 0) {
  215. dev_err(dev, "failed to enable dcu clk\n");
  216. return ret;
  217. }
  218. ret = clk_prepare_enable(fsl_dev->pix_clk);
  219. if (ret < 0) {
  220. dev_err(dev, "failed to enable pix clk\n");
  221. return ret;
  222. }
  223. fsl_dcu_drm_init_planes(fsl_dev->drm);
  224. drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
  225. console_lock();
  226. drm_fbdev_cma_set_suspend(fsl_dev->fbdev, 0);
  227. console_unlock();
  228. drm_kms_helper_poll_enable(fsl_dev->drm);
  229. enable_irq(fsl_dev->irq);
  230. return 0;
  231. }
  232. #endif
  233. static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
  234. SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend, fsl_dcu_drm_pm_resume)
  235. };
  236. static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = {
  237. .name = "ls1021a",
  238. .total_layer = 16,
  239. .max_layer = 4,
  240. .layer_regs = LS1021A_LAYER_REG_NUM,
  241. };
  242. static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
  243. .name = "vf610",
  244. .total_layer = 64,
  245. .max_layer = 6,
  246. .layer_regs = VF610_LAYER_REG_NUM,
  247. };
  248. static const struct of_device_id fsl_dcu_of_match[] = {
  249. {
  250. .compatible = "fsl,ls1021a-dcu",
  251. .data = &fsl_dcu_ls1021a_data,
  252. }, {
  253. .compatible = "fsl,vf610-dcu",
  254. .data = &fsl_dcu_vf610_data,
  255. }, {
  256. },
  257. };
  258. MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
  259. static int fsl_dcu_drm_probe(struct platform_device *pdev)
  260. {
  261. struct fsl_dcu_drm_device *fsl_dev;
  262. struct drm_device *drm;
  263. struct device *dev = &pdev->dev;
  264. struct resource *res;
  265. void __iomem *base;
  266. struct drm_driver *driver = &fsl_dcu_drm_driver;
  267. struct clk *pix_clk_in;
  268. char pix_clk_name[32];
  269. const char *pix_clk_in_name;
  270. const struct of_device_id *id;
  271. int ret;
  272. fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
  273. if (!fsl_dev)
  274. return -ENOMEM;
  275. id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
  276. if (!id)
  277. return -ENODEV;
  278. fsl_dev->soc = id->data;
  279. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  280. if (!res) {
  281. dev_err(dev, "could not get memory IO resource\n");
  282. return -ENODEV;
  283. }
  284. base = devm_ioremap_resource(dev, res);
  285. if (IS_ERR(base)) {
  286. ret = PTR_ERR(base);
  287. return ret;
  288. }
  289. fsl_dev->irq = platform_get_irq(pdev, 0);
  290. if (fsl_dev->irq < 0) {
  291. dev_err(dev, "failed to get irq\n");
  292. return -ENXIO;
  293. }
  294. fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
  295. &fsl_dcu_regmap_config);
  296. if (IS_ERR(fsl_dev->regmap)) {
  297. dev_err(dev, "regmap init failed\n");
  298. return PTR_ERR(fsl_dev->regmap);
  299. }
  300. fsl_dev->clk = devm_clk_get(dev, "dcu");
  301. if (IS_ERR(fsl_dev->clk)) {
  302. dev_err(dev, "failed to get dcu clock\n");
  303. return PTR_ERR(fsl_dev->clk);
  304. }
  305. ret = clk_prepare_enable(fsl_dev->clk);
  306. if (ret < 0) {
  307. dev_err(dev, "failed to enable dcu clk\n");
  308. return ret;
  309. }
  310. pix_clk_in = devm_clk_get(dev, "pix");
  311. if (IS_ERR(pix_clk_in)) {
  312. /* legancy binding, use dcu clock as pixel clock input */
  313. pix_clk_in = fsl_dev->clk;
  314. }
  315. pix_clk_in_name = __clk_get_name(pix_clk_in);
  316. snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
  317. fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
  318. pix_clk_in_name, 0, base + DCU_DIV_RATIO,
  319. 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
  320. if (IS_ERR(fsl_dev->pix_clk)) {
  321. dev_err(dev, "failed to register pix clk\n");
  322. ret = PTR_ERR(fsl_dev->pix_clk);
  323. goto disable_clk;
  324. }
  325. ret = clk_prepare_enable(fsl_dev->pix_clk);
  326. if (ret < 0) {
  327. dev_err(dev, "failed to enable pix clk\n");
  328. goto unregister_pix_clk;
  329. }
  330. fsl_dev->tcon = fsl_tcon_init(dev);
  331. drm = drm_dev_alloc(driver, dev);
  332. if (!drm) {
  333. ret = -ENOMEM;
  334. goto disable_pix_clk;
  335. }
  336. fsl_dev->dev = dev;
  337. fsl_dev->drm = drm;
  338. fsl_dev->np = dev->of_node;
  339. drm->dev_private = fsl_dev;
  340. dev_set_drvdata(dev, fsl_dev);
  341. ret = drm_dev_register(drm, 0);
  342. if (ret < 0)
  343. goto unref;
  344. DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name,
  345. driver->major, driver->minor, driver->patchlevel,
  346. driver->date, drm->primary->index);
  347. return 0;
  348. unref:
  349. drm_dev_unref(drm);
  350. disable_pix_clk:
  351. clk_disable_unprepare(fsl_dev->pix_clk);
  352. unregister_pix_clk:
  353. clk_unregister(fsl_dev->pix_clk);
  354. disable_clk:
  355. clk_disable_unprepare(fsl_dev->clk);
  356. return ret;
  357. }
  358. static int fsl_dcu_drm_remove(struct platform_device *pdev)
  359. {
  360. struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
  361. clk_disable_unprepare(fsl_dev->clk);
  362. clk_disable_unprepare(fsl_dev->pix_clk);
  363. clk_unregister(fsl_dev->pix_clk);
  364. drm_put_dev(fsl_dev->drm);
  365. return 0;
  366. }
  367. static struct platform_driver fsl_dcu_drm_platform_driver = {
  368. .probe = fsl_dcu_drm_probe,
  369. .remove = fsl_dcu_drm_remove,
  370. .driver = {
  371. .name = "fsl-dcu",
  372. .pm = &fsl_dcu_drm_pm_ops,
  373. .of_match_table = fsl_dcu_of_match,
  374. },
  375. };
  376. module_platform_driver(fsl_dcu_drm_platform_driver);
  377. MODULE_DESCRIPTION("Freescale DCU DRM Driver");
  378. MODULE_LICENSE("GPL");