fsl_dcu_drm_crtc.c 4.8 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * Freescale DCU drm device driver
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/regmap.h>
  13. #include <drm/drmP.h>
  14. #include <drm/drm_atomic.h>
  15. #include <drm/drm_atomic_helper.h>
  16. #include <drm/drm_crtc.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include "fsl_dcu_drm_crtc.h"
  19. #include "fsl_dcu_drm_drv.h"
  20. #include "fsl_dcu_drm_plane.h"
  21. static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  22. struct drm_crtc_state *old_crtc_state)
  23. {
  24. struct drm_pending_vblank_event *event = crtc->state->event;
  25. if (event) {
  26. crtc->state->event = NULL;
  27. spin_lock_irq(&crtc->dev->event_lock);
  28. if (drm_crtc_vblank_get(crtc) == 0)
  29. drm_crtc_arm_vblank_event(crtc, event);
  30. else
  31. drm_crtc_send_vblank_event(crtc, event);
  32. spin_unlock_irq(&crtc->dev->event_lock);
  33. }
  34. }
  35. static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
  36. {
  37. struct drm_device *dev = crtc->dev;
  38. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  39. drm_crtc_vblank_off(crtc);
  40. regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  41. DCU_MODE_DCU_MODE_MASK,
  42. DCU_MODE_DCU_MODE(DCU_MODE_OFF));
  43. regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  44. DCU_UPDATE_MODE_READREG);
  45. }
  46. static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
  47. {
  48. struct drm_device *dev = crtc->dev;
  49. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  50. regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  51. DCU_MODE_DCU_MODE_MASK,
  52. DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
  53. regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  54. DCU_UPDATE_MODE_READREG);
  55. drm_crtc_vblank_on(crtc);
  56. }
  57. static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
  58. {
  59. struct drm_device *dev = crtc->dev;
  60. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  61. struct drm_connector *con = &fsl_dev->connector.base;
  62. struct drm_display_mode *mode = &crtc->state->mode;
  63. unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
  64. index = drm_crtc_index(crtc);
  65. clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
  66. /* Configure timings: */
  67. hbp = mode->htotal - mode->hsync_end;
  68. hfp = mode->hsync_start - mode->hdisplay;
  69. hsw = mode->hsync_end - mode->hsync_start;
  70. vbp = mode->vtotal - mode->vsync_end;
  71. vfp = mode->vsync_start - mode->vdisplay;
  72. vsw = mode->vsync_end - mode->vsync_start;
  73. /* INV_PXCK as default (most display sample data on rising edge) */
  74. if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE))
  75. pol |= DCU_SYN_POL_INV_PXCK;
  76. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  77. pol |= DCU_SYN_POL_INV_HS_LOW;
  78. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  79. pol |= DCU_SYN_POL_INV_VS_LOW;
  80. regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
  81. DCU_HSYN_PARA_BP(hbp) |
  82. DCU_HSYN_PARA_PW(hsw) |
  83. DCU_HSYN_PARA_FP(hfp));
  84. regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
  85. DCU_VSYN_PARA_BP(vbp) |
  86. DCU_VSYN_PARA_PW(vsw) |
  87. DCU_VSYN_PARA_FP(vfp));
  88. regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
  89. DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
  90. DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
  91. regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
  92. regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
  93. DCU_BGND_G(0) | DCU_BGND_B(0));
  94. regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
  95. DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
  96. regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
  97. DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
  98. DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
  99. DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
  100. regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  101. DCU_UPDATE_MODE_READREG);
  102. return;
  103. }
  104. static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
  105. .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
  106. .disable = fsl_dcu_drm_disable_crtc,
  107. .enable = fsl_dcu_drm_crtc_enable,
  108. .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
  109. };
  110. static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
  111. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  112. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  113. .destroy = drm_crtc_cleanup,
  114. .page_flip = drm_atomic_helper_page_flip,
  115. .reset = drm_atomic_helper_crtc_reset,
  116. .set_config = drm_atomic_helper_set_config,
  117. };
  118. int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
  119. {
  120. struct drm_plane *primary;
  121. struct drm_crtc *crtc = &fsl_dev->crtc;
  122. int ret;
  123. fsl_dcu_drm_init_planes(fsl_dev->drm);
  124. primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
  125. if (!primary)
  126. return -ENOMEM;
  127. ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
  128. &fsl_dcu_drm_crtc_funcs, NULL);
  129. if (ret) {
  130. primary->funcs->destroy(primary);
  131. return ret;
  132. }
  133. drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
  134. return 0;
  135. }