malidp_drv.c 13 KB

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  1. /*
  2. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  3. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4. *
  5. * This program is free software and is provided to you under the terms of the
  6. * GNU General Public License version 2 as published by the Free Software
  7. * Foundation, and any use by you of this program is subject to the terms
  8. * of such GNU licence.
  9. *
  10. * ARM Mali DP500/DP550/DP650 KMS/DRM driver
  11. */
  12. #include <linux/module.h>
  13. #include <linux/clk.h>
  14. #include <linux/component.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/of_reserved_mem.h>
  18. #include <drm/drmP.h>
  19. #include <drm/drm_atomic.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include <drm/drm_fb_cma_helper.h>
  25. #include <drm/drm_gem_cma_helper.h>
  26. #include <drm/drm_of.h>
  27. #include "malidp_drv.h"
  28. #include "malidp_regs.h"
  29. #include "malidp_hw.h"
  30. #define MALIDP_CONF_VALID_TIMEOUT 250
  31. /*
  32. * set the "config valid" bit and wait until the hardware acts on it
  33. */
  34. static int malidp_set_and_wait_config_valid(struct drm_device *drm)
  35. {
  36. struct malidp_drm *malidp = drm->dev_private;
  37. struct malidp_hw_device *hwdev = malidp->dev;
  38. int ret;
  39. hwdev->set_config_valid(hwdev);
  40. /* don't wait for config_valid flag if we are in config mode */
  41. if (hwdev->in_config_mode(hwdev))
  42. return 0;
  43. ret = wait_event_interruptible_timeout(malidp->wq,
  44. atomic_read(&malidp->config_valid) == 1,
  45. msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
  46. return (ret > 0) ? 0 : -ETIMEDOUT;
  47. }
  48. static void malidp_output_poll_changed(struct drm_device *drm)
  49. {
  50. struct malidp_drm *malidp = drm->dev_private;
  51. drm_fbdev_cma_hotplug_event(malidp->fbdev);
  52. }
  53. static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
  54. {
  55. struct drm_pending_vblank_event *event;
  56. struct drm_device *drm = state->dev;
  57. struct malidp_drm *malidp = drm->dev_private;
  58. int ret = malidp_set_and_wait_config_valid(drm);
  59. if (ret)
  60. DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
  61. event = malidp->crtc.state->event;
  62. if (event) {
  63. malidp->crtc.state->event = NULL;
  64. spin_lock_irq(&drm->event_lock);
  65. if (drm_crtc_vblank_get(&malidp->crtc) == 0)
  66. drm_crtc_arm_vblank_event(&malidp->crtc, event);
  67. else
  68. drm_crtc_send_vblank_event(&malidp->crtc, event);
  69. spin_unlock_irq(&drm->event_lock);
  70. }
  71. drm_atomic_helper_commit_hw_done(state);
  72. }
  73. static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
  74. {
  75. struct drm_device *drm = state->dev;
  76. drm_atomic_helper_commit_modeset_disables(drm, state);
  77. drm_atomic_helper_commit_modeset_enables(drm, state);
  78. drm_atomic_helper_commit_planes(drm, state, true);
  79. malidp_atomic_commit_hw_done(state);
  80. drm_atomic_helper_wait_for_vblanks(drm, state);
  81. drm_atomic_helper_cleanup_planes(drm, state);
  82. }
  83. static struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
  84. .atomic_commit_tail = malidp_atomic_commit_tail,
  85. };
  86. static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
  87. .fb_create = drm_fb_cma_create,
  88. .output_poll_changed = malidp_output_poll_changed,
  89. .atomic_check = drm_atomic_helper_check,
  90. .atomic_commit = drm_atomic_helper_commit,
  91. };
  92. static int malidp_enable_vblank(struct drm_device *drm, unsigned int crtc)
  93. {
  94. struct malidp_drm *malidp = drm->dev_private;
  95. struct malidp_hw_device *hwdev = malidp->dev;
  96. malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
  97. hwdev->map.de_irq_map.vsync_irq);
  98. return 0;
  99. }
  100. static void malidp_disable_vblank(struct drm_device *drm, unsigned int pipe)
  101. {
  102. struct malidp_drm *malidp = drm->dev_private;
  103. struct malidp_hw_device *hwdev = malidp->dev;
  104. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
  105. hwdev->map.de_irq_map.vsync_irq);
  106. }
  107. static int malidp_init(struct drm_device *drm)
  108. {
  109. int ret;
  110. struct malidp_drm *malidp = drm->dev_private;
  111. struct malidp_hw_device *hwdev = malidp->dev;
  112. drm_mode_config_init(drm);
  113. drm->mode_config.min_width = hwdev->min_line_size;
  114. drm->mode_config.min_height = hwdev->min_line_size;
  115. drm->mode_config.max_width = hwdev->max_line_size;
  116. drm->mode_config.max_height = hwdev->max_line_size;
  117. drm->mode_config.funcs = &malidp_mode_config_funcs;
  118. drm->mode_config.helper_private = &malidp_mode_config_helpers;
  119. ret = malidp_crtc_init(drm);
  120. if (ret) {
  121. drm_mode_config_cleanup(drm);
  122. return ret;
  123. }
  124. return 0;
  125. }
  126. static int malidp_irq_init(struct platform_device *pdev)
  127. {
  128. int irq_de, irq_se, ret = 0;
  129. struct drm_device *drm = dev_get_drvdata(&pdev->dev);
  130. /* fetch the interrupts from DT */
  131. irq_de = platform_get_irq_byname(pdev, "DE");
  132. if (irq_de < 0) {
  133. DRM_ERROR("no 'DE' IRQ specified!\n");
  134. return irq_de;
  135. }
  136. irq_se = platform_get_irq_byname(pdev, "SE");
  137. if (irq_se < 0) {
  138. DRM_ERROR("no 'SE' IRQ specified!\n");
  139. return irq_se;
  140. }
  141. ret = malidp_de_irq_init(drm, irq_de);
  142. if (ret)
  143. return ret;
  144. ret = malidp_se_irq_init(drm, irq_se);
  145. if (ret) {
  146. malidp_de_irq_fini(drm);
  147. return ret;
  148. }
  149. return 0;
  150. }
  151. static void malidp_lastclose(struct drm_device *drm)
  152. {
  153. struct malidp_drm *malidp = drm->dev_private;
  154. drm_fbdev_cma_restore_mode(malidp->fbdev);
  155. }
  156. static const struct file_operations fops = {
  157. .owner = THIS_MODULE,
  158. .open = drm_open,
  159. .release = drm_release,
  160. .unlocked_ioctl = drm_ioctl,
  161. #ifdef CONFIG_COMPAT
  162. .compat_ioctl = drm_compat_ioctl,
  163. #endif
  164. .poll = drm_poll,
  165. .read = drm_read,
  166. .llseek = noop_llseek,
  167. .mmap = drm_gem_cma_mmap,
  168. };
  169. static struct drm_driver malidp_driver = {
  170. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
  171. DRIVER_PRIME,
  172. .lastclose = malidp_lastclose,
  173. .get_vblank_counter = drm_vblank_no_hw_counter,
  174. .enable_vblank = malidp_enable_vblank,
  175. .disable_vblank = malidp_disable_vblank,
  176. .gem_free_object_unlocked = drm_gem_cma_free_object,
  177. .gem_vm_ops = &drm_gem_cma_vm_ops,
  178. .dumb_create = drm_gem_cma_dumb_create,
  179. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  180. .dumb_destroy = drm_gem_dumb_destroy,
  181. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  182. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  183. .gem_prime_export = drm_gem_prime_export,
  184. .gem_prime_import = drm_gem_prime_import,
  185. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  186. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  187. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  188. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  189. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  190. .fops = &fops,
  191. .name = "mali-dp",
  192. .desc = "ARM Mali Display Processor driver",
  193. .date = "20160106",
  194. .major = 1,
  195. .minor = 0,
  196. };
  197. static const struct of_device_id malidp_drm_of_match[] = {
  198. {
  199. .compatible = "arm,mali-dp500",
  200. .data = &malidp_device[MALIDP_500]
  201. },
  202. {
  203. .compatible = "arm,mali-dp550",
  204. .data = &malidp_device[MALIDP_550]
  205. },
  206. {
  207. .compatible = "arm,mali-dp650",
  208. .data = &malidp_device[MALIDP_650]
  209. },
  210. {},
  211. };
  212. MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
  213. #define MAX_OUTPUT_CHANNELS 3
  214. static int malidp_bind(struct device *dev)
  215. {
  216. struct resource *res;
  217. struct drm_device *drm;
  218. struct device_node *ep;
  219. struct malidp_drm *malidp;
  220. struct malidp_hw_device *hwdev;
  221. struct platform_device *pdev = to_platform_device(dev);
  222. /* number of lines for the R, G and B output */
  223. u8 output_width[MAX_OUTPUT_CHANNELS];
  224. int ret = 0, i;
  225. u32 version, out_depth = 0;
  226. malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
  227. if (!malidp)
  228. return -ENOMEM;
  229. hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
  230. if (!hwdev)
  231. return -ENOMEM;
  232. /*
  233. * copy the associated data from malidp_drm_of_match to avoid
  234. * having to keep a reference to the OF node after binding
  235. */
  236. memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
  237. malidp->dev = hwdev;
  238. INIT_LIST_HEAD(&malidp->event_list);
  239. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  240. hwdev->regs = devm_ioremap_resource(dev, res);
  241. if (IS_ERR(hwdev->regs))
  242. return PTR_ERR(hwdev->regs);
  243. hwdev->pclk = devm_clk_get(dev, "pclk");
  244. if (IS_ERR(hwdev->pclk))
  245. return PTR_ERR(hwdev->pclk);
  246. hwdev->aclk = devm_clk_get(dev, "aclk");
  247. if (IS_ERR(hwdev->aclk))
  248. return PTR_ERR(hwdev->aclk);
  249. hwdev->mclk = devm_clk_get(dev, "mclk");
  250. if (IS_ERR(hwdev->mclk))
  251. return PTR_ERR(hwdev->mclk);
  252. hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
  253. if (IS_ERR(hwdev->pxlclk))
  254. return PTR_ERR(hwdev->pxlclk);
  255. /* Get the optional framebuffer memory resource */
  256. ret = of_reserved_mem_device_init(dev);
  257. if (ret && ret != -ENODEV)
  258. return ret;
  259. drm = drm_dev_alloc(&malidp_driver, dev);
  260. if (!drm) {
  261. ret = -ENOMEM;
  262. goto alloc_fail;
  263. }
  264. /* Enable APB clock in order to get access to the registers */
  265. clk_prepare_enable(hwdev->pclk);
  266. /*
  267. * Enable AXI clock and main clock so that prefetch can start once
  268. * the registers are set
  269. */
  270. clk_prepare_enable(hwdev->aclk);
  271. clk_prepare_enable(hwdev->mclk);
  272. ret = hwdev->query_hw(hwdev);
  273. if (ret) {
  274. DRM_ERROR("Invalid HW configuration\n");
  275. goto query_hw_fail;
  276. }
  277. version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
  278. DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
  279. (version >> 12) & 0xf, (version >> 8) & 0xf);
  280. /* set the number of lines used for output of RGB data */
  281. ret = of_property_read_u8_array(dev->of_node,
  282. "arm,malidp-output-port-lines",
  283. output_width, MAX_OUTPUT_CHANNELS);
  284. if (ret)
  285. goto query_hw_fail;
  286. for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
  287. out_depth = (out_depth << 8) | (output_width[i] & 0xf);
  288. malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
  289. drm->dev_private = malidp;
  290. dev_set_drvdata(dev, drm);
  291. atomic_set(&malidp->config_valid, 0);
  292. init_waitqueue_head(&malidp->wq);
  293. ret = malidp_init(drm);
  294. if (ret < 0)
  295. goto init_fail;
  296. ret = drm_dev_register(drm, 0);
  297. if (ret)
  298. goto register_fail;
  299. /* Set the CRTC's port so that the encoder component can find it */
  300. ep = of_graph_get_next_endpoint(dev->of_node, NULL);
  301. if (!ep) {
  302. ret = -EINVAL;
  303. goto port_fail;
  304. }
  305. malidp->crtc.port = of_get_next_parent(ep);
  306. ret = component_bind_all(dev, drm);
  307. if (ret) {
  308. DRM_ERROR("Failed to bind all components\n");
  309. goto bind_fail;
  310. }
  311. ret = malidp_irq_init(pdev);
  312. if (ret < 0)
  313. goto irq_init_fail;
  314. ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
  315. if (ret < 0) {
  316. DRM_ERROR("failed to initialise vblank\n");
  317. goto vblank_fail;
  318. }
  319. drm_mode_config_reset(drm);
  320. malidp->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
  321. drm->mode_config.num_connector);
  322. if (IS_ERR(malidp->fbdev)) {
  323. ret = PTR_ERR(malidp->fbdev);
  324. malidp->fbdev = NULL;
  325. goto fbdev_fail;
  326. }
  327. drm_kms_helper_poll_init(drm);
  328. return 0;
  329. fbdev_fail:
  330. drm_vblank_cleanup(drm);
  331. vblank_fail:
  332. malidp_se_irq_fini(drm);
  333. malidp_de_irq_fini(drm);
  334. irq_init_fail:
  335. component_unbind_all(dev, drm);
  336. bind_fail:
  337. of_node_put(malidp->crtc.port);
  338. malidp->crtc.port = NULL;
  339. port_fail:
  340. drm_dev_unregister(drm);
  341. register_fail:
  342. malidp_de_planes_destroy(drm);
  343. drm_mode_config_cleanup(drm);
  344. init_fail:
  345. drm->dev_private = NULL;
  346. dev_set_drvdata(dev, NULL);
  347. query_hw_fail:
  348. clk_disable_unprepare(hwdev->mclk);
  349. clk_disable_unprepare(hwdev->aclk);
  350. clk_disable_unprepare(hwdev->pclk);
  351. drm_dev_unref(drm);
  352. alloc_fail:
  353. of_reserved_mem_device_release(dev);
  354. return ret;
  355. }
  356. static void malidp_unbind(struct device *dev)
  357. {
  358. struct drm_device *drm = dev_get_drvdata(dev);
  359. struct malidp_drm *malidp = drm->dev_private;
  360. struct malidp_hw_device *hwdev = malidp->dev;
  361. if (malidp->fbdev) {
  362. drm_fbdev_cma_fini(malidp->fbdev);
  363. malidp->fbdev = NULL;
  364. }
  365. drm_kms_helper_poll_fini(drm);
  366. malidp_se_irq_fini(drm);
  367. malidp_de_irq_fini(drm);
  368. drm_vblank_cleanup(drm);
  369. component_unbind_all(dev, drm);
  370. of_node_put(malidp->crtc.port);
  371. malidp->crtc.port = NULL;
  372. drm_dev_unregister(drm);
  373. malidp_de_planes_destroy(drm);
  374. drm_mode_config_cleanup(drm);
  375. drm->dev_private = NULL;
  376. dev_set_drvdata(dev, NULL);
  377. clk_disable_unprepare(hwdev->mclk);
  378. clk_disable_unprepare(hwdev->aclk);
  379. clk_disable_unprepare(hwdev->pclk);
  380. drm_dev_unref(drm);
  381. of_reserved_mem_device_release(dev);
  382. }
  383. static const struct component_master_ops malidp_master_ops = {
  384. .bind = malidp_bind,
  385. .unbind = malidp_unbind,
  386. };
  387. static int malidp_compare_dev(struct device *dev, void *data)
  388. {
  389. struct device_node *np = data;
  390. return dev->of_node == np;
  391. }
  392. static int malidp_platform_probe(struct platform_device *pdev)
  393. {
  394. struct device_node *port, *ep;
  395. struct component_match *match = NULL;
  396. if (!pdev->dev.of_node)
  397. return -ENODEV;
  398. /* there is only one output port inside each device, find it */
  399. ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
  400. if (!ep)
  401. return -ENODEV;
  402. if (!of_device_is_available(ep)) {
  403. of_node_put(ep);
  404. return -ENODEV;
  405. }
  406. /* add the remote encoder port as component */
  407. port = of_graph_get_remote_port_parent(ep);
  408. of_node_put(ep);
  409. if (!port || !of_device_is_available(port)) {
  410. of_node_put(port);
  411. return -EAGAIN;
  412. }
  413. component_match_add(&pdev->dev, &match, malidp_compare_dev, port);
  414. return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
  415. match);
  416. }
  417. static int malidp_platform_remove(struct platform_device *pdev)
  418. {
  419. component_master_del(&pdev->dev, &malidp_master_ops);
  420. return 0;
  421. }
  422. static struct platform_driver malidp_platform_driver = {
  423. .probe = malidp_platform_probe,
  424. .remove = malidp_platform_remove,
  425. .driver = {
  426. .name = "mali-dp",
  427. .of_match_table = malidp_drm_of_match,
  428. },
  429. };
  430. module_platform_driver(malidp_platform_driver);
  431. MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
  432. MODULE_DESCRIPTION("ARM Mali DP DRM driver");
  433. MODULE_LICENSE("GPL v2");