gpio-pca953x.c 22 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/acpi.h>
  23. #define PCA953X_INPUT 0
  24. #define PCA953X_OUTPUT 1
  25. #define PCA953X_INVERT 2
  26. #define PCA953X_DIRECTION 3
  27. #define REG_ADDR_AI 0x80
  28. #define PCA957X_IN 0
  29. #define PCA957X_INVRT 1
  30. #define PCA957X_BKEN 2
  31. #define PCA957X_PUPD 3
  32. #define PCA957X_CFG 4
  33. #define PCA957X_OUT 5
  34. #define PCA957X_MSK 6
  35. #define PCA957X_INTS 7
  36. #define PCAL953X_IN_LATCH 34
  37. #define PCAL953X_INT_MASK 37
  38. #define PCAL953X_INT_STAT 38
  39. #define PCA_GPIO_MASK 0x00FF
  40. #define PCA_INT 0x0100
  41. #define PCA_PCAL 0x0200
  42. #define PCA953X_TYPE 0x1000
  43. #define PCA957X_TYPE 0x2000
  44. #define PCA_TYPE_MASK 0xF000
  45. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  46. static const struct i2c_device_id pca953x_id[] = {
  47. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9536", 4 | PCA953X_TYPE, },
  51. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  53. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  54. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  55. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  56. { "pca9556", 8 | PCA953X_TYPE, },
  57. { "pca9557", 8 | PCA953X_TYPE, },
  58. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  59. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  60. { "pca9698", 40 | PCA953X_TYPE, },
  61. { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  62. { "max7310", 8 | PCA953X_TYPE, },
  63. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  64. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  65. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  66. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  67. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  68. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  69. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  70. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  71. { "xra1202", 8 | PCA953X_TYPE },
  72. { }
  73. };
  74. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  75. static const struct acpi_device_id pca953x_acpi_ids[] = {
  76. { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  77. { }
  78. };
  79. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  80. #define MAX_BANK 5
  81. #define BANK_SZ 8
  82. #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
  83. struct pca953x_chip {
  84. unsigned gpio_start;
  85. u8 reg_output[MAX_BANK];
  86. u8 reg_direction[MAX_BANK];
  87. struct mutex i2c_lock;
  88. #ifdef CONFIG_GPIO_PCA953X_IRQ
  89. struct mutex irq_lock;
  90. u8 irq_mask[MAX_BANK];
  91. u8 irq_stat[MAX_BANK];
  92. u8 irq_trig_raise[MAX_BANK];
  93. u8 irq_trig_fall[MAX_BANK];
  94. #endif
  95. struct i2c_client *client;
  96. struct gpio_chip gpio_chip;
  97. const char *const *names;
  98. int chip_type;
  99. unsigned long driver_data;
  100. };
  101. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  102. int off)
  103. {
  104. int ret;
  105. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  106. int offset = off / BANK_SZ;
  107. ret = i2c_smbus_read_byte_data(chip->client,
  108. (reg << bank_shift) + offset);
  109. *val = ret;
  110. if (ret < 0) {
  111. dev_err(&chip->client->dev, "failed reading register\n");
  112. return ret;
  113. }
  114. return 0;
  115. }
  116. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  117. int off)
  118. {
  119. int ret;
  120. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  121. int offset = off / BANK_SZ;
  122. ret = i2c_smbus_write_byte_data(chip->client,
  123. (reg << bank_shift) + offset, val);
  124. if (ret < 0) {
  125. dev_err(&chip->client->dev, "failed writing register\n");
  126. return ret;
  127. }
  128. return 0;
  129. }
  130. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  131. {
  132. int ret = 0;
  133. if (chip->gpio_chip.ngpio <= 8)
  134. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  135. else if (chip->gpio_chip.ngpio >= 24) {
  136. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  137. ret = i2c_smbus_write_i2c_block_data(chip->client,
  138. (reg << bank_shift) | REG_ADDR_AI,
  139. NBANK(chip), val);
  140. } else {
  141. switch (chip->chip_type) {
  142. case PCA953X_TYPE: {
  143. __le16 word = cpu_to_le16(get_unaligned((u16 *)val));
  144. ret = i2c_smbus_write_word_data(chip->client, reg << 1,
  145. (__force u16)word);
  146. break;
  147. }
  148. case PCA957X_TYPE:
  149. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  150. val[0]);
  151. if (ret < 0)
  152. break;
  153. ret = i2c_smbus_write_byte_data(chip->client,
  154. (reg << 1) + 1,
  155. val[1]);
  156. break;
  157. }
  158. }
  159. if (ret < 0) {
  160. dev_err(&chip->client->dev, "failed writing register\n");
  161. return ret;
  162. }
  163. return 0;
  164. }
  165. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  166. {
  167. int ret;
  168. if (chip->gpio_chip.ngpio <= 8) {
  169. ret = i2c_smbus_read_byte_data(chip->client, reg);
  170. *val = ret;
  171. } else if (chip->gpio_chip.ngpio >= 24) {
  172. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  173. ret = i2c_smbus_read_i2c_block_data(chip->client,
  174. (reg << bank_shift) | REG_ADDR_AI,
  175. NBANK(chip), val);
  176. } else {
  177. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  178. val[0] = (u16)ret & 0xFF;
  179. val[1] = (u16)ret >> 8;
  180. }
  181. if (ret < 0) {
  182. dev_err(&chip->client->dev, "failed reading register\n");
  183. return ret;
  184. }
  185. return 0;
  186. }
  187. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  188. {
  189. struct pca953x_chip *chip = gpiochip_get_data(gc);
  190. u8 reg_val;
  191. int ret, offset = 0;
  192. mutex_lock(&chip->i2c_lock);
  193. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  194. switch (chip->chip_type) {
  195. case PCA953X_TYPE:
  196. offset = PCA953X_DIRECTION;
  197. break;
  198. case PCA957X_TYPE:
  199. offset = PCA957X_CFG;
  200. break;
  201. }
  202. ret = pca953x_write_single(chip, offset, reg_val, off);
  203. if (ret)
  204. goto exit;
  205. chip->reg_direction[off / BANK_SZ] = reg_val;
  206. exit:
  207. mutex_unlock(&chip->i2c_lock);
  208. return ret;
  209. }
  210. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  211. unsigned off, int val)
  212. {
  213. struct pca953x_chip *chip = gpiochip_get_data(gc);
  214. u8 reg_val;
  215. int ret, offset = 0;
  216. mutex_lock(&chip->i2c_lock);
  217. /* set output level */
  218. if (val)
  219. reg_val = chip->reg_output[off / BANK_SZ]
  220. | (1u << (off % BANK_SZ));
  221. else
  222. reg_val = chip->reg_output[off / BANK_SZ]
  223. & ~(1u << (off % BANK_SZ));
  224. switch (chip->chip_type) {
  225. case PCA953X_TYPE:
  226. offset = PCA953X_OUTPUT;
  227. break;
  228. case PCA957X_TYPE:
  229. offset = PCA957X_OUT;
  230. break;
  231. }
  232. ret = pca953x_write_single(chip, offset, reg_val, off);
  233. if (ret)
  234. goto exit;
  235. chip->reg_output[off / BANK_SZ] = reg_val;
  236. /* then direction */
  237. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  238. switch (chip->chip_type) {
  239. case PCA953X_TYPE:
  240. offset = PCA953X_DIRECTION;
  241. break;
  242. case PCA957X_TYPE:
  243. offset = PCA957X_CFG;
  244. break;
  245. }
  246. ret = pca953x_write_single(chip, offset, reg_val, off);
  247. if (ret)
  248. goto exit;
  249. chip->reg_direction[off / BANK_SZ] = reg_val;
  250. exit:
  251. mutex_unlock(&chip->i2c_lock);
  252. return ret;
  253. }
  254. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  255. {
  256. struct pca953x_chip *chip = gpiochip_get_data(gc);
  257. u32 reg_val;
  258. int ret, offset = 0;
  259. mutex_lock(&chip->i2c_lock);
  260. switch (chip->chip_type) {
  261. case PCA953X_TYPE:
  262. offset = PCA953X_INPUT;
  263. break;
  264. case PCA957X_TYPE:
  265. offset = PCA957X_IN;
  266. break;
  267. }
  268. ret = pca953x_read_single(chip, offset, &reg_val, off);
  269. mutex_unlock(&chip->i2c_lock);
  270. if (ret < 0) {
  271. /* NOTE: diagnostic already emitted; that's all we should
  272. * do unless gpio_*_value_cansleep() calls become different
  273. * from their nonsleeping siblings (and report faults).
  274. */
  275. return 0;
  276. }
  277. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  278. }
  279. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  280. {
  281. struct pca953x_chip *chip = gpiochip_get_data(gc);
  282. u8 reg_val;
  283. int ret, offset = 0;
  284. mutex_lock(&chip->i2c_lock);
  285. if (val)
  286. reg_val = chip->reg_output[off / BANK_SZ]
  287. | (1u << (off % BANK_SZ));
  288. else
  289. reg_val = chip->reg_output[off / BANK_SZ]
  290. & ~(1u << (off % BANK_SZ));
  291. switch (chip->chip_type) {
  292. case PCA953X_TYPE:
  293. offset = PCA953X_OUTPUT;
  294. break;
  295. case PCA957X_TYPE:
  296. offset = PCA957X_OUT;
  297. break;
  298. }
  299. ret = pca953x_write_single(chip, offset, reg_val, off);
  300. if (ret)
  301. goto exit;
  302. chip->reg_output[off / BANK_SZ] = reg_val;
  303. exit:
  304. mutex_unlock(&chip->i2c_lock);
  305. }
  306. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  307. unsigned long *mask, unsigned long *bits)
  308. {
  309. struct pca953x_chip *chip = gpiochip_get_data(gc);
  310. u8 reg_val[MAX_BANK];
  311. int ret, offset = 0;
  312. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  313. int bank;
  314. switch (chip->chip_type) {
  315. case PCA953X_TYPE:
  316. offset = PCA953X_OUTPUT;
  317. break;
  318. case PCA957X_TYPE:
  319. offset = PCA957X_OUT;
  320. break;
  321. }
  322. memcpy(reg_val, chip->reg_output, NBANK(chip));
  323. mutex_lock(&chip->i2c_lock);
  324. for(bank=0; bank<NBANK(chip); bank++) {
  325. unsigned bankmask = mask[bank / sizeof(*mask)] >>
  326. ((bank % sizeof(*mask)) * 8);
  327. if(bankmask) {
  328. unsigned bankval = bits[bank / sizeof(*bits)] >>
  329. ((bank % sizeof(*bits)) * 8);
  330. reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
  331. }
  332. }
  333. ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
  334. if (ret)
  335. goto exit;
  336. memcpy(chip->reg_output, reg_val, NBANK(chip));
  337. exit:
  338. mutex_unlock(&chip->i2c_lock);
  339. }
  340. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  341. {
  342. struct gpio_chip *gc;
  343. gc = &chip->gpio_chip;
  344. gc->direction_input = pca953x_gpio_direction_input;
  345. gc->direction_output = pca953x_gpio_direction_output;
  346. gc->get = pca953x_gpio_get_value;
  347. gc->set = pca953x_gpio_set_value;
  348. gc->set_multiple = pca953x_gpio_set_multiple;
  349. gc->can_sleep = true;
  350. gc->base = chip->gpio_start;
  351. gc->ngpio = gpios;
  352. gc->label = chip->client->name;
  353. gc->parent = &chip->client->dev;
  354. gc->owner = THIS_MODULE;
  355. gc->names = chip->names;
  356. }
  357. #ifdef CONFIG_GPIO_PCA953X_IRQ
  358. static void pca953x_irq_mask(struct irq_data *d)
  359. {
  360. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  361. struct pca953x_chip *chip = gpiochip_get_data(gc);
  362. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  363. }
  364. static void pca953x_irq_unmask(struct irq_data *d)
  365. {
  366. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  367. struct pca953x_chip *chip = gpiochip_get_data(gc);
  368. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  369. }
  370. static void pca953x_irq_bus_lock(struct irq_data *d)
  371. {
  372. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  373. struct pca953x_chip *chip = gpiochip_get_data(gc);
  374. mutex_lock(&chip->irq_lock);
  375. }
  376. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  377. {
  378. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  379. struct pca953x_chip *chip = gpiochip_get_data(gc);
  380. u8 new_irqs;
  381. int level, i;
  382. u8 invert_irq_mask[MAX_BANK];
  383. if (chip->driver_data & PCA_PCAL) {
  384. /* Enable latch on interrupt-enabled inputs */
  385. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  386. for (i = 0; i < NBANK(chip); i++)
  387. invert_irq_mask[i] = ~chip->irq_mask[i];
  388. /* Unmask enabled interrupts */
  389. pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
  390. }
  391. /* Look for any newly setup interrupt */
  392. for (i = 0; i < NBANK(chip); i++) {
  393. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  394. new_irqs &= ~chip->reg_direction[i];
  395. while (new_irqs) {
  396. level = __ffs(new_irqs);
  397. pca953x_gpio_direction_input(&chip->gpio_chip,
  398. level + (BANK_SZ * i));
  399. new_irqs &= ~(1 << level);
  400. }
  401. }
  402. mutex_unlock(&chip->irq_lock);
  403. }
  404. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  405. {
  406. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  407. struct pca953x_chip *chip = gpiochip_get_data(gc);
  408. int bank_nb = d->hwirq / BANK_SZ;
  409. u8 mask = 1 << (d->hwirq % BANK_SZ);
  410. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  411. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  412. d->irq, type);
  413. return -EINVAL;
  414. }
  415. if (type & IRQ_TYPE_EDGE_FALLING)
  416. chip->irq_trig_fall[bank_nb] |= mask;
  417. else
  418. chip->irq_trig_fall[bank_nb] &= ~mask;
  419. if (type & IRQ_TYPE_EDGE_RISING)
  420. chip->irq_trig_raise[bank_nb] |= mask;
  421. else
  422. chip->irq_trig_raise[bank_nb] &= ~mask;
  423. return 0;
  424. }
  425. static struct irq_chip pca953x_irq_chip = {
  426. .name = "pca953x",
  427. .irq_mask = pca953x_irq_mask,
  428. .irq_unmask = pca953x_irq_unmask,
  429. .irq_bus_lock = pca953x_irq_bus_lock,
  430. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  431. .irq_set_type = pca953x_irq_set_type,
  432. };
  433. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  434. {
  435. u8 cur_stat[MAX_BANK];
  436. u8 old_stat[MAX_BANK];
  437. bool pending_seen = false;
  438. bool trigger_seen = false;
  439. u8 trigger[MAX_BANK];
  440. int ret, i, offset = 0;
  441. if (chip->driver_data & PCA_PCAL) {
  442. /* Read the current interrupt status from the device */
  443. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  444. if (ret)
  445. return false;
  446. /* Check latched inputs and clear interrupt status */
  447. ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
  448. if (ret)
  449. return false;
  450. for (i = 0; i < NBANK(chip); i++) {
  451. /* Apply filter for rising/falling edge selection */
  452. pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
  453. (cur_stat[i] & chip->irq_trig_raise[i]);
  454. pending[i] &= trigger[i];
  455. if (pending[i])
  456. pending_seen = true;
  457. }
  458. return pending_seen;
  459. }
  460. switch (chip->chip_type) {
  461. case PCA953X_TYPE:
  462. offset = PCA953X_INPUT;
  463. break;
  464. case PCA957X_TYPE:
  465. offset = PCA957X_IN;
  466. break;
  467. }
  468. ret = pca953x_read_regs(chip, offset, cur_stat);
  469. if (ret)
  470. return false;
  471. /* Remove output pins from the equation */
  472. for (i = 0; i < NBANK(chip); i++)
  473. cur_stat[i] &= chip->reg_direction[i];
  474. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  475. for (i = 0; i < NBANK(chip); i++) {
  476. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  477. if (trigger[i])
  478. trigger_seen = true;
  479. }
  480. if (!trigger_seen)
  481. return false;
  482. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  483. for (i = 0; i < NBANK(chip); i++) {
  484. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  485. (cur_stat[i] & chip->irq_trig_raise[i]);
  486. pending[i] &= trigger[i];
  487. if (pending[i])
  488. pending_seen = true;
  489. }
  490. return pending_seen;
  491. }
  492. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  493. {
  494. struct pca953x_chip *chip = devid;
  495. u8 pending[MAX_BANK];
  496. u8 level;
  497. unsigned nhandled = 0;
  498. int i;
  499. if (!pca953x_irq_pending(chip, pending))
  500. return IRQ_NONE;
  501. for (i = 0; i < NBANK(chip); i++) {
  502. while (pending[i]) {
  503. level = __ffs(pending[i]);
  504. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  505. level + (BANK_SZ * i)));
  506. pending[i] &= ~(1 << level);
  507. nhandled++;
  508. }
  509. }
  510. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  511. }
  512. static int pca953x_irq_setup(struct pca953x_chip *chip,
  513. int irq_base)
  514. {
  515. struct i2c_client *client = chip->client;
  516. int ret, i, offset = 0;
  517. if (client->irq && irq_base != -1
  518. && (chip->driver_data & PCA_INT)) {
  519. switch (chip->chip_type) {
  520. case PCA953X_TYPE:
  521. offset = PCA953X_INPUT;
  522. break;
  523. case PCA957X_TYPE:
  524. offset = PCA957X_IN;
  525. break;
  526. }
  527. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  528. if (ret)
  529. return ret;
  530. /*
  531. * There is no way to know which GPIO line generated the
  532. * interrupt. We have to rely on the previous read for
  533. * this purpose.
  534. */
  535. for (i = 0; i < NBANK(chip); i++)
  536. chip->irq_stat[i] &= chip->reg_direction[i];
  537. mutex_init(&chip->irq_lock);
  538. ret = devm_request_threaded_irq(&client->dev,
  539. client->irq,
  540. NULL,
  541. pca953x_irq_handler,
  542. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  543. IRQF_SHARED,
  544. dev_name(&client->dev), chip);
  545. if (ret) {
  546. dev_err(&client->dev, "failed to request irq %d\n",
  547. client->irq);
  548. return ret;
  549. }
  550. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  551. &pca953x_irq_chip,
  552. irq_base,
  553. handle_simple_irq,
  554. IRQ_TYPE_NONE);
  555. if (ret) {
  556. dev_err(&client->dev,
  557. "could not connect irqchip to gpiochip\n");
  558. return ret;
  559. }
  560. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  561. &pca953x_irq_chip,
  562. client->irq, NULL);
  563. }
  564. return 0;
  565. }
  566. #else /* CONFIG_GPIO_PCA953X_IRQ */
  567. static int pca953x_irq_setup(struct pca953x_chip *chip,
  568. int irq_base)
  569. {
  570. struct i2c_client *client = chip->client;
  571. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  572. dev_warn(&client->dev, "interrupt support not compiled in\n");
  573. return 0;
  574. }
  575. #endif
  576. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  577. {
  578. int ret;
  579. u8 val[MAX_BANK];
  580. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  581. if (ret)
  582. goto out;
  583. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  584. chip->reg_direction);
  585. if (ret)
  586. goto out;
  587. /* set platform specific polarity inversion */
  588. if (invert)
  589. memset(val, 0xFF, NBANK(chip));
  590. else
  591. memset(val, 0, NBANK(chip));
  592. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  593. out:
  594. return ret;
  595. }
  596. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  597. {
  598. int ret;
  599. u8 val[MAX_BANK];
  600. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  601. if (ret)
  602. goto out;
  603. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  604. if (ret)
  605. goto out;
  606. /* set platform specific polarity inversion */
  607. if (invert)
  608. memset(val, 0xFF, NBANK(chip));
  609. else
  610. memset(val, 0, NBANK(chip));
  611. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  612. if (ret)
  613. goto out;
  614. /* To enable register 6, 7 to control pull up and pull down */
  615. memset(val, 0x02, NBANK(chip));
  616. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  617. if (ret)
  618. goto out;
  619. return 0;
  620. out:
  621. return ret;
  622. }
  623. static const struct of_device_id pca953x_dt_ids[];
  624. static int pca953x_probe(struct i2c_client *client,
  625. const struct i2c_device_id *id)
  626. {
  627. struct pca953x_platform_data *pdata;
  628. struct pca953x_chip *chip;
  629. int irq_base = 0;
  630. int ret;
  631. u32 invert = 0;
  632. chip = devm_kzalloc(&client->dev,
  633. sizeof(struct pca953x_chip), GFP_KERNEL);
  634. if (chip == NULL)
  635. return -ENOMEM;
  636. pdata = dev_get_platdata(&client->dev);
  637. if (pdata) {
  638. irq_base = pdata->irq_base;
  639. chip->gpio_start = pdata->gpio_base;
  640. invert = pdata->invert;
  641. chip->names = pdata->names;
  642. } else {
  643. chip->gpio_start = -1;
  644. irq_base = 0;
  645. }
  646. chip->client = client;
  647. if (id) {
  648. chip->driver_data = id->driver_data;
  649. } else {
  650. const struct acpi_device_id *id;
  651. const struct of_device_id *match;
  652. match = of_match_device(pca953x_dt_ids, &client->dev);
  653. if (match) {
  654. chip->driver_data = (int)(uintptr_t)match->data;
  655. } else {
  656. id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  657. if (!id)
  658. return -ENODEV;
  659. chip->driver_data = id->driver_data;
  660. }
  661. }
  662. chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
  663. mutex_init(&chip->i2c_lock);
  664. /* initialize cached registers from their original values.
  665. * we can't share this chip with another i2c master.
  666. */
  667. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  668. if (chip->chip_type == PCA953X_TYPE)
  669. ret = device_pca953x_init(chip, invert);
  670. else
  671. ret = device_pca957x_init(chip, invert);
  672. if (ret)
  673. return ret;
  674. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  675. if (ret)
  676. return ret;
  677. ret = pca953x_irq_setup(chip, irq_base);
  678. if (ret)
  679. return ret;
  680. if (pdata && pdata->setup) {
  681. ret = pdata->setup(client, chip->gpio_chip.base,
  682. chip->gpio_chip.ngpio, pdata->context);
  683. if (ret < 0)
  684. dev_warn(&client->dev, "setup failed, %d\n", ret);
  685. }
  686. i2c_set_clientdata(client, chip);
  687. return 0;
  688. }
  689. static int pca953x_remove(struct i2c_client *client)
  690. {
  691. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  692. struct pca953x_chip *chip = i2c_get_clientdata(client);
  693. int ret;
  694. if (pdata && pdata->teardown) {
  695. ret = pdata->teardown(client, chip->gpio_chip.base,
  696. chip->gpio_chip.ngpio, pdata->context);
  697. if (ret < 0) {
  698. dev_err(&client->dev, "%s failed, %d\n",
  699. "teardown", ret);
  700. return ret;
  701. }
  702. }
  703. return 0;
  704. }
  705. /* convenience to stop overlong match-table lines */
  706. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  707. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  708. static const struct of_device_id pca953x_dt_ids[] = {
  709. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  710. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  711. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  712. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  713. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  714. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  715. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  716. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  717. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  718. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  719. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  720. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  721. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  722. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  723. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  724. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  725. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  726. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  727. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  728. { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
  729. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  730. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  731. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  732. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  733. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  734. { }
  735. };
  736. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  737. static struct i2c_driver pca953x_driver = {
  738. .driver = {
  739. .name = "pca953x",
  740. .of_match_table = pca953x_dt_ids,
  741. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  742. },
  743. .probe = pca953x_probe,
  744. .remove = pca953x_remove,
  745. .id_table = pca953x_id,
  746. };
  747. static int __init pca953x_init(void)
  748. {
  749. return i2c_add_driver(&pca953x_driver);
  750. }
  751. /* register after i2c postcore initcall and before
  752. * subsys initcalls that may rely on these GPIOs
  753. */
  754. subsys_initcall(pca953x_init);
  755. static void __exit pca953x_exit(void)
  756. {
  757. i2c_del_driver(&pca953x_driver);
  758. }
  759. module_exit(pca953x_exit);
  760. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  761. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  762. MODULE_LICENSE("GPL");