ccp-dev.h 10 KB

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  1. /*
  2. * AMD Cryptographic Coprocessor (CCP) driver
  3. *
  4. * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
  5. *
  6. * Author: Tom Lendacky <thomas.lendacky@amd.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef __CCP_DEV_H__
  13. #define __CCP_DEV_H__
  14. #include <linux/device.h>
  15. #include <linux/pci.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/mutex.h>
  18. #include <linux/list.h>
  19. #include <linux/wait.h>
  20. #include <linux/dmapool.h>
  21. #include <linux/hw_random.h>
  22. #include <linux/bitops.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irqreturn.h>
  25. #include <linux/dmaengine.h>
  26. #define MAX_CCP_NAME_LEN 16
  27. #define MAX_DMAPOOL_NAME_LEN 32
  28. #define MAX_HW_QUEUES 5
  29. #define MAX_CMD_QLEN 100
  30. #define TRNG_RETRIES 10
  31. #define CACHE_NONE 0x00
  32. #define CACHE_WB_NO_ALLOC 0xb7
  33. /****** Register Mappings ******/
  34. #define Q_MASK_REG 0x000
  35. #define TRNG_OUT_REG 0x00c
  36. #define IRQ_MASK_REG 0x040
  37. #define IRQ_STATUS_REG 0x200
  38. #define DEL_CMD_Q_JOB 0x124
  39. #define DEL_Q_ACTIVE 0x00000200
  40. #define DEL_Q_ID_SHIFT 6
  41. #define CMD_REQ0 0x180
  42. #define CMD_REQ_INCR 0x04
  43. #define CMD_Q_STATUS_BASE 0x210
  44. #define CMD_Q_INT_STATUS_BASE 0x214
  45. #define CMD_Q_STATUS_INCR 0x20
  46. #define CMD_Q_CACHE_BASE 0x228
  47. #define CMD_Q_CACHE_INC 0x20
  48. #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
  49. #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
  50. /****** REQ0 Related Values ******/
  51. #define REQ0_WAIT_FOR_WRITE 0x00000004
  52. #define REQ0_INT_ON_COMPLETE 0x00000002
  53. #define REQ0_STOP_ON_COMPLETE 0x00000001
  54. #define REQ0_CMD_Q_SHIFT 9
  55. #define REQ0_JOBID_SHIFT 3
  56. /****** REQ1 Related Values ******/
  57. #define REQ1_PROTECT_SHIFT 27
  58. #define REQ1_ENGINE_SHIFT 23
  59. #define REQ1_KEY_KSB_SHIFT 2
  60. #define REQ1_EOM 0x00000002
  61. #define REQ1_INIT 0x00000001
  62. /* AES Related Values */
  63. #define REQ1_AES_TYPE_SHIFT 21
  64. #define REQ1_AES_MODE_SHIFT 18
  65. #define REQ1_AES_ACTION_SHIFT 17
  66. #define REQ1_AES_CFB_SIZE_SHIFT 10
  67. /* XTS-AES Related Values */
  68. #define REQ1_XTS_AES_SIZE_SHIFT 10
  69. /* SHA Related Values */
  70. #define REQ1_SHA_TYPE_SHIFT 21
  71. /* RSA Related Values */
  72. #define REQ1_RSA_MOD_SIZE_SHIFT 10
  73. /* Pass-Through Related Values */
  74. #define REQ1_PT_BW_SHIFT 12
  75. #define REQ1_PT_BS_SHIFT 10
  76. /* ECC Related Values */
  77. #define REQ1_ECC_AFFINE_CONVERT 0x00200000
  78. #define REQ1_ECC_FUNCTION_SHIFT 18
  79. /****** REQ4 Related Values ******/
  80. #define REQ4_KSB_SHIFT 18
  81. #define REQ4_MEMTYPE_SHIFT 16
  82. /****** REQ6 Related Values ******/
  83. #define REQ6_MEMTYPE_SHIFT 16
  84. /****** Key Storage Block ******/
  85. #define KSB_START 77
  86. #define KSB_END 127
  87. #define KSB_COUNT (KSB_END - KSB_START + 1)
  88. #define CCP_KSB_BITS 256
  89. #define CCP_KSB_BYTES 32
  90. #define CCP_JOBID_MASK 0x0000003f
  91. #define CCP_DMAPOOL_MAX_SIZE 64
  92. #define CCP_DMAPOOL_ALIGN BIT(5)
  93. #define CCP_REVERSE_BUF_SIZE 64
  94. #define CCP_AES_KEY_KSB_COUNT 1
  95. #define CCP_AES_CTX_KSB_COUNT 1
  96. #define CCP_XTS_AES_KEY_KSB_COUNT 1
  97. #define CCP_XTS_AES_CTX_KSB_COUNT 1
  98. #define CCP_SHA_KSB_COUNT 1
  99. #define CCP_RSA_MAX_WIDTH 4096
  100. #define CCP_PASSTHRU_BLOCKSIZE 256
  101. #define CCP_PASSTHRU_MASKSIZE 32
  102. #define CCP_PASSTHRU_KSB_COUNT 1
  103. #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
  104. #define CCP_ECC_MAX_OPERANDS 6
  105. #define CCP_ECC_MAX_OUTPUTS 3
  106. #define CCP_ECC_SRC_BUF_SIZE 448
  107. #define CCP_ECC_DST_BUF_SIZE 192
  108. #define CCP_ECC_OPERAND_SIZE 64
  109. #define CCP_ECC_OUTPUT_SIZE 64
  110. #define CCP_ECC_RESULT_OFFSET 60
  111. #define CCP_ECC_RESULT_SUCCESS 0x0001
  112. struct ccp_op;
  113. /* Structure for computation functions that are device-specific */
  114. struct ccp_actions {
  115. int (*perform_aes)(struct ccp_op *);
  116. int (*perform_xts_aes)(struct ccp_op *);
  117. int (*perform_sha)(struct ccp_op *);
  118. int (*perform_rsa)(struct ccp_op *);
  119. int (*perform_passthru)(struct ccp_op *);
  120. int (*perform_ecc)(struct ccp_op *);
  121. int (*init)(struct ccp_device *);
  122. void (*destroy)(struct ccp_device *);
  123. irqreturn_t (*irqhandler)(int, void *);
  124. };
  125. /* Structure to hold CCP version-specific values */
  126. struct ccp_vdata {
  127. unsigned int version;
  128. const struct ccp_actions *perform;
  129. };
  130. extern struct ccp_vdata ccpv3;
  131. struct ccp_device;
  132. struct ccp_cmd;
  133. struct ccp_dma_cmd {
  134. struct list_head entry;
  135. struct ccp_cmd ccp_cmd;
  136. };
  137. struct ccp_dma_desc {
  138. struct list_head entry;
  139. struct ccp_device *ccp;
  140. struct list_head pending;
  141. struct list_head active;
  142. enum dma_status status;
  143. struct dma_async_tx_descriptor tx_desc;
  144. size_t len;
  145. };
  146. struct ccp_dma_chan {
  147. struct ccp_device *ccp;
  148. spinlock_t lock;
  149. struct list_head pending;
  150. struct list_head active;
  151. struct list_head complete;
  152. struct tasklet_struct cleanup_tasklet;
  153. enum dma_status status;
  154. struct dma_chan dma_chan;
  155. };
  156. struct ccp_cmd_queue {
  157. struct ccp_device *ccp;
  158. /* Queue identifier */
  159. u32 id;
  160. /* Queue dma pool */
  161. struct dma_pool *dma_pool;
  162. /* Queue reserved KSB regions */
  163. u32 ksb_key;
  164. u32 ksb_ctx;
  165. /* Queue processing thread */
  166. struct task_struct *kthread;
  167. unsigned int active;
  168. unsigned int suspended;
  169. /* Number of free command slots available */
  170. unsigned int free_slots;
  171. /* Interrupt masks */
  172. u32 int_ok;
  173. u32 int_err;
  174. /* Register addresses for queue */
  175. void __iomem *reg_status;
  176. void __iomem *reg_int_status;
  177. /* Status values from job */
  178. u32 int_status;
  179. u32 q_status;
  180. u32 q_int_status;
  181. u32 cmd_error;
  182. /* Interrupt wait queue */
  183. wait_queue_head_t int_queue;
  184. unsigned int int_rcvd;
  185. } ____cacheline_aligned;
  186. struct ccp_device {
  187. struct list_head entry;
  188. struct ccp_vdata *vdata;
  189. unsigned int ord;
  190. char name[MAX_CCP_NAME_LEN];
  191. char rngname[MAX_CCP_NAME_LEN];
  192. struct device *dev;
  193. /*
  194. * Bus specific device information
  195. */
  196. void *dev_specific;
  197. int (*get_irq)(struct ccp_device *ccp);
  198. void (*free_irq)(struct ccp_device *ccp);
  199. unsigned int irq;
  200. /*
  201. * I/O area used for device communication. The register mapping
  202. * starts at an offset into the mapped bar.
  203. * The CMD_REQx registers and the Delete_Cmd_Queue_Job register
  204. * need to be protected while a command queue thread is accessing
  205. * them.
  206. */
  207. struct mutex req_mutex ____cacheline_aligned;
  208. void __iomem *io_map;
  209. void __iomem *io_regs;
  210. /*
  211. * Master lists that all cmds are queued on. Because there can be
  212. * more than one CCP command queue that can process a cmd a separate
  213. * backlog list is neeeded so that the backlog completion call
  214. * completes before the cmd is available for execution.
  215. */
  216. spinlock_t cmd_lock ____cacheline_aligned;
  217. unsigned int cmd_count;
  218. struct list_head cmd;
  219. struct list_head backlog;
  220. /*
  221. * The command queues. These represent the queues available on the
  222. * CCP that are available for processing cmds
  223. */
  224. struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
  225. unsigned int cmd_q_count;
  226. /*
  227. * Support for the CCP True RNG
  228. */
  229. struct hwrng hwrng;
  230. unsigned int hwrng_retries;
  231. /*
  232. * Support for the CCP DMA capabilities
  233. */
  234. struct dma_device dma_dev;
  235. struct ccp_dma_chan *ccp_dma_chan;
  236. struct kmem_cache *dma_cmd_cache;
  237. struct kmem_cache *dma_desc_cache;
  238. /*
  239. * A counter used to generate job-ids for cmds submitted to the CCP
  240. */
  241. atomic_t current_id ____cacheline_aligned;
  242. /*
  243. * The CCP uses key storage blocks (KSB) to maintain context for certain
  244. * operations. To prevent multiple cmds from using the same KSB range
  245. * a command queue reserves a KSB range for the duration of the cmd.
  246. * Each queue, will however, reserve 2 KSB blocks for operations that
  247. * only require single KSB entries (eg. AES context/iv and key) in order
  248. * to avoid allocation contention. This will reserve at most 10 KSB
  249. * entries, leaving 40 KSB entries available for dynamic allocation.
  250. */
  251. struct mutex ksb_mutex ____cacheline_aligned;
  252. DECLARE_BITMAP(ksb, KSB_COUNT);
  253. wait_queue_head_t ksb_queue;
  254. unsigned int ksb_avail;
  255. unsigned int ksb_count;
  256. u32 ksb_start;
  257. /* Suspend support */
  258. unsigned int suspending;
  259. wait_queue_head_t suspend_queue;
  260. /* DMA caching attribute support */
  261. unsigned int axcache;
  262. };
  263. enum ccp_memtype {
  264. CCP_MEMTYPE_SYSTEM = 0,
  265. CCP_MEMTYPE_KSB,
  266. CCP_MEMTYPE_LOCAL,
  267. CCP_MEMTYPE__LAST,
  268. };
  269. struct ccp_dma_info {
  270. dma_addr_t address;
  271. unsigned int offset;
  272. unsigned int length;
  273. enum dma_data_direction dir;
  274. };
  275. struct ccp_dm_workarea {
  276. struct device *dev;
  277. struct dma_pool *dma_pool;
  278. unsigned int length;
  279. u8 *address;
  280. struct ccp_dma_info dma;
  281. };
  282. struct ccp_sg_workarea {
  283. struct scatterlist *sg;
  284. int nents;
  285. struct scatterlist *dma_sg;
  286. struct device *dma_dev;
  287. unsigned int dma_count;
  288. enum dma_data_direction dma_dir;
  289. unsigned int sg_used;
  290. u64 bytes_left;
  291. };
  292. struct ccp_data {
  293. struct ccp_sg_workarea sg_wa;
  294. struct ccp_dm_workarea dm_wa;
  295. };
  296. struct ccp_mem {
  297. enum ccp_memtype type;
  298. union {
  299. struct ccp_dma_info dma;
  300. u32 ksb;
  301. } u;
  302. };
  303. struct ccp_aes_op {
  304. enum ccp_aes_type type;
  305. enum ccp_aes_mode mode;
  306. enum ccp_aes_action action;
  307. };
  308. struct ccp_xts_aes_op {
  309. enum ccp_aes_action action;
  310. enum ccp_xts_aes_unit_size unit_size;
  311. };
  312. struct ccp_sha_op {
  313. enum ccp_sha_type type;
  314. u64 msg_bits;
  315. };
  316. struct ccp_rsa_op {
  317. u32 mod_size;
  318. u32 input_len;
  319. };
  320. struct ccp_passthru_op {
  321. enum ccp_passthru_bitwise bit_mod;
  322. enum ccp_passthru_byteswap byte_swap;
  323. };
  324. struct ccp_ecc_op {
  325. enum ccp_ecc_function function;
  326. };
  327. struct ccp_op {
  328. struct ccp_cmd_queue *cmd_q;
  329. u32 jobid;
  330. u32 ioc;
  331. u32 soc;
  332. u32 ksb_key;
  333. u32 ksb_ctx;
  334. u32 init;
  335. u32 eom;
  336. struct ccp_mem src;
  337. struct ccp_mem dst;
  338. union {
  339. struct ccp_aes_op aes;
  340. struct ccp_xts_aes_op xts;
  341. struct ccp_sha_op sha;
  342. struct ccp_rsa_op rsa;
  343. struct ccp_passthru_op passthru;
  344. struct ccp_ecc_op ecc;
  345. } u;
  346. };
  347. static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
  348. {
  349. return lower_32_bits(info->address + info->offset);
  350. }
  351. static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
  352. {
  353. return upper_32_bits(info->address + info->offset) & 0x0000ffff;
  354. }
  355. int ccp_pci_init(void);
  356. void ccp_pci_exit(void);
  357. int ccp_platform_init(void);
  358. void ccp_platform_exit(void);
  359. void ccp_add_device(struct ccp_device *ccp);
  360. void ccp_del_device(struct ccp_device *ccp);
  361. struct ccp_device *ccp_alloc_struct(struct device *dev);
  362. bool ccp_queues_suspended(struct ccp_device *ccp);
  363. int ccp_cmd_queue_thread(void *data);
  364. int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
  365. int ccp_dmaengine_register(struct ccp_device *ccp);
  366. void ccp_dmaengine_unregister(struct ccp_device *ccp);
  367. #endif