clk-mmp2.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456
  1. /*
  2. * mmp2 clock framework source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/io.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include "clk.h"
  19. #define APBC_RTC 0x0
  20. #define APBC_TWSI0 0x4
  21. #define APBC_TWSI1 0x8
  22. #define APBC_TWSI2 0xc
  23. #define APBC_TWSI3 0x10
  24. #define APBC_TWSI4 0x7c
  25. #define APBC_TWSI5 0x80
  26. #define APBC_KPC 0x18
  27. #define APBC_UART0 0x2c
  28. #define APBC_UART1 0x30
  29. #define APBC_UART2 0x34
  30. #define APBC_UART3 0x88
  31. #define APBC_GPIO 0x38
  32. #define APBC_PWM0 0x3c
  33. #define APBC_PWM1 0x40
  34. #define APBC_PWM2 0x44
  35. #define APBC_PWM3 0x48
  36. #define APBC_SSP0 0x50
  37. #define APBC_SSP1 0x54
  38. #define APBC_SSP2 0x58
  39. #define APBC_SSP3 0x5c
  40. #define APMU_SDH0 0x54
  41. #define APMU_SDH1 0x58
  42. #define APMU_SDH2 0xe8
  43. #define APMU_SDH3 0xec
  44. #define APMU_USB 0x5c
  45. #define APMU_DISP0 0x4c
  46. #define APMU_DISP1 0x110
  47. #define APMU_CCIC0 0x50
  48. #define APMU_CCIC1 0xf4
  49. #define MPMU_UART_PLL 0x14
  50. static DEFINE_SPINLOCK(clk_lock);
  51. static struct mmp_clk_factor_masks uart_factor_masks = {
  52. .factor = 2,
  53. .num_mask = 0x1fff,
  54. .den_mask = 0x1fff,
  55. .num_shift = 16,
  56. .den_shift = 0,
  57. };
  58. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  59. {.num = 8125, .den = 1536}, /*14.745MHZ */
  60. {.num = 3521, .den = 689}, /*19.23MHZ */
  61. };
  62. static const char *uart_parent[] = {"uart_pll", "vctcxo"};
  63. static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
  64. static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
  65. static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
  66. static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
  67. void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  68. phys_addr_t apbc_phys)
  69. {
  70. struct clk *clk;
  71. struct clk *vctcxo;
  72. void __iomem *mpmu_base;
  73. void __iomem *apmu_base;
  74. void __iomem *apbc_base;
  75. mpmu_base = ioremap(mpmu_phys, SZ_4K);
  76. if (mpmu_base == NULL) {
  77. pr_err("error to ioremap MPMU base\n");
  78. return;
  79. }
  80. apmu_base = ioremap(apmu_phys, SZ_4K);
  81. if (apmu_base == NULL) {
  82. pr_err("error to ioremap APMU base\n");
  83. return;
  84. }
  85. apbc_base = ioremap(apbc_phys, SZ_4K);
  86. if (apbc_base == NULL) {
  87. pr_err("error to ioremap APBC base\n");
  88. return;
  89. }
  90. clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
  91. clk_register_clkdev(clk, "clk32", NULL);
  92. vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
  93. clk_register_clkdev(vctcxo, "vctcxo", NULL);
  94. clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
  95. clk_register_clkdev(clk, "pll1", NULL);
  96. clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
  97. clk_register_clkdev(clk, "usb_pll", NULL);
  98. clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
  99. clk_register_clkdev(clk, "pll2", NULL);
  100. clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
  101. CLK_SET_RATE_PARENT, 1, 2);
  102. clk_register_clkdev(clk, "pll1_2", NULL);
  103. clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
  104. CLK_SET_RATE_PARENT, 1, 2);
  105. clk_register_clkdev(clk, "pll1_4", NULL);
  106. clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
  107. CLK_SET_RATE_PARENT, 1, 2);
  108. clk_register_clkdev(clk, "pll1_8", NULL);
  109. clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
  110. CLK_SET_RATE_PARENT, 1, 2);
  111. clk_register_clkdev(clk, "pll1_16", NULL);
  112. clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
  113. CLK_SET_RATE_PARENT, 1, 5);
  114. clk_register_clkdev(clk, "pll1_20", NULL);
  115. clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
  116. CLK_SET_RATE_PARENT, 1, 3);
  117. clk_register_clkdev(clk, "pll1_3", NULL);
  118. clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
  119. CLK_SET_RATE_PARENT, 1, 2);
  120. clk_register_clkdev(clk, "pll1_6", NULL);
  121. clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
  122. CLK_SET_RATE_PARENT, 1, 2);
  123. clk_register_clkdev(clk, "pll1_12", NULL);
  124. clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
  125. CLK_SET_RATE_PARENT, 1, 2);
  126. clk_register_clkdev(clk, "pll2_2", NULL);
  127. clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
  128. CLK_SET_RATE_PARENT, 1, 2);
  129. clk_register_clkdev(clk, "pll2_4", NULL);
  130. clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
  131. CLK_SET_RATE_PARENT, 1, 2);
  132. clk_register_clkdev(clk, "pll2_8", NULL);
  133. clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
  134. CLK_SET_RATE_PARENT, 1, 2);
  135. clk_register_clkdev(clk, "pll2_16", NULL);
  136. clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
  137. CLK_SET_RATE_PARENT, 1, 3);
  138. clk_register_clkdev(clk, "pll2_3", NULL);
  139. clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
  140. CLK_SET_RATE_PARENT, 1, 2);
  141. clk_register_clkdev(clk, "pll2_6", NULL);
  142. clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
  143. CLK_SET_RATE_PARENT, 1, 2);
  144. clk_register_clkdev(clk, "pll2_12", NULL);
  145. clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
  146. CLK_SET_RATE_PARENT, 1, 2);
  147. clk_register_clkdev(clk, "vctcxo_2", NULL);
  148. clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
  149. CLK_SET_RATE_PARENT, 1, 2);
  150. clk_register_clkdev(clk, "vctcxo_4", NULL);
  151. clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
  152. mpmu_base + MPMU_UART_PLL,
  153. &uart_factor_masks, uart_factor_tbl,
  154. ARRAY_SIZE(uart_factor_tbl), &clk_lock);
  155. clk_set_rate(clk, 14745600);
  156. clk_register_clkdev(clk, "uart_pll", NULL);
  157. clk = mmp_clk_register_apbc("twsi0", "vctcxo",
  158. apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
  159. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
  160. clk = mmp_clk_register_apbc("twsi1", "vctcxo",
  161. apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
  162. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
  163. clk = mmp_clk_register_apbc("twsi2", "vctcxo",
  164. apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
  165. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
  166. clk = mmp_clk_register_apbc("twsi3", "vctcxo",
  167. apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
  168. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
  169. clk = mmp_clk_register_apbc("twsi4", "vctcxo",
  170. apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
  171. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
  172. clk = mmp_clk_register_apbc("twsi5", "vctcxo",
  173. apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
  174. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
  175. clk = mmp_clk_register_apbc("gpio", "vctcxo",
  176. apbc_base + APBC_GPIO, 10, 0, &clk_lock);
  177. clk_register_clkdev(clk, NULL, "mmp2-gpio");
  178. clk = mmp_clk_register_apbc("kpc", "clk32",
  179. apbc_base + APBC_KPC, 10, 0, &clk_lock);
  180. clk_register_clkdev(clk, NULL, "pxa27x-keypad");
  181. clk = mmp_clk_register_apbc("rtc", "clk32",
  182. apbc_base + APBC_RTC, 10, 0, &clk_lock);
  183. clk_register_clkdev(clk, NULL, "mmp-rtc");
  184. clk = mmp_clk_register_apbc("pwm0", "vctcxo",
  185. apbc_base + APBC_PWM0, 10, 0, &clk_lock);
  186. clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
  187. clk = mmp_clk_register_apbc("pwm1", "vctcxo",
  188. apbc_base + APBC_PWM1, 10, 0, &clk_lock);
  189. clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
  190. clk = mmp_clk_register_apbc("pwm2", "vctcxo",
  191. apbc_base + APBC_PWM2, 10, 0, &clk_lock);
  192. clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
  193. clk = mmp_clk_register_apbc("pwm3", "vctcxo",
  194. apbc_base + APBC_PWM3, 10, 0, &clk_lock);
  195. clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
  196. clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
  197. ARRAY_SIZE(uart_parent),
  198. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  199. apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
  200. clk_set_parent(clk, vctcxo);
  201. clk_register_clkdev(clk, "uart_mux.0", NULL);
  202. clk = mmp_clk_register_apbc("uart0", "uart0_mux",
  203. apbc_base + APBC_UART0, 10, 0, &clk_lock);
  204. clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
  205. clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
  206. ARRAY_SIZE(uart_parent),
  207. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  208. apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
  209. clk_set_parent(clk, vctcxo);
  210. clk_register_clkdev(clk, "uart_mux.1", NULL);
  211. clk = mmp_clk_register_apbc("uart1", "uart1_mux",
  212. apbc_base + APBC_UART1, 10, 0, &clk_lock);
  213. clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
  214. clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
  215. ARRAY_SIZE(uart_parent),
  216. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  217. apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
  218. clk_set_parent(clk, vctcxo);
  219. clk_register_clkdev(clk, "uart_mux.2", NULL);
  220. clk = mmp_clk_register_apbc("uart2", "uart2_mux",
  221. apbc_base + APBC_UART2, 10, 0, &clk_lock);
  222. clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
  223. clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
  224. ARRAY_SIZE(uart_parent),
  225. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  226. apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
  227. clk_set_parent(clk, vctcxo);
  228. clk_register_clkdev(clk, "uart_mux.3", NULL);
  229. clk = mmp_clk_register_apbc("uart3", "uart3_mux",
  230. apbc_base + APBC_UART3, 10, 0, &clk_lock);
  231. clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
  232. clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
  233. ARRAY_SIZE(ssp_parent),
  234. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  235. apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
  236. clk_register_clkdev(clk, "uart_mux.0", NULL);
  237. clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
  238. apbc_base + APBC_SSP0, 10, 0, &clk_lock);
  239. clk_register_clkdev(clk, NULL, "mmp-ssp.0");
  240. clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
  241. ARRAY_SIZE(ssp_parent),
  242. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  243. apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
  244. clk_register_clkdev(clk, "ssp_mux.1", NULL);
  245. clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
  246. apbc_base + APBC_SSP1, 10, 0, &clk_lock);
  247. clk_register_clkdev(clk, NULL, "mmp-ssp.1");
  248. clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
  249. ARRAY_SIZE(ssp_parent),
  250. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  251. apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
  252. clk_register_clkdev(clk, "ssp_mux.2", NULL);
  253. clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
  254. apbc_base + APBC_SSP2, 10, 0, &clk_lock);
  255. clk_register_clkdev(clk, NULL, "mmp-ssp.2");
  256. clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
  257. ARRAY_SIZE(ssp_parent),
  258. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  259. apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
  260. clk_register_clkdev(clk, "ssp_mux.3", NULL);
  261. clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
  262. apbc_base + APBC_SSP3, 10, 0, &clk_lock);
  263. clk_register_clkdev(clk, NULL, "mmp-ssp.3");
  264. clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
  265. ARRAY_SIZE(sdh_parent),
  266. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  267. apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
  268. clk_register_clkdev(clk, "sdh_mux", NULL);
  269. clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
  270. CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
  271. 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  272. clk_register_clkdev(clk, "sdh_div", NULL);
  273. clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
  274. 0x1b, &clk_lock);
  275. clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
  276. clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
  277. 0x1b, &clk_lock);
  278. clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
  279. clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
  280. 0x1b, &clk_lock);
  281. clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
  282. clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
  283. 0x1b, &clk_lock);
  284. clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
  285. clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
  286. 0x9, &clk_lock);
  287. clk_register_clkdev(clk, "usb_clk", NULL);
  288. clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
  289. ARRAY_SIZE(disp_parent),
  290. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  291. apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
  292. clk_register_clkdev(clk, "disp_mux.0", NULL);
  293. clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
  294. CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
  295. 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  296. clk_register_clkdev(clk, "disp_div.0", NULL);
  297. clk = mmp_clk_register_apmu("disp0", "disp0_div",
  298. apmu_base + APMU_DISP0, 0x1b, &clk_lock);
  299. clk_register_clkdev(clk, NULL, "mmp-disp.0");
  300. clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
  301. apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
  302. clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
  303. clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
  304. apmu_base + APMU_DISP0, 0x1024, &clk_lock);
  305. clk_register_clkdev(clk, "disp_sphy.0", NULL);
  306. clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
  307. ARRAY_SIZE(disp_parent),
  308. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  309. apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
  310. clk_register_clkdev(clk, "disp_mux.1", NULL);
  311. clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
  312. CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
  313. 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  314. clk_register_clkdev(clk, "disp_div.1", NULL);
  315. clk = mmp_clk_register_apmu("disp1", "disp1_div",
  316. apmu_base + APMU_DISP1, 0x1b, &clk_lock);
  317. clk_register_clkdev(clk, NULL, "mmp-disp.1");
  318. clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
  319. apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
  320. clk_register_clkdev(clk, "ccic_arbiter", NULL);
  321. clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
  322. ARRAY_SIZE(ccic_parent),
  323. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  324. apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
  325. clk_register_clkdev(clk, "ccic_mux.0", NULL);
  326. clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
  327. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
  328. 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  329. clk_register_clkdev(clk, "ccic_div.0", NULL);
  330. clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
  331. apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
  332. clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
  333. clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
  334. apmu_base + APMU_CCIC0, 0x24, &clk_lock);
  335. clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
  336. clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
  337. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
  338. 10, 5, 0, &clk_lock);
  339. clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
  340. clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
  341. apmu_base + APMU_CCIC0, 0x300, &clk_lock);
  342. clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
  343. clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
  344. ARRAY_SIZE(ccic_parent),
  345. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  346. apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
  347. clk_register_clkdev(clk, "ccic_mux.1", NULL);
  348. clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
  349. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
  350. 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  351. clk_register_clkdev(clk, "ccic_div.1", NULL);
  352. clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
  353. apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
  354. clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
  355. clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
  356. apmu_base + APMU_CCIC1, 0x24, &clk_lock);
  357. clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
  358. clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
  359. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
  360. 10, 5, 0, &clk_lock);
  361. clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
  362. clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
  363. apmu_base + APMU_CCIC1, 0x300, &clk_lock);
  364. clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
  365. }