omap_drv.c 18 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "omap_drv.h"
  20. #include "drm_crtc_helper.h"
  21. #include "drm_fb_helper.h"
  22. #include "omap_dmm_tiler.h"
  23. #define DRIVER_NAME MODULE_NAME
  24. #define DRIVER_DESC "OMAP DRM"
  25. #define DRIVER_DATE "20110917"
  26. #define DRIVER_MAJOR 1
  27. #define DRIVER_MINOR 0
  28. #define DRIVER_PATCHLEVEL 0
  29. static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
  30. MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
  31. module_param(num_crtc, int, 0600);
  32. /*
  33. * mode config funcs
  34. */
  35. /* Notes about mapping DSS and DRM entities:
  36. * CRTC: overlay
  37. * encoder: manager.. with some extension to allow one primary CRTC
  38. * and zero or more video CRTC's to be mapped to one encoder?
  39. * connector: dssdev.. manager can be attached/detached from different
  40. * devices
  41. */
  42. static void omap_fb_output_poll_changed(struct drm_device *dev)
  43. {
  44. struct omap_drm_private *priv = dev->dev_private;
  45. DBG("dev=%p", dev);
  46. if (priv->fbdev)
  47. drm_fb_helper_hotplug_event(priv->fbdev);
  48. }
  49. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  50. .fb_create = omap_framebuffer_create,
  51. .output_poll_changed = omap_fb_output_poll_changed,
  52. };
  53. static int get_connector_type(struct omap_dss_device *dssdev)
  54. {
  55. switch (dssdev->type) {
  56. case OMAP_DISPLAY_TYPE_HDMI:
  57. return DRM_MODE_CONNECTOR_HDMIA;
  58. case OMAP_DISPLAY_TYPE_DVI:
  59. return DRM_MODE_CONNECTOR_DVID;
  60. default:
  61. return DRM_MODE_CONNECTOR_Unknown;
  62. }
  63. }
  64. static bool channel_used(struct drm_device *dev, enum omap_channel channel)
  65. {
  66. struct omap_drm_private *priv = dev->dev_private;
  67. int i;
  68. for (i = 0; i < priv->num_crtcs; i++) {
  69. struct drm_crtc *crtc = priv->crtcs[i];
  70. if (omap_crtc_channel(crtc) == channel)
  71. return true;
  72. }
  73. return false;
  74. }
  75. static void omap_disconnect_dssdevs(void)
  76. {
  77. struct omap_dss_device *dssdev = NULL;
  78. for_each_dss_dev(dssdev)
  79. dssdev->driver->disconnect(dssdev);
  80. }
  81. static int omap_connect_dssdevs(void)
  82. {
  83. int r;
  84. struct omap_dss_device *dssdev = NULL;
  85. bool no_displays = true;
  86. for_each_dss_dev(dssdev) {
  87. r = dssdev->driver->connect(dssdev);
  88. if (r == -EPROBE_DEFER) {
  89. omap_dss_put_device(dssdev);
  90. goto cleanup;
  91. } else if (r) {
  92. dev_warn(dssdev->dev, "could not connect display: %s\n",
  93. dssdev->name);
  94. } else {
  95. no_displays = false;
  96. }
  97. }
  98. if (no_displays)
  99. return -EPROBE_DEFER;
  100. return 0;
  101. cleanup:
  102. /*
  103. * if we are deferring probe, we disconnect the devices we previously
  104. * connected
  105. */
  106. omap_disconnect_dssdevs();
  107. return r;
  108. }
  109. static int omap_modeset_init(struct drm_device *dev)
  110. {
  111. struct omap_drm_private *priv = dev->dev_private;
  112. struct omap_dss_device *dssdev = NULL;
  113. int num_ovls = dss_feat_get_num_ovls();
  114. int num_mgrs = dss_feat_get_num_mgrs();
  115. int num_crtcs;
  116. int i, id = 0;
  117. drm_mode_config_init(dev);
  118. omap_drm_irq_install(dev);
  119. /*
  120. * We usually don't want to create a CRTC for each manager, at least
  121. * not until we have a way to expose private planes to userspace.
  122. * Otherwise there would not be enough video pipes left for drm planes.
  123. * We use the num_crtc argument to limit the number of crtcs we create.
  124. */
  125. num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
  126. dssdev = NULL;
  127. for_each_dss_dev(dssdev) {
  128. struct drm_connector *connector;
  129. struct drm_encoder *encoder;
  130. enum omap_channel channel;
  131. struct omap_overlay_manager *mgr;
  132. if (!omapdss_device_is_connected(dssdev))
  133. continue;
  134. encoder = omap_encoder_init(dev, dssdev);
  135. if (!encoder) {
  136. dev_err(dev->dev, "could not create encoder: %s\n",
  137. dssdev->name);
  138. return -ENOMEM;
  139. }
  140. connector = omap_connector_init(dev,
  141. get_connector_type(dssdev), dssdev, encoder);
  142. if (!connector) {
  143. dev_err(dev->dev, "could not create connector: %s\n",
  144. dssdev->name);
  145. return -ENOMEM;
  146. }
  147. BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
  148. BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
  149. priv->encoders[priv->num_encoders++] = encoder;
  150. priv->connectors[priv->num_connectors++] = connector;
  151. drm_mode_connector_attach_encoder(connector, encoder);
  152. /*
  153. * if we have reached the limit of the crtcs we are allowed to
  154. * create, let's not try to look for a crtc for this
  155. * panel/encoder and onwards, we will, of course, populate the
  156. * the possible_crtcs field for all the encoders with the final
  157. * set of crtcs we create
  158. */
  159. if (id == num_crtcs)
  160. continue;
  161. /*
  162. * get the recommended DISPC channel for this encoder. For now,
  163. * we only try to get create a crtc out of the recommended, the
  164. * other possible channels to which the encoder can connect are
  165. * not considered.
  166. */
  167. mgr = omapdss_find_mgr_from_display(dssdev);
  168. channel = mgr->id;
  169. /*
  170. * if this channel hasn't already been taken by a previously
  171. * allocated crtc, we create a new crtc for it
  172. */
  173. if (!channel_used(dev, channel)) {
  174. struct drm_plane *plane;
  175. struct drm_crtc *crtc;
  176. plane = omap_plane_init(dev, id, true);
  177. crtc = omap_crtc_init(dev, plane, channel, id);
  178. BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
  179. priv->crtcs[id] = crtc;
  180. priv->num_crtcs++;
  181. priv->planes[id] = plane;
  182. priv->num_planes++;
  183. id++;
  184. }
  185. }
  186. /*
  187. * we have allocated crtcs according to the need of the panels/encoders,
  188. * adding more crtcs here if needed
  189. */
  190. for (; id < num_crtcs; id++) {
  191. /* find a free manager for this crtc */
  192. for (i = 0; i < num_mgrs; i++) {
  193. if (!channel_used(dev, i)) {
  194. struct drm_plane *plane;
  195. struct drm_crtc *crtc;
  196. plane = omap_plane_init(dev, id, true);
  197. crtc = omap_crtc_init(dev, plane, i, id);
  198. BUG_ON(priv->num_crtcs >=
  199. ARRAY_SIZE(priv->crtcs));
  200. priv->crtcs[id] = crtc;
  201. priv->num_crtcs++;
  202. priv->planes[id] = plane;
  203. priv->num_planes++;
  204. break;
  205. } else {
  206. continue;
  207. }
  208. }
  209. if (i == num_mgrs) {
  210. /* this shouldn't really happen */
  211. dev_err(dev->dev, "no managers left for crtc\n");
  212. return -ENOMEM;
  213. }
  214. }
  215. /*
  216. * Create normal planes for the remaining overlays:
  217. */
  218. for (; id < num_ovls; id++) {
  219. struct drm_plane *plane = omap_plane_init(dev, id, false);
  220. BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
  221. priv->planes[priv->num_planes++] = plane;
  222. }
  223. for (i = 0; i < priv->num_encoders; i++) {
  224. struct drm_encoder *encoder = priv->encoders[i];
  225. struct omap_dss_device *dssdev =
  226. omap_encoder_get_dssdev(encoder);
  227. struct omap_dss_device *output;
  228. output = omapdss_find_output_from_display(dssdev);
  229. /* figure out which crtc's we can connect the encoder to: */
  230. encoder->possible_crtcs = 0;
  231. for (id = 0; id < priv->num_crtcs; id++) {
  232. struct drm_crtc *crtc = priv->crtcs[id];
  233. enum omap_channel crtc_channel;
  234. enum omap_dss_output_id supported_outputs;
  235. crtc_channel = omap_crtc_channel(crtc);
  236. supported_outputs =
  237. dss_feat_get_supported_outputs(crtc_channel);
  238. if (supported_outputs & output->id)
  239. encoder->possible_crtcs |= (1 << id);
  240. }
  241. omap_dss_put_device(output);
  242. }
  243. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  244. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  245. priv->num_connectors);
  246. dev->mode_config.min_width = 32;
  247. dev->mode_config.min_height = 32;
  248. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  249. * to fill in these limits properly on different OMAP generations..
  250. */
  251. dev->mode_config.max_width = 2048;
  252. dev->mode_config.max_height = 2048;
  253. dev->mode_config.funcs = &omap_mode_config_funcs;
  254. return 0;
  255. }
  256. static void omap_modeset_free(struct drm_device *dev)
  257. {
  258. drm_mode_config_cleanup(dev);
  259. }
  260. /*
  261. * drm ioctl funcs
  262. */
  263. static int ioctl_get_param(struct drm_device *dev, void *data,
  264. struct drm_file *file_priv)
  265. {
  266. struct omap_drm_private *priv = dev->dev_private;
  267. struct drm_omap_param *args = data;
  268. DBG("%p: param=%llu", dev, args->param);
  269. switch (args->param) {
  270. case OMAP_PARAM_CHIPSET_ID:
  271. args->value = priv->omaprev;
  272. break;
  273. default:
  274. DBG("unknown parameter %lld", args->param);
  275. return -EINVAL;
  276. }
  277. return 0;
  278. }
  279. static int ioctl_set_param(struct drm_device *dev, void *data,
  280. struct drm_file *file_priv)
  281. {
  282. struct drm_omap_param *args = data;
  283. switch (args->param) {
  284. default:
  285. DBG("unknown parameter %lld", args->param);
  286. return -EINVAL;
  287. }
  288. return 0;
  289. }
  290. static int ioctl_gem_new(struct drm_device *dev, void *data,
  291. struct drm_file *file_priv)
  292. {
  293. struct drm_omap_gem_new *args = data;
  294. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  295. args->size.bytes, args->flags);
  296. return omap_gem_new_handle(dev, file_priv, args->size,
  297. args->flags, &args->handle);
  298. }
  299. static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  300. struct drm_file *file_priv)
  301. {
  302. struct drm_omap_gem_cpu_prep *args = data;
  303. struct drm_gem_object *obj;
  304. int ret;
  305. VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
  306. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  307. if (!obj)
  308. return -ENOENT;
  309. ret = omap_gem_op_sync(obj, args->op);
  310. if (!ret)
  311. ret = omap_gem_op_start(obj, args->op);
  312. drm_gem_object_unreference_unlocked(obj);
  313. return ret;
  314. }
  315. static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  316. struct drm_file *file_priv)
  317. {
  318. struct drm_omap_gem_cpu_fini *args = data;
  319. struct drm_gem_object *obj;
  320. int ret;
  321. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  322. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  323. if (!obj)
  324. return -ENOENT;
  325. /* XXX flushy, flushy */
  326. ret = 0;
  327. if (!ret)
  328. ret = omap_gem_op_finish(obj, args->op);
  329. drm_gem_object_unreference_unlocked(obj);
  330. return ret;
  331. }
  332. static int ioctl_gem_info(struct drm_device *dev, void *data,
  333. struct drm_file *file_priv)
  334. {
  335. struct drm_omap_gem_info *args = data;
  336. struct drm_gem_object *obj;
  337. int ret = 0;
  338. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  339. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  340. if (!obj)
  341. return -ENOENT;
  342. args->size = omap_gem_mmap_size(obj);
  343. args->offset = omap_gem_mmap_offset(obj);
  344. drm_gem_object_unreference_unlocked(obj);
  345. return ret;
  346. }
  347. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  348. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH),
  349. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  350. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH),
  351. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
  352. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
  353. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH),
  354. };
  355. /*
  356. * drm driver funcs
  357. */
  358. /**
  359. * load - setup chip and create an initial config
  360. * @dev: DRM device
  361. * @flags: startup flags
  362. *
  363. * The driver load routine has to do several things:
  364. * - initialize the memory manager
  365. * - allocate initial config memory
  366. * - setup the DRM framebuffer with the allocated memory
  367. */
  368. static int dev_load(struct drm_device *dev, unsigned long flags)
  369. {
  370. struct omap_drm_platform_data *pdata = dev->dev->platform_data;
  371. struct omap_drm_private *priv;
  372. int ret;
  373. DBG("load: dev=%p", dev);
  374. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  375. if (!priv)
  376. return -ENOMEM;
  377. priv->omaprev = pdata->omaprev;
  378. dev->dev_private = priv;
  379. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  380. INIT_LIST_HEAD(&priv->obj_list);
  381. omap_gem_init(dev);
  382. ret = omap_modeset_init(dev);
  383. if (ret) {
  384. dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  385. dev->dev_private = NULL;
  386. kfree(priv);
  387. return ret;
  388. }
  389. ret = drm_vblank_init(dev, priv->num_crtcs);
  390. if (ret)
  391. dev_warn(dev->dev, "could not init vblank\n");
  392. priv->fbdev = omap_fbdev_init(dev);
  393. if (!priv->fbdev) {
  394. dev_warn(dev->dev, "omap_fbdev_init failed\n");
  395. /* well, limp along without an fbdev.. maybe X11 will work? */
  396. }
  397. /* store off drm_device for use in pm ops */
  398. dev_set_drvdata(dev->dev, dev);
  399. drm_kms_helper_poll_init(dev);
  400. return 0;
  401. }
  402. static int dev_unload(struct drm_device *dev)
  403. {
  404. struct omap_drm_private *priv = dev->dev_private;
  405. DBG("unload: dev=%p", dev);
  406. drm_kms_helper_poll_fini(dev);
  407. omap_fbdev_free(dev);
  408. omap_modeset_free(dev);
  409. omap_gem_deinit(dev);
  410. destroy_workqueue(priv->wq);
  411. drm_vblank_cleanup(dev);
  412. omap_drm_irq_uninstall(dev);
  413. kfree(dev->dev_private);
  414. dev->dev_private = NULL;
  415. dev_set_drvdata(dev->dev, NULL);
  416. return 0;
  417. }
  418. static int dev_open(struct drm_device *dev, struct drm_file *file)
  419. {
  420. file->driver_priv = NULL;
  421. DBG("open: dev=%p, file=%p", dev, file);
  422. return 0;
  423. }
  424. /**
  425. * lastclose - clean up after all DRM clients have exited
  426. * @dev: DRM device
  427. *
  428. * Take care of cleaning up after all DRM clients have exited. In the
  429. * mode setting case, we want to restore the kernel's initial mode (just
  430. * in case the last client left us in a bad state).
  431. */
  432. static void dev_lastclose(struct drm_device *dev)
  433. {
  434. int i;
  435. /* we don't support vga-switcheroo.. so just make sure the fbdev
  436. * mode is active
  437. */
  438. struct omap_drm_private *priv = dev->dev_private;
  439. int ret;
  440. DBG("lastclose: dev=%p", dev);
  441. if (priv->rotation_prop) {
  442. /* need to restore default rotation state.. not sure
  443. * if there is a cleaner way to restore properties to
  444. * default state? Maybe a flag that properties should
  445. * automatically be restored to default state on
  446. * lastclose?
  447. */
  448. for (i = 0; i < priv->num_crtcs; i++) {
  449. drm_object_property_set_value(&priv->crtcs[i]->base,
  450. priv->rotation_prop, 0);
  451. }
  452. for (i = 0; i < priv->num_planes; i++) {
  453. drm_object_property_set_value(&priv->planes[i]->base,
  454. priv->rotation_prop, 0);
  455. }
  456. }
  457. drm_modeset_lock_all(dev);
  458. ret = drm_fb_helper_restore_fbdev_mode(priv->fbdev);
  459. drm_modeset_unlock_all(dev);
  460. if (ret)
  461. DBG("failed to restore crtc mode");
  462. }
  463. static void dev_preclose(struct drm_device *dev, struct drm_file *file)
  464. {
  465. DBG("preclose: dev=%p", dev);
  466. }
  467. static void dev_postclose(struct drm_device *dev, struct drm_file *file)
  468. {
  469. DBG("postclose: dev=%p, file=%p", dev, file);
  470. }
  471. static const struct vm_operations_struct omap_gem_vm_ops = {
  472. .fault = omap_gem_fault,
  473. .open = drm_gem_vm_open,
  474. .close = drm_gem_vm_close,
  475. };
  476. static const struct file_operations omapdriver_fops = {
  477. .owner = THIS_MODULE,
  478. .open = drm_open,
  479. .unlocked_ioctl = drm_ioctl,
  480. .release = drm_release,
  481. .mmap = omap_gem_mmap,
  482. .poll = drm_poll,
  483. .read = drm_read,
  484. .llseek = noop_llseek,
  485. };
  486. static struct drm_driver omap_drm_driver = {
  487. .driver_features =
  488. DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
  489. .load = dev_load,
  490. .unload = dev_unload,
  491. .open = dev_open,
  492. .lastclose = dev_lastclose,
  493. .preclose = dev_preclose,
  494. .postclose = dev_postclose,
  495. .get_vblank_counter = drm_vblank_count,
  496. .enable_vblank = omap_irq_enable_vblank,
  497. .disable_vblank = omap_irq_disable_vblank,
  498. .irq_preinstall = omap_irq_preinstall,
  499. .irq_postinstall = omap_irq_postinstall,
  500. .irq_uninstall = omap_irq_uninstall,
  501. .irq_handler = omap_irq_handler,
  502. #ifdef CONFIG_DEBUG_FS
  503. .debugfs_init = omap_debugfs_init,
  504. .debugfs_cleanup = omap_debugfs_cleanup,
  505. #endif
  506. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  507. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  508. .gem_prime_export = omap_gem_prime_export,
  509. .gem_prime_import = omap_gem_prime_import,
  510. .gem_free_object = omap_gem_free_object,
  511. .gem_vm_ops = &omap_gem_vm_ops,
  512. .dumb_create = omap_gem_dumb_create,
  513. .dumb_map_offset = omap_gem_dumb_map_offset,
  514. .dumb_destroy = drm_gem_dumb_destroy,
  515. .ioctls = ioctls,
  516. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  517. .fops = &omapdriver_fops,
  518. .name = DRIVER_NAME,
  519. .desc = DRIVER_DESC,
  520. .date = DRIVER_DATE,
  521. .major = DRIVER_MAJOR,
  522. .minor = DRIVER_MINOR,
  523. .patchlevel = DRIVER_PATCHLEVEL,
  524. };
  525. static int pdev_suspend(struct platform_device *pDevice, pm_message_t state)
  526. {
  527. DBG("");
  528. return 0;
  529. }
  530. static int pdev_resume(struct platform_device *device)
  531. {
  532. DBG("");
  533. return 0;
  534. }
  535. static void pdev_shutdown(struct platform_device *device)
  536. {
  537. DBG("");
  538. }
  539. static int pdev_probe(struct platform_device *device)
  540. {
  541. int r;
  542. if (omapdss_is_initialized() == false)
  543. return -EPROBE_DEFER;
  544. omap_crtc_pre_init();
  545. r = omap_connect_dssdevs();
  546. if (r) {
  547. omap_crtc_pre_uninit();
  548. return r;
  549. }
  550. DBG("%s", device->name);
  551. return drm_platform_init(&omap_drm_driver, device);
  552. }
  553. static int pdev_remove(struct platform_device *device)
  554. {
  555. DBG("");
  556. omap_disconnect_dssdevs();
  557. omap_crtc_pre_uninit();
  558. drm_put_dev(platform_get_drvdata(device));
  559. return 0;
  560. }
  561. #ifdef CONFIG_PM
  562. static const struct dev_pm_ops omapdrm_pm_ops = {
  563. .resume = omap_gem_resume,
  564. };
  565. #endif
  566. static struct platform_driver pdev = {
  567. .driver = {
  568. .name = DRIVER_NAME,
  569. .owner = THIS_MODULE,
  570. #ifdef CONFIG_PM
  571. .pm = &omapdrm_pm_ops,
  572. #endif
  573. },
  574. .probe = pdev_probe,
  575. .remove = pdev_remove,
  576. .suspend = pdev_suspend,
  577. .resume = pdev_resume,
  578. .shutdown = pdev_shutdown,
  579. };
  580. static int __init omap_drm_init(void)
  581. {
  582. DBG("init");
  583. if (platform_driver_register(&omap_dmm_driver)) {
  584. /* we can continue on without DMM.. so not fatal */
  585. dev_err(NULL, "DMM registration failed\n");
  586. }
  587. return platform_driver_register(&pdev);
  588. }
  589. static void __exit omap_drm_fini(void)
  590. {
  591. DBG("fini");
  592. platform_driver_unregister(&pdev);
  593. }
  594. /* need late_initcall() so we load after dss_driver's are loaded */
  595. late_initcall(omap_drm_init);
  596. module_exit(omap_drm_fini);
  597. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  598. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  599. MODULE_ALIAS("platform:" DRIVER_NAME);
  600. MODULE_LICENSE("GPL v2");