amdgpu_ib.c 8.7 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. * Christian König
  28. */
  29. #include <linux/seq_file.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/amdgpu_drm.h>
  33. #include "amdgpu.h"
  34. #include "atom.h"
  35. /*
  36. * IB
  37. * IBs (Indirect Buffers) and areas of GPU accessible memory where
  38. * commands are stored. You can put a pointer to the IB in the
  39. * command ring and the hw will fetch the commands from the IB
  40. * and execute them. Generally userspace acceleration drivers
  41. * produce command buffers which are send to the kernel and
  42. * put in IBs for execution by the requested ring.
  43. */
  44. static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
  45. /**
  46. * amdgpu_ib_get - request an IB (Indirect Buffer)
  47. *
  48. * @ring: ring index the IB is associated with
  49. * @size: requested IB size
  50. * @ib: IB object returned
  51. *
  52. * Request an IB (all asics). IBs are allocated using the
  53. * suballocator.
  54. * Returns 0 on success, error on failure.
  55. */
  56. int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
  57. unsigned size, struct amdgpu_ib *ib)
  58. {
  59. struct amdgpu_device *adev = ring->adev;
  60. int r;
  61. if (size) {
  62. r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo,
  63. &ib->sa_bo, size, 256);
  64. if (r) {
  65. dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
  66. return r;
  67. }
  68. ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
  69. if (!vm)
  70. ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
  71. else
  72. ib->gpu_addr = 0;
  73. } else {
  74. ib->sa_bo = NULL;
  75. ib->ptr = NULL;
  76. ib->gpu_addr = 0;
  77. }
  78. amdgpu_sync_create(&ib->sync);
  79. ib->ring = ring;
  80. ib->fence = NULL;
  81. ib->user = NULL;
  82. ib->vm = vm;
  83. ib->gds_base = 0;
  84. ib->gds_size = 0;
  85. ib->gws_base = 0;
  86. ib->gws_size = 0;
  87. ib->oa_base = 0;
  88. ib->oa_size = 0;
  89. ib->flags = 0;
  90. return 0;
  91. }
  92. /**
  93. * amdgpu_ib_free - free an IB (Indirect Buffer)
  94. *
  95. * @adev: amdgpu_device pointer
  96. * @ib: IB object to free
  97. *
  98. * Free an IB (all asics).
  99. */
  100. void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
  101. {
  102. amdgpu_sync_free(adev, &ib->sync, ib->fence);
  103. amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence);
  104. amdgpu_fence_unref(&ib->fence);
  105. }
  106. /**
  107. * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
  108. *
  109. * @adev: amdgpu_device pointer
  110. * @num_ibs: number of IBs to schedule
  111. * @ibs: IB objects to schedule
  112. * @owner: owner for creating the fences
  113. *
  114. * Schedule an IB on the associated ring (all asics).
  115. * Returns 0 on success, error on failure.
  116. *
  117. * On SI, there are two parallel engines fed from the primary ring,
  118. * the CE (Constant Engine) and the DE (Drawing Engine). Since
  119. * resource descriptors have moved to memory, the CE allows you to
  120. * prime the caches while the DE is updating register state so that
  121. * the resource descriptors will be already in cache when the draw is
  122. * processed. To accomplish this, the userspace driver submits two
  123. * IBs, one for the CE and one for the DE. If there is a CE IB (called
  124. * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
  125. * to SI there was just a DE IB.
  126. */
  127. int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
  128. struct amdgpu_ib *ibs, void *owner)
  129. {
  130. struct amdgpu_ring *ring;
  131. struct amdgpu_vm *vm = ibs->vm;
  132. struct amdgpu_ib *ib = &ibs[0];
  133. unsigned i;
  134. int r = 0;
  135. bool flush_hdp = true;
  136. if (num_ibs == 0)
  137. return -EINVAL;
  138. ring = ibs->ring;
  139. if (!ring->ready) {
  140. dev_err(adev->dev, "couldn't schedule ib\n");
  141. return -EINVAL;
  142. }
  143. r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
  144. if (r) {
  145. dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
  146. return r;
  147. }
  148. if (vm) {
  149. /* grab a vm id if necessary */
  150. struct amdgpu_fence *vm_id_fence = NULL;
  151. vm_id_fence = amdgpu_vm_grab_id(ibs->ring, ibs->vm);
  152. amdgpu_sync_fence(&ibs->sync, vm_id_fence);
  153. }
  154. r = amdgpu_sync_rings(&ibs->sync, ring);
  155. if (r) {
  156. amdgpu_ring_unlock_undo(ring);
  157. dev_err(adev->dev, "failed to sync rings (%d)\n", r);
  158. return r;
  159. }
  160. if (vm) {
  161. /* do context switch */
  162. amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
  163. }
  164. if (ring->funcs->emit_gds_switch && ib->vm && (ib->flags & AMDGPU_IB_FLAG_GDS))
  165. amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
  166. ib->gds_base, ib->gds_size,
  167. ib->gws_base, ib->gws_size,
  168. ib->oa_base, ib->oa_size);
  169. for (i = 0; i < num_ibs; ++i) {
  170. ib = &ibs[i];
  171. if (ib->ring != ring) {
  172. amdgpu_ring_unlock_undo(ring);
  173. return -EINVAL;
  174. }
  175. ib->flush_hdp_writefifo = flush_hdp;
  176. flush_hdp = false;
  177. amdgpu_ring_emit_ib(ring, ib);
  178. }
  179. r = amdgpu_fence_emit(ring, owner, &ib->fence);
  180. if (r) {
  181. dev_err(adev->dev, "failed to emit fence (%d)\n", r);
  182. amdgpu_ring_unlock_undo(ring);
  183. return r;
  184. }
  185. /* wrap the last IB with fence */
  186. if (ib->user) {
  187. uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
  188. addr += ib->user->offset;
  189. amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, true);
  190. }
  191. if (ib->vm)
  192. amdgpu_vm_fence(adev, ib->vm, ib->fence);
  193. amdgpu_ring_unlock_commit(ring);
  194. return 0;
  195. }
  196. /**
  197. * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
  198. *
  199. * @adev: amdgpu_device pointer
  200. *
  201. * Initialize the suballocator to manage a pool of memory
  202. * for use as IBs (all asics).
  203. * Returns 0 on success, error on failure.
  204. */
  205. int amdgpu_ib_pool_init(struct amdgpu_device *adev)
  206. {
  207. int r;
  208. if (adev->ib_pool_ready) {
  209. return 0;
  210. }
  211. r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
  212. AMDGPU_IB_POOL_SIZE*64*1024,
  213. AMDGPU_GPU_PAGE_SIZE,
  214. AMDGPU_GEM_DOMAIN_GTT);
  215. if (r) {
  216. return r;
  217. }
  218. r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
  219. if (r) {
  220. return r;
  221. }
  222. adev->ib_pool_ready = true;
  223. if (amdgpu_debugfs_sa_init(adev)) {
  224. dev_err(adev->dev, "failed to register debugfs file for SA\n");
  225. }
  226. return 0;
  227. }
  228. /**
  229. * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
  230. *
  231. * @adev: amdgpu_device pointer
  232. *
  233. * Tear down the suballocator managing the pool of memory
  234. * for use as IBs (all asics).
  235. */
  236. void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
  237. {
  238. if (adev->ib_pool_ready) {
  239. amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
  240. amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
  241. adev->ib_pool_ready = false;
  242. }
  243. }
  244. /**
  245. * amdgpu_ib_ring_tests - test IBs on the rings
  246. *
  247. * @adev: amdgpu_device pointer
  248. *
  249. * Test an IB (Indirect Buffer) on each ring.
  250. * If the test fails, disable the ring.
  251. * Returns 0 on success, error if the primary GFX ring
  252. * IB test fails.
  253. */
  254. int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
  255. {
  256. unsigned i;
  257. int r;
  258. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  259. struct amdgpu_ring *ring = adev->rings[i];
  260. if (!ring || !ring->ready)
  261. continue;
  262. r = amdgpu_ring_test_ib(ring);
  263. if (r) {
  264. ring->ready = false;
  265. adev->needs_reset = false;
  266. if (ring == &adev->gfx.gfx_ring[0]) {
  267. /* oh, oh, that's really bad */
  268. DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
  269. adev->accel_working = false;
  270. return r;
  271. } else {
  272. /* still not good, but we can live with it */
  273. DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
  274. }
  275. }
  276. }
  277. return 0;
  278. }
  279. /*
  280. * Debugfs info
  281. */
  282. #if defined(CONFIG_DEBUG_FS)
  283. static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
  284. {
  285. struct drm_info_node *node = (struct drm_info_node *) m->private;
  286. struct drm_device *dev = node->minor->dev;
  287. struct amdgpu_device *adev = dev->dev_private;
  288. amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
  289. return 0;
  290. }
  291. static struct drm_info_list amdgpu_debugfs_sa_list[] = {
  292. {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
  293. };
  294. #endif
  295. static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
  296. {
  297. #if defined(CONFIG_DEBUG_FS)
  298. return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
  299. #else
  300. return 0;
  301. #endif
  302. }