msm_drv.c 20 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "msm_drv.h"
  18. #include "msm_gpu.h"
  19. #include "msm_kms.h"
  20. static void msm_fb_output_poll_changed(struct drm_device *dev)
  21. {
  22. struct msm_drm_private *priv = dev->dev_private;
  23. if (priv->fbdev)
  24. drm_fb_helper_hotplug_event(priv->fbdev);
  25. }
  26. static const struct drm_mode_config_funcs mode_config_funcs = {
  27. .fb_create = msm_framebuffer_create,
  28. .output_poll_changed = msm_fb_output_poll_changed,
  29. };
  30. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
  31. {
  32. struct msm_drm_private *priv = dev->dev_private;
  33. int idx = priv->num_mmus++;
  34. if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
  35. return -EINVAL;
  36. priv->mmus[idx] = mmu;
  37. return idx;
  38. }
  39. #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
  40. static bool reglog = false;
  41. MODULE_PARM_DESC(reglog, "Enable register read/write logging");
  42. module_param(reglog, bool, 0600);
  43. #else
  44. #define reglog 0
  45. #endif
  46. static char *vram;
  47. MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
  48. module_param(vram, charp, 0);
  49. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  50. const char *dbgname)
  51. {
  52. struct resource *res;
  53. unsigned long size;
  54. void __iomem *ptr;
  55. if (name)
  56. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  57. else
  58. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  59. if (!res) {
  60. dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
  61. return ERR_PTR(-EINVAL);
  62. }
  63. size = resource_size(res);
  64. ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
  65. if (!ptr) {
  66. dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
  67. return ERR_PTR(-ENOMEM);
  68. }
  69. if (reglog)
  70. printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
  71. return ptr;
  72. }
  73. void msm_writel(u32 data, void __iomem *addr)
  74. {
  75. if (reglog)
  76. printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
  77. writel(data, addr);
  78. }
  79. u32 msm_readl(const void __iomem *addr)
  80. {
  81. u32 val = readl(addr);
  82. if (reglog)
  83. printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
  84. return val;
  85. }
  86. /*
  87. * DRM operations:
  88. */
  89. static int msm_unload(struct drm_device *dev)
  90. {
  91. struct msm_drm_private *priv = dev->dev_private;
  92. struct msm_kms *kms = priv->kms;
  93. struct msm_gpu *gpu = priv->gpu;
  94. drm_kms_helper_poll_fini(dev);
  95. drm_mode_config_cleanup(dev);
  96. drm_vblank_cleanup(dev);
  97. pm_runtime_get_sync(dev->dev);
  98. drm_irq_uninstall(dev);
  99. pm_runtime_put_sync(dev->dev);
  100. flush_workqueue(priv->wq);
  101. destroy_workqueue(priv->wq);
  102. if (kms) {
  103. pm_runtime_disable(dev->dev);
  104. kms->funcs->destroy(kms);
  105. }
  106. if (gpu) {
  107. mutex_lock(&dev->struct_mutex);
  108. gpu->funcs->pm_suspend(gpu);
  109. gpu->funcs->destroy(gpu);
  110. mutex_unlock(&dev->struct_mutex);
  111. }
  112. if (priv->vram.paddr) {
  113. DEFINE_DMA_ATTRS(attrs);
  114. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  115. drm_mm_takedown(&priv->vram.mm);
  116. dma_free_attrs(dev->dev, priv->vram.size, NULL,
  117. priv->vram.paddr, &attrs);
  118. }
  119. dev->dev_private = NULL;
  120. kfree(priv);
  121. return 0;
  122. }
  123. static int msm_load(struct drm_device *dev, unsigned long flags)
  124. {
  125. struct platform_device *pdev = dev->platformdev;
  126. struct msm_drm_private *priv;
  127. struct msm_kms *kms;
  128. int ret;
  129. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  130. if (!priv) {
  131. dev_err(dev->dev, "failed to allocate private data\n");
  132. return -ENOMEM;
  133. }
  134. dev->dev_private = priv;
  135. priv->wq = alloc_ordered_workqueue("msm", 0);
  136. init_waitqueue_head(&priv->fence_event);
  137. INIT_LIST_HEAD(&priv->inactive_list);
  138. INIT_LIST_HEAD(&priv->fence_cbs);
  139. drm_mode_config_init(dev);
  140. /* if we have no IOMMU, then we need to use carveout allocator.
  141. * Grab the entire CMA chunk carved out in early startup in
  142. * mach-msm:
  143. */
  144. if (!iommu_present(&platform_bus_type)) {
  145. DEFINE_DMA_ATTRS(attrs);
  146. unsigned long size;
  147. void *p;
  148. DBG("using %s VRAM carveout", vram);
  149. size = memparse(vram, NULL);
  150. priv->vram.size = size;
  151. drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
  152. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  153. dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
  154. /* note that for no-kernel-mapping, the vaddr returned
  155. * is bogus, but non-null if allocation succeeded:
  156. */
  157. p = dma_alloc_attrs(dev->dev, size,
  158. &priv->vram.paddr, 0, &attrs);
  159. if (!p) {
  160. dev_err(dev->dev, "failed to allocate VRAM\n");
  161. priv->vram.paddr = 0;
  162. ret = -ENOMEM;
  163. goto fail;
  164. }
  165. dev_info(dev->dev, "VRAM: %08x->%08x\n",
  166. (uint32_t)priv->vram.paddr,
  167. (uint32_t)(priv->vram.paddr + size));
  168. }
  169. kms = mdp4_kms_init(dev);
  170. if (IS_ERR(kms)) {
  171. /*
  172. * NOTE: once we have GPU support, having no kms should not
  173. * be considered fatal.. ideally we would still support gpu
  174. * and (for example) use dmabuf/prime to share buffers with
  175. * imx drm driver on iMX5
  176. */
  177. dev_err(dev->dev, "failed to load kms\n");
  178. ret = PTR_ERR(kms);
  179. goto fail;
  180. }
  181. priv->kms = kms;
  182. if (kms) {
  183. pm_runtime_enable(dev->dev);
  184. ret = kms->funcs->hw_init(kms);
  185. if (ret) {
  186. dev_err(dev->dev, "kms hw init failed: %d\n", ret);
  187. goto fail;
  188. }
  189. }
  190. dev->mode_config.min_width = 0;
  191. dev->mode_config.min_height = 0;
  192. dev->mode_config.max_width = 2048;
  193. dev->mode_config.max_height = 2048;
  194. dev->mode_config.funcs = &mode_config_funcs;
  195. ret = drm_vblank_init(dev, 1);
  196. if (ret < 0) {
  197. dev_err(dev->dev, "failed to initialize vblank\n");
  198. goto fail;
  199. }
  200. pm_runtime_get_sync(dev->dev);
  201. ret = drm_irq_install(dev);
  202. pm_runtime_put_sync(dev->dev);
  203. if (ret < 0) {
  204. dev_err(dev->dev, "failed to install IRQ handler\n");
  205. goto fail;
  206. }
  207. platform_set_drvdata(pdev, dev);
  208. #ifdef CONFIG_DRM_MSM_FBDEV
  209. priv->fbdev = msm_fbdev_init(dev);
  210. #endif
  211. drm_kms_helper_poll_init(dev);
  212. return 0;
  213. fail:
  214. msm_unload(dev);
  215. return ret;
  216. }
  217. static void load_gpu(struct drm_device *dev)
  218. {
  219. struct msm_drm_private *priv = dev->dev_private;
  220. struct msm_gpu *gpu;
  221. if (priv->gpu)
  222. return;
  223. mutex_lock(&dev->struct_mutex);
  224. gpu = a3xx_gpu_init(dev);
  225. if (IS_ERR(gpu)) {
  226. dev_warn(dev->dev, "failed to load a3xx gpu\n");
  227. gpu = NULL;
  228. /* not fatal */
  229. }
  230. mutex_unlock(&dev->struct_mutex);
  231. if (gpu) {
  232. int ret;
  233. gpu->funcs->pm_resume(gpu);
  234. ret = gpu->funcs->hw_init(gpu);
  235. if (ret) {
  236. dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
  237. gpu->funcs->destroy(gpu);
  238. gpu = NULL;
  239. }
  240. }
  241. priv->gpu = gpu;
  242. }
  243. static int msm_open(struct drm_device *dev, struct drm_file *file)
  244. {
  245. struct msm_file_private *ctx;
  246. /* For now, load gpu on open.. to avoid the requirement of having
  247. * firmware in the initrd.
  248. */
  249. load_gpu(dev);
  250. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  251. if (!ctx)
  252. return -ENOMEM;
  253. file->driver_priv = ctx;
  254. return 0;
  255. }
  256. static void msm_preclose(struct drm_device *dev, struct drm_file *file)
  257. {
  258. struct msm_drm_private *priv = dev->dev_private;
  259. struct msm_file_private *ctx = file->driver_priv;
  260. struct msm_kms *kms = priv->kms;
  261. if (kms)
  262. kms->funcs->preclose(kms, file);
  263. mutex_lock(&dev->struct_mutex);
  264. if (ctx == priv->lastctx)
  265. priv->lastctx = NULL;
  266. mutex_unlock(&dev->struct_mutex);
  267. kfree(ctx);
  268. }
  269. static void msm_lastclose(struct drm_device *dev)
  270. {
  271. struct msm_drm_private *priv = dev->dev_private;
  272. if (priv->fbdev) {
  273. drm_modeset_lock_all(dev);
  274. drm_fb_helper_restore_fbdev_mode(priv->fbdev);
  275. drm_modeset_unlock_all(dev);
  276. }
  277. }
  278. static irqreturn_t msm_irq(int irq, void *arg)
  279. {
  280. struct drm_device *dev = arg;
  281. struct msm_drm_private *priv = dev->dev_private;
  282. struct msm_kms *kms = priv->kms;
  283. BUG_ON(!kms);
  284. return kms->funcs->irq(kms);
  285. }
  286. static void msm_irq_preinstall(struct drm_device *dev)
  287. {
  288. struct msm_drm_private *priv = dev->dev_private;
  289. struct msm_kms *kms = priv->kms;
  290. BUG_ON(!kms);
  291. kms->funcs->irq_preinstall(kms);
  292. }
  293. static int msm_irq_postinstall(struct drm_device *dev)
  294. {
  295. struct msm_drm_private *priv = dev->dev_private;
  296. struct msm_kms *kms = priv->kms;
  297. BUG_ON(!kms);
  298. return kms->funcs->irq_postinstall(kms);
  299. }
  300. static void msm_irq_uninstall(struct drm_device *dev)
  301. {
  302. struct msm_drm_private *priv = dev->dev_private;
  303. struct msm_kms *kms = priv->kms;
  304. BUG_ON(!kms);
  305. kms->funcs->irq_uninstall(kms);
  306. }
  307. static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
  308. {
  309. struct msm_drm_private *priv = dev->dev_private;
  310. struct msm_kms *kms = priv->kms;
  311. if (!kms)
  312. return -ENXIO;
  313. DBG("dev=%p, crtc=%d", dev, crtc_id);
  314. return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
  315. }
  316. static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
  317. {
  318. struct msm_drm_private *priv = dev->dev_private;
  319. struct msm_kms *kms = priv->kms;
  320. if (!kms)
  321. return;
  322. DBG("dev=%p, crtc=%d", dev, crtc_id);
  323. kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
  324. }
  325. /*
  326. * DRM debugfs:
  327. */
  328. #ifdef CONFIG_DEBUG_FS
  329. static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
  330. {
  331. struct msm_drm_private *priv = dev->dev_private;
  332. struct msm_gpu *gpu = priv->gpu;
  333. if (gpu) {
  334. seq_printf(m, "%s Status:\n", gpu->name);
  335. gpu->funcs->show(gpu, m);
  336. }
  337. return 0;
  338. }
  339. static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
  340. {
  341. struct msm_drm_private *priv = dev->dev_private;
  342. struct msm_gpu *gpu = priv->gpu;
  343. if (gpu) {
  344. seq_printf(m, "Active Objects (%s):\n", gpu->name);
  345. msm_gem_describe_objects(&gpu->active_list, m);
  346. }
  347. seq_printf(m, "Inactive Objects:\n");
  348. msm_gem_describe_objects(&priv->inactive_list, m);
  349. return 0;
  350. }
  351. static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
  352. {
  353. return drm_mm_dump_table(m, dev->mm_private);
  354. }
  355. static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
  356. {
  357. struct msm_drm_private *priv = dev->dev_private;
  358. struct drm_framebuffer *fb, *fbdev_fb = NULL;
  359. if (priv->fbdev) {
  360. seq_printf(m, "fbcon ");
  361. fbdev_fb = priv->fbdev->fb;
  362. msm_framebuffer_describe(fbdev_fb, m);
  363. }
  364. mutex_lock(&dev->mode_config.fb_lock);
  365. list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
  366. if (fb == fbdev_fb)
  367. continue;
  368. seq_printf(m, "user ");
  369. msm_framebuffer_describe(fb, m);
  370. }
  371. mutex_unlock(&dev->mode_config.fb_lock);
  372. return 0;
  373. }
  374. static int show_locked(struct seq_file *m, void *arg)
  375. {
  376. struct drm_info_node *node = (struct drm_info_node *) m->private;
  377. struct drm_device *dev = node->minor->dev;
  378. int (*show)(struct drm_device *dev, struct seq_file *m) =
  379. node->info_ent->data;
  380. int ret;
  381. ret = mutex_lock_interruptible(&dev->struct_mutex);
  382. if (ret)
  383. return ret;
  384. ret = show(dev, m);
  385. mutex_unlock(&dev->struct_mutex);
  386. return ret;
  387. }
  388. static struct drm_info_list msm_debugfs_list[] = {
  389. {"gpu", show_locked, 0, msm_gpu_show},
  390. {"gem", show_locked, 0, msm_gem_show},
  391. { "mm", show_locked, 0, msm_mm_show },
  392. { "fb", show_locked, 0, msm_fb_show },
  393. };
  394. static int msm_debugfs_init(struct drm_minor *minor)
  395. {
  396. struct drm_device *dev = minor->dev;
  397. int ret;
  398. ret = drm_debugfs_create_files(msm_debugfs_list,
  399. ARRAY_SIZE(msm_debugfs_list),
  400. minor->debugfs_root, minor);
  401. if (ret) {
  402. dev_err(dev->dev, "could not install msm_debugfs_list\n");
  403. return ret;
  404. }
  405. return ret;
  406. }
  407. static void msm_debugfs_cleanup(struct drm_minor *minor)
  408. {
  409. drm_debugfs_remove_files(msm_debugfs_list,
  410. ARRAY_SIZE(msm_debugfs_list), minor);
  411. }
  412. #endif
  413. /*
  414. * Fences:
  415. */
  416. int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
  417. struct timespec *timeout)
  418. {
  419. struct msm_drm_private *priv = dev->dev_private;
  420. int ret;
  421. if (!priv->gpu)
  422. return 0;
  423. if (fence > priv->gpu->submitted_fence) {
  424. DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
  425. fence, priv->gpu->submitted_fence);
  426. return -EINVAL;
  427. }
  428. if (!timeout) {
  429. /* no-wait: */
  430. ret = fence_completed(dev, fence) ? 0 : -EBUSY;
  431. } else {
  432. unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
  433. unsigned long start_jiffies = jiffies;
  434. unsigned long remaining_jiffies;
  435. if (time_after(start_jiffies, timeout_jiffies))
  436. remaining_jiffies = 0;
  437. else
  438. remaining_jiffies = timeout_jiffies - start_jiffies;
  439. ret = wait_event_interruptible_timeout(priv->fence_event,
  440. fence_completed(dev, fence),
  441. remaining_jiffies);
  442. if (ret == 0) {
  443. DBG("timeout waiting for fence: %u (completed: %u)",
  444. fence, priv->completed_fence);
  445. ret = -ETIMEDOUT;
  446. } else if (ret != -ERESTARTSYS) {
  447. ret = 0;
  448. }
  449. }
  450. return ret;
  451. }
  452. /* called from workqueue */
  453. void msm_update_fence(struct drm_device *dev, uint32_t fence)
  454. {
  455. struct msm_drm_private *priv = dev->dev_private;
  456. mutex_lock(&dev->struct_mutex);
  457. priv->completed_fence = max(fence, priv->completed_fence);
  458. while (!list_empty(&priv->fence_cbs)) {
  459. struct msm_fence_cb *cb;
  460. cb = list_first_entry(&priv->fence_cbs,
  461. struct msm_fence_cb, work.entry);
  462. if (cb->fence > priv->completed_fence)
  463. break;
  464. list_del_init(&cb->work.entry);
  465. queue_work(priv->wq, &cb->work);
  466. }
  467. mutex_unlock(&dev->struct_mutex);
  468. wake_up_all(&priv->fence_event);
  469. }
  470. void __msm_fence_worker(struct work_struct *work)
  471. {
  472. struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
  473. cb->func(cb);
  474. }
  475. /*
  476. * DRM ioctls:
  477. */
  478. static int msm_ioctl_get_param(struct drm_device *dev, void *data,
  479. struct drm_file *file)
  480. {
  481. struct msm_drm_private *priv = dev->dev_private;
  482. struct drm_msm_param *args = data;
  483. struct msm_gpu *gpu;
  484. /* for now, we just have 3d pipe.. eventually this would need to
  485. * be more clever to dispatch to appropriate gpu module:
  486. */
  487. if (args->pipe != MSM_PIPE_3D0)
  488. return -EINVAL;
  489. gpu = priv->gpu;
  490. if (!gpu)
  491. return -ENXIO;
  492. return gpu->funcs->get_param(gpu, args->param, &args->value);
  493. }
  494. static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
  495. struct drm_file *file)
  496. {
  497. struct drm_msm_gem_new *args = data;
  498. return msm_gem_new_handle(dev, file, args->size,
  499. args->flags, &args->handle);
  500. }
  501. #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
  502. static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  503. struct drm_file *file)
  504. {
  505. struct drm_msm_gem_cpu_prep *args = data;
  506. struct drm_gem_object *obj;
  507. int ret;
  508. obj = drm_gem_object_lookup(dev, file, args->handle);
  509. if (!obj)
  510. return -ENOENT;
  511. ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
  512. drm_gem_object_unreference_unlocked(obj);
  513. return ret;
  514. }
  515. static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  516. struct drm_file *file)
  517. {
  518. struct drm_msm_gem_cpu_fini *args = data;
  519. struct drm_gem_object *obj;
  520. int ret;
  521. obj = drm_gem_object_lookup(dev, file, args->handle);
  522. if (!obj)
  523. return -ENOENT;
  524. ret = msm_gem_cpu_fini(obj);
  525. drm_gem_object_unreference_unlocked(obj);
  526. return ret;
  527. }
  528. static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
  529. struct drm_file *file)
  530. {
  531. struct drm_msm_gem_info *args = data;
  532. struct drm_gem_object *obj;
  533. int ret = 0;
  534. if (args->pad)
  535. return -EINVAL;
  536. obj = drm_gem_object_lookup(dev, file, args->handle);
  537. if (!obj)
  538. return -ENOENT;
  539. args->offset = msm_gem_mmap_offset(obj);
  540. drm_gem_object_unreference_unlocked(obj);
  541. return ret;
  542. }
  543. static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
  544. struct drm_file *file)
  545. {
  546. struct drm_msm_wait_fence *args = data;
  547. return msm_wait_fence_interruptable(dev, args->fence, &TS(args->timeout));
  548. }
  549. static const struct drm_ioctl_desc msm_ioctls[] = {
  550. DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  551. DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  552. DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  553. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  554. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  555. DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  556. DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  557. };
  558. static const struct vm_operations_struct vm_ops = {
  559. .fault = msm_gem_fault,
  560. .open = drm_gem_vm_open,
  561. .close = drm_gem_vm_close,
  562. };
  563. static const struct file_operations fops = {
  564. .owner = THIS_MODULE,
  565. .open = drm_open,
  566. .release = drm_release,
  567. .unlocked_ioctl = drm_ioctl,
  568. #ifdef CONFIG_COMPAT
  569. .compat_ioctl = drm_compat_ioctl,
  570. #endif
  571. .poll = drm_poll,
  572. .read = drm_read,
  573. .llseek = no_llseek,
  574. .mmap = msm_gem_mmap,
  575. };
  576. static struct drm_driver msm_driver = {
  577. .driver_features = DRIVER_HAVE_IRQ |
  578. DRIVER_GEM |
  579. DRIVER_PRIME |
  580. DRIVER_RENDER |
  581. DRIVER_MODESET,
  582. .load = msm_load,
  583. .unload = msm_unload,
  584. .open = msm_open,
  585. .preclose = msm_preclose,
  586. .lastclose = msm_lastclose,
  587. .irq_handler = msm_irq,
  588. .irq_preinstall = msm_irq_preinstall,
  589. .irq_postinstall = msm_irq_postinstall,
  590. .irq_uninstall = msm_irq_uninstall,
  591. .get_vblank_counter = drm_vblank_count,
  592. .enable_vblank = msm_enable_vblank,
  593. .disable_vblank = msm_disable_vblank,
  594. .gem_free_object = msm_gem_free_object,
  595. .gem_vm_ops = &vm_ops,
  596. .dumb_create = msm_gem_dumb_create,
  597. .dumb_map_offset = msm_gem_dumb_map_offset,
  598. .dumb_destroy = drm_gem_dumb_destroy,
  599. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  600. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  601. .gem_prime_export = drm_gem_prime_export,
  602. .gem_prime_import = drm_gem_prime_import,
  603. .gem_prime_pin = msm_gem_prime_pin,
  604. .gem_prime_unpin = msm_gem_prime_unpin,
  605. .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
  606. .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
  607. .gem_prime_vmap = msm_gem_prime_vmap,
  608. .gem_prime_vunmap = msm_gem_prime_vunmap,
  609. #ifdef CONFIG_DEBUG_FS
  610. .debugfs_init = msm_debugfs_init,
  611. .debugfs_cleanup = msm_debugfs_cleanup,
  612. #endif
  613. .ioctls = msm_ioctls,
  614. .num_ioctls = DRM_MSM_NUM_IOCTLS,
  615. .fops = &fops,
  616. .name = "msm",
  617. .desc = "MSM Snapdragon DRM",
  618. .date = "20130625",
  619. .major = 1,
  620. .minor = 0,
  621. };
  622. #ifdef CONFIG_PM_SLEEP
  623. static int msm_pm_suspend(struct device *dev)
  624. {
  625. struct drm_device *ddev = dev_get_drvdata(dev);
  626. drm_kms_helper_poll_disable(ddev);
  627. return 0;
  628. }
  629. static int msm_pm_resume(struct device *dev)
  630. {
  631. struct drm_device *ddev = dev_get_drvdata(dev);
  632. drm_kms_helper_poll_enable(ddev);
  633. return 0;
  634. }
  635. #endif
  636. static const struct dev_pm_ops msm_pm_ops = {
  637. SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
  638. };
  639. /*
  640. * Platform driver:
  641. */
  642. static int msm_pdev_probe(struct platform_device *pdev)
  643. {
  644. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  645. return drm_platform_init(&msm_driver, pdev);
  646. }
  647. static int msm_pdev_remove(struct platform_device *pdev)
  648. {
  649. drm_put_dev(platform_get_drvdata(pdev));
  650. return 0;
  651. }
  652. static const struct platform_device_id msm_id[] = {
  653. { "mdp", 0 },
  654. { }
  655. };
  656. static struct platform_driver msm_platform_driver = {
  657. .probe = msm_pdev_probe,
  658. .remove = msm_pdev_remove,
  659. .driver = {
  660. .owner = THIS_MODULE,
  661. .name = "msm",
  662. .pm = &msm_pm_ops,
  663. },
  664. .id_table = msm_id,
  665. };
  666. static int __init msm_drm_register(void)
  667. {
  668. DBG("init");
  669. hdmi_register();
  670. a3xx_register();
  671. return platform_driver_register(&msm_platform_driver);
  672. }
  673. static void __exit msm_drm_unregister(void)
  674. {
  675. DBG("fini");
  676. platform_driver_unregister(&msm_platform_driver);
  677. hdmi_unregister();
  678. a3xx_unregister();
  679. }
  680. module_init(msm_drm_register);
  681. module_exit(msm_drm_unregister);
  682. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  683. MODULE_DESCRIPTION("MSM DRM Driver");
  684. MODULE_LICENSE("GPL");