i915_gem_context.c 24 KB

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  1. /*
  2. * Copyright © 2011-2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Ben Widawsky <ben@bwidawsk.net>
  25. *
  26. */
  27. /*
  28. * This file implements HW context support. On gen5+ a HW context consists of an
  29. * opaque GPU object which is referenced at times of context saves and restores.
  30. * With RC6 enabled, the context is also referenced as the GPU enters and exists
  31. * from RC6 (GPU has it's own internal power context, except on gen5). Though
  32. * something like a context does exist for the media ring, the code only
  33. * supports contexts for the render ring.
  34. *
  35. * In software, there is a distinction between contexts created by the user,
  36. * and the default HW context. The default HW context is used by GPU clients
  37. * that do not request setup of their own hardware context. The default
  38. * context's state is never restored to help prevent programming errors. This
  39. * would happen if a client ran and piggy-backed off another clients GPU state.
  40. * The default context only exists to give the GPU some offset to load as the
  41. * current to invoke a save of the context we actually care about. In fact, the
  42. * code could likely be constructed, albeit in a more complicated fashion, to
  43. * never use the default context, though that limits the driver's ability to
  44. * swap out, and/or destroy other contexts.
  45. *
  46. * All other contexts are created as a request by the GPU client. These contexts
  47. * store GPU state, and thus allow GPU clients to not re-emit state (and
  48. * potentially query certain state) at any time. The kernel driver makes
  49. * certain that the appropriate commands are inserted.
  50. *
  51. * The context life cycle is semi-complicated in that context BOs may live
  52. * longer than the context itself because of the way the hardware, and object
  53. * tracking works. Below is a very crude representation of the state machine
  54. * describing the context life.
  55. * refcount pincount active
  56. * S0: initial state 0 0 0
  57. * S1: context created 1 0 0
  58. * S2: context is currently running 2 1 X
  59. * S3: GPU referenced, but not current 2 0 1
  60. * S4: context is current, but destroyed 1 1 0
  61. * S5: like S3, but destroyed 1 0 1
  62. *
  63. * The most common (but not all) transitions:
  64. * S0->S1: client creates a context
  65. * S1->S2: client submits execbuf with context
  66. * S2->S3: other clients submits execbuf with context
  67. * S3->S1: context object was retired
  68. * S3->S2: clients submits another execbuf
  69. * S2->S4: context destroy called with current context
  70. * S3->S5->S0: destroy path
  71. * S4->S5->S0: destroy path on current context
  72. *
  73. * There are two confusing terms used above:
  74. * The "current context" means the context which is currently running on the
  75. * GPU. The GPU has loaded its state already and has stored away the gtt
  76. * offset of the BO. The GPU is not actively referencing the data at this
  77. * offset, but it will on the next context switch. The only way to avoid this
  78. * is to do a GPU reset.
  79. *
  80. * An "active context' is one which was previously the "current context" and is
  81. * on the active list waiting for the next context switch to occur. Until this
  82. * happens, the object must remain at the same gtt offset. It is therefore
  83. * possible to destroy a context, but it is still active.
  84. *
  85. */
  86. #include <linux/log2.h>
  87. #include <drm/drmP.h>
  88. #include <drm/i915_drm.h>
  89. #include "i915_drv.h"
  90. #include "i915_trace.h"
  91. #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
  92. static void lut_close(struct i915_gem_context *ctx)
  93. {
  94. struct i915_lut_handle *lut, *ln;
  95. struct radix_tree_iter iter;
  96. void __rcu **slot;
  97. list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) {
  98. list_del(&lut->obj_link);
  99. kmem_cache_free(ctx->i915->luts, lut);
  100. }
  101. rcu_read_lock();
  102. radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
  103. struct i915_vma *vma = rcu_dereference_raw(*slot);
  104. radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
  105. __i915_gem_object_release_unless_active(vma->obj);
  106. }
  107. rcu_read_unlock();
  108. }
  109. static void i915_gem_context_free(struct i915_gem_context *ctx)
  110. {
  111. int i;
  112. lockdep_assert_held(&ctx->i915->drm.struct_mutex);
  113. GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
  114. i915_ppgtt_put(ctx->ppgtt);
  115. for (i = 0; i < I915_NUM_ENGINES; i++) {
  116. struct intel_context *ce = &ctx->engine[i];
  117. if (!ce->state)
  118. continue;
  119. WARN_ON(ce->pin_count);
  120. if (ce->ring)
  121. intel_ring_free(ce->ring);
  122. __i915_gem_object_release_unless_active(ce->state->obj);
  123. }
  124. kfree(ctx->name);
  125. put_pid(ctx->pid);
  126. list_del(&ctx->link);
  127. ida_simple_remove(&ctx->i915->contexts.hw_ida, ctx->hw_id);
  128. kfree_rcu(ctx, rcu);
  129. }
  130. static void contexts_free(struct drm_i915_private *i915)
  131. {
  132. struct llist_node *freed = llist_del_all(&i915->contexts.free_list);
  133. struct i915_gem_context *ctx, *cn;
  134. lockdep_assert_held(&i915->drm.struct_mutex);
  135. llist_for_each_entry_safe(ctx, cn, freed, free_link)
  136. i915_gem_context_free(ctx);
  137. }
  138. static void contexts_free_first(struct drm_i915_private *i915)
  139. {
  140. struct i915_gem_context *ctx;
  141. struct llist_node *freed;
  142. lockdep_assert_held(&i915->drm.struct_mutex);
  143. freed = llist_del_first(&i915->contexts.free_list);
  144. if (!freed)
  145. return;
  146. ctx = container_of(freed, typeof(*ctx), free_link);
  147. i915_gem_context_free(ctx);
  148. }
  149. static void contexts_free_worker(struct work_struct *work)
  150. {
  151. struct drm_i915_private *i915 =
  152. container_of(work, typeof(*i915), contexts.free_work);
  153. mutex_lock(&i915->drm.struct_mutex);
  154. contexts_free(i915);
  155. mutex_unlock(&i915->drm.struct_mutex);
  156. }
  157. void i915_gem_context_release(struct kref *ref)
  158. {
  159. struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
  160. struct drm_i915_private *i915 = ctx->i915;
  161. trace_i915_context_free(ctx);
  162. if (llist_add(&ctx->free_link, &i915->contexts.free_list))
  163. queue_work(i915->wq, &i915->contexts.free_work);
  164. }
  165. static void context_close(struct i915_gem_context *ctx)
  166. {
  167. i915_gem_context_set_closed(ctx);
  168. /*
  169. * The LUT uses the VMA as a backpointer to unref the object,
  170. * so we need to clear the LUT before we close all the VMA (inside
  171. * the ppgtt).
  172. */
  173. lut_close(ctx);
  174. if (ctx->ppgtt)
  175. i915_ppgtt_close(&ctx->ppgtt->base);
  176. ctx->file_priv = ERR_PTR(-EBADF);
  177. i915_gem_context_put(ctx);
  178. }
  179. static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
  180. {
  181. int ret;
  182. ret = ida_simple_get(&dev_priv->contexts.hw_ida,
  183. 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
  184. if (ret < 0) {
  185. /* Contexts are only released when no longer active.
  186. * Flush any pending retires to hopefully release some
  187. * stale contexts and try again.
  188. */
  189. i915_gem_retire_requests(dev_priv);
  190. ret = ida_simple_get(&dev_priv->contexts.hw_ida,
  191. 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
  192. if (ret < 0)
  193. return ret;
  194. }
  195. *out = ret;
  196. return 0;
  197. }
  198. static u32 default_desc_template(const struct drm_i915_private *i915,
  199. const struct i915_hw_ppgtt *ppgtt)
  200. {
  201. u32 address_mode;
  202. u32 desc;
  203. desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
  204. address_mode = INTEL_LEGACY_32B_CONTEXT;
  205. if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
  206. address_mode = INTEL_LEGACY_64B_CONTEXT;
  207. desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
  208. if (IS_GEN8(i915))
  209. desc |= GEN8_CTX_L3LLC_COHERENT;
  210. /* TODO: WaDisableLiteRestore when we start using semaphore
  211. * signalling between Command Streamers
  212. * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
  213. */
  214. return desc;
  215. }
  216. static struct i915_gem_context *
  217. __create_hw_context(struct drm_i915_private *dev_priv,
  218. struct drm_i915_file_private *file_priv)
  219. {
  220. struct i915_gem_context *ctx;
  221. int ret;
  222. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  223. if (ctx == NULL)
  224. return ERR_PTR(-ENOMEM);
  225. ret = assign_hw_id(dev_priv, &ctx->hw_id);
  226. if (ret) {
  227. kfree(ctx);
  228. return ERR_PTR(ret);
  229. }
  230. kref_init(&ctx->ref);
  231. list_add_tail(&ctx->link, &dev_priv->contexts.list);
  232. ctx->i915 = dev_priv;
  233. ctx->priority = I915_PRIORITY_NORMAL;
  234. INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
  235. INIT_LIST_HEAD(&ctx->handles_list);
  236. /* Default context will never have a file_priv */
  237. ret = DEFAULT_CONTEXT_HANDLE;
  238. if (file_priv) {
  239. ret = idr_alloc(&file_priv->context_idr, ctx,
  240. DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
  241. if (ret < 0)
  242. goto err_lut;
  243. }
  244. ctx->user_handle = ret;
  245. ctx->file_priv = file_priv;
  246. if (file_priv) {
  247. ctx->pid = get_task_pid(current, PIDTYPE_PID);
  248. ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
  249. current->comm,
  250. pid_nr(ctx->pid),
  251. ctx->user_handle);
  252. if (!ctx->name) {
  253. ret = -ENOMEM;
  254. goto err_pid;
  255. }
  256. }
  257. /* NB: Mark all slices as needing a remap so that when the context first
  258. * loads it will restore whatever remap state already exists. If there
  259. * is no remap info, it will be a NOP. */
  260. ctx->remap_slice = ALL_L3_SLICES(dev_priv);
  261. i915_gem_context_set_bannable(ctx);
  262. ctx->ring_size = 4 * PAGE_SIZE;
  263. ctx->desc_template =
  264. default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
  265. /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
  266. * present or not in use we still need a small bias as ring wraparound
  267. * at offset 0 sometimes hangs. No idea why.
  268. */
  269. if (USES_GUC(dev_priv))
  270. ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
  271. else
  272. ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
  273. return ctx;
  274. err_pid:
  275. put_pid(ctx->pid);
  276. idr_remove(&file_priv->context_idr, ctx->user_handle);
  277. err_lut:
  278. context_close(ctx);
  279. return ERR_PTR(ret);
  280. }
  281. static void __destroy_hw_context(struct i915_gem_context *ctx,
  282. struct drm_i915_file_private *file_priv)
  283. {
  284. idr_remove(&file_priv->context_idr, ctx->user_handle);
  285. context_close(ctx);
  286. }
  287. /**
  288. * The default context needs to exist per ring that uses contexts. It stores the
  289. * context state of the GPU for applications that don't utilize HW contexts, as
  290. * well as an idle case.
  291. */
  292. static struct i915_gem_context *
  293. i915_gem_create_context(struct drm_i915_private *dev_priv,
  294. struct drm_i915_file_private *file_priv)
  295. {
  296. struct i915_gem_context *ctx;
  297. lockdep_assert_held(&dev_priv->drm.struct_mutex);
  298. /* Reap the most stale context */
  299. contexts_free_first(dev_priv);
  300. ctx = __create_hw_context(dev_priv, file_priv);
  301. if (IS_ERR(ctx))
  302. return ctx;
  303. if (USES_FULL_PPGTT(dev_priv)) {
  304. struct i915_hw_ppgtt *ppgtt;
  305. ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
  306. if (IS_ERR(ppgtt)) {
  307. DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
  308. PTR_ERR(ppgtt));
  309. __destroy_hw_context(ctx, file_priv);
  310. return ERR_CAST(ppgtt);
  311. }
  312. ctx->ppgtt = ppgtt;
  313. ctx->desc_template = default_desc_template(dev_priv, ppgtt);
  314. }
  315. trace_i915_context_create(ctx);
  316. return ctx;
  317. }
  318. /**
  319. * i915_gem_context_create_gvt - create a GVT GEM context
  320. * @dev: drm device *
  321. *
  322. * This function is used to create a GVT specific GEM context.
  323. *
  324. * Returns:
  325. * pointer to i915_gem_context on success, error pointer if failed
  326. *
  327. */
  328. struct i915_gem_context *
  329. i915_gem_context_create_gvt(struct drm_device *dev)
  330. {
  331. struct i915_gem_context *ctx;
  332. int ret;
  333. if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
  334. return ERR_PTR(-ENODEV);
  335. ret = i915_mutex_lock_interruptible(dev);
  336. if (ret)
  337. return ERR_PTR(ret);
  338. ctx = __create_hw_context(to_i915(dev), NULL);
  339. if (IS_ERR(ctx))
  340. goto out;
  341. ctx->file_priv = ERR_PTR(-EBADF);
  342. i915_gem_context_set_closed(ctx); /* not user accessible */
  343. i915_gem_context_clear_bannable(ctx);
  344. i915_gem_context_set_force_single_submission(ctx);
  345. if (!USES_GUC_SUBMISSION(to_i915(dev)))
  346. ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
  347. GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
  348. out:
  349. mutex_unlock(&dev->struct_mutex);
  350. return ctx;
  351. }
  352. struct i915_gem_context *
  353. i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
  354. {
  355. struct i915_gem_context *ctx;
  356. ctx = i915_gem_create_context(i915, NULL);
  357. if (IS_ERR(ctx))
  358. return ctx;
  359. i915_gem_context_clear_bannable(ctx);
  360. ctx->priority = prio;
  361. ctx->ring_size = PAGE_SIZE;
  362. GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
  363. return ctx;
  364. }
  365. static void
  366. destroy_kernel_context(struct i915_gem_context **ctxp)
  367. {
  368. struct i915_gem_context *ctx;
  369. /* Keep the context ref so that we can free it immediately ourselves */
  370. ctx = i915_gem_context_get(fetch_and_zero(ctxp));
  371. GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
  372. context_close(ctx);
  373. i915_gem_context_free(ctx);
  374. }
  375. int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
  376. {
  377. struct i915_gem_context *ctx;
  378. int err;
  379. GEM_BUG_ON(dev_priv->kernel_context);
  380. INIT_LIST_HEAD(&dev_priv->contexts.list);
  381. INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
  382. init_llist_head(&dev_priv->contexts.free_list);
  383. /* Using the simple ida interface, the max is limited by sizeof(int) */
  384. BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
  385. ida_init(&dev_priv->contexts.hw_ida);
  386. /* lowest priority; idle task */
  387. ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN);
  388. if (IS_ERR(ctx)) {
  389. DRM_ERROR("Failed to create default global context\n");
  390. err = PTR_ERR(ctx);
  391. goto err;
  392. }
  393. /*
  394. * For easy recognisablity, we want the kernel context to be 0 and then
  395. * all user contexts will have non-zero hw_id.
  396. */
  397. GEM_BUG_ON(ctx->hw_id);
  398. dev_priv->kernel_context = ctx;
  399. /* highest priority; preempting task */
  400. ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
  401. if (IS_ERR(ctx)) {
  402. DRM_ERROR("Failed to create default preempt context\n");
  403. err = PTR_ERR(ctx);
  404. goto err_kernel_context;
  405. }
  406. dev_priv->preempt_context = ctx;
  407. DRM_DEBUG_DRIVER("%s context support initialized\n",
  408. dev_priv->engine[RCS]->context_size ? "logical" :
  409. "fake");
  410. return 0;
  411. err_kernel_context:
  412. destroy_kernel_context(&dev_priv->kernel_context);
  413. err:
  414. return err;
  415. }
  416. void i915_gem_contexts_lost(struct drm_i915_private *dev_priv)
  417. {
  418. struct intel_engine_cs *engine;
  419. enum intel_engine_id id;
  420. lockdep_assert_held(&dev_priv->drm.struct_mutex);
  421. for_each_engine(engine, dev_priv, id) {
  422. engine->legacy_active_context = NULL;
  423. engine->legacy_active_ppgtt = NULL;
  424. if (!engine->last_retired_context)
  425. continue;
  426. engine->context_unpin(engine, engine->last_retired_context);
  427. engine->last_retired_context = NULL;
  428. }
  429. }
  430. void i915_gem_contexts_fini(struct drm_i915_private *i915)
  431. {
  432. lockdep_assert_held(&i915->drm.struct_mutex);
  433. destroy_kernel_context(&i915->preempt_context);
  434. destroy_kernel_context(&i915->kernel_context);
  435. /* Must free all deferred contexts (via flush_workqueue) first */
  436. ida_destroy(&i915->contexts.hw_ida);
  437. }
  438. static int context_idr_cleanup(int id, void *p, void *data)
  439. {
  440. struct i915_gem_context *ctx = p;
  441. context_close(ctx);
  442. return 0;
  443. }
  444. int i915_gem_context_open(struct drm_i915_private *i915,
  445. struct drm_file *file)
  446. {
  447. struct drm_i915_file_private *file_priv = file->driver_priv;
  448. struct i915_gem_context *ctx;
  449. idr_init(&file_priv->context_idr);
  450. mutex_lock(&i915->drm.struct_mutex);
  451. ctx = i915_gem_create_context(i915, file_priv);
  452. mutex_unlock(&i915->drm.struct_mutex);
  453. if (IS_ERR(ctx)) {
  454. idr_destroy(&file_priv->context_idr);
  455. return PTR_ERR(ctx);
  456. }
  457. GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
  458. return 0;
  459. }
  460. void i915_gem_context_close(struct drm_file *file)
  461. {
  462. struct drm_i915_file_private *file_priv = file->driver_priv;
  463. lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
  464. idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
  465. idr_destroy(&file_priv->context_idr);
  466. }
  467. static bool engine_has_idle_kernel_context(struct intel_engine_cs *engine)
  468. {
  469. struct i915_gem_timeline *timeline;
  470. list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
  471. struct intel_timeline *tl;
  472. if (timeline == &engine->i915->gt.global_timeline)
  473. continue;
  474. tl = &timeline->engine[engine->id];
  475. if (i915_gem_active_peek(&tl->last_request,
  476. &engine->i915->drm.struct_mutex))
  477. return false;
  478. }
  479. return intel_engine_has_kernel_context(engine);
  480. }
  481. int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
  482. {
  483. struct intel_engine_cs *engine;
  484. struct i915_gem_timeline *timeline;
  485. enum intel_engine_id id;
  486. lockdep_assert_held(&dev_priv->drm.struct_mutex);
  487. i915_gem_retire_requests(dev_priv);
  488. for_each_engine(engine, dev_priv, id) {
  489. struct drm_i915_gem_request *req;
  490. if (engine_has_idle_kernel_context(engine))
  491. continue;
  492. req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
  493. if (IS_ERR(req))
  494. return PTR_ERR(req);
  495. /* Queue this switch after all other activity */
  496. list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
  497. struct drm_i915_gem_request *prev;
  498. struct intel_timeline *tl;
  499. tl = &timeline->engine[engine->id];
  500. prev = i915_gem_active_raw(&tl->last_request,
  501. &dev_priv->drm.struct_mutex);
  502. if (prev)
  503. i915_sw_fence_await_sw_fence_gfp(&req->submit,
  504. &prev->submit,
  505. I915_FENCE_GFP);
  506. }
  507. /*
  508. * Force a flush after the switch to ensure that all rendering
  509. * and operations prior to switching to the kernel context hits
  510. * memory. This should be guaranteed by the previous request,
  511. * but an extra layer of paranoia before we declare the system
  512. * idle (on suspend etc) is advisable!
  513. */
  514. __i915_add_request(req, true);
  515. }
  516. return 0;
  517. }
  518. static bool client_is_banned(struct drm_i915_file_private *file_priv)
  519. {
  520. return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS;
  521. }
  522. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  523. struct drm_file *file)
  524. {
  525. struct drm_i915_private *dev_priv = to_i915(dev);
  526. struct drm_i915_gem_context_create *args = data;
  527. struct drm_i915_file_private *file_priv = file->driver_priv;
  528. struct i915_gem_context *ctx;
  529. int ret;
  530. if (!dev_priv->engine[RCS]->context_size)
  531. return -ENODEV;
  532. if (args->pad != 0)
  533. return -EINVAL;
  534. if (client_is_banned(file_priv)) {
  535. DRM_DEBUG("client %s[%d] banned from creating ctx\n",
  536. current->comm,
  537. pid_nr(get_task_pid(current, PIDTYPE_PID)));
  538. return -EIO;
  539. }
  540. ret = i915_mutex_lock_interruptible(dev);
  541. if (ret)
  542. return ret;
  543. ctx = i915_gem_create_context(dev_priv, file_priv);
  544. mutex_unlock(&dev->struct_mutex);
  545. if (IS_ERR(ctx))
  546. return PTR_ERR(ctx);
  547. GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
  548. args->ctx_id = ctx->user_handle;
  549. DRM_DEBUG("HW context %d created\n", args->ctx_id);
  550. return 0;
  551. }
  552. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  553. struct drm_file *file)
  554. {
  555. struct drm_i915_gem_context_destroy *args = data;
  556. struct drm_i915_file_private *file_priv = file->driver_priv;
  557. struct i915_gem_context *ctx;
  558. int ret;
  559. if (args->pad != 0)
  560. return -EINVAL;
  561. if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
  562. return -ENOENT;
  563. ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
  564. if (!ctx)
  565. return -ENOENT;
  566. ret = mutex_lock_interruptible(&dev->struct_mutex);
  567. if (ret)
  568. goto out;
  569. __destroy_hw_context(ctx, file_priv);
  570. mutex_unlock(&dev->struct_mutex);
  571. out:
  572. i915_gem_context_put(ctx);
  573. return 0;
  574. }
  575. int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
  576. struct drm_file *file)
  577. {
  578. struct drm_i915_file_private *file_priv = file->driver_priv;
  579. struct drm_i915_gem_context_param *args = data;
  580. struct i915_gem_context *ctx;
  581. int ret = 0;
  582. ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
  583. if (!ctx)
  584. return -ENOENT;
  585. args->size = 0;
  586. switch (args->param) {
  587. case I915_CONTEXT_PARAM_BAN_PERIOD:
  588. ret = -EINVAL;
  589. break;
  590. case I915_CONTEXT_PARAM_NO_ZEROMAP:
  591. args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
  592. break;
  593. case I915_CONTEXT_PARAM_GTT_SIZE:
  594. if (ctx->ppgtt)
  595. args->value = ctx->ppgtt->base.total;
  596. else if (to_i915(dev)->mm.aliasing_ppgtt)
  597. args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
  598. else
  599. args->value = to_i915(dev)->ggtt.base.total;
  600. break;
  601. case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
  602. args->value = i915_gem_context_no_error_capture(ctx);
  603. break;
  604. case I915_CONTEXT_PARAM_BANNABLE:
  605. args->value = i915_gem_context_is_bannable(ctx);
  606. break;
  607. case I915_CONTEXT_PARAM_PRIORITY:
  608. args->value = ctx->priority;
  609. break;
  610. default:
  611. ret = -EINVAL;
  612. break;
  613. }
  614. i915_gem_context_put(ctx);
  615. return ret;
  616. }
  617. int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
  618. struct drm_file *file)
  619. {
  620. struct drm_i915_file_private *file_priv = file->driver_priv;
  621. struct drm_i915_gem_context_param *args = data;
  622. struct i915_gem_context *ctx;
  623. int ret;
  624. ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
  625. if (!ctx)
  626. return -ENOENT;
  627. ret = i915_mutex_lock_interruptible(dev);
  628. if (ret)
  629. goto out;
  630. switch (args->param) {
  631. case I915_CONTEXT_PARAM_BAN_PERIOD:
  632. ret = -EINVAL;
  633. break;
  634. case I915_CONTEXT_PARAM_NO_ZEROMAP:
  635. if (args->size) {
  636. ret = -EINVAL;
  637. } else {
  638. ctx->flags &= ~CONTEXT_NO_ZEROMAP;
  639. ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
  640. }
  641. break;
  642. case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
  643. if (args->size)
  644. ret = -EINVAL;
  645. else if (args->value)
  646. i915_gem_context_set_no_error_capture(ctx);
  647. else
  648. i915_gem_context_clear_no_error_capture(ctx);
  649. break;
  650. case I915_CONTEXT_PARAM_BANNABLE:
  651. if (args->size)
  652. ret = -EINVAL;
  653. else if (!capable(CAP_SYS_ADMIN) && !args->value)
  654. ret = -EPERM;
  655. else if (args->value)
  656. i915_gem_context_set_bannable(ctx);
  657. else
  658. i915_gem_context_clear_bannable(ctx);
  659. break;
  660. case I915_CONTEXT_PARAM_PRIORITY:
  661. {
  662. int priority = args->value;
  663. if (args->size)
  664. ret = -EINVAL;
  665. else if (!to_i915(dev)->engine[RCS]->schedule)
  666. ret = -ENODEV;
  667. else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
  668. priority < I915_CONTEXT_MIN_USER_PRIORITY)
  669. ret = -EINVAL;
  670. else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
  671. !capable(CAP_SYS_NICE))
  672. ret = -EPERM;
  673. else
  674. ctx->priority = priority;
  675. }
  676. break;
  677. default:
  678. ret = -EINVAL;
  679. break;
  680. }
  681. mutex_unlock(&dev->struct_mutex);
  682. out:
  683. i915_gem_context_put(ctx);
  684. return ret;
  685. }
  686. int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
  687. void *data, struct drm_file *file)
  688. {
  689. struct drm_i915_private *dev_priv = to_i915(dev);
  690. struct drm_i915_reset_stats *args = data;
  691. struct i915_gem_context *ctx;
  692. int ret;
  693. if (args->flags || args->pad)
  694. return -EINVAL;
  695. ret = -ENOENT;
  696. rcu_read_lock();
  697. ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
  698. if (!ctx)
  699. goto out;
  700. /*
  701. * We opt for unserialised reads here. This may result in tearing
  702. * in the extremely unlikely event of a GPU hang on this context
  703. * as we are querying them. If we need that extra layer of protection,
  704. * we should wrap the hangstats with a seqlock.
  705. */
  706. if (capable(CAP_SYS_ADMIN))
  707. args->reset_count = i915_reset_count(&dev_priv->gpu_error);
  708. else
  709. args->reset_count = 0;
  710. args->batch_active = atomic_read(&ctx->guilty_count);
  711. args->batch_pending = atomic_read(&ctx->active_count);
  712. ret = 0;
  713. out:
  714. rcu_read_unlock();
  715. return ret;
  716. }
  717. #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  718. #include "selftests/mock_context.c"
  719. #include "selftests/i915_gem_context.c"
  720. #endif