kfd_device_queue_manager.c 34 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/slab.h>
  24. #include <linux/list.h>
  25. #include <linux/types.h>
  26. #include <linux/printk.h>
  27. #include <linux/bitops.h>
  28. #include <linux/sched.h>
  29. #include "kfd_priv.h"
  30. #include "kfd_device_queue_manager.h"
  31. #include "kfd_mqd_manager.h"
  32. #include "cik_regs.h"
  33. #include "kfd_kernel_queue.h"
  34. /* Size of the per-pipe EOP queue */
  35. #define CIK_HPD_EOP_BYTES_LOG2 11
  36. #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
  37. static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
  38. unsigned int pasid, unsigned int vmid);
  39. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  40. struct queue *q,
  41. struct qcm_process_device *qpd);
  42. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  43. enum kfd_unmap_queues_filter filter,
  44. uint32_t filter_param);
  45. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  46. enum kfd_unmap_queues_filter filter,
  47. uint32_t filter_param);
  48. static int map_queues_cpsch(struct device_queue_manager *dqm);
  49. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  50. struct queue *q,
  51. struct qcm_process_device *qpd);
  52. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  53. unsigned int sdma_queue_id);
  54. static inline
  55. enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
  56. {
  57. if (type == KFD_QUEUE_TYPE_SDMA)
  58. return KFD_MQD_TYPE_SDMA;
  59. return KFD_MQD_TYPE_CP;
  60. }
  61. static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
  62. {
  63. int i;
  64. int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
  65. + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
  66. /* queue is available for KFD usage if bit is 1 */
  67. for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
  68. if (test_bit(pipe_offset + i,
  69. dqm->dev->shared_resources.queue_bitmap))
  70. return true;
  71. return false;
  72. }
  73. unsigned int get_queues_num(struct device_queue_manager *dqm)
  74. {
  75. return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
  76. KGD_MAX_QUEUES);
  77. }
  78. unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
  79. {
  80. return dqm->dev->shared_resources.num_queue_per_pipe;
  81. }
  82. unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
  83. {
  84. return dqm->dev->shared_resources.num_pipe_per_mec;
  85. }
  86. void program_sh_mem_settings(struct device_queue_manager *dqm,
  87. struct qcm_process_device *qpd)
  88. {
  89. return dqm->dev->kfd2kgd->program_sh_mem_settings(
  90. dqm->dev->kgd, qpd->vmid,
  91. qpd->sh_mem_config,
  92. qpd->sh_mem_ape1_base,
  93. qpd->sh_mem_ape1_limit,
  94. qpd->sh_mem_bases);
  95. }
  96. static int allocate_vmid(struct device_queue_manager *dqm,
  97. struct qcm_process_device *qpd,
  98. struct queue *q)
  99. {
  100. int bit, allocated_vmid;
  101. if (dqm->vmid_bitmap == 0)
  102. return -ENOMEM;
  103. bit = find_first_bit((unsigned long *)&dqm->vmid_bitmap,
  104. dqm->dev->vm_info.vmid_num_kfd);
  105. clear_bit(bit, (unsigned long *)&dqm->vmid_bitmap);
  106. allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
  107. pr_debug("vmid allocation %d\n", allocated_vmid);
  108. qpd->vmid = allocated_vmid;
  109. q->properties.vmid = allocated_vmid;
  110. set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
  111. program_sh_mem_settings(dqm, qpd);
  112. return 0;
  113. }
  114. static void deallocate_vmid(struct device_queue_manager *dqm,
  115. struct qcm_process_device *qpd,
  116. struct queue *q)
  117. {
  118. int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
  119. /* Release the vmid mapping */
  120. set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
  121. set_bit(bit, (unsigned long *)&dqm->vmid_bitmap);
  122. qpd->vmid = 0;
  123. q->properties.vmid = 0;
  124. }
  125. static int create_queue_nocpsch(struct device_queue_manager *dqm,
  126. struct queue *q,
  127. struct qcm_process_device *qpd)
  128. {
  129. int retval;
  130. print_queue(q);
  131. mutex_lock(&dqm->lock);
  132. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  133. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  134. dqm->total_queue_count);
  135. retval = -EPERM;
  136. goto out_unlock;
  137. }
  138. if (list_empty(&qpd->queues_list)) {
  139. retval = allocate_vmid(dqm, qpd, q);
  140. if (retval)
  141. goto out_unlock;
  142. }
  143. q->properties.vmid = qpd->vmid;
  144. q->properties.tba_addr = qpd->tba_addr;
  145. q->properties.tma_addr = qpd->tma_addr;
  146. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
  147. retval = create_compute_queue_nocpsch(dqm, q, qpd);
  148. else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  149. retval = create_sdma_queue_nocpsch(dqm, q, qpd);
  150. else
  151. retval = -EINVAL;
  152. if (retval) {
  153. if (list_empty(&qpd->queues_list))
  154. deallocate_vmid(dqm, qpd, q);
  155. goto out_unlock;
  156. }
  157. list_add(&q->list, &qpd->queues_list);
  158. qpd->queue_count++;
  159. if (q->properties.is_active)
  160. dqm->queue_count++;
  161. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  162. dqm->sdma_queue_count++;
  163. /*
  164. * Unconditionally increment this counter, regardless of the queue's
  165. * type or whether the queue is active.
  166. */
  167. dqm->total_queue_count++;
  168. pr_debug("Total of %d queues are accountable so far\n",
  169. dqm->total_queue_count);
  170. out_unlock:
  171. mutex_unlock(&dqm->lock);
  172. return retval;
  173. }
  174. static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
  175. {
  176. bool set;
  177. int pipe, bit, i;
  178. set = false;
  179. for (pipe = dqm->next_pipe_to_allocate, i = 0;
  180. i < get_pipes_per_mec(dqm);
  181. pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
  182. if (!is_pipe_enabled(dqm, 0, pipe))
  183. continue;
  184. if (dqm->allocated_queues[pipe] != 0) {
  185. bit = find_first_bit(
  186. (unsigned long *)&dqm->allocated_queues[pipe],
  187. get_queues_per_pipe(dqm));
  188. clear_bit(bit,
  189. (unsigned long *)&dqm->allocated_queues[pipe]);
  190. q->pipe = pipe;
  191. q->queue = bit;
  192. set = true;
  193. break;
  194. }
  195. }
  196. if (!set)
  197. return -EBUSY;
  198. pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
  199. /* horizontal hqd allocation */
  200. dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
  201. return 0;
  202. }
  203. static inline void deallocate_hqd(struct device_queue_manager *dqm,
  204. struct queue *q)
  205. {
  206. set_bit(q->queue, (unsigned long *)&dqm->allocated_queues[q->pipe]);
  207. }
  208. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  209. struct queue *q,
  210. struct qcm_process_device *qpd)
  211. {
  212. int retval;
  213. struct mqd_manager *mqd;
  214. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
  215. if (!mqd)
  216. return -ENOMEM;
  217. retval = allocate_hqd(dqm, q);
  218. if (retval)
  219. return retval;
  220. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  221. &q->gart_mqd_addr, &q->properties);
  222. if (retval)
  223. goto out_deallocate_hqd;
  224. pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
  225. q->pipe, q->queue);
  226. dqm->dev->kfd2kgd->set_scratch_backing_va(
  227. dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
  228. if (!q->properties.is_active)
  229. return 0;
  230. retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties,
  231. q->process->mm);
  232. if (retval)
  233. goto out_uninit_mqd;
  234. return 0;
  235. out_uninit_mqd:
  236. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  237. out_deallocate_hqd:
  238. deallocate_hqd(dqm, q);
  239. return retval;
  240. }
  241. /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
  242. * to avoid asynchronized access
  243. */
  244. static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
  245. struct qcm_process_device *qpd,
  246. struct queue *q)
  247. {
  248. int retval;
  249. struct mqd_manager *mqd;
  250. mqd = dqm->ops.get_mqd_manager(dqm,
  251. get_mqd_type_from_queue_type(q->properties.type));
  252. if (!mqd)
  253. return -ENOMEM;
  254. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
  255. deallocate_hqd(dqm, q);
  256. } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  257. dqm->sdma_queue_count--;
  258. deallocate_sdma_queue(dqm, q->sdma_id);
  259. } else {
  260. pr_debug("q->properties.type %d is invalid\n",
  261. q->properties.type);
  262. return -EINVAL;
  263. }
  264. dqm->total_queue_count--;
  265. retval = mqd->destroy_mqd(mqd, q->mqd,
  266. KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
  267. KFD_UNMAP_LATENCY_MS,
  268. q->pipe, q->queue);
  269. if (retval == -ETIME)
  270. qpd->reset_wavefronts = true;
  271. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  272. list_del(&q->list);
  273. if (list_empty(&qpd->queues_list)) {
  274. if (qpd->reset_wavefronts) {
  275. pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
  276. dqm->dev);
  277. /* dbgdev_wave_reset_wavefronts has to be called before
  278. * deallocate_vmid(), i.e. when vmid is still in use.
  279. */
  280. dbgdev_wave_reset_wavefronts(dqm->dev,
  281. qpd->pqm->process);
  282. qpd->reset_wavefronts = false;
  283. }
  284. deallocate_vmid(dqm, qpd, q);
  285. }
  286. qpd->queue_count--;
  287. if (q->properties.is_active)
  288. dqm->queue_count--;
  289. return retval;
  290. }
  291. static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
  292. struct qcm_process_device *qpd,
  293. struct queue *q)
  294. {
  295. int retval;
  296. mutex_lock(&dqm->lock);
  297. retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
  298. mutex_unlock(&dqm->lock);
  299. return retval;
  300. }
  301. static int update_queue(struct device_queue_manager *dqm, struct queue *q)
  302. {
  303. int retval;
  304. struct mqd_manager *mqd;
  305. bool prev_active = false;
  306. mutex_lock(&dqm->lock);
  307. mqd = dqm->ops.get_mqd_manager(dqm,
  308. get_mqd_type_from_queue_type(q->properties.type));
  309. if (!mqd) {
  310. retval = -ENOMEM;
  311. goto out_unlock;
  312. }
  313. /* Save previous activity state for counters */
  314. prev_active = q->properties.is_active;
  315. /* Make sure the queue is unmapped before updating the MQD */
  316. if (sched_policy != KFD_SCHED_POLICY_NO_HWS) {
  317. retval = unmap_queues_cpsch(dqm,
  318. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  319. if (retval) {
  320. pr_err("unmap queue failed\n");
  321. goto out_unlock;
  322. }
  323. } else if (prev_active &&
  324. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  325. q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
  326. retval = mqd->destroy_mqd(mqd, q->mqd,
  327. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  328. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  329. if (retval) {
  330. pr_err("destroy mqd failed\n");
  331. goto out_unlock;
  332. }
  333. }
  334. retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
  335. /*
  336. * check active state vs. the previous state and modify
  337. * counter accordingly. map_queues_cpsch uses the
  338. * dqm->queue_count to determine whether a new runlist must be
  339. * uploaded.
  340. */
  341. if (q->properties.is_active && !prev_active)
  342. dqm->queue_count++;
  343. else if (!q->properties.is_active && prev_active)
  344. dqm->queue_count--;
  345. if (sched_policy != KFD_SCHED_POLICY_NO_HWS)
  346. retval = map_queues_cpsch(dqm);
  347. else if (q->properties.is_active &&
  348. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  349. q->properties.type == KFD_QUEUE_TYPE_SDMA))
  350. retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue,
  351. &q->properties, q->process->mm);
  352. out_unlock:
  353. mutex_unlock(&dqm->lock);
  354. return retval;
  355. }
  356. static struct mqd_manager *get_mqd_manager(
  357. struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
  358. {
  359. struct mqd_manager *mqd;
  360. if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
  361. return NULL;
  362. pr_debug("mqd type %d\n", type);
  363. mqd = dqm->mqds[type];
  364. if (!mqd) {
  365. mqd = mqd_manager_init(type, dqm->dev);
  366. if (!mqd)
  367. pr_err("mqd manager is NULL");
  368. dqm->mqds[type] = mqd;
  369. }
  370. return mqd;
  371. }
  372. static int register_process(struct device_queue_manager *dqm,
  373. struct qcm_process_device *qpd)
  374. {
  375. struct device_process_node *n;
  376. int retval;
  377. n = kzalloc(sizeof(*n), GFP_KERNEL);
  378. if (!n)
  379. return -ENOMEM;
  380. n->qpd = qpd;
  381. mutex_lock(&dqm->lock);
  382. list_add(&n->list, &dqm->queues);
  383. retval = dqm->asic_ops.update_qpd(dqm, qpd);
  384. dqm->processes_count++;
  385. mutex_unlock(&dqm->lock);
  386. return retval;
  387. }
  388. static int unregister_process(struct device_queue_manager *dqm,
  389. struct qcm_process_device *qpd)
  390. {
  391. int retval;
  392. struct device_process_node *cur, *next;
  393. pr_debug("qpd->queues_list is %s\n",
  394. list_empty(&qpd->queues_list) ? "empty" : "not empty");
  395. retval = 0;
  396. mutex_lock(&dqm->lock);
  397. list_for_each_entry_safe(cur, next, &dqm->queues, list) {
  398. if (qpd == cur->qpd) {
  399. list_del(&cur->list);
  400. kfree(cur);
  401. dqm->processes_count--;
  402. goto out;
  403. }
  404. }
  405. /* qpd not found in dqm list */
  406. retval = 1;
  407. out:
  408. mutex_unlock(&dqm->lock);
  409. return retval;
  410. }
  411. static int
  412. set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
  413. unsigned int vmid)
  414. {
  415. uint32_t pasid_mapping;
  416. pasid_mapping = (pasid == 0) ? 0 :
  417. (uint32_t)pasid |
  418. ATC_VMID_PASID_MAPPING_VALID;
  419. return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
  420. dqm->dev->kgd, pasid_mapping,
  421. vmid);
  422. }
  423. static void init_interrupts(struct device_queue_manager *dqm)
  424. {
  425. unsigned int i;
  426. for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
  427. if (is_pipe_enabled(dqm, 0, i))
  428. dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
  429. }
  430. static int initialize_nocpsch(struct device_queue_manager *dqm)
  431. {
  432. int pipe, queue;
  433. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  434. dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
  435. sizeof(unsigned int), GFP_KERNEL);
  436. if (!dqm->allocated_queues)
  437. return -ENOMEM;
  438. mutex_init(&dqm->lock);
  439. INIT_LIST_HEAD(&dqm->queues);
  440. dqm->queue_count = dqm->next_pipe_to_allocate = 0;
  441. dqm->sdma_queue_count = 0;
  442. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  443. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  444. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
  445. if (test_bit(pipe_offset + queue,
  446. dqm->dev->shared_resources.queue_bitmap))
  447. dqm->allocated_queues[pipe] |= 1 << queue;
  448. }
  449. dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
  450. dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
  451. return 0;
  452. }
  453. static void uninitialize(struct device_queue_manager *dqm)
  454. {
  455. int i;
  456. WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
  457. kfree(dqm->allocated_queues);
  458. for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
  459. kfree(dqm->mqds[i]);
  460. mutex_destroy(&dqm->lock);
  461. kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
  462. }
  463. static int start_nocpsch(struct device_queue_manager *dqm)
  464. {
  465. init_interrupts(dqm);
  466. return 0;
  467. }
  468. static int stop_nocpsch(struct device_queue_manager *dqm)
  469. {
  470. return 0;
  471. }
  472. static int allocate_sdma_queue(struct device_queue_manager *dqm,
  473. unsigned int *sdma_queue_id)
  474. {
  475. int bit;
  476. if (dqm->sdma_bitmap == 0)
  477. return -ENOMEM;
  478. bit = find_first_bit((unsigned long *)&dqm->sdma_bitmap,
  479. CIK_SDMA_QUEUES);
  480. clear_bit(bit, (unsigned long *)&dqm->sdma_bitmap);
  481. *sdma_queue_id = bit;
  482. return 0;
  483. }
  484. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  485. unsigned int sdma_queue_id)
  486. {
  487. if (sdma_queue_id >= CIK_SDMA_QUEUES)
  488. return;
  489. set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap);
  490. }
  491. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  492. struct queue *q,
  493. struct qcm_process_device *qpd)
  494. {
  495. struct mqd_manager *mqd;
  496. int retval;
  497. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
  498. if (!mqd)
  499. return -ENOMEM;
  500. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  501. if (retval)
  502. return retval;
  503. q->properties.sdma_queue_id = q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
  504. q->properties.sdma_engine_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
  505. pr_debug("SDMA id is: %d\n", q->sdma_id);
  506. pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
  507. pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
  508. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  509. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  510. &q->gart_mqd_addr, &q->properties);
  511. if (retval)
  512. goto out_deallocate_sdma_queue;
  513. retval = mqd->load_mqd(mqd, q->mqd, 0, 0, &q->properties, NULL);
  514. if (retval)
  515. goto out_uninit_mqd;
  516. return 0;
  517. out_uninit_mqd:
  518. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  519. out_deallocate_sdma_queue:
  520. deallocate_sdma_queue(dqm, q->sdma_id);
  521. return retval;
  522. }
  523. /*
  524. * Device Queue Manager implementation for cp scheduler
  525. */
  526. static int set_sched_resources(struct device_queue_manager *dqm)
  527. {
  528. int i, mec;
  529. struct scheduling_resources res;
  530. res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
  531. res.queue_mask = 0;
  532. for (i = 0; i < KGD_MAX_QUEUES; ++i) {
  533. mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
  534. / dqm->dev->shared_resources.num_pipe_per_mec;
  535. if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
  536. continue;
  537. /* only acquire queues from the first MEC */
  538. if (mec > 0)
  539. continue;
  540. /* This situation may be hit in the future if a new HW
  541. * generation exposes more than 64 queues. If so, the
  542. * definition of res.queue_mask needs updating
  543. */
  544. if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
  545. pr_err("Invalid queue enabled by amdgpu: %d\n", i);
  546. break;
  547. }
  548. res.queue_mask |= (1ull << i);
  549. }
  550. res.gws_mask = res.oac_mask = res.gds_heap_base =
  551. res.gds_heap_size = 0;
  552. pr_debug("Scheduling resources:\n"
  553. "vmid mask: 0x%8X\n"
  554. "queue mask: 0x%8llX\n",
  555. res.vmid_mask, res.queue_mask);
  556. return pm_send_set_resources(&dqm->packets, &res);
  557. }
  558. static int initialize_cpsch(struct device_queue_manager *dqm)
  559. {
  560. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  561. mutex_init(&dqm->lock);
  562. INIT_LIST_HEAD(&dqm->queues);
  563. dqm->queue_count = dqm->processes_count = 0;
  564. dqm->sdma_queue_count = 0;
  565. dqm->active_runlist = false;
  566. dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
  567. return 0;
  568. }
  569. static int start_cpsch(struct device_queue_manager *dqm)
  570. {
  571. int retval;
  572. retval = 0;
  573. retval = pm_init(&dqm->packets, dqm);
  574. if (retval)
  575. goto fail_packet_manager_init;
  576. retval = set_sched_resources(dqm);
  577. if (retval)
  578. goto fail_set_sched_resources;
  579. pr_debug("Allocating fence memory\n");
  580. /* allocate fence memory on the gart */
  581. retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
  582. &dqm->fence_mem);
  583. if (retval)
  584. goto fail_allocate_vidmem;
  585. dqm->fence_addr = dqm->fence_mem->cpu_ptr;
  586. dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
  587. init_interrupts(dqm);
  588. mutex_lock(&dqm->lock);
  589. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  590. mutex_unlock(&dqm->lock);
  591. return 0;
  592. fail_allocate_vidmem:
  593. fail_set_sched_resources:
  594. pm_uninit(&dqm->packets);
  595. fail_packet_manager_init:
  596. return retval;
  597. }
  598. static int stop_cpsch(struct device_queue_manager *dqm)
  599. {
  600. mutex_lock(&dqm->lock);
  601. unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  602. mutex_unlock(&dqm->lock);
  603. kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
  604. pm_uninit(&dqm->packets);
  605. return 0;
  606. }
  607. static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
  608. struct kernel_queue *kq,
  609. struct qcm_process_device *qpd)
  610. {
  611. mutex_lock(&dqm->lock);
  612. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  613. pr_warn("Can't create new kernel queue because %d queues were already created\n",
  614. dqm->total_queue_count);
  615. mutex_unlock(&dqm->lock);
  616. return -EPERM;
  617. }
  618. /*
  619. * Unconditionally increment this counter, regardless of the queue's
  620. * type or whether the queue is active.
  621. */
  622. dqm->total_queue_count++;
  623. pr_debug("Total of %d queues are accountable so far\n",
  624. dqm->total_queue_count);
  625. list_add(&kq->list, &qpd->priv_queue_list);
  626. dqm->queue_count++;
  627. qpd->is_debug = true;
  628. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  629. mutex_unlock(&dqm->lock);
  630. return 0;
  631. }
  632. static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
  633. struct kernel_queue *kq,
  634. struct qcm_process_device *qpd)
  635. {
  636. mutex_lock(&dqm->lock);
  637. list_del(&kq->list);
  638. dqm->queue_count--;
  639. qpd->is_debug = false;
  640. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  641. /*
  642. * Unconditionally decrement this counter, regardless of the queue's
  643. * type.
  644. */
  645. dqm->total_queue_count--;
  646. pr_debug("Total of %d queues are accountable so far\n",
  647. dqm->total_queue_count);
  648. mutex_unlock(&dqm->lock);
  649. }
  650. static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
  651. struct qcm_process_device *qpd)
  652. {
  653. int retval;
  654. struct mqd_manager *mqd;
  655. retval = 0;
  656. mutex_lock(&dqm->lock);
  657. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  658. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  659. dqm->total_queue_count);
  660. retval = -EPERM;
  661. goto out;
  662. }
  663. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  664. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  665. if (retval)
  666. goto out;
  667. q->properties.sdma_queue_id =
  668. q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
  669. q->properties.sdma_engine_id =
  670. q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
  671. }
  672. mqd = dqm->ops.get_mqd_manager(dqm,
  673. get_mqd_type_from_queue_type(q->properties.type));
  674. if (!mqd) {
  675. retval = -ENOMEM;
  676. goto out;
  677. }
  678. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  679. q->properties.tba_addr = qpd->tba_addr;
  680. q->properties.tma_addr = qpd->tma_addr;
  681. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  682. &q->gart_mqd_addr, &q->properties);
  683. if (retval)
  684. goto out;
  685. list_add(&q->list, &qpd->queues_list);
  686. qpd->queue_count++;
  687. if (q->properties.is_active) {
  688. dqm->queue_count++;
  689. retval = execute_queues_cpsch(dqm,
  690. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  691. }
  692. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  693. dqm->sdma_queue_count++;
  694. /*
  695. * Unconditionally increment this counter, regardless of the queue's
  696. * type or whether the queue is active.
  697. */
  698. dqm->total_queue_count++;
  699. pr_debug("Total of %d queues are accountable so far\n",
  700. dqm->total_queue_count);
  701. out:
  702. mutex_unlock(&dqm->lock);
  703. return retval;
  704. }
  705. int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
  706. unsigned int fence_value,
  707. unsigned int timeout_ms)
  708. {
  709. unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
  710. while (*fence_addr != fence_value) {
  711. if (time_after(jiffies, end_jiffies)) {
  712. pr_err("qcm fence wait loop timeout expired\n");
  713. return -ETIME;
  714. }
  715. schedule();
  716. }
  717. return 0;
  718. }
  719. static int unmap_sdma_queues(struct device_queue_manager *dqm,
  720. unsigned int sdma_engine)
  721. {
  722. return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
  723. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
  724. sdma_engine);
  725. }
  726. /* dqm->lock mutex has to be locked before calling this function */
  727. static int map_queues_cpsch(struct device_queue_manager *dqm)
  728. {
  729. int retval;
  730. if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
  731. return 0;
  732. if (dqm->active_runlist)
  733. return 0;
  734. retval = pm_send_runlist(&dqm->packets, &dqm->queues);
  735. if (retval) {
  736. pr_err("failed to execute runlist\n");
  737. return retval;
  738. }
  739. dqm->active_runlist = true;
  740. return retval;
  741. }
  742. /* dqm->lock mutex has to be locked before calling this function */
  743. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  744. enum kfd_unmap_queues_filter filter,
  745. uint32_t filter_param)
  746. {
  747. int retval = 0;
  748. if (!dqm->active_runlist)
  749. return retval;
  750. pr_debug("Before destroying queues, sdma queue count is : %u\n",
  751. dqm->sdma_queue_count);
  752. if (dqm->sdma_queue_count > 0) {
  753. unmap_sdma_queues(dqm, 0);
  754. unmap_sdma_queues(dqm, 1);
  755. }
  756. retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
  757. filter, filter_param, false, 0);
  758. if (retval)
  759. return retval;
  760. *dqm->fence_addr = KFD_FENCE_INIT;
  761. pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
  762. KFD_FENCE_COMPLETED);
  763. /* should be timed out */
  764. retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
  765. QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
  766. if (retval)
  767. return retval;
  768. pm_release_ib(&dqm->packets);
  769. dqm->active_runlist = false;
  770. return retval;
  771. }
  772. /* dqm->lock mutex has to be locked before calling this function */
  773. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  774. enum kfd_unmap_queues_filter filter,
  775. uint32_t filter_param)
  776. {
  777. int retval;
  778. retval = unmap_queues_cpsch(dqm, filter, filter_param);
  779. if (retval) {
  780. pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
  781. return retval;
  782. }
  783. return map_queues_cpsch(dqm);
  784. }
  785. static int destroy_queue_cpsch(struct device_queue_manager *dqm,
  786. struct qcm_process_device *qpd,
  787. struct queue *q)
  788. {
  789. int retval;
  790. struct mqd_manager *mqd;
  791. bool preempt_all_queues;
  792. preempt_all_queues = false;
  793. retval = 0;
  794. /* remove queue from list to prevent rescheduling after preemption */
  795. mutex_lock(&dqm->lock);
  796. if (qpd->is_debug) {
  797. /*
  798. * error, currently we do not allow to destroy a queue
  799. * of a currently debugged process
  800. */
  801. retval = -EBUSY;
  802. goto failed_try_destroy_debugged_queue;
  803. }
  804. mqd = dqm->ops.get_mqd_manager(dqm,
  805. get_mqd_type_from_queue_type(q->properties.type));
  806. if (!mqd) {
  807. retval = -ENOMEM;
  808. goto failed;
  809. }
  810. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  811. dqm->sdma_queue_count--;
  812. deallocate_sdma_queue(dqm, q->sdma_id);
  813. }
  814. list_del(&q->list);
  815. qpd->queue_count--;
  816. if (q->properties.is_active)
  817. dqm->queue_count--;
  818. retval = execute_queues_cpsch(dqm,
  819. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  820. if (retval == -ETIME)
  821. qpd->reset_wavefronts = true;
  822. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  823. /*
  824. * Unconditionally decrement this counter, regardless of the queue's
  825. * type
  826. */
  827. dqm->total_queue_count--;
  828. pr_debug("Total of %d queues are accountable so far\n",
  829. dqm->total_queue_count);
  830. mutex_unlock(&dqm->lock);
  831. return 0;
  832. failed:
  833. failed_try_destroy_debugged_queue:
  834. mutex_unlock(&dqm->lock);
  835. return retval;
  836. }
  837. /*
  838. * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
  839. * stay in user mode.
  840. */
  841. #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
  842. /* APE1 limit is inclusive and 64K aligned. */
  843. #define APE1_LIMIT_ALIGNMENT 0xFFFF
  844. static bool set_cache_memory_policy(struct device_queue_manager *dqm,
  845. struct qcm_process_device *qpd,
  846. enum cache_policy default_policy,
  847. enum cache_policy alternate_policy,
  848. void __user *alternate_aperture_base,
  849. uint64_t alternate_aperture_size)
  850. {
  851. bool retval;
  852. mutex_lock(&dqm->lock);
  853. if (alternate_aperture_size == 0) {
  854. /* base > limit disables APE1 */
  855. qpd->sh_mem_ape1_base = 1;
  856. qpd->sh_mem_ape1_limit = 0;
  857. } else {
  858. /*
  859. * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
  860. * SH_MEM_APE1_BASE[31:0], 0x0000 }
  861. * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
  862. * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
  863. * Verify that the base and size parameters can be
  864. * represented in this format and convert them.
  865. * Additionally restrict APE1 to user-mode addresses.
  866. */
  867. uint64_t base = (uintptr_t)alternate_aperture_base;
  868. uint64_t limit = base + alternate_aperture_size - 1;
  869. if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
  870. (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
  871. retval = false;
  872. goto out;
  873. }
  874. qpd->sh_mem_ape1_base = base >> 16;
  875. qpd->sh_mem_ape1_limit = limit >> 16;
  876. }
  877. retval = dqm->asic_ops.set_cache_memory_policy(
  878. dqm,
  879. qpd,
  880. default_policy,
  881. alternate_policy,
  882. alternate_aperture_base,
  883. alternate_aperture_size);
  884. if ((sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
  885. program_sh_mem_settings(dqm, qpd);
  886. pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
  887. qpd->sh_mem_config, qpd->sh_mem_ape1_base,
  888. qpd->sh_mem_ape1_limit);
  889. out:
  890. mutex_unlock(&dqm->lock);
  891. return retval;
  892. }
  893. static int set_trap_handler(struct device_queue_manager *dqm,
  894. struct qcm_process_device *qpd,
  895. uint64_t tba_addr,
  896. uint64_t tma_addr)
  897. {
  898. uint64_t *tma;
  899. if (dqm->dev->cwsr_enabled) {
  900. /* Jump from CWSR trap handler to user trap */
  901. tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
  902. tma[0] = tba_addr;
  903. tma[1] = tma_addr;
  904. } else {
  905. qpd->tba_addr = tba_addr;
  906. qpd->tma_addr = tma_addr;
  907. }
  908. return 0;
  909. }
  910. static int process_termination_nocpsch(struct device_queue_manager *dqm,
  911. struct qcm_process_device *qpd)
  912. {
  913. struct queue *q, *next;
  914. struct device_process_node *cur, *next_dpn;
  915. int retval = 0;
  916. mutex_lock(&dqm->lock);
  917. /* Clear all user mode queues */
  918. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  919. int ret;
  920. ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
  921. if (ret)
  922. retval = ret;
  923. }
  924. /* Unregister process */
  925. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  926. if (qpd == cur->qpd) {
  927. list_del(&cur->list);
  928. kfree(cur);
  929. dqm->processes_count--;
  930. break;
  931. }
  932. }
  933. mutex_unlock(&dqm->lock);
  934. return retval;
  935. }
  936. static int process_termination_cpsch(struct device_queue_manager *dqm,
  937. struct qcm_process_device *qpd)
  938. {
  939. int retval;
  940. struct queue *q, *next;
  941. struct kernel_queue *kq, *kq_next;
  942. struct mqd_manager *mqd;
  943. struct device_process_node *cur, *next_dpn;
  944. enum kfd_unmap_queues_filter filter =
  945. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
  946. retval = 0;
  947. mutex_lock(&dqm->lock);
  948. /* Clean all kernel queues */
  949. list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
  950. list_del(&kq->list);
  951. dqm->queue_count--;
  952. qpd->is_debug = false;
  953. dqm->total_queue_count--;
  954. filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
  955. }
  956. /* Clear all user mode queues */
  957. list_for_each_entry(q, &qpd->queues_list, list) {
  958. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  959. dqm->sdma_queue_count--;
  960. if (q->properties.is_active)
  961. dqm->queue_count--;
  962. dqm->total_queue_count--;
  963. }
  964. /* Unregister process */
  965. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  966. if (qpd == cur->qpd) {
  967. list_del(&cur->list);
  968. kfree(cur);
  969. dqm->processes_count--;
  970. break;
  971. }
  972. }
  973. retval = execute_queues_cpsch(dqm, filter, 0);
  974. if (retval || qpd->reset_wavefronts) {
  975. pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
  976. dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
  977. qpd->reset_wavefronts = false;
  978. }
  979. /* lastly, free mqd resources */
  980. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  981. mqd = dqm->ops.get_mqd_manager(dqm,
  982. get_mqd_type_from_queue_type(q->properties.type));
  983. if (!mqd) {
  984. retval = -ENOMEM;
  985. goto out;
  986. }
  987. list_del(&q->list);
  988. qpd->queue_count--;
  989. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  990. }
  991. out:
  992. mutex_unlock(&dqm->lock);
  993. return retval;
  994. }
  995. struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
  996. {
  997. struct device_queue_manager *dqm;
  998. pr_debug("Loading device queue manager\n");
  999. dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
  1000. if (!dqm)
  1001. return NULL;
  1002. dqm->dev = dev;
  1003. switch (sched_policy) {
  1004. case KFD_SCHED_POLICY_HWS:
  1005. case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
  1006. /* initialize dqm for cp scheduling */
  1007. dqm->ops.create_queue = create_queue_cpsch;
  1008. dqm->ops.initialize = initialize_cpsch;
  1009. dqm->ops.start = start_cpsch;
  1010. dqm->ops.stop = stop_cpsch;
  1011. dqm->ops.destroy_queue = destroy_queue_cpsch;
  1012. dqm->ops.update_queue = update_queue;
  1013. dqm->ops.get_mqd_manager = get_mqd_manager;
  1014. dqm->ops.register_process = register_process;
  1015. dqm->ops.unregister_process = unregister_process;
  1016. dqm->ops.uninitialize = uninitialize;
  1017. dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
  1018. dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
  1019. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1020. dqm->ops.set_trap_handler = set_trap_handler;
  1021. dqm->ops.process_termination = process_termination_cpsch;
  1022. break;
  1023. case KFD_SCHED_POLICY_NO_HWS:
  1024. /* initialize dqm for no cp scheduling */
  1025. dqm->ops.start = start_nocpsch;
  1026. dqm->ops.stop = stop_nocpsch;
  1027. dqm->ops.create_queue = create_queue_nocpsch;
  1028. dqm->ops.destroy_queue = destroy_queue_nocpsch;
  1029. dqm->ops.update_queue = update_queue;
  1030. dqm->ops.get_mqd_manager = get_mqd_manager;
  1031. dqm->ops.register_process = register_process;
  1032. dqm->ops.unregister_process = unregister_process;
  1033. dqm->ops.initialize = initialize_nocpsch;
  1034. dqm->ops.uninitialize = uninitialize;
  1035. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1036. dqm->ops.set_trap_handler = set_trap_handler;
  1037. dqm->ops.process_termination = process_termination_nocpsch;
  1038. break;
  1039. default:
  1040. pr_err("Invalid scheduling policy %d\n", sched_policy);
  1041. goto out_free;
  1042. }
  1043. switch (dev->device_info->asic_family) {
  1044. case CHIP_CARRIZO:
  1045. device_queue_manager_init_vi(&dqm->asic_ops);
  1046. break;
  1047. case CHIP_KAVERI:
  1048. device_queue_manager_init_cik(&dqm->asic_ops);
  1049. break;
  1050. default:
  1051. WARN(1, "Unexpected ASIC family %u",
  1052. dev->device_info->asic_family);
  1053. goto out_free;
  1054. }
  1055. if (!dqm->ops.initialize(dqm))
  1056. return dqm;
  1057. out_free:
  1058. kfree(dqm);
  1059. return NULL;
  1060. }
  1061. void device_queue_manager_uninit(struct device_queue_manager *dqm)
  1062. {
  1063. dqm->ops.uninitialize(dqm);
  1064. kfree(dqm);
  1065. }
  1066. #if defined(CONFIG_DEBUG_FS)
  1067. static void seq_reg_dump(struct seq_file *m,
  1068. uint32_t (*dump)[2], uint32_t n_regs)
  1069. {
  1070. uint32_t i, count;
  1071. for (i = 0, count = 0; i < n_regs; i++) {
  1072. if (count == 0 ||
  1073. dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
  1074. seq_printf(m, "%s %08x: %08x",
  1075. i ? "\n" : "",
  1076. dump[i][0], dump[i][1]);
  1077. count = 7;
  1078. } else {
  1079. seq_printf(m, " %08x", dump[i][1]);
  1080. count--;
  1081. }
  1082. }
  1083. seq_puts(m, "\n");
  1084. }
  1085. int dqm_debugfs_hqds(struct seq_file *m, void *data)
  1086. {
  1087. struct device_queue_manager *dqm = data;
  1088. uint32_t (*dump)[2], n_regs;
  1089. int pipe, queue;
  1090. int r = 0;
  1091. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  1092. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  1093. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
  1094. if (!test_bit(pipe_offset + queue,
  1095. dqm->dev->shared_resources.queue_bitmap))
  1096. continue;
  1097. r = dqm->dev->kfd2kgd->hqd_dump(
  1098. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1099. if (r)
  1100. break;
  1101. seq_printf(m, " CP Pipe %d, Queue %d\n",
  1102. pipe, queue);
  1103. seq_reg_dump(m, dump, n_regs);
  1104. kfree(dump);
  1105. }
  1106. }
  1107. for (pipe = 0; pipe < CIK_SDMA_ENGINE_NUM; pipe++) {
  1108. for (queue = 0; queue < CIK_SDMA_QUEUES_PER_ENGINE; queue++) {
  1109. r = dqm->dev->kfd2kgd->hqd_sdma_dump(
  1110. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1111. if (r)
  1112. break;
  1113. seq_printf(m, " SDMA Engine %d, RLC %d\n",
  1114. pipe, queue);
  1115. seq_reg_dump(m, dump, n_regs);
  1116. kfree(dump);
  1117. }
  1118. }
  1119. return r;
  1120. }
  1121. #endif