kfd_device.c 16 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. */
  22. #include <linux/amd-iommu.h>
  23. #include <linux/bsearch.h>
  24. #include <linux/pci.h>
  25. #include <linux/slab.h>
  26. #include "kfd_priv.h"
  27. #include "kfd_device_queue_manager.h"
  28. #include "kfd_pm4_headers_vi.h"
  29. #include "cwsr_trap_handler_gfx8.asm"
  30. #define MQD_SIZE_ALIGNED 768
  31. static const struct kfd_device_info kaveri_device_info = {
  32. .asic_family = CHIP_KAVERI,
  33. .max_pasid_bits = 16,
  34. /* max num of queues for KV.TODO should be a dynamic value */
  35. .max_no_of_hqd = 24,
  36. .ih_ring_entry_size = 4 * sizeof(uint32_t),
  37. .event_interrupt_class = &event_interrupt_class_cik,
  38. .num_of_watch_points = 4,
  39. .mqd_size_aligned = MQD_SIZE_ALIGNED,
  40. .supports_cwsr = false,
  41. };
  42. static const struct kfd_device_info carrizo_device_info = {
  43. .asic_family = CHIP_CARRIZO,
  44. .max_pasid_bits = 16,
  45. /* max num of queues for CZ.TODO should be a dynamic value */
  46. .max_no_of_hqd = 24,
  47. .ih_ring_entry_size = 4 * sizeof(uint32_t),
  48. .event_interrupt_class = &event_interrupt_class_cik,
  49. .num_of_watch_points = 4,
  50. .mqd_size_aligned = MQD_SIZE_ALIGNED,
  51. .supports_cwsr = true,
  52. };
  53. struct kfd_deviceid {
  54. unsigned short did;
  55. const struct kfd_device_info *device_info;
  56. };
  57. /* Please keep this sorted by increasing device id. */
  58. static const struct kfd_deviceid supported_devices[] = {
  59. { 0x1304, &kaveri_device_info }, /* Kaveri */
  60. { 0x1305, &kaveri_device_info }, /* Kaveri */
  61. { 0x1306, &kaveri_device_info }, /* Kaveri */
  62. { 0x1307, &kaveri_device_info }, /* Kaveri */
  63. { 0x1309, &kaveri_device_info }, /* Kaveri */
  64. { 0x130A, &kaveri_device_info }, /* Kaveri */
  65. { 0x130B, &kaveri_device_info }, /* Kaveri */
  66. { 0x130C, &kaveri_device_info }, /* Kaveri */
  67. { 0x130D, &kaveri_device_info }, /* Kaveri */
  68. { 0x130E, &kaveri_device_info }, /* Kaveri */
  69. { 0x130F, &kaveri_device_info }, /* Kaveri */
  70. { 0x1310, &kaveri_device_info }, /* Kaveri */
  71. { 0x1311, &kaveri_device_info }, /* Kaveri */
  72. { 0x1312, &kaveri_device_info }, /* Kaveri */
  73. { 0x1313, &kaveri_device_info }, /* Kaveri */
  74. { 0x1315, &kaveri_device_info }, /* Kaveri */
  75. { 0x1316, &kaveri_device_info }, /* Kaveri */
  76. { 0x1317, &kaveri_device_info }, /* Kaveri */
  77. { 0x1318, &kaveri_device_info }, /* Kaveri */
  78. { 0x131B, &kaveri_device_info }, /* Kaveri */
  79. { 0x131C, &kaveri_device_info }, /* Kaveri */
  80. { 0x131D, &kaveri_device_info }, /* Kaveri */
  81. { 0x9870, &carrizo_device_info }, /* Carrizo */
  82. { 0x9874, &carrizo_device_info }, /* Carrizo */
  83. { 0x9875, &carrizo_device_info }, /* Carrizo */
  84. { 0x9876, &carrizo_device_info }, /* Carrizo */
  85. { 0x9877, &carrizo_device_info } /* Carrizo */
  86. };
  87. static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
  88. unsigned int chunk_size);
  89. static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
  90. static int kfd_resume(struct kfd_dev *kfd);
  91. static const struct kfd_device_info *lookup_device_info(unsigned short did)
  92. {
  93. size_t i;
  94. for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
  95. if (supported_devices[i].did == did) {
  96. WARN_ON(!supported_devices[i].device_info);
  97. return supported_devices[i].device_info;
  98. }
  99. }
  100. dev_warn(kfd_device, "DID %04x is missing in supported_devices\n",
  101. did);
  102. return NULL;
  103. }
  104. struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
  105. struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
  106. {
  107. struct kfd_dev *kfd;
  108. const struct kfd_device_info *device_info =
  109. lookup_device_info(pdev->device);
  110. if (!device_info) {
  111. dev_err(kfd_device, "kgd2kfd_probe failed\n");
  112. return NULL;
  113. }
  114. kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
  115. if (!kfd)
  116. return NULL;
  117. kfd->kgd = kgd;
  118. kfd->device_info = device_info;
  119. kfd->pdev = pdev;
  120. kfd->init_complete = false;
  121. kfd->kfd2kgd = f2g;
  122. mutex_init(&kfd->doorbell_mutex);
  123. memset(&kfd->doorbell_available_index, 0,
  124. sizeof(kfd->doorbell_available_index));
  125. return kfd;
  126. }
  127. static bool device_iommu_pasid_init(struct kfd_dev *kfd)
  128. {
  129. const u32 required_iommu_flags = AMD_IOMMU_DEVICE_FLAG_ATS_SUP |
  130. AMD_IOMMU_DEVICE_FLAG_PRI_SUP |
  131. AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
  132. struct amd_iommu_device_info iommu_info;
  133. unsigned int pasid_limit;
  134. int err;
  135. err = amd_iommu_device_info(kfd->pdev, &iommu_info);
  136. if (err < 0) {
  137. dev_err(kfd_device,
  138. "error getting iommu info. is the iommu enabled?\n");
  139. return false;
  140. }
  141. if ((iommu_info.flags & required_iommu_flags) != required_iommu_flags) {
  142. dev_err(kfd_device, "error required iommu flags ats %i, pri %i, pasid %i\n",
  143. (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP) != 0,
  144. (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) != 0,
  145. (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP)
  146. != 0);
  147. return false;
  148. }
  149. pasid_limit = min_t(unsigned int,
  150. (unsigned int)(1 << kfd->device_info->max_pasid_bits),
  151. iommu_info.max_pasids);
  152. if (!kfd_set_pasid_limit(pasid_limit)) {
  153. dev_err(kfd_device, "error setting pasid limit\n");
  154. return false;
  155. }
  156. return true;
  157. }
  158. static void iommu_pasid_shutdown_callback(struct pci_dev *pdev, int pasid)
  159. {
  160. struct kfd_dev *dev = kfd_device_by_pci_dev(pdev);
  161. if (dev)
  162. kfd_process_iommu_unbind_callback(dev, pasid);
  163. }
  164. /*
  165. * This function called by IOMMU driver on PPR failure
  166. */
  167. static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid,
  168. unsigned long address, u16 flags)
  169. {
  170. struct kfd_dev *dev;
  171. dev_warn(kfd_device,
  172. "Invalid PPR device %x:%x.%x pasid %d address 0x%lX flags 0x%X",
  173. PCI_BUS_NUM(pdev->devfn),
  174. PCI_SLOT(pdev->devfn),
  175. PCI_FUNC(pdev->devfn),
  176. pasid,
  177. address,
  178. flags);
  179. dev = kfd_device_by_pci_dev(pdev);
  180. if (!WARN_ON(!dev))
  181. kfd_signal_iommu_event(dev, pasid, address,
  182. flags & PPR_FAULT_WRITE, flags & PPR_FAULT_EXEC);
  183. return AMD_IOMMU_INV_PRI_RSP_INVALID;
  184. }
  185. static void kfd_cwsr_init(struct kfd_dev *kfd)
  186. {
  187. if (cwsr_enable && kfd->device_info->supports_cwsr) {
  188. BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
  189. kfd->cwsr_isa = cwsr_trap_gfx8_hex;
  190. kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
  191. kfd->cwsr_enabled = true;
  192. }
  193. }
  194. bool kgd2kfd_device_init(struct kfd_dev *kfd,
  195. const struct kgd2kfd_shared_resources *gpu_resources)
  196. {
  197. unsigned int size;
  198. kfd->shared_resources = *gpu_resources;
  199. kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
  200. kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
  201. kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
  202. - kfd->vm_info.first_vmid_kfd + 1;
  203. /* Verify module parameters regarding mapped process number*/
  204. if ((hws_max_conc_proc < 0)
  205. || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
  206. dev_err(kfd_device,
  207. "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
  208. hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
  209. kfd->vm_info.vmid_num_kfd);
  210. kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
  211. } else
  212. kfd->max_proc_per_quantum = hws_max_conc_proc;
  213. /* calculate max size of mqds needed for queues */
  214. size = max_num_of_queues_per_device *
  215. kfd->device_info->mqd_size_aligned;
  216. /*
  217. * calculate max size of runlist packet.
  218. * There can be only 2 packets at once
  219. */
  220. size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
  221. max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
  222. + sizeof(struct pm4_mes_runlist)) * 2;
  223. /* Add size of HIQ & DIQ */
  224. size += KFD_KERNEL_QUEUE_SIZE * 2;
  225. /* add another 512KB for all other allocations on gart (HPD, fences) */
  226. size += 512 * 1024;
  227. if (kfd->kfd2kgd->init_gtt_mem_allocation(
  228. kfd->kgd, size, &kfd->gtt_mem,
  229. &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){
  230. dev_err(kfd_device, "Could not allocate %d bytes\n", size);
  231. goto out;
  232. }
  233. dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
  234. /* Initialize GTT sa with 512 byte chunk size */
  235. if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
  236. dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
  237. goto kfd_gtt_sa_init_error;
  238. }
  239. if (kfd_doorbell_init(kfd)) {
  240. dev_err(kfd_device,
  241. "Error initializing doorbell aperture\n");
  242. goto kfd_doorbell_error;
  243. }
  244. if (kfd_topology_add_device(kfd)) {
  245. dev_err(kfd_device, "Error adding device to topology\n");
  246. goto kfd_topology_add_device_error;
  247. }
  248. if (kfd_interrupt_init(kfd)) {
  249. dev_err(kfd_device, "Error initializing interrupts\n");
  250. goto kfd_interrupt_error;
  251. }
  252. kfd->dqm = device_queue_manager_init(kfd);
  253. if (!kfd->dqm) {
  254. dev_err(kfd_device, "Error initializing queue manager\n");
  255. goto device_queue_manager_error;
  256. }
  257. if (!device_iommu_pasid_init(kfd)) {
  258. dev_err(kfd_device,
  259. "Error initializing iommuv2 for device %x:%x\n",
  260. kfd->pdev->vendor, kfd->pdev->device);
  261. goto device_iommu_pasid_error;
  262. }
  263. kfd_cwsr_init(kfd);
  264. if (kfd_resume(kfd))
  265. goto kfd_resume_error;
  266. kfd->dbgmgr = NULL;
  267. kfd->init_complete = true;
  268. dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
  269. kfd->pdev->device);
  270. pr_debug("Starting kfd with the following scheduling policy %d\n",
  271. sched_policy);
  272. goto out;
  273. kfd_resume_error:
  274. device_iommu_pasid_error:
  275. device_queue_manager_uninit(kfd->dqm);
  276. device_queue_manager_error:
  277. kfd_interrupt_exit(kfd);
  278. kfd_interrupt_error:
  279. kfd_topology_remove_device(kfd);
  280. kfd_topology_add_device_error:
  281. kfd_doorbell_fini(kfd);
  282. kfd_doorbell_error:
  283. kfd_gtt_sa_fini(kfd);
  284. kfd_gtt_sa_init_error:
  285. kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem);
  286. dev_err(kfd_device,
  287. "device %x:%x NOT added due to errors\n",
  288. kfd->pdev->vendor, kfd->pdev->device);
  289. out:
  290. return kfd->init_complete;
  291. }
  292. void kgd2kfd_device_exit(struct kfd_dev *kfd)
  293. {
  294. if (kfd->init_complete) {
  295. kgd2kfd_suspend(kfd);
  296. device_queue_manager_uninit(kfd->dqm);
  297. kfd_interrupt_exit(kfd);
  298. kfd_topology_remove_device(kfd);
  299. kfd_doorbell_fini(kfd);
  300. kfd_gtt_sa_fini(kfd);
  301. kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem);
  302. }
  303. kfree(kfd);
  304. }
  305. void kgd2kfd_suspend(struct kfd_dev *kfd)
  306. {
  307. if (!kfd->init_complete)
  308. return;
  309. kfd->dqm->ops.stop(kfd->dqm);
  310. kfd_unbind_processes_from_device(kfd);
  311. amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
  312. amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
  313. amd_iommu_free_device(kfd->pdev);
  314. }
  315. int kgd2kfd_resume(struct kfd_dev *kfd)
  316. {
  317. if (!kfd->init_complete)
  318. return 0;
  319. return kfd_resume(kfd);
  320. }
  321. static int kfd_resume(struct kfd_dev *kfd)
  322. {
  323. int err = 0;
  324. unsigned int pasid_limit = kfd_get_pasid_limit();
  325. err = amd_iommu_init_device(kfd->pdev, pasid_limit);
  326. if (err)
  327. return -ENXIO;
  328. amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
  329. iommu_pasid_shutdown_callback);
  330. amd_iommu_set_invalid_ppr_cb(kfd->pdev,
  331. iommu_invalid_ppr_cb);
  332. err = kfd_bind_processes_to_device(kfd);
  333. if (err)
  334. goto processes_bind_error;
  335. err = kfd->dqm->ops.start(kfd->dqm);
  336. if (err) {
  337. dev_err(kfd_device,
  338. "Error starting queue manager for device %x:%x\n",
  339. kfd->pdev->vendor, kfd->pdev->device);
  340. goto dqm_start_error;
  341. }
  342. return err;
  343. dqm_start_error:
  344. processes_bind_error:
  345. amd_iommu_free_device(kfd->pdev);
  346. return err;
  347. }
  348. /* This is called directly from KGD at ISR. */
  349. void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
  350. {
  351. if (!kfd->init_complete)
  352. return;
  353. spin_lock(&kfd->interrupt_lock);
  354. if (kfd->interrupts_active
  355. && interrupt_is_wanted(kfd, ih_ring_entry)
  356. && enqueue_ih_ring_entry(kfd, ih_ring_entry))
  357. queue_work(kfd->ih_wq, &kfd->interrupt_work);
  358. spin_unlock(&kfd->interrupt_lock);
  359. }
  360. static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
  361. unsigned int chunk_size)
  362. {
  363. unsigned int num_of_longs;
  364. if (WARN_ON(buf_size < chunk_size))
  365. return -EINVAL;
  366. if (WARN_ON(buf_size == 0))
  367. return -EINVAL;
  368. if (WARN_ON(chunk_size == 0))
  369. return -EINVAL;
  370. kfd->gtt_sa_chunk_size = chunk_size;
  371. kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
  372. num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
  373. BITS_PER_LONG;
  374. kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
  375. if (!kfd->gtt_sa_bitmap)
  376. return -ENOMEM;
  377. pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
  378. kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
  379. mutex_init(&kfd->gtt_sa_lock);
  380. return 0;
  381. }
  382. static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
  383. {
  384. mutex_destroy(&kfd->gtt_sa_lock);
  385. kfree(kfd->gtt_sa_bitmap);
  386. }
  387. static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
  388. unsigned int bit_num,
  389. unsigned int chunk_size)
  390. {
  391. return start_addr + bit_num * chunk_size;
  392. }
  393. static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
  394. unsigned int bit_num,
  395. unsigned int chunk_size)
  396. {
  397. return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
  398. }
  399. int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
  400. struct kfd_mem_obj **mem_obj)
  401. {
  402. unsigned int found, start_search, cur_size;
  403. if (size == 0)
  404. return -EINVAL;
  405. if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
  406. return -ENOMEM;
  407. *mem_obj = kmalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
  408. if ((*mem_obj) == NULL)
  409. return -ENOMEM;
  410. pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
  411. start_search = 0;
  412. mutex_lock(&kfd->gtt_sa_lock);
  413. kfd_gtt_restart_search:
  414. /* Find the first chunk that is free */
  415. found = find_next_zero_bit(kfd->gtt_sa_bitmap,
  416. kfd->gtt_sa_num_of_chunks,
  417. start_search);
  418. pr_debug("Found = %d\n", found);
  419. /* If there wasn't any free chunk, bail out */
  420. if (found == kfd->gtt_sa_num_of_chunks)
  421. goto kfd_gtt_no_free_chunk;
  422. /* Update fields of mem_obj */
  423. (*mem_obj)->range_start = found;
  424. (*mem_obj)->range_end = found;
  425. (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
  426. kfd->gtt_start_gpu_addr,
  427. found,
  428. kfd->gtt_sa_chunk_size);
  429. (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
  430. kfd->gtt_start_cpu_ptr,
  431. found,
  432. kfd->gtt_sa_chunk_size);
  433. pr_debug("gpu_addr = %p, cpu_addr = %p\n",
  434. (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
  435. /* If we need only one chunk, mark it as allocated and get out */
  436. if (size <= kfd->gtt_sa_chunk_size) {
  437. pr_debug("Single bit\n");
  438. set_bit(found, kfd->gtt_sa_bitmap);
  439. goto kfd_gtt_out;
  440. }
  441. /* Otherwise, try to see if we have enough contiguous chunks */
  442. cur_size = size - kfd->gtt_sa_chunk_size;
  443. do {
  444. (*mem_obj)->range_end =
  445. find_next_zero_bit(kfd->gtt_sa_bitmap,
  446. kfd->gtt_sa_num_of_chunks, ++found);
  447. /*
  448. * If next free chunk is not contiguous than we need to
  449. * restart our search from the last free chunk we found (which
  450. * wasn't contiguous to the previous ones
  451. */
  452. if ((*mem_obj)->range_end != found) {
  453. start_search = found;
  454. goto kfd_gtt_restart_search;
  455. }
  456. /*
  457. * If we reached end of buffer, bail out with error
  458. */
  459. if (found == kfd->gtt_sa_num_of_chunks)
  460. goto kfd_gtt_no_free_chunk;
  461. /* Check if we don't need another chunk */
  462. if (cur_size <= kfd->gtt_sa_chunk_size)
  463. cur_size = 0;
  464. else
  465. cur_size -= kfd->gtt_sa_chunk_size;
  466. } while (cur_size > 0);
  467. pr_debug("range_start = %d, range_end = %d\n",
  468. (*mem_obj)->range_start, (*mem_obj)->range_end);
  469. /* Mark the chunks as allocated */
  470. for (found = (*mem_obj)->range_start;
  471. found <= (*mem_obj)->range_end;
  472. found++)
  473. set_bit(found, kfd->gtt_sa_bitmap);
  474. kfd_gtt_out:
  475. mutex_unlock(&kfd->gtt_sa_lock);
  476. return 0;
  477. kfd_gtt_no_free_chunk:
  478. pr_debug("Allocation failed with mem_obj = %p\n", mem_obj);
  479. mutex_unlock(&kfd->gtt_sa_lock);
  480. kfree(mem_obj);
  481. return -ENOMEM;
  482. }
  483. int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
  484. {
  485. unsigned int bit;
  486. /* Act like kfree when trying to free a NULL object */
  487. if (!mem_obj)
  488. return 0;
  489. pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
  490. mem_obj, mem_obj->range_start, mem_obj->range_end);
  491. mutex_lock(&kfd->gtt_sa_lock);
  492. /* Mark the chunks as free */
  493. for (bit = mem_obj->range_start;
  494. bit <= mem_obj->range_end;
  495. bit++)
  496. clear_bit(bit, kfd->gtt_sa_bitmap);
  497. mutex_unlock(&kfd->gtt_sa_lock);
  498. kfree(mem_obj);
  499. return 0;
  500. }