sdi.c 9.1 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/sdi.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define DSS_SUBSYS_NAME "SDI"
  20. #include <linux/kernel.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/export.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/string.h>
  27. #include <linux/of.h>
  28. #include <video/omapdss.h>
  29. #include "dss.h"
  30. static struct {
  31. struct platform_device *pdev;
  32. bool update_enabled;
  33. struct regulator *vdds_sdi_reg;
  34. struct dss_lcd_mgr_config mgr_config;
  35. struct omap_video_timings timings;
  36. int datapairs;
  37. struct omap_dss_device output;
  38. bool port_initialized;
  39. } sdi;
  40. struct sdi_clk_calc_ctx {
  41. unsigned long pck_min, pck_max;
  42. unsigned long fck;
  43. struct dispc_clock_info dispc_cinfo;
  44. };
  45. static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
  46. unsigned long pck, void *data)
  47. {
  48. struct sdi_clk_calc_ctx *ctx = data;
  49. ctx->dispc_cinfo.lck_div = lckd;
  50. ctx->dispc_cinfo.pck_div = pckd;
  51. ctx->dispc_cinfo.lck = lck;
  52. ctx->dispc_cinfo.pck = pck;
  53. return true;
  54. }
  55. static bool dpi_calc_dss_cb(unsigned long fck, void *data)
  56. {
  57. struct sdi_clk_calc_ctx *ctx = data;
  58. ctx->fck = fck;
  59. return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
  60. dpi_calc_dispc_cb, ctx);
  61. }
  62. static int sdi_calc_clock_div(unsigned long pclk,
  63. unsigned long *fck,
  64. struct dispc_clock_info *dispc_cinfo)
  65. {
  66. int i;
  67. struct sdi_clk_calc_ctx ctx;
  68. /*
  69. * DSS fclk gives us very few possibilities, so finding a good pixel
  70. * clock may not be possible. We try multiple times to find the clock,
  71. * each time widening the pixel clock range we look for, up to
  72. * +/- 1MHz.
  73. */
  74. for (i = 0; i < 10; ++i) {
  75. bool ok;
  76. memset(&ctx, 0, sizeof(ctx));
  77. if (pclk > 1000 * i * i * i)
  78. ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
  79. else
  80. ctx.pck_min = 0;
  81. ctx.pck_max = pclk + 1000 * i * i * i;
  82. ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
  83. if (ok) {
  84. *fck = ctx.fck;
  85. *dispc_cinfo = ctx.dispc_cinfo;
  86. return 0;
  87. }
  88. }
  89. return -EINVAL;
  90. }
  91. static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
  92. {
  93. struct omap_overlay_manager *mgr = sdi.output.manager;
  94. sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
  95. sdi.mgr_config.stallmode = false;
  96. sdi.mgr_config.fifohandcheck = false;
  97. sdi.mgr_config.video_port_width = 24;
  98. sdi.mgr_config.lcden_sig_polarity = 1;
  99. dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
  100. }
  101. static int sdi_display_enable(struct omap_dss_device *dssdev)
  102. {
  103. struct omap_dss_device *out = &sdi.output;
  104. struct omap_video_timings *t = &sdi.timings;
  105. unsigned long fck;
  106. struct dispc_clock_info dispc_cinfo;
  107. unsigned long pck;
  108. int r;
  109. if (out == NULL || out->manager == NULL) {
  110. DSSERR("failed to enable display: no output/manager\n");
  111. return -ENODEV;
  112. }
  113. r = regulator_enable(sdi.vdds_sdi_reg);
  114. if (r)
  115. goto err_reg_enable;
  116. r = dispc_runtime_get();
  117. if (r)
  118. goto err_get_dispc;
  119. /* 15.5.9.1.2 */
  120. t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
  121. t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
  122. r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo);
  123. if (r)
  124. goto err_calc_clock_div;
  125. sdi.mgr_config.clock_info = dispc_cinfo;
  126. pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
  127. if (pck != t->pixelclock) {
  128. DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
  129. t->pixelclock, pck);
  130. t->pixelclock = pck;
  131. }
  132. dss_mgr_set_timings(out->manager, t);
  133. r = dss_set_fck_rate(fck);
  134. if (r)
  135. goto err_set_dss_clock_div;
  136. sdi_config_lcd_manager(dssdev);
  137. /*
  138. * LCLK and PCLK divisors are located in shadow registers, and we
  139. * normally write them to DISPC registers when enabling the output.
  140. * However, SDI uses pck-free as source clock for its PLL, and pck-free
  141. * is affected by the divisors. And as we need the PLL before enabling
  142. * the output, we need to write the divisors early.
  143. *
  144. * It seems just writing to the DISPC register is enough, and we don't
  145. * need to care about the shadow register mechanism for pck-free. The
  146. * exact reason for this is unknown.
  147. */
  148. dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
  149. dss_sdi_init(sdi.datapairs);
  150. r = dss_sdi_enable();
  151. if (r)
  152. goto err_sdi_enable;
  153. mdelay(2);
  154. r = dss_mgr_enable(out->manager);
  155. if (r)
  156. goto err_mgr_enable;
  157. return 0;
  158. err_mgr_enable:
  159. dss_sdi_disable();
  160. err_sdi_enable:
  161. err_set_dss_clock_div:
  162. err_calc_clock_div:
  163. dispc_runtime_put();
  164. err_get_dispc:
  165. regulator_disable(sdi.vdds_sdi_reg);
  166. err_reg_enable:
  167. return r;
  168. }
  169. static void sdi_display_disable(struct omap_dss_device *dssdev)
  170. {
  171. struct omap_overlay_manager *mgr = sdi.output.manager;
  172. dss_mgr_disable(mgr);
  173. dss_sdi_disable();
  174. dispc_runtime_put();
  175. regulator_disable(sdi.vdds_sdi_reg);
  176. }
  177. static void sdi_set_timings(struct omap_dss_device *dssdev,
  178. struct omap_video_timings *timings)
  179. {
  180. sdi.timings = *timings;
  181. }
  182. static void sdi_get_timings(struct omap_dss_device *dssdev,
  183. struct omap_video_timings *timings)
  184. {
  185. *timings = sdi.timings;
  186. }
  187. static int sdi_check_timings(struct omap_dss_device *dssdev,
  188. struct omap_video_timings *timings)
  189. {
  190. struct omap_overlay_manager *mgr = sdi.output.manager;
  191. if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
  192. return -EINVAL;
  193. if (timings->pixelclock == 0)
  194. return -EINVAL;
  195. return 0;
  196. }
  197. static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
  198. {
  199. sdi.datapairs = datapairs;
  200. }
  201. static int sdi_init_regulator(void)
  202. {
  203. struct regulator *vdds_sdi;
  204. if (sdi.vdds_sdi_reg)
  205. return 0;
  206. vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
  207. if (IS_ERR(vdds_sdi)) {
  208. if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
  209. DSSERR("can't get VDDS_SDI regulator\n");
  210. return PTR_ERR(vdds_sdi);
  211. }
  212. sdi.vdds_sdi_reg = vdds_sdi;
  213. return 0;
  214. }
  215. static int sdi_connect(struct omap_dss_device *dssdev,
  216. struct omap_dss_device *dst)
  217. {
  218. struct omap_overlay_manager *mgr;
  219. int r;
  220. r = sdi_init_regulator();
  221. if (r)
  222. return r;
  223. mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
  224. if (!mgr)
  225. return -ENODEV;
  226. r = dss_mgr_connect(mgr, dssdev);
  227. if (r)
  228. return r;
  229. r = omapdss_output_set_device(dssdev, dst);
  230. if (r) {
  231. DSSERR("failed to connect output to new device: %s\n",
  232. dst->name);
  233. dss_mgr_disconnect(mgr, dssdev);
  234. return r;
  235. }
  236. return 0;
  237. }
  238. static void sdi_disconnect(struct omap_dss_device *dssdev,
  239. struct omap_dss_device *dst)
  240. {
  241. WARN_ON(dst != dssdev->dst);
  242. if (dst != dssdev->dst)
  243. return;
  244. omapdss_output_unset_device(dssdev);
  245. if (dssdev->manager)
  246. dss_mgr_disconnect(dssdev->manager, dssdev);
  247. }
  248. static const struct omapdss_sdi_ops sdi_ops = {
  249. .connect = sdi_connect,
  250. .disconnect = sdi_disconnect,
  251. .enable = sdi_display_enable,
  252. .disable = sdi_display_disable,
  253. .check_timings = sdi_check_timings,
  254. .set_timings = sdi_set_timings,
  255. .get_timings = sdi_get_timings,
  256. .set_datapairs = sdi_set_datapairs,
  257. };
  258. static void sdi_init_output(struct platform_device *pdev)
  259. {
  260. struct omap_dss_device *out = &sdi.output;
  261. out->dev = &pdev->dev;
  262. out->id = OMAP_DSS_OUTPUT_SDI;
  263. out->output_type = OMAP_DISPLAY_TYPE_SDI;
  264. out->name = "sdi.0";
  265. out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
  266. /* We have SDI only on OMAP3, where it's on port 1 */
  267. out->port_num = 1;
  268. out->ops.sdi = &sdi_ops;
  269. out->owner = THIS_MODULE;
  270. omapdss_register_output(out);
  271. }
  272. static void __exit sdi_uninit_output(struct platform_device *pdev)
  273. {
  274. struct omap_dss_device *out = &sdi.output;
  275. omapdss_unregister_output(out);
  276. }
  277. static int omap_sdi_probe(struct platform_device *pdev)
  278. {
  279. sdi.pdev = pdev;
  280. sdi_init_output(pdev);
  281. return 0;
  282. }
  283. static int __exit omap_sdi_remove(struct platform_device *pdev)
  284. {
  285. sdi_uninit_output(pdev);
  286. return 0;
  287. }
  288. static struct platform_driver omap_sdi_driver = {
  289. .probe = omap_sdi_probe,
  290. .remove = __exit_p(omap_sdi_remove),
  291. .driver = {
  292. .name = "omapdss_sdi",
  293. .suppress_bind_attrs = true,
  294. },
  295. };
  296. int __init sdi_init_platform_driver(void)
  297. {
  298. return platform_driver_register(&omap_sdi_driver);
  299. }
  300. void __exit sdi_uninit_platform_driver(void)
  301. {
  302. platform_driver_unregister(&omap_sdi_driver);
  303. }
  304. int __init sdi_init_port(struct platform_device *pdev, struct device_node *port)
  305. {
  306. struct device_node *ep;
  307. u32 datapairs;
  308. int r;
  309. ep = omapdss_of_get_next_endpoint(port, NULL);
  310. if (!ep)
  311. return 0;
  312. r = of_property_read_u32(ep, "datapairs", &datapairs);
  313. if (r) {
  314. DSSERR("failed to parse datapairs\n");
  315. goto err_datapairs;
  316. }
  317. sdi.datapairs = datapairs;
  318. of_node_put(ep);
  319. sdi.pdev = pdev;
  320. sdi_init_output(pdev);
  321. sdi.port_initialized = true;
  322. return 0;
  323. err_datapairs:
  324. of_node_put(ep);
  325. return r;
  326. }
  327. void __exit sdi_uninit_port(struct device_node *port)
  328. {
  329. if (!sdi.port_initialized)
  330. return;
  331. sdi_uninit_output(sdi.pdev);
  332. }