s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #define pr_fmt(fmt) "s3c2410_udc: " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/delay.h>
  18. #include <linux/ioport.h>
  19. #include <linux/sched.h>
  20. #include <linux/slab.h>
  21. #include <linux/errno.h>
  22. #include <linux/init.h>
  23. #include <linux/timer.h>
  24. #include <linux/list.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/gpio.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/io.h>
  31. #include <linux/debugfs.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/usb.h>
  34. #include <linux/usb/gadget.h>
  35. #include <asm/byteorder.h>
  36. #include <asm/irq.h>
  37. #include <asm/unaligned.h>
  38. #include <mach/irqs.h>
  39. #include <mach/hardware.h>
  40. #include <plat/regs-udc.h>
  41. #include <linux/platform_data/usb-s3c2410_udc.h>
  42. #include "s3c2410_udc.h"
  43. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  44. #define DRIVER_VERSION "29 Apr 2007"
  45. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  46. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  47. static const char gadget_name[] = "s3c2410_udc";
  48. static const char driver_desc[] = DRIVER_DESC;
  49. static struct s3c2410_udc *the_controller;
  50. static struct clk *udc_clock;
  51. static struct clk *usb_bus_clock;
  52. static void __iomem *base_addr;
  53. static u64 rsrc_start;
  54. static u64 rsrc_len;
  55. static struct dentry *s3c2410_udc_debugfs_root;
  56. static inline u32 udc_read(u32 reg)
  57. {
  58. return readb(base_addr + reg);
  59. }
  60. static inline void udc_write(u32 value, u32 reg)
  61. {
  62. writeb(value, base_addr + reg);
  63. }
  64. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  65. {
  66. writeb(value, base + reg);
  67. }
  68. static struct s3c2410_udc_mach_info *udc_info;
  69. /*************************** DEBUG FUNCTION ***************************/
  70. #define DEBUG_NORMAL 1
  71. #define DEBUG_VERBOSE 2
  72. #ifdef CONFIG_USB_S3C2410_DEBUG
  73. #define USB_S3C2410_DEBUG_LEVEL 0
  74. static uint32_t s3c2410_ticks = 0;
  75. static int dprintk(int level, const char *fmt, ...)
  76. {
  77. static char printk_buf[1024];
  78. static long prevticks;
  79. static int invocation;
  80. va_list args;
  81. int len;
  82. if (level > USB_S3C2410_DEBUG_LEVEL)
  83. return 0;
  84. if (s3c2410_ticks != prevticks) {
  85. prevticks = s3c2410_ticks;
  86. invocation = 0;
  87. }
  88. len = scnprintf(printk_buf,
  89. sizeof(printk_buf), "%1lu.%02d USB: ",
  90. prevticks, invocation++);
  91. va_start(args, fmt);
  92. len = vscnprintf(printk_buf+len,
  93. sizeof(printk_buf)-len, fmt, args);
  94. va_end(args);
  95. pr_debug("%s", printk_buf);
  96. return len;
  97. }
  98. #else
  99. static int dprintk(int level, const char *fmt, ...)
  100. {
  101. return 0;
  102. }
  103. #endif
  104. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  105. {
  106. u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
  107. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  108. u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
  109. u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
  110. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  111. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  112. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  113. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  114. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  115. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  116. udc_write(0, S3C2410_UDC_INDEX_REG);
  117. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  118. udc_write(1, S3C2410_UDC_INDEX_REG);
  119. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  120. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  121. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  122. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  123. udc_write(2, S3C2410_UDC_INDEX_REG);
  124. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  125. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  126. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  127. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  128. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  129. "PWR_REG : 0x%04X\n"
  130. "EP_INT_REG : 0x%04X\n"
  131. "USB_INT_REG : 0x%04X\n"
  132. "EP_INT_EN_REG : 0x%04X\n"
  133. "USB_INT_EN_REG : 0x%04X\n"
  134. "EP0_CSR : 0x%04X\n"
  135. "EP1_I_CSR1 : 0x%04X\n"
  136. "EP1_I_CSR2 : 0x%04X\n"
  137. "EP1_O_CSR1 : 0x%04X\n"
  138. "EP1_O_CSR2 : 0x%04X\n"
  139. "EP2_I_CSR1 : 0x%04X\n"
  140. "EP2_I_CSR2 : 0x%04X\n"
  141. "EP2_O_CSR1 : 0x%04X\n"
  142. "EP2_O_CSR2 : 0x%04X\n",
  143. addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
  144. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  145. ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
  146. ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
  147. );
  148. return 0;
  149. }
  150. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  151. struct file *file)
  152. {
  153. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  154. }
  155. static const struct file_operations s3c2410_udc_debugfs_fops = {
  156. .open = s3c2410_udc_debugfs_fops_open,
  157. .read = seq_read,
  158. .llseek = seq_lseek,
  159. .release = single_release,
  160. .owner = THIS_MODULE,
  161. };
  162. /* io macros */
  163. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  164. {
  165. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  166. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  167. S3C2410_UDC_EP0_CSR_REG);
  168. }
  169. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  170. {
  171. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  172. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  173. }
  174. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  175. {
  176. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  177. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  178. }
  179. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  180. {
  181. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  182. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  183. }
  184. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  185. {
  186. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  187. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  188. }
  189. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  190. {
  191. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  192. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  193. }
  194. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  195. {
  196. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  197. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  198. | S3C2410_UDC_EP0_CSR_DE),
  199. S3C2410_UDC_EP0_CSR_REG);
  200. }
  201. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  202. {
  203. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  204. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  205. | S3C2410_UDC_EP0_CSR_SSE),
  206. S3C2410_UDC_EP0_CSR_REG);
  207. }
  208. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  209. {
  210. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  211. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  212. | S3C2410_UDC_EP0_CSR_DE),
  213. S3C2410_UDC_EP0_CSR_REG);
  214. }
  215. /*------------------------- I/O ----------------------------------*/
  216. /*
  217. * s3c2410_udc_done
  218. */
  219. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  220. struct s3c2410_request *req, int status)
  221. {
  222. unsigned halted = ep->halted;
  223. list_del_init(&req->queue);
  224. if (likely(req->req.status == -EINPROGRESS))
  225. req->req.status = status;
  226. else
  227. status = req->req.status;
  228. ep->halted = 1;
  229. usb_gadget_giveback_request(&ep->ep, &req->req);
  230. ep->halted = halted;
  231. }
  232. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  233. struct s3c2410_ep *ep, int status)
  234. {
  235. /* Sanity check */
  236. if (&ep->queue == NULL)
  237. return;
  238. while (!list_empty(&ep->queue)) {
  239. struct s3c2410_request *req;
  240. req = list_entry(ep->queue.next, struct s3c2410_request,
  241. queue);
  242. s3c2410_udc_done(ep, req, status);
  243. }
  244. }
  245. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  246. {
  247. unsigned i;
  248. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  249. * fifos, and pending transactions mustn't be continued in any case.
  250. */
  251. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  252. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  253. }
  254. static inline int s3c2410_udc_fifo_count_out(void)
  255. {
  256. int tmp;
  257. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  258. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  259. return tmp;
  260. }
  261. /*
  262. * s3c2410_udc_write_packet
  263. */
  264. static inline int s3c2410_udc_write_packet(int fifo,
  265. struct s3c2410_request *req,
  266. unsigned max)
  267. {
  268. unsigned len = min(req->req.length - req->req.actual, max);
  269. u8 *buf = req->req.buf + req->req.actual;
  270. prefetch(buf);
  271. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  272. req->req.actual, req->req.length, len, req->req.actual + len);
  273. req->req.actual += len;
  274. udelay(5);
  275. writesb(base_addr + fifo, buf, len);
  276. return len;
  277. }
  278. /*
  279. * s3c2410_udc_write_fifo
  280. *
  281. * return: 0 = still running, 1 = completed, negative = errno
  282. */
  283. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  284. struct s3c2410_request *req)
  285. {
  286. unsigned count;
  287. int is_last;
  288. u32 idx;
  289. int fifo_reg;
  290. u32 ep_csr;
  291. idx = ep->bEndpointAddress & 0x7F;
  292. switch (idx) {
  293. default:
  294. idx = 0;
  295. case 0:
  296. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  297. break;
  298. case 1:
  299. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  300. break;
  301. case 2:
  302. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  303. break;
  304. case 3:
  305. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  306. break;
  307. case 4:
  308. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  309. break;
  310. }
  311. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  312. /* last packet is often short (sometimes a zlp) */
  313. if (count != ep->ep.maxpacket)
  314. is_last = 1;
  315. else if (req->req.length != req->req.actual || req->req.zero)
  316. is_last = 0;
  317. else
  318. is_last = 2;
  319. /* Only ep0 debug messages are interesting */
  320. if (idx == 0)
  321. dprintk(DEBUG_NORMAL,
  322. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  323. idx, count, req->req.actual, req->req.length,
  324. is_last, req->req.zero);
  325. if (is_last) {
  326. /* The order is important. It prevents sending 2 packets
  327. * at the same time */
  328. if (idx == 0) {
  329. /* Reset signal => no need to say 'data sent' */
  330. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  331. & S3C2410_UDC_USBINT_RESET))
  332. s3c2410_udc_set_ep0_de_in(base_addr);
  333. ep->dev->ep0state = EP0_IDLE;
  334. } else {
  335. udc_write(idx, S3C2410_UDC_INDEX_REG);
  336. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  337. udc_write(idx, S3C2410_UDC_INDEX_REG);
  338. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  339. S3C2410_UDC_IN_CSR1_REG);
  340. }
  341. s3c2410_udc_done(ep, req, 0);
  342. is_last = 1;
  343. } else {
  344. if (idx == 0) {
  345. /* Reset signal => no need to say 'data sent' */
  346. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  347. & S3C2410_UDC_USBINT_RESET))
  348. s3c2410_udc_set_ep0_ipr(base_addr);
  349. } else {
  350. udc_write(idx, S3C2410_UDC_INDEX_REG);
  351. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  352. udc_write(idx, S3C2410_UDC_INDEX_REG);
  353. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  354. S3C2410_UDC_IN_CSR1_REG);
  355. }
  356. }
  357. return is_last;
  358. }
  359. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  360. struct s3c2410_request *req, unsigned avail)
  361. {
  362. unsigned len;
  363. len = min(req->req.length - req->req.actual, avail);
  364. req->req.actual += len;
  365. readsb(fifo + base_addr, buf, len);
  366. return len;
  367. }
  368. /*
  369. * return: 0 = still running, 1 = queue empty, negative = errno
  370. */
  371. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  372. struct s3c2410_request *req)
  373. {
  374. u8 *buf;
  375. u32 ep_csr;
  376. unsigned bufferspace;
  377. int is_last = 1;
  378. unsigned avail;
  379. int fifo_count = 0;
  380. u32 idx;
  381. int fifo_reg;
  382. idx = ep->bEndpointAddress & 0x7F;
  383. switch (idx) {
  384. default:
  385. idx = 0;
  386. case 0:
  387. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  388. break;
  389. case 1:
  390. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  391. break;
  392. case 2:
  393. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  394. break;
  395. case 3:
  396. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  397. break;
  398. case 4:
  399. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  400. break;
  401. }
  402. if (!req->req.length)
  403. return 1;
  404. buf = req->req.buf + req->req.actual;
  405. bufferspace = req->req.length - req->req.actual;
  406. if (!bufferspace) {
  407. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  408. return -1;
  409. }
  410. udc_write(idx, S3C2410_UDC_INDEX_REG);
  411. fifo_count = s3c2410_udc_fifo_count_out();
  412. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  413. if (fifo_count > ep->ep.maxpacket)
  414. avail = ep->ep.maxpacket;
  415. else
  416. avail = fifo_count;
  417. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  418. /* checking this with ep0 is not accurate as we already
  419. * read a control request
  420. **/
  421. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  422. is_last = 1;
  423. /* overflowed this request? flush extra data */
  424. if (fifo_count != avail)
  425. req->req.status = -EOVERFLOW;
  426. } else {
  427. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  428. }
  429. udc_write(idx, S3C2410_UDC_INDEX_REG);
  430. fifo_count = s3c2410_udc_fifo_count_out();
  431. /* Only ep0 debug messages are interesting */
  432. if (idx == 0)
  433. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  434. __func__, fifo_count, is_last);
  435. if (is_last) {
  436. if (idx == 0) {
  437. s3c2410_udc_set_ep0_de_out(base_addr);
  438. ep->dev->ep0state = EP0_IDLE;
  439. } else {
  440. udc_write(idx, S3C2410_UDC_INDEX_REG);
  441. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  442. udc_write(idx, S3C2410_UDC_INDEX_REG);
  443. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  444. S3C2410_UDC_OUT_CSR1_REG);
  445. }
  446. s3c2410_udc_done(ep, req, 0);
  447. } else {
  448. if (idx == 0) {
  449. s3c2410_udc_clear_ep0_opr(base_addr);
  450. } else {
  451. udc_write(idx, S3C2410_UDC_INDEX_REG);
  452. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  453. udc_write(idx, S3C2410_UDC_INDEX_REG);
  454. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  455. S3C2410_UDC_OUT_CSR1_REG);
  456. }
  457. }
  458. return is_last;
  459. }
  460. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  461. {
  462. unsigned char *outbuf = (unsigned char *)crq;
  463. int bytes_read = 0;
  464. udc_write(0, S3C2410_UDC_INDEX_REG);
  465. bytes_read = s3c2410_udc_fifo_count_out();
  466. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  467. if (bytes_read > sizeof(struct usb_ctrlrequest))
  468. bytes_read = sizeof(struct usb_ctrlrequest);
  469. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  470. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  471. bytes_read, crq->bRequest, crq->bRequestType,
  472. crq->wValue, crq->wIndex, crq->wLength);
  473. return bytes_read;
  474. }
  475. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  476. struct usb_ctrlrequest *crq)
  477. {
  478. u16 status = 0;
  479. u8 ep_num = crq->wIndex & 0x7F;
  480. u8 is_in = crq->wIndex & USB_DIR_IN;
  481. switch (crq->bRequestType & USB_RECIP_MASK) {
  482. case USB_RECIP_INTERFACE:
  483. break;
  484. case USB_RECIP_DEVICE:
  485. status = dev->devstatus;
  486. break;
  487. case USB_RECIP_ENDPOINT:
  488. if (ep_num > 4 || crq->wLength > 2)
  489. return 1;
  490. if (ep_num == 0) {
  491. udc_write(0, S3C2410_UDC_INDEX_REG);
  492. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  493. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  494. } else {
  495. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  496. if (is_in) {
  497. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  498. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  499. } else {
  500. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  501. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  502. }
  503. }
  504. status = status ? 1 : 0;
  505. break;
  506. default:
  507. return 1;
  508. }
  509. /* Seems to be needed to get it working. ouch :( */
  510. udelay(5);
  511. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  512. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  513. s3c2410_udc_set_ep0_de_in(base_addr);
  514. return 0;
  515. }
  516. /*------------------------- usb state machine -------------------------------*/
  517. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  518. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  519. struct s3c2410_ep *ep,
  520. struct usb_ctrlrequest *crq,
  521. u32 ep0csr)
  522. {
  523. int len, ret, tmp;
  524. /* start control request? */
  525. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  526. return;
  527. s3c2410_udc_nuke(dev, ep, -EPROTO);
  528. len = s3c2410_udc_read_fifo_crq(crq);
  529. if (len != sizeof(*crq)) {
  530. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  531. " wanted %d bytes got %d. Stalling out...\n",
  532. sizeof(*crq), len);
  533. s3c2410_udc_set_ep0_ss(base_addr);
  534. return;
  535. }
  536. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  537. crq->bRequest, crq->bRequestType, crq->wLength);
  538. /* cope with automagic for some standard requests. */
  539. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  540. == USB_TYPE_STANDARD;
  541. dev->req_config = 0;
  542. dev->req_pending = 1;
  543. switch (crq->bRequest) {
  544. case USB_REQ_SET_CONFIGURATION:
  545. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
  546. if (crq->bRequestType == USB_RECIP_DEVICE) {
  547. dev->req_config = 1;
  548. s3c2410_udc_set_ep0_de_out(base_addr);
  549. }
  550. break;
  551. case USB_REQ_SET_INTERFACE:
  552. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
  553. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  554. dev->req_config = 1;
  555. s3c2410_udc_set_ep0_de_out(base_addr);
  556. }
  557. break;
  558. case USB_REQ_SET_ADDRESS:
  559. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
  560. if (crq->bRequestType == USB_RECIP_DEVICE) {
  561. tmp = crq->wValue & 0x7F;
  562. dev->address = tmp;
  563. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  564. S3C2410_UDC_FUNC_ADDR_REG);
  565. s3c2410_udc_set_ep0_de_out(base_addr);
  566. return;
  567. }
  568. break;
  569. case USB_REQ_GET_STATUS:
  570. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
  571. s3c2410_udc_clear_ep0_opr(base_addr);
  572. if (dev->req_std) {
  573. if (!s3c2410_udc_get_status(dev, crq))
  574. return;
  575. }
  576. break;
  577. case USB_REQ_CLEAR_FEATURE:
  578. s3c2410_udc_clear_ep0_opr(base_addr);
  579. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  580. break;
  581. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  582. break;
  583. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  584. s3c2410_udc_set_ep0_de_out(base_addr);
  585. return;
  586. case USB_REQ_SET_FEATURE:
  587. s3c2410_udc_clear_ep0_opr(base_addr);
  588. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  589. break;
  590. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  591. break;
  592. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  593. s3c2410_udc_set_ep0_de_out(base_addr);
  594. return;
  595. default:
  596. s3c2410_udc_clear_ep0_opr(base_addr);
  597. break;
  598. }
  599. if (crq->bRequestType & USB_DIR_IN)
  600. dev->ep0state = EP0_IN_DATA_PHASE;
  601. else
  602. dev->ep0state = EP0_OUT_DATA_PHASE;
  603. if (!dev->driver)
  604. return;
  605. /* deliver the request to the gadget driver */
  606. ret = dev->driver->setup(&dev->gadget, crq);
  607. if (ret < 0) {
  608. if (dev->req_config) {
  609. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  610. crq->bRequest, ret);
  611. return;
  612. }
  613. if (ret == -EOPNOTSUPP)
  614. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  615. else
  616. dprintk(DEBUG_NORMAL,
  617. "dev->driver->setup failed. (%d)\n", ret);
  618. udelay(5);
  619. s3c2410_udc_set_ep0_ss(base_addr);
  620. s3c2410_udc_set_ep0_de_out(base_addr);
  621. dev->ep0state = EP0_IDLE;
  622. /* deferred i/o == no response yet */
  623. } else if (dev->req_pending) {
  624. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  625. dev->req_pending = 0;
  626. }
  627. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  628. }
  629. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  630. {
  631. u32 ep0csr;
  632. struct s3c2410_ep *ep = &dev->ep[0];
  633. struct s3c2410_request *req;
  634. struct usb_ctrlrequest crq;
  635. if (list_empty(&ep->queue))
  636. req = NULL;
  637. else
  638. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  639. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  640. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  641. udc_write(0, S3C2410_UDC_INDEX_REG);
  642. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  643. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  644. ep0csr, ep0states[dev->ep0state]);
  645. /* clear stall status */
  646. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  647. s3c2410_udc_nuke(dev, ep, -EPIPE);
  648. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  649. s3c2410_udc_clear_ep0_sst(base_addr);
  650. dev->ep0state = EP0_IDLE;
  651. return;
  652. }
  653. /* clear setup end */
  654. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  655. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  656. s3c2410_udc_nuke(dev, ep, 0);
  657. s3c2410_udc_clear_ep0_se(base_addr);
  658. dev->ep0state = EP0_IDLE;
  659. }
  660. switch (dev->ep0state) {
  661. case EP0_IDLE:
  662. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  663. break;
  664. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  665. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  666. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
  667. s3c2410_udc_write_fifo(ep, req);
  668. break;
  669. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  670. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  671. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
  672. s3c2410_udc_read_fifo(ep, req);
  673. break;
  674. case EP0_END_XFER:
  675. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  676. dev->ep0state = EP0_IDLE;
  677. break;
  678. case EP0_STALL:
  679. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  680. dev->ep0state = EP0_IDLE;
  681. break;
  682. }
  683. }
  684. /*
  685. * handle_ep - Manage I/O endpoints
  686. */
  687. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  688. {
  689. struct s3c2410_request *req;
  690. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  691. u32 ep_csr1;
  692. u32 idx;
  693. if (likely(!list_empty(&ep->queue)))
  694. req = list_entry(ep->queue.next,
  695. struct s3c2410_request, queue);
  696. else
  697. req = NULL;
  698. idx = ep->bEndpointAddress & 0x7F;
  699. if (is_in) {
  700. udc_write(idx, S3C2410_UDC_INDEX_REG);
  701. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  702. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  703. idx, ep_csr1, req ? 1 : 0);
  704. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  705. dprintk(DEBUG_VERBOSE, "st\n");
  706. udc_write(idx, S3C2410_UDC_INDEX_REG);
  707. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  708. S3C2410_UDC_IN_CSR1_REG);
  709. return;
  710. }
  711. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
  712. s3c2410_udc_write_fifo(ep, req);
  713. } else {
  714. udc_write(idx, S3C2410_UDC_INDEX_REG);
  715. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  716. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  717. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  718. udc_write(idx, S3C2410_UDC_INDEX_REG);
  719. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  720. S3C2410_UDC_OUT_CSR1_REG);
  721. return;
  722. }
  723. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
  724. s3c2410_udc_read_fifo(ep, req);
  725. }
  726. }
  727. #include <mach/regs-irq.h>
  728. /*
  729. * s3c2410_udc_irq - interrupt handler
  730. */
  731. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  732. {
  733. struct s3c2410_udc *dev = _dev;
  734. int usb_status;
  735. int usbd_status;
  736. int pwr_reg;
  737. int ep0csr;
  738. int i;
  739. u32 idx, idx2;
  740. unsigned long flags;
  741. spin_lock_irqsave(&dev->lock, flags);
  742. /* Driver connected ? */
  743. if (!dev->driver) {
  744. /* Clear interrupts */
  745. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  746. S3C2410_UDC_USB_INT_REG);
  747. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  748. S3C2410_UDC_EP_INT_REG);
  749. }
  750. /* Save index */
  751. idx = udc_read(S3C2410_UDC_INDEX_REG);
  752. /* Read status registers */
  753. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  754. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  755. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  756. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  757. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  758. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  759. usb_status, usbd_status, pwr_reg, ep0csr);
  760. /*
  761. * Now, handle interrupts. There's two types :
  762. * - Reset, Resume, Suspend coming -> usb_int_reg
  763. * - EP -> ep_int_reg
  764. */
  765. /* RESET */
  766. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  767. /* two kind of reset :
  768. * - reset start -> pwr reg = 8
  769. * - reset end -> pwr reg = 0
  770. **/
  771. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  772. ep0csr, pwr_reg);
  773. dev->gadget.speed = USB_SPEED_UNKNOWN;
  774. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  775. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  776. S3C2410_UDC_MAXP_REG);
  777. dev->address = 0;
  778. dev->ep0state = EP0_IDLE;
  779. dev->gadget.speed = USB_SPEED_FULL;
  780. /* clear interrupt */
  781. udc_write(S3C2410_UDC_USBINT_RESET,
  782. S3C2410_UDC_USB_INT_REG);
  783. udc_write(idx, S3C2410_UDC_INDEX_REG);
  784. spin_unlock_irqrestore(&dev->lock, flags);
  785. return IRQ_HANDLED;
  786. }
  787. /* RESUME */
  788. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  789. dprintk(DEBUG_NORMAL, "USB resume\n");
  790. /* clear interrupt */
  791. udc_write(S3C2410_UDC_USBINT_RESUME,
  792. S3C2410_UDC_USB_INT_REG);
  793. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  794. && dev->driver
  795. && dev->driver->resume)
  796. dev->driver->resume(&dev->gadget);
  797. }
  798. /* SUSPEND */
  799. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  800. dprintk(DEBUG_NORMAL, "USB suspend\n");
  801. /* clear interrupt */
  802. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  803. S3C2410_UDC_USB_INT_REG);
  804. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  805. && dev->driver
  806. && dev->driver->suspend)
  807. dev->driver->suspend(&dev->gadget);
  808. dev->ep0state = EP0_IDLE;
  809. }
  810. /* EP */
  811. /* control traffic */
  812. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  813. * generate an interrupt
  814. */
  815. if (usbd_status & S3C2410_UDC_INT_EP0) {
  816. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  817. /* Clear the interrupt bit by setting it to 1 */
  818. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  819. s3c2410_udc_handle_ep0(dev);
  820. }
  821. /* endpoint data transfers */
  822. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  823. u32 tmp = 1 << i;
  824. if (usbd_status & tmp) {
  825. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  826. /* Clear the interrupt bit by setting it to 1 */
  827. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  828. s3c2410_udc_handle_ep(&dev->ep[i]);
  829. }
  830. }
  831. /* what else causes this interrupt? a receive! who is it? */
  832. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  833. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  834. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  835. udc_write(i, S3C2410_UDC_INDEX_REG);
  836. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  837. s3c2410_udc_handle_ep(&dev->ep[i]);
  838. /* restore index */
  839. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  840. }
  841. }
  842. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  843. /* Restore old index */
  844. udc_write(idx, S3C2410_UDC_INDEX_REG);
  845. spin_unlock_irqrestore(&dev->lock, flags);
  846. return IRQ_HANDLED;
  847. }
  848. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  849. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  850. {
  851. return container_of(ep, struct s3c2410_ep, ep);
  852. }
  853. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  854. {
  855. return container_of(gadget, struct s3c2410_udc, gadget);
  856. }
  857. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  858. {
  859. return container_of(req, struct s3c2410_request, req);
  860. }
  861. /*
  862. * s3c2410_udc_ep_enable
  863. */
  864. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  865. const struct usb_endpoint_descriptor *desc)
  866. {
  867. struct s3c2410_udc *dev;
  868. struct s3c2410_ep *ep;
  869. u32 max, tmp;
  870. unsigned long flags;
  871. u32 csr1, csr2;
  872. u32 int_en_reg;
  873. ep = to_s3c2410_ep(_ep);
  874. if (!_ep || !desc
  875. || _ep->name == ep0name
  876. || desc->bDescriptorType != USB_DT_ENDPOINT)
  877. return -EINVAL;
  878. dev = ep->dev;
  879. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  880. return -ESHUTDOWN;
  881. max = usb_endpoint_maxp(desc) & 0x1fff;
  882. local_irq_save(flags);
  883. _ep->maxpacket = max & 0x7ff;
  884. ep->ep.desc = desc;
  885. ep->halted = 0;
  886. ep->bEndpointAddress = desc->bEndpointAddress;
  887. /* set max packet */
  888. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  889. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  890. /* set type, direction, address; reset fifo counters */
  891. if (desc->bEndpointAddress & USB_DIR_IN) {
  892. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  893. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  894. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  895. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  896. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  897. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  898. } else {
  899. /* don't flush in fifo or it will cause endpoint interrupt */
  900. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  901. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  902. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  903. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  904. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  905. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  906. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  907. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  908. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  909. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  910. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  911. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  912. }
  913. /* enable irqs */
  914. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  915. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  916. /* print some debug message */
  917. tmp = desc->bEndpointAddress;
  918. dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  919. _ep->name, ep->num, tmp,
  920. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  921. local_irq_restore(flags);
  922. s3c2410_udc_set_halt(_ep, 0);
  923. return 0;
  924. }
  925. /*
  926. * s3c2410_udc_ep_disable
  927. */
  928. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  929. {
  930. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  931. unsigned long flags;
  932. u32 int_en_reg;
  933. if (!_ep || !ep->ep.desc) {
  934. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  935. _ep ? ep->ep.name : NULL);
  936. return -EINVAL;
  937. }
  938. local_irq_save(flags);
  939. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  940. ep->ep.desc = NULL;
  941. ep->halted = 1;
  942. s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
  943. /* disable irqs */
  944. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  945. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  946. local_irq_restore(flags);
  947. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  948. return 0;
  949. }
  950. /*
  951. * s3c2410_udc_alloc_request
  952. */
  953. static struct usb_request *
  954. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  955. {
  956. struct s3c2410_request *req;
  957. dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
  958. if (!_ep)
  959. return NULL;
  960. req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
  961. if (!req)
  962. return NULL;
  963. INIT_LIST_HEAD(&req->queue);
  964. return &req->req;
  965. }
  966. /*
  967. * s3c2410_udc_free_request
  968. */
  969. static void
  970. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  971. {
  972. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  973. struct s3c2410_request *req = to_s3c2410_req(_req);
  974. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  975. if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
  976. return;
  977. WARN_ON(!list_empty(&req->queue));
  978. kfree(req);
  979. }
  980. /*
  981. * s3c2410_udc_queue
  982. */
  983. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  984. gfp_t gfp_flags)
  985. {
  986. struct s3c2410_request *req = to_s3c2410_req(_req);
  987. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  988. struct s3c2410_udc *dev;
  989. u32 ep_csr = 0;
  990. int fifo_count = 0;
  991. unsigned long flags;
  992. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  993. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  994. return -EINVAL;
  995. }
  996. dev = ep->dev;
  997. if (unlikely(!dev->driver
  998. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  999. return -ESHUTDOWN;
  1000. }
  1001. local_irq_save(flags);
  1002. if (unlikely(!_req || !_req->complete
  1003. || !_req->buf || !list_empty(&req->queue))) {
  1004. if (!_req)
  1005. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1006. else {
  1007. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1008. __func__, !_req->complete, !_req->buf,
  1009. !list_empty(&req->queue));
  1010. }
  1011. local_irq_restore(flags);
  1012. return -EINVAL;
  1013. }
  1014. _req->status = -EINPROGRESS;
  1015. _req->actual = 0;
  1016. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1017. __func__, ep->bEndpointAddress, _req->length);
  1018. if (ep->bEndpointAddress) {
  1019. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1020. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1021. ? S3C2410_UDC_IN_CSR1_REG
  1022. : S3C2410_UDC_OUT_CSR1_REG);
  1023. fifo_count = s3c2410_udc_fifo_count_out();
  1024. } else {
  1025. udc_write(0, S3C2410_UDC_INDEX_REG);
  1026. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1027. fifo_count = s3c2410_udc_fifo_count_out();
  1028. }
  1029. /* kickstart this i/o queue? */
  1030. if (list_empty(&ep->queue) && !ep->halted) {
  1031. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1032. switch (dev->ep0state) {
  1033. case EP0_IN_DATA_PHASE:
  1034. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1035. && s3c2410_udc_write_fifo(ep,
  1036. req)) {
  1037. dev->ep0state = EP0_IDLE;
  1038. req = NULL;
  1039. }
  1040. break;
  1041. case EP0_OUT_DATA_PHASE:
  1042. if ((!_req->length)
  1043. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1044. && s3c2410_udc_read_fifo(ep,
  1045. req))) {
  1046. dev->ep0state = EP0_IDLE;
  1047. req = NULL;
  1048. }
  1049. break;
  1050. default:
  1051. local_irq_restore(flags);
  1052. return -EL2HLT;
  1053. }
  1054. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1055. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1056. && s3c2410_udc_write_fifo(ep, req)) {
  1057. req = NULL;
  1058. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1059. && fifo_count
  1060. && s3c2410_udc_read_fifo(ep, req)) {
  1061. req = NULL;
  1062. }
  1063. }
  1064. /* pio or dma irq handler advances the queue. */
  1065. if (likely(req))
  1066. list_add_tail(&req->queue, &ep->queue);
  1067. local_irq_restore(flags);
  1068. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1069. return 0;
  1070. }
  1071. /*
  1072. * s3c2410_udc_dequeue
  1073. */
  1074. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1075. {
  1076. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1077. struct s3c2410_udc *udc;
  1078. int retval = -EINVAL;
  1079. unsigned long flags;
  1080. struct s3c2410_request *req = NULL;
  1081. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1082. if (!the_controller->driver)
  1083. return -ESHUTDOWN;
  1084. if (!_ep || !_req)
  1085. return retval;
  1086. udc = to_s3c2410_udc(ep->gadget);
  1087. local_irq_save(flags);
  1088. list_for_each_entry(req, &ep->queue, queue) {
  1089. if (&req->req == _req) {
  1090. list_del_init(&req->queue);
  1091. _req->status = -ECONNRESET;
  1092. retval = 0;
  1093. break;
  1094. }
  1095. }
  1096. if (retval == 0) {
  1097. dprintk(DEBUG_VERBOSE,
  1098. "dequeued req %p from %s, len %d buf %p\n",
  1099. req, _ep->name, _req->length, _req->buf);
  1100. s3c2410_udc_done(ep, req, -ECONNRESET);
  1101. }
  1102. local_irq_restore(flags);
  1103. return retval;
  1104. }
  1105. /*
  1106. * s3c2410_udc_set_halt
  1107. */
  1108. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1109. {
  1110. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1111. u32 ep_csr = 0;
  1112. unsigned long flags;
  1113. u32 idx;
  1114. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  1115. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1116. return -EINVAL;
  1117. }
  1118. local_irq_save(flags);
  1119. idx = ep->bEndpointAddress & 0x7F;
  1120. if (idx == 0) {
  1121. s3c2410_udc_set_ep0_ss(base_addr);
  1122. s3c2410_udc_set_ep0_de_out(base_addr);
  1123. } else {
  1124. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1125. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1126. ? S3C2410_UDC_IN_CSR1_REG
  1127. : S3C2410_UDC_OUT_CSR1_REG);
  1128. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1129. if (value)
  1130. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1131. S3C2410_UDC_IN_CSR1_REG);
  1132. else {
  1133. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1134. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1135. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1136. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1137. }
  1138. } else {
  1139. if (value)
  1140. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1141. S3C2410_UDC_OUT_CSR1_REG);
  1142. else {
  1143. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1144. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1145. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1146. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1147. }
  1148. }
  1149. }
  1150. ep->halted = value ? 1 : 0;
  1151. local_irq_restore(flags);
  1152. return 0;
  1153. }
  1154. static const struct usb_ep_ops s3c2410_ep_ops = {
  1155. .enable = s3c2410_udc_ep_enable,
  1156. .disable = s3c2410_udc_ep_disable,
  1157. .alloc_request = s3c2410_udc_alloc_request,
  1158. .free_request = s3c2410_udc_free_request,
  1159. .queue = s3c2410_udc_queue,
  1160. .dequeue = s3c2410_udc_dequeue,
  1161. .set_halt = s3c2410_udc_set_halt,
  1162. };
  1163. /*------------------------- usb_gadget_ops ----------------------------------*/
  1164. /*
  1165. * s3c2410_udc_get_frame
  1166. */
  1167. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1168. {
  1169. int tmp;
  1170. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1171. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1172. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1173. return tmp;
  1174. }
  1175. /*
  1176. * s3c2410_udc_wakeup
  1177. */
  1178. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1179. {
  1180. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1181. return 0;
  1182. }
  1183. /*
  1184. * s3c2410_udc_set_selfpowered
  1185. */
  1186. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1187. {
  1188. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1189. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1190. if (value)
  1191. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1192. else
  1193. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1194. return 0;
  1195. }
  1196. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1197. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1198. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1199. {
  1200. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1201. if (udc_info && (udc_info->udc_command ||
  1202. gpio_is_valid(udc_info->pullup_pin))) {
  1203. if (is_on)
  1204. s3c2410_udc_enable(udc);
  1205. else {
  1206. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1207. if (udc->driver && udc->driver->disconnect)
  1208. udc->driver->disconnect(&udc->gadget);
  1209. }
  1210. s3c2410_udc_disable(udc);
  1211. }
  1212. } else {
  1213. return -EOPNOTSUPP;
  1214. }
  1215. return 0;
  1216. }
  1217. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1218. {
  1219. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1220. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1221. udc->vbus = (is_active != 0);
  1222. s3c2410_udc_set_pullup(udc, is_active);
  1223. return 0;
  1224. }
  1225. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1226. {
  1227. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1228. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1229. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1230. return 0;
  1231. }
  1232. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1233. {
  1234. struct s3c2410_udc *dev = _dev;
  1235. unsigned int value;
  1236. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1237. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1238. if (udc_info->vbus_pin_inverted)
  1239. value = !value;
  1240. if (value != dev->vbus)
  1241. s3c2410_udc_vbus_session(&dev->gadget, value);
  1242. return IRQ_HANDLED;
  1243. }
  1244. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1245. {
  1246. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1247. if (udc_info && udc_info->vbus_draw) {
  1248. udc_info->vbus_draw(ma);
  1249. return 0;
  1250. }
  1251. return -ENOTSUPP;
  1252. }
  1253. static int s3c2410_udc_start(struct usb_gadget *g,
  1254. struct usb_gadget_driver *driver);
  1255. static int s3c2410_udc_stop(struct usb_gadget *g);
  1256. static const struct usb_gadget_ops s3c2410_ops = {
  1257. .get_frame = s3c2410_udc_get_frame,
  1258. .wakeup = s3c2410_udc_wakeup,
  1259. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1260. .pullup = s3c2410_udc_pullup,
  1261. .vbus_session = s3c2410_udc_vbus_session,
  1262. .vbus_draw = s3c2410_vbus_draw,
  1263. .udc_start = s3c2410_udc_start,
  1264. .udc_stop = s3c2410_udc_stop,
  1265. };
  1266. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1267. {
  1268. if (!udc_info)
  1269. return;
  1270. if (udc_info->udc_command) {
  1271. udc_info->udc_command(cmd);
  1272. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1273. int value;
  1274. switch (cmd) {
  1275. case S3C2410_UDC_P_ENABLE:
  1276. value = 1;
  1277. break;
  1278. case S3C2410_UDC_P_DISABLE:
  1279. value = 0;
  1280. break;
  1281. default:
  1282. return;
  1283. }
  1284. value ^= udc_info->pullup_pin_inverted;
  1285. gpio_set_value(udc_info->pullup_pin, value);
  1286. }
  1287. }
  1288. /*------------------------- gadget driver handling---------------------------*/
  1289. /*
  1290. * s3c2410_udc_disable
  1291. */
  1292. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1293. {
  1294. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1295. /* Disable all interrupts */
  1296. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1297. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1298. /* Clear the interrupt registers */
  1299. udc_write(S3C2410_UDC_USBINT_RESET
  1300. | S3C2410_UDC_USBINT_RESUME
  1301. | S3C2410_UDC_USBINT_SUSPEND,
  1302. S3C2410_UDC_USB_INT_REG);
  1303. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1304. /* Good bye, cruel world */
  1305. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1306. /* Set speed to unknown */
  1307. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1308. }
  1309. /*
  1310. * s3c2410_udc_reinit
  1311. */
  1312. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1313. {
  1314. u32 i;
  1315. /* device/ep0 records init */
  1316. INIT_LIST_HEAD(&dev->gadget.ep_list);
  1317. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  1318. dev->ep0state = EP0_IDLE;
  1319. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1320. struct s3c2410_ep *ep = &dev->ep[i];
  1321. if (i != 0)
  1322. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1323. ep->dev = dev;
  1324. ep->ep.desc = NULL;
  1325. ep->halted = 0;
  1326. INIT_LIST_HEAD(&ep->queue);
  1327. usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
  1328. }
  1329. }
  1330. /*
  1331. * s3c2410_udc_enable
  1332. */
  1333. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1334. {
  1335. int i;
  1336. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1337. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1338. dev->gadget.speed = USB_SPEED_FULL;
  1339. /* Set MAXP for all endpoints */
  1340. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1341. udc_write(i, S3C2410_UDC_INDEX_REG);
  1342. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1343. S3C2410_UDC_MAXP_REG);
  1344. }
  1345. /* Set default power state */
  1346. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1347. /* Enable reset and suspend interrupt interrupts */
  1348. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1349. S3C2410_UDC_USB_INT_EN_REG);
  1350. /* Enable ep0 interrupt */
  1351. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1352. /* time to say "hello, world" */
  1353. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1354. }
  1355. static int s3c2410_udc_start(struct usb_gadget *g,
  1356. struct usb_gadget_driver *driver)
  1357. {
  1358. struct s3c2410_udc *udc = to_s3c2410(g);
  1359. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1360. /* Hook the driver */
  1361. udc->driver = driver;
  1362. /* Enable udc */
  1363. s3c2410_udc_enable(udc);
  1364. return 0;
  1365. }
  1366. static int s3c2410_udc_stop(struct usb_gadget *g)
  1367. {
  1368. struct s3c2410_udc *udc = to_s3c2410(g);
  1369. udc->driver = NULL;
  1370. /* Disable udc */
  1371. s3c2410_udc_disable(udc);
  1372. return 0;
  1373. }
  1374. /*---------------------------------------------------------------------------*/
  1375. static struct s3c2410_udc memory = {
  1376. .gadget = {
  1377. .ops = &s3c2410_ops,
  1378. .ep0 = &memory.ep[0].ep,
  1379. .name = gadget_name,
  1380. .dev = {
  1381. .init_name = "gadget",
  1382. },
  1383. },
  1384. /* control endpoint */
  1385. .ep[0] = {
  1386. .num = 0,
  1387. .ep = {
  1388. .name = ep0name,
  1389. .ops = &s3c2410_ep_ops,
  1390. .maxpacket = EP0_FIFO_SIZE,
  1391. },
  1392. .dev = &memory,
  1393. },
  1394. /* first group of endpoints */
  1395. .ep[1] = {
  1396. .num = 1,
  1397. .ep = {
  1398. .name = "ep1-bulk",
  1399. .ops = &s3c2410_ep_ops,
  1400. .maxpacket = EP_FIFO_SIZE,
  1401. },
  1402. .dev = &memory,
  1403. .fifo_size = EP_FIFO_SIZE,
  1404. .bEndpointAddress = 1,
  1405. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1406. },
  1407. .ep[2] = {
  1408. .num = 2,
  1409. .ep = {
  1410. .name = "ep2-bulk",
  1411. .ops = &s3c2410_ep_ops,
  1412. .maxpacket = EP_FIFO_SIZE,
  1413. },
  1414. .dev = &memory,
  1415. .fifo_size = EP_FIFO_SIZE,
  1416. .bEndpointAddress = 2,
  1417. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1418. },
  1419. .ep[3] = {
  1420. .num = 3,
  1421. .ep = {
  1422. .name = "ep3-bulk",
  1423. .ops = &s3c2410_ep_ops,
  1424. .maxpacket = EP_FIFO_SIZE,
  1425. },
  1426. .dev = &memory,
  1427. .fifo_size = EP_FIFO_SIZE,
  1428. .bEndpointAddress = 3,
  1429. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1430. },
  1431. .ep[4] = {
  1432. .num = 4,
  1433. .ep = {
  1434. .name = "ep4-bulk",
  1435. .ops = &s3c2410_ep_ops,
  1436. .maxpacket = EP_FIFO_SIZE,
  1437. },
  1438. .dev = &memory,
  1439. .fifo_size = EP_FIFO_SIZE,
  1440. .bEndpointAddress = 4,
  1441. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1442. }
  1443. };
  1444. /*
  1445. * probe - binds to the platform device
  1446. */
  1447. static int s3c2410_udc_probe(struct platform_device *pdev)
  1448. {
  1449. struct s3c2410_udc *udc = &memory;
  1450. struct device *dev = &pdev->dev;
  1451. int retval;
  1452. int irq;
  1453. dev_dbg(dev, "%s()\n", __func__);
  1454. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1455. if (IS_ERR(usb_bus_clock)) {
  1456. dev_err(dev, "failed to get usb bus clock source\n");
  1457. return PTR_ERR(usb_bus_clock);
  1458. }
  1459. clk_prepare_enable(usb_bus_clock);
  1460. udc_clock = clk_get(NULL, "usb-device");
  1461. if (IS_ERR(udc_clock)) {
  1462. dev_err(dev, "failed to get udc clock source\n");
  1463. return PTR_ERR(udc_clock);
  1464. }
  1465. clk_prepare_enable(udc_clock);
  1466. mdelay(10);
  1467. dev_dbg(dev, "got and enabled clocks\n");
  1468. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1469. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1470. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1471. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1472. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1473. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1474. }
  1475. spin_lock_init(&udc->lock);
  1476. udc_info = dev_get_platdata(&pdev->dev);
  1477. rsrc_start = S3C2410_PA_USBDEV;
  1478. rsrc_len = S3C24XX_SZ_USBDEV;
  1479. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1480. return -EBUSY;
  1481. base_addr = ioremap(rsrc_start, rsrc_len);
  1482. if (!base_addr) {
  1483. retval = -ENOMEM;
  1484. goto err_mem;
  1485. }
  1486. the_controller = udc;
  1487. platform_set_drvdata(pdev, udc);
  1488. s3c2410_udc_disable(udc);
  1489. s3c2410_udc_reinit(udc);
  1490. /* irq setup after old hardware state is cleaned up */
  1491. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1492. 0, gadget_name, udc);
  1493. if (retval != 0) {
  1494. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1495. retval = -EBUSY;
  1496. goto err_map;
  1497. }
  1498. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1499. if (udc_info && udc_info->vbus_pin > 0) {
  1500. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1501. if (retval < 0) {
  1502. dev_err(dev, "cannot claim vbus pin\n");
  1503. goto err_int;
  1504. }
  1505. irq = gpio_to_irq(udc_info->vbus_pin);
  1506. if (irq < 0) {
  1507. dev_err(dev, "no irq for gpio vbus pin\n");
  1508. retval = irq;
  1509. goto err_gpio_claim;
  1510. }
  1511. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1512. IRQF_TRIGGER_RISING
  1513. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1514. gadget_name, udc);
  1515. if (retval != 0) {
  1516. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1517. irq, retval);
  1518. retval = -EBUSY;
  1519. goto err_gpio_claim;
  1520. }
  1521. dev_dbg(dev, "got irq %i\n", irq);
  1522. } else {
  1523. udc->vbus = 1;
  1524. }
  1525. if (udc_info && !udc_info->udc_command &&
  1526. gpio_is_valid(udc_info->pullup_pin)) {
  1527. retval = gpio_request_one(udc_info->pullup_pin,
  1528. udc_info->vbus_pin_inverted ?
  1529. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1530. "udc pullup");
  1531. if (retval)
  1532. goto err_vbus_irq;
  1533. }
  1534. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1535. if (retval)
  1536. goto err_add_udc;
  1537. if (s3c2410_udc_debugfs_root) {
  1538. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1539. s3c2410_udc_debugfs_root,
  1540. udc, &s3c2410_udc_debugfs_fops);
  1541. if (!udc->regs_info)
  1542. dev_warn(dev, "debugfs file creation failed\n");
  1543. }
  1544. dev_dbg(dev, "probe ok\n");
  1545. return 0;
  1546. err_add_udc:
  1547. if (udc_info && !udc_info->udc_command &&
  1548. gpio_is_valid(udc_info->pullup_pin))
  1549. gpio_free(udc_info->pullup_pin);
  1550. err_vbus_irq:
  1551. if (udc_info && udc_info->vbus_pin > 0)
  1552. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1553. err_gpio_claim:
  1554. if (udc_info && udc_info->vbus_pin > 0)
  1555. gpio_free(udc_info->vbus_pin);
  1556. err_int:
  1557. free_irq(IRQ_USBD, udc);
  1558. err_map:
  1559. iounmap(base_addr);
  1560. err_mem:
  1561. release_mem_region(rsrc_start, rsrc_len);
  1562. return retval;
  1563. }
  1564. /*
  1565. * s3c2410_udc_remove
  1566. */
  1567. static int s3c2410_udc_remove(struct platform_device *pdev)
  1568. {
  1569. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1570. unsigned int irq;
  1571. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1572. if (udc->driver)
  1573. return -EBUSY;
  1574. usb_del_gadget_udc(&udc->gadget);
  1575. debugfs_remove(udc->regs_info);
  1576. if (udc_info && !udc_info->udc_command &&
  1577. gpio_is_valid(udc_info->pullup_pin))
  1578. gpio_free(udc_info->pullup_pin);
  1579. if (udc_info && udc_info->vbus_pin > 0) {
  1580. irq = gpio_to_irq(udc_info->vbus_pin);
  1581. free_irq(irq, udc);
  1582. }
  1583. free_irq(IRQ_USBD, udc);
  1584. iounmap(base_addr);
  1585. release_mem_region(rsrc_start, rsrc_len);
  1586. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1587. clk_disable_unprepare(udc_clock);
  1588. clk_put(udc_clock);
  1589. udc_clock = NULL;
  1590. }
  1591. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1592. clk_disable_unprepare(usb_bus_clock);
  1593. clk_put(usb_bus_clock);
  1594. usb_bus_clock = NULL;
  1595. }
  1596. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1597. return 0;
  1598. }
  1599. #ifdef CONFIG_PM
  1600. static int
  1601. s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1602. {
  1603. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1604. return 0;
  1605. }
  1606. static int s3c2410_udc_resume(struct platform_device *pdev)
  1607. {
  1608. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1609. return 0;
  1610. }
  1611. #else
  1612. #define s3c2410_udc_suspend NULL
  1613. #define s3c2410_udc_resume NULL
  1614. #endif
  1615. static const struct platform_device_id s3c_udc_ids[] = {
  1616. { "s3c2410-usbgadget", },
  1617. { "s3c2440-usbgadget", },
  1618. { }
  1619. };
  1620. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1621. static struct platform_driver udc_driver_24x0 = {
  1622. .driver = {
  1623. .name = "s3c24x0-usbgadget",
  1624. },
  1625. .probe = s3c2410_udc_probe,
  1626. .remove = s3c2410_udc_remove,
  1627. .suspend = s3c2410_udc_suspend,
  1628. .resume = s3c2410_udc_resume,
  1629. .id_table = s3c_udc_ids,
  1630. };
  1631. static int __init udc_init(void)
  1632. {
  1633. int retval;
  1634. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1635. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1636. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1637. pr_err("%s: debugfs dir creation failed %ld\n",
  1638. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1639. s3c2410_udc_debugfs_root = NULL;
  1640. }
  1641. retval = platform_driver_register(&udc_driver_24x0);
  1642. if (retval)
  1643. goto err;
  1644. return 0;
  1645. err:
  1646. debugfs_remove(s3c2410_udc_debugfs_root);
  1647. return retval;
  1648. }
  1649. static void __exit udc_exit(void)
  1650. {
  1651. platform_driver_unregister(&udc_driver_24x0);
  1652. debugfs_remove(s3c2410_udc_debugfs_root);
  1653. }
  1654. module_init(udc_init);
  1655. module_exit(udc_exit);
  1656. MODULE_AUTHOR(DRIVER_AUTHOR);
  1657. MODULE_DESCRIPTION(DRIVER_DESC);
  1658. MODULE_VERSION(DRIVER_VERSION);
  1659. MODULE_LICENSE("GPL");