aerdrv_errprint.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270
  1. /*
  2. * drivers/pci/pcie/aer/aerdrv_errprint.c
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Format error messages and print them to console.
  9. *
  10. * Copyright (C) 2006 Intel Corp.
  11. * Tom Long Nguyen (tom.l.nguyen@intel.com)
  12. * Zhang Yanmin (yanmin.zhang@intel.com)
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/pm.h>
  20. #include <linux/suspend.h>
  21. #include <linux/cper.h>
  22. #include "aerdrv.h"
  23. #include <ras/ras_event.h>
  24. #define AER_AGENT_RECEIVER 0
  25. #define AER_AGENT_REQUESTER 1
  26. #define AER_AGENT_COMPLETER 2
  27. #define AER_AGENT_TRANSMITTER 3
  28. #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
  29. 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
  30. #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
  31. 0 : PCI_ERR_UNC_COMP_ABORT)
  32. #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
  33. (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
  34. #define AER_GET_AGENT(t, e) \
  35. ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
  36. (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
  37. (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
  38. AER_AGENT_RECEIVER)
  39. #define AER_PHYSICAL_LAYER_ERROR 0
  40. #define AER_DATA_LINK_LAYER_ERROR 1
  41. #define AER_TRANSACTION_LAYER_ERROR 2
  42. #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
  43. PCI_ERR_COR_RCVR : 0)
  44. #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
  45. (PCI_ERR_COR_BAD_TLP| \
  46. PCI_ERR_COR_BAD_DLLP| \
  47. PCI_ERR_COR_REP_ROLL| \
  48. PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
  49. #define AER_GET_LAYER_ERROR(t, e) \
  50. ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
  51. (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
  52. AER_TRANSACTION_LAYER_ERROR)
  53. /*
  54. * AER error strings
  55. */
  56. static const char *aer_error_severity_string[] = {
  57. "Uncorrected (Non-Fatal)",
  58. "Uncorrected (Fatal)",
  59. "Corrected"
  60. };
  61. static const char *aer_error_layer[] = {
  62. "Physical Layer",
  63. "Data Link Layer",
  64. "Transaction Layer"
  65. };
  66. static const char *aer_correctable_error_string[] = {
  67. "Receiver Error", /* Bit Position 0 */
  68. NULL,
  69. NULL,
  70. NULL,
  71. NULL,
  72. NULL,
  73. "Bad TLP", /* Bit Position 6 */
  74. "Bad DLLP", /* Bit Position 7 */
  75. "RELAY_NUM Rollover", /* Bit Position 8 */
  76. NULL,
  77. NULL,
  78. NULL,
  79. "Replay Timer Timeout", /* Bit Position 12 */
  80. "Advisory Non-Fatal", /* Bit Position 13 */
  81. "Corrected Internal Error", /* Bit Position 14 */
  82. "Header Log Overflow", /* Bit Position 15 */
  83. };
  84. static const char *aer_uncorrectable_error_string[] = {
  85. "Undefined", /* Bit Position 0 */
  86. NULL,
  87. NULL,
  88. NULL,
  89. "Data Link Protocol", /* Bit Position 4 */
  90. "Surprise Down Error", /* Bit Position 5 */
  91. NULL,
  92. NULL,
  93. NULL,
  94. NULL,
  95. NULL,
  96. NULL,
  97. "Poisoned TLP", /* Bit Position 12 */
  98. "Flow Control Protocol", /* Bit Position 13 */
  99. "Completion Timeout", /* Bit Position 14 */
  100. "Completer Abort", /* Bit Position 15 */
  101. "Unexpected Completion", /* Bit Position 16 */
  102. "Receiver Overflow", /* Bit Position 17 */
  103. "Malformed TLP", /* Bit Position 18 */
  104. "ECRC", /* Bit Position 19 */
  105. "Unsupported Request", /* Bit Position 20 */
  106. "ACS Violation", /* Bit Position 21 */
  107. "Uncorrectable Internal Error", /* Bit Position 22 */
  108. "MC Blocked TLP", /* Bit Position 23 */
  109. "AtomicOp Egress Blocked", /* Bit Position 24 */
  110. "TLP Prefix Blocked Error", /* Bit Position 25 */
  111. };
  112. static const char *aer_agent_string[] = {
  113. "Receiver ID",
  114. "Requester ID",
  115. "Completer ID",
  116. "Transmitter ID"
  117. };
  118. static void __print_tlp_header(struct pci_dev *dev,
  119. struct aer_header_log_regs *t)
  120. {
  121. unsigned char *tlp = (unsigned char *)&t;
  122. dev_err(&dev->dev, " TLP Header:"
  123. " %02x%02x%02x%02x %02x%02x%02x%02x"
  124. " %02x%02x%02x%02x %02x%02x%02x%02x\n",
  125. *(tlp + 3), *(tlp + 2), *(tlp + 1), *tlp,
  126. *(tlp + 7), *(tlp + 6), *(tlp + 5), *(tlp + 4),
  127. *(tlp + 11), *(tlp + 10), *(tlp + 9),
  128. *(tlp + 8), *(tlp + 15), *(tlp + 14),
  129. *(tlp + 13), *(tlp + 12));
  130. }
  131. static void __aer_print_error(struct pci_dev *dev,
  132. struct aer_err_info *info)
  133. {
  134. int i, status;
  135. const char *errmsg = NULL;
  136. status = (info->status & ~info->mask);
  137. for (i = 0; i < 32; i++) {
  138. if (!(status & (1 << i)))
  139. continue;
  140. if (info->severity == AER_CORRECTABLE)
  141. errmsg = i < ARRAY_SIZE(aer_correctable_error_string) ?
  142. aer_correctable_error_string[i] : NULL;
  143. else
  144. errmsg = i < ARRAY_SIZE(aer_uncorrectable_error_string) ?
  145. aer_uncorrectable_error_string[i] : NULL;
  146. if (errmsg)
  147. dev_err(&dev->dev, " [%2d] %-22s%s\n", i, errmsg,
  148. info->first_error == i ? " (First)" : "");
  149. else
  150. dev_err(&dev->dev, " [%2d] Unknown Error Bit%s\n",
  151. i, info->first_error == i ? " (First)" : "");
  152. }
  153. }
  154. void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
  155. {
  156. int layer, agent;
  157. int id = ((dev->bus->number << 8) | dev->devfn);
  158. if (!info->status) {
  159. dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n",
  160. aer_error_severity_string[info->severity], id);
  161. goto out;
  162. }
  163. layer = AER_GET_LAYER_ERROR(info->severity, info->status);
  164. agent = AER_GET_AGENT(info->severity, info->status);
  165. dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
  166. aer_error_severity_string[info->severity],
  167. aer_error_layer[layer], id, aer_agent_string[agent]);
  168. dev_err(&dev->dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
  169. dev->vendor, dev->device,
  170. info->status, info->mask);
  171. __aer_print_error(dev, info);
  172. if (info->tlp_header_valid)
  173. __print_tlp_header(dev, &info->tlp);
  174. out:
  175. if (info->id && info->error_dev_num > 1 && info->id == id)
  176. dev_err(&dev->dev, " Error of this Agent(%04x) is reported first\n", id);
  177. trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
  178. info->severity);
  179. }
  180. void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
  181. {
  182. dev_info(&dev->dev, "AER: %s%s error received: id=%04x\n",
  183. info->multi_error_valid ? "Multiple " : "",
  184. aer_error_severity_string[info->severity], info->id);
  185. }
  186. #ifdef CONFIG_ACPI_APEI_PCIEAER
  187. int cper_severity_to_aer(int cper_severity)
  188. {
  189. switch (cper_severity) {
  190. case CPER_SEV_RECOVERABLE:
  191. return AER_NONFATAL;
  192. case CPER_SEV_FATAL:
  193. return AER_FATAL;
  194. default:
  195. return AER_CORRECTABLE;
  196. }
  197. }
  198. EXPORT_SYMBOL_GPL(cper_severity_to_aer);
  199. void cper_print_aer(struct pci_dev *dev, int cper_severity,
  200. struct aer_capability_regs *aer)
  201. {
  202. int aer_severity, layer, agent, status_strs_size, tlp_header_valid = 0;
  203. u32 status, mask;
  204. const char **status_strs;
  205. aer_severity = cper_severity_to_aer(cper_severity);
  206. if (aer_severity == AER_CORRECTABLE) {
  207. status = aer->cor_status;
  208. mask = aer->cor_mask;
  209. status_strs = aer_correctable_error_string;
  210. status_strs_size = ARRAY_SIZE(aer_correctable_error_string);
  211. } else {
  212. status = aer->uncor_status;
  213. mask = aer->uncor_mask;
  214. status_strs = aer_uncorrectable_error_string;
  215. status_strs_size = ARRAY_SIZE(aer_uncorrectable_error_string);
  216. tlp_header_valid = status & AER_LOG_TLP_MASKS;
  217. }
  218. layer = AER_GET_LAYER_ERROR(aer_severity, status);
  219. agent = AER_GET_AGENT(aer_severity, status);
  220. dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
  221. cper_print_bits("", status, status_strs, status_strs_size);
  222. dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",
  223. aer_error_layer[layer], aer_agent_string[agent]);
  224. if (aer_severity != AER_CORRECTABLE)
  225. dev_err(&dev->dev, "aer_uncor_severity: 0x%08x\n",
  226. aer->uncor_severity);
  227. if (tlp_header_valid)
  228. __print_tlp_header(dev, &aer->header_log);
  229. trace_aer_event(dev_name(&dev->dev), (status & ~mask),
  230. aer_severity);
  231. }
  232. #endif