pcie.c 70 KB

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  1. /*
  2. * Marvell Wireless LAN device driver: PCIE specific handling
  3. *
  4. * Copyright (C) 2011-2014, Marvell International Ltd.
  5. *
  6. * This software file (the "File") is distributed by Marvell International
  7. * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  8. * (the "License"). You may use, redistribute and/or modify this File in
  9. * accordance with the terms and conditions of the License, a copy of which
  10. * is available by writing to the Free Software Foundation, Inc.,
  11. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12. * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13. *
  14. * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16. * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
  17. * this warranty disclaimer.
  18. */
  19. #include <linux/firmware.h>
  20. #include "decl.h"
  21. #include "ioctl.h"
  22. #include "util.h"
  23. #include "fw.h"
  24. #include "main.h"
  25. #include "wmm.h"
  26. #include "11n.h"
  27. #include "pcie.h"
  28. #define PCIE_VERSION "1.0"
  29. #define DRV_NAME "Marvell mwifiex PCIe"
  30. static u8 user_rmmod;
  31. static struct mwifiex_if_ops pcie_ops;
  32. static struct semaphore add_remove_card_sem;
  33. static struct memory_type_mapping mem_type_mapping_tbl[] = {
  34. {"ITCM", NULL, 0, 0xF0},
  35. {"DTCM", NULL, 0, 0xF1},
  36. {"SQRAM", NULL, 0, 0xF2},
  37. {"IRAM", NULL, 0, 0xF3},
  38. {"APU", NULL, 0, 0xF4},
  39. {"CIU", NULL, 0, 0xF5},
  40. {"ICU", NULL, 0, 0xF6},
  41. {"MAC", NULL, 0, 0xF7},
  42. };
  43. static int
  44. mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
  45. size_t size, int flags)
  46. {
  47. struct pcie_service_card *card = adapter->card;
  48. struct mwifiex_dma_mapping mapping;
  49. mapping.addr = pci_map_single(card->dev, skb->data, size, flags);
  50. if (pci_dma_mapping_error(card->dev, mapping.addr)) {
  51. dev_err(adapter->dev, "failed to map pci memory!\n");
  52. return -1;
  53. }
  54. mapping.len = size;
  55. mwifiex_store_mapping(skb, &mapping);
  56. return 0;
  57. }
  58. static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
  59. struct sk_buff *skb, int flags)
  60. {
  61. struct pcie_service_card *card = adapter->card;
  62. struct mwifiex_dma_mapping mapping;
  63. mwifiex_get_mapping(skb, &mapping);
  64. pci_unmap_single(card->dev, mapping.addr, mapping.len, flags);
  65. }
  66. /*
  67. * This function reads sleep cookie and checks if FW is ready
  68. */
  69. static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
  70. {
  71. u32 *cookie_addr;
  72. struct pcie_service_card *card = adapter->card;
  73. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  74. if (!reg->sleep_cookie)
  75. return true;
  76. if (card->sleep_cookie_vbase) {
  77. cookie_addr = (u32 *)card->sleep_cookie_vbase;
  78. dev_dbg(adapter->dev, "info: ACCESS_HW: sleep cookie=0x%x\n",
  79. *cookie_addr);
  80. if (*cookie_addr == FW_AWAKE_COOKIE)
  81. return true;
  82. }
  83. return false;
  84. }
  85. #ifdef CONFIG_PM_SLEEP
  86. /*
  87. * Kernel needs to suspend all functions separately. Therefore all
  88. * registered functions must have drivers with suspend and resume
  89. * methods. Failing that the kernel simply removes the whole card.
  90. *
  91. * If already not suspended, this function allocates and sends a host
  92. * sleep activate request to the firmware and turns off the traffic.
  93. */
  94. static int mwifiex_pcie_suspend(struct device *dev)
  95. {
  96. struct mwifiex_adapter *adapter;
  97. struct pcie_service_card *card;
  98. int hs_actived;
  99. struct pci_dev *pdev = to_pci_dev(dev);
  100. if (pdev) {
  101. card = pci_get_drvdata(pdev);
  102. if (!card || !card->adapter) {
  103. pr_err("Card or adapter structure is not valid\n");
  104. return 0;
  105. }
  106. } else {
  107. pr_err("PCIE device is not specified\n");
  108. return 0;
  109. }
  110. adapter = card->adapter;
  111. hs_actived = mwifiex_enable_hs(adapter);
  112. /* Indicate device suspended */
  113. adapter->is_suspended = true;
  114. adapter->hs_enabling = false;
  115. return 0;
  116. }
  117. /*
  118. * Kernel needs to suspend all functions separately. Therefore all
  119. * registered functions must have drivers with suspend and resume
  120. * methods. Failing that the kernel simply removes the whole card.
  121. *
  122. * If already not resumed, this function turns on the traffic and
  123. * sends a host sleep cancel request to the firmware.
  124. */
  125. static int mwifiex_pcie_resume(struct device *dev)
  126. {
  127. struct mwifiex_adapter *adapter;
  128. struct pcie_service_card *card;
  129. struct pci_dev *pdev = to_pci_dev(dev);
  130. if (pdev) {
  131. card = pci_get_drvdata(pdev);
  132. if (!card || !card->adapter) {
  133. pr_err("Card or adapter structure is not valid\n");
  134. return 0;
  135. }
  136. } else {
  137. pr_err("PCIE device is not specified\n");
  138. return 0;
  139. }
  140. adapter = card->adapter;
  141. if (!adapter->is_suspended) {
  142. dev_warn(adapter->dev, "Device already resumed\n");
  143. return 0;
  144. }
  145. adapter->is_suspended = false;
  146. mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
  147. MWIFIEX_ASYNC_CMD);
  148. return 0;
  149. }
  150. #endif
  151. /*
  152. * This function probes an mwifiex device and registers it. It allocates
  153. * the card structure, enables PCIE function number and initiates the
  154. * device registration and initialization procedure by adding a logical
  155. * interface.
  156. */
  157. static int mwifiex_pcie_probe(struct pci_dev *pdev,
  158. const struct pci_device_id *ent)
  159. {
  160. struct pcie_service_card *card;
  161. pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
  162. pdev->vendor, pdev->device, pdev->revision);
  163. card = kzalloc(sizeof(struct pcie_service_card), GFP_KERNEL);
  164. if (!card)
  165. return -ENOMEM;
  166. card->dev = pdev;
  167. if (ent->driver_data) {
  168. struct mwifiex_pcie_device *data = (void *)ent->driver_data;
  169. card->pcie.firmware = data->firmware;
  170. card->pcie.reg = data->reg;
  171. card->pcie.blksz_fw_dl = data->blksz_fw_dl;
  172. card->pcie.tx_buf_size = data->tx_buf_size;
  173. card->pcie.supports_fw_dump = data->supports_fw_dump;
  174. }
  175. if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
  176. MWIFIEX_PCIE)) {
  177. pr_err("%s failed\n", __func__);
  178. kfree(card);
  179. return -1;
  180. }
  181. return 0;
  182. }
  183. /*
  184. * This function removes the interface and frees up the card structure.
  185. */
  186. static void mwifiex_pcie_remove(struct pci_dev *pdev)
  187. {
  188. struct pcie_service_card *card;
  189. struct mwifiex_adapter *adapter;
  190. struct mwifiex_private *priv;
  191. card = pci_get_drvdata(pdev);
  192. if (!card)
  193. return;
  194. adapter = card->adapter;
  195. if (!adapter || !adapter->priv_num)
  196. return;
  197. cancel_work_sync(&adapter->iface_work);
  198. if (user_rmmod) {
  199. #ifdef CONFIG_PM_SLEEP
  200. if (adapter->is_suspended)
  201. mwifiex_pcie_resume(&pdev->dev);
  202. #endif
  203. mwifiex_deauthenticate_all(adapter);
  204. priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
  205. mwifiex_disable_auto_ds(priv);
  206. mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
  207. }
  208. mwifiex_remove_card(card->adapter, &add_remove_card_sem);
  209. }
  210. static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
  211. {
  212. user_rmmod = 1;
  213. mwifiex_pcie_remove(pdev);
  214. return;
  215. }
  216. static const struct pci_device_id mwifiex_ids[] = {
  217. {
  218. PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
  219. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  220. .driver_data = (unsigned long) &mwifiex_pcie8766,
  221. },
  222. {
  223. PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
  224. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  225. .driver_data = (unsigned long) &mwifiex_pcie8897,
  226. },
  227. {},
  228. };
  229. MODULE_DEVICE_TABLE(pci, mwifiex_ids);
  230. #ifdef CONFIG_PM_SLEEP
  231. /* Power Management Hooks */
  232. static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
  233. mwifiex_pcie_resume);
  234. #endif
  235. /* PCI Device Driver */
  236. static struct pci_driver __refdata mwifiex_pcie = {
  237. .name = "mwifiex_pcie",
  238. .id_table = mwifiex_ids,
  239. .probe = mwifiex_pcie_probe,
  240. .remove = mwifiex_pcie_remove,
  241. #ifdef CONFIG_PM_SLEEP
  242. .driver = {
  243. .pm = &mwifiex_pcie_pm_ops,
  244. },
  245. #endif
  246. .shutdown = mwifiex_pcie_shutdown,
  247. };
  248. /*
  249. * This function writes data into PCIE card register.
  250. */
  251. static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
  252. {
  253. struct pcie_service_card *card = adapter->card;
  254. iowrite32(data, card->pci_mmap1 + reg);
  255. return 0;
  256. }
  257. /*
  258. * This function reads data from PCIE card register.
  259. */
  260. static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
  261. {
  262. struct pcie_service_card *card = adapter->card;
  263. *data = ioread32(card->pci_mmap1 + reg);
  264. return 0;
  265. }
  266. /* This function reads u8 data from PCIE card register. */
  267. static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
  268. int reg, u8 *data)
  269. {
  270. struct pcie_service_card *card = adapter->card;
  271. *data = ioread8(card->pci_mmap1 + reg);
  272. return 0;
  273. }
  274. /*
  275. * This function adds delay loop to ensure FW is awake before proceeding.
  276. */
  277. static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
  278. {
  279. int i = 0;
  280. while (mwifiex_pcie_ok_to_access_hw(adapter)) {
  281. i++;
  282. usleep_range(10, 20);
  283. /* 50ms max wait */
  284. if (i == 5000)
  285. break;
  286. }
  287. return;
  288. }
  289. static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
  290. u32 max_delay_loop_cnt)
  291. {
  292. struct pcie_service_card *card = adapter->card;
  293. u8 *buffer;
  294. u32 sleep_cookie, count;
  295. for (count = 0; count < max_delay_loop_cnt; count++) {
  296. buffer = card->cmdrsp_buf->data - INTF_HEADER_LEN;
  297. sleep_cookie = *(u32 *)buffer;
  298. if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
  299. dev_dbg(adapter->dev,
  300. "sleep cookie found at count %d\n", count);
  301. break;
  302. }
  303. usleep_range(20, 30);
  304. }
  305. if (count >= max_delay_loop_cnt)
  306. dev_dbg(adapter->dev,
  307. "max count reached while accessing sleep cookie\n");
  308. }
  309. /* This function wakes up the card by reading fw_status register. */
  310. static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
  311. {
  312. u32 fw_status;
  313. struct pcie_service_card *card = adapter->card;
  314. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  315. dev_dbg(adapter->dev, "event: Wakeup device...\n");
  316. if (reg->sleep_cookie)
  317. mwifiex_pcie_dev_wakeup_delay(adapter);
  318. /* Reading fw_status register will wakeup device */
  319. if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) {
  320. dev_warn(adapter->dev, "Reading fw_status register failed\n");
  321. return -1;
  322. }
  323. if (reg->sleep_cookie) {
  324. mwifiex_pcie_dev_wakeup_delay(adapter);
  325. dev_dbg(adapter->dev, "PCIE wakeup: Setting PS_STATE_AWAKE\n");
  326. adapter->ps_state = PS_STATE_AWAKE;
  327. }
  328. return 0;
  329. }
  330. /*
  331. * This function is called after the card has woken up.
  332. *
  333. * The card configuration register is reset.
  334. */
  335. static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
  336. {
  337. dev_dbg(adapter->dev, "cmd: Wakeup device completed\n");
  338. return 0;
  339. }
  340. /*
  341. * This function disables the host interrupt.
  342. *
  343. * The host interrupt mask is read, the disable bit is reset and
  344. * written back to the card host interrupt mask register.
  345. */
  346. static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
  347. {
  348. if (mwifiex_pcie_ok_to_access_hw(adapter)) {
  349. if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
  350. 0x00000000)) {
  351. dev_warn(adapter->dev, "Disable host interrupt failed\n");
  352. return -1;
  353. }
  354. }
  355. return 0;
  356. }
  357. /*
  358. * This function enables the host interrupt.
  359. *
  360. * The host interrupt enable mask is written to the card
  361. * host interrupt mask register.
  362. */
  363. static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
  364. {
  365. if (mwifiex_pcie_ok_to_access_hw(adapter)) {
  366. /* Simply write the mask to the register */
  367. if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
  368. HOST_INTR_MASK)) {
  369. dev_warn(adapter->dev, "Enable host interrupt failed\n");
  370. return -1;
  371. }
  372. }
  373. return 0;
  374. }
  375. /*
  376. * This function initializes TX buffer ring descriptors
  377. */
  378. static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
  379. {
  380. struct pcie_service_card *card = adapter->card;
  381. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  382. struct mwifiex_pcie_buf_desc *desc;
  383. struct mwifiex_pfu_buf_desc *desc2;
  384. int i;
  385. for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
  386. card->tx_buf_list[i] = NULL;
  387. if (reg->pfu_enabled) {
  388. card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
  389. (sizeof(*desc2) * i);
  390. desc2 = card->txbd_ring[i];
  391. memset(desc2, 0, sizeof(*desc2));
  392. } else {
  393. card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
  394. (sizeof(*desc) * i);
  395. desc = card->txbd_ring[i];
  396. memset(desc, 0, sizeof(*desc));
  397. }
  398. }
  399. return 0;
  400. }
  401. /* This function initializes RX buffer ring descriptors. Each SKB is allocated
  402. * here and after mapping PCI memory, its physical address is assigned to
  403. * PCIE Rx buffer descriptor's physical address.
  404. */
  405. static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
  406. {
  407. struct pcie_service_card *card = adapter->card;
  408. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  409. struct sk_buff *skb;
  410. struct mwifiex_pcie_buf_desc *desc;
  411. struct mwifiex_pfu_buf_desc *desc2;
  412. dma_addr_t buf_pa;
  413. int i;
  414. for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
  415. /* Allocate skb here so that firmware can DMA data from it */
  416. skb = dev_alloc_skb(MWIFIEX_RX_DATA_BUF_SIZE);
  417. if (!skb) {
  418. dev_err(adapter->dev,
  419. "Unable to allocate skb for RX ring.\n");
  420. kfree(card->rxbd_ring_vbase);
  421. return -ENOMEM;
  422. }
  423. if (mwifiex_map_pci_memory(adapter, skb,
  424. MWIFIEX_RX_DATA_BUF_SIZE,
  425. PCI_DMA_FROMDEVICE))
  426. return -1;
  427. buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
  428. dev_dbg(adapter->dev,
  429. "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
  430. skb, skb->len, skb->data, (u32)buf_pa,
  431. (u32)((u64)buf_pa >> 32));
  432. card->rx_buf_list[i] = skb;
  433. if (reg->pfu_enabled) {
  434. card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
  435. (sizeof(*desc2) * i);
  436. desc2 = card->rxbd_ring[i];
  437. desc2->paddr = buf_pa;
  438. desc2->len = (u16)skb->len;
  439. desc2->frag_len = (u16)skb->len;
  440. desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
  441. desc2->offset = 0;
  442. } else {
  443. card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
  444. (sizeof(*desc) * i));
  445. desc = card->rxbd_ring[i];
  446. desc->paddr = buf_pa;
  447. desc->len = (u16)skb->len;
  448. desc->flags = 0;
  449. }
  450. }
  451. return 0;
  452. }
  453. /* This function initializes event buffer ring descriptors. Each SKB is
  454. * allocated here and after mapping PCI memory, its physical address is assigned
  455. * to PCIE Rx buffer descriptor's physical address
  456. */
  457. static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
  458. {
  459. struct pcie_service_card *card = adapter->card;
  460. struct mwifiex_evt_buf_desc *desc;
  461. struct sk_buff *skb;
  462. dma_addr_t buf_pa;
  463. int i;
  464. for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
  465. /* Allocate skb here so that firmware can DMA data from it */
  466. skb = dev_alloc_skb(MAX_EVENT_SIZE);
  467. if (!skb) {
  468. dev_err(adapter->dev,
  469. "Unable to allocate skb for EVENT buf.\n");
  470. kfree(card->evtbd_ring_vbase);
  471. return -ENOMEM;
  472. }
  473. skb_put(skb, MAX_EVENT_SIZE);
  474. if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
  475. PCI_DMA_FROMDEVICE))
  476. return -1;
  477. buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
  478. dev_dbg(adapter->dev,
  479. "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
  480. skb, skb->len, skb->data, (u32)buf_pa,
  481. (u32)((u64)buf_pa >> 32));
  482. card->evt_buf_list[i] = skb;
  483. card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
  484. (sizeof(*desc) * i));
  485. desc = card->evtbd_ring[i];
  486. desc->paddr = buf_pa;
  487. desc->len = (u16)skb->len;
  488. desc->flags = 0;
  489. }
  490. return 0;
  491. }
  492. /* This function cleans up TX buffer rings. If any of the buffer list has valid
  493. * SKB address, associated SKB is freed.
  494. */
  495. static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
  496. {
  497. struct pcie_service_card *card = adapter->card;
  498. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  499. struct sk_buff *skb;
  500. struct mwifiex_pcie_buf_desc *desc;
  501. struct mwifiex_pfu_buf_desc *desc2;
  502. int i;
  503. for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
  504. if (reg->pfu_enabled) {
  505. desc2 = card->txbd_ring[i];
  506. if (card->tx_buf_list[i]) {
  507. skb = card->tx_buf_list[i];
  508. mwifiex_unmap_pci_memory(adapter, skb,
  509. PCI_DMA_TODEVICE);
  510. dev_kfree_skb_any(skb);
  511. }
  512. memset(desc2, 0, sizeof(*desc2));
  513. } else {
  514. desc = card->txbd_ring[i];
  515. if (card->tx_buf_list[i]) {
  516. skb = card->tx_buf_list[i];
  517. mwifiex_unmap_pci_memory(adapter, skb,
  518. PCI_DMA_TODEVICE);
  519. dev_kfree_skb_any(skb);
  520. }
  521. memset(desc, 0, sizeof(*desc));
  522. }
  523. card->tx_buf_list[i] = NULL;
  524. }
  525. return;
  526. }
  527. /* This function cleans up RX buffer rings. If any of the buffer list has valid
  528. * SKB address, associated SKB is freed.
  529. */
  530. static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
  531. {
  532. struct pcie_service_card *card = adapter->card;
  533. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  534. struct mwifiex_pcie_buf_desc *desc;
  535. struct mwifiex_pfu_buf_desc *desc2;
  536. struct sk_buff *skb;
  537. int i;
  538. for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
  539. if (reg->pfu_enabled) {
  540. desc2 = card->rxbd_ring[i];
  541. if (card->rx_buf_list[i]) {
  542. skb = card->rx_buf_list[i];
  543. mwifiex_unmap_pci_memory(adapter, skb,
  544. PCI_DMA_FROMDEVICE);
  545. dev_kfree_skb_any(skb);
  546. }
  547. memset(desc2, 0, sizeof(*desc2));
  548. } else {
  549. desc = card->rxbd_ring[i];
  550. if (card->rx_buf_list[i]) {
  551. skb = card->rx_buf_list[i];
  552. mwifiex_unmap_pci_memory(adapter, skb,
  553. PCI_DMA_FROMDEVICE);
  554. dev_kfree_skb_any(skb);
  555. }
  556. memset(desc, 0, sizeof(*desc));
  557. }
  558. card->rx_buf_list[i] = NULL;
  559. }
  560. return;
  561. }
  562. /* This function cleans up event buffer rings. If any of the buffer list has
  563. * valid SKB address, associated SKB is freed.
  564. */
  565. static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
  566. {
  567. struct pcie_service_card *card = adapter->card;
  568. struct mwifiex_evt_buf_desc *desc;
  569. struct sk_buff *skb;
  570. int i;
  571. for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
  572. desc = card->evtbd_ring[i];
  573. if (card->evt_buf_list[i]) {
  574. skb = card->evt_buf_list[i];
  575. mwifiex_unmap_pci_memory(adapter, skb,
  576. PCI_DMA_FROMDEVICE);
  577. dev_kfree_skb_any(skb);
  578. }
  579. card->evt_buf_list[i] = NULL;
  580. memset(desc, 0, sizeof(*desc));
  581. }
  582. return;
  583. }
  584. /* This function creates buffer descriptor ring for TX
  585. */
  586. static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
  587. {
  588. struct pcie_service_card *card = adapter->card;
  589. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  590. /*
  591. * driver maintaines the write pointer and firmware maintaines the read
  592. * pointer. The write pointer starts at 0 (zero) while the read pointer
  593. * starts at zero with rollover bit set
  594. */
  595. card->txbd_wrptr = 0;
  596. if (reg->pfu_enabled)
  597. card->txbd_rdptr = 0;
  598. else
  599. card->txbd_rdptr |= reg->tx_rollover_ind;
  600. /* allocate shared memory for the BD ring and divide the same in to
  601. several descriptors */
  602. if (reg->pfu_enabled)
  603. card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
  604. MWIFIEX_MAX_TXRX_BD;
  605. else
  606. card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
  607. MWIFIEX_MAX_TXRX_BD;
  608. dev_dbg(adapter->dev, "info: txbd_ring: Allocating %d bytes\n",
  609. card->txbd_ring_size);
  610. card->txbd_ring_vbase = pci_alloc_consistent(card->dev,
  611. card->txbd_ring_size,
  612. &card->txbd_ring_pbase);
  613. if (!card->txbd_ring_vbase) {
  614. dev_err(adapter->dev,
  615. "allocate consistent memory (%d bytes) failed!\n",
  616. card->txbd_ring_size);
  617. return -ENOMEM;
  618. }
  619. dev_dbg(adapter->dev,
  620. "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n",
  621. card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase,
  622. (u32)((u64)card->txbd_ring_pbase >> 32), card->txbd_ring_size);
  623. return mwifiex_init_txq_ring(adapter);
  624. }
  625. static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
  626. {
  627. struct pcie_service_card *card = adapter->card;
  628. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  629. mwifiex_cleanup_txq_ring(adapter);
  630. if (card->txbd_ring_vbase)
  631. pci_free_consistent(card->dev, card->txbd_ring_size,
  632. card->txbd_ring_vbase,
  633. card->txbd_ring_pbase);
  634. card->txbd_ring_size = 0;
  635. card->txbd_wrptr = 0;
  636. card->txbd_rdptr = 0 | reg->tx_rollover_ind;
  637. card->txbd_ring_vbase = NULL;
  638. card->txbd_ring_pbase = 0;
  639. return 0;
  640. }
  641. /*
  642. * This function creates buffer descriptor ring for RX
  643. */
  644. static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
  645. {
  646. struct pcie_service_card *card = adapter->card;
  647. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  648. /*
  649. * driver maintaines the read pointer and firmware maintaines the write
  650. * pointer. The write pointer starts at 0 (zero) while the read pointer
  651. * starts at zero with rollover bit set
  652. */
  653. card->rxbd_wrptr = 0;
  654. card->rxbd_rdptr = reg->rx_rollover_ind;
  655. if (reg->pfu_enabled)
  656. card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
  657. MWIFIEX_MAX_TXRX_BD;
  658. else
  659. card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
  660. MWIFIEX_MAX_TXRX_BD;
  661. dev_dbg(adapter->dev, "info: rxbd_ring: Allocating %d bytes\n",
  662. card->rxbd_ring_size);
  663. card->rxbd_ring_vbase = pci_alloc_consistent(card->dev,
  664. card->rxbd_ring_size,
  665. &card->rxbd_ring_pbase);
  666. if (!card->rxbd_ring_vbase) {
  667. dev_err(adapter->dev,
  668. "allocate consistent memory (%d bytes) failed!\n",
  669. card->rxbd_ring_size);
  670. return -ENOMEM;
  671. }
  672. dev_dbg(adapter->dev,
  673. "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
  674. card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
  675. (u32)((u64)card->rxbd_ring_pbase >> 32),
  676. card->rxbd_ring_size);
  677. return mwifiex_init_rxq_ring(adapter);
  678. }
  679. /*
  680. * This function deletes Buffer descriptor ring for RX
  681. */
  682. static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
  683. {
  684. struct pcie_service_card *card = adapter->card;
  685. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  686. mwifiex_cleanup_rxq_ring(adapter);
  687. if (card->rxbd_ring_vbase)
  688. pci_free_consistent(card->dev, card->rxbd_ring_size,
  689. card->rxbd_ring_vbase,
  690. card->rxbd_ring_pbase);
  691. card->rxbd_ring_size = 0;
  692. card->rxbd_wrptr = 0;
  693. card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
  694. card->rxbd_ring_vbase = NULL;
  695. card->rxbd_ring_pbase = 0;
  696. return 0;
  697. }
  698. /*
  699. * This function creates buffer descriptor ring for Events
  700. */
  701. static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
  702. {
  703. struct pcie_service_card *card = adapter->card;
  704. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  705. /*
  706. * driver maintaines the read pointer and firmware maintaines the write
  707. * pointer. The write pointer starts at 0 (zero) while the read pointer
  708. * starts at zero with rollover bit set
  709. */
  710. card->evtbd_wrptr = 0;
  711. card->evtbd_rdptr = reg->evt_rollover_ind;
  712. card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
  713. MWIFIEX_MAX_EVT_BD;
  714. dev_dbg(adapter->dev, "info: evtbd_ring: Allocating %d bytes\n",
  715. card->evtbd_ring_size);
  716. card->evtbd_ring_vbase = pci_alloc_consistent(card->dev,
  717. card->evtbd_ring_size,
  718. &card->evtbd_ring_pbase);
  719. if (!card->evtbd_ring_vbase) {
  720. dev_err(adapter->dev,
  721. "allocate consistent memory (%d bytes) failed!\n",
  722. card->evtbd_ring_size);
  723. return -ENOMEM;
  724. }
  725. dev_dbg(adapter->dev,
  726. "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
  727. card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
  728. (u32)((u64)card->evtbd_ring_pbase >> 32),
  729. card->evtbd_ring_size);
  730. return mwifiex_pcie_init_evt_ring(adapter);
  731. }
  732. /*
  733. * This function deletes Buffer descriptor ring for Events
  734. */
  735. static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
  736. {
  737. struct pcie_service_card *card = adapter->card;
  738. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  739. mwifiex_cleanup_evt_ring(adapter);
  740. if (card->evtbd_ring_vbase)
  741. pci_free_consistent(card->dev, card->evtbd_ring_size,
  742. card->evtbd_ring_vbase,
  743. card->evtbd_ring_pbase);
  744. card->evtbd_wrptr = 0;
  745. card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
  746. card->evtbd_ring_size = 0;
  747. card->evtbd_ring_vbase = NULL;
  748. card->evtbd_ring_pbase = 0;
  749. return 0;
  750. }
  751. /*
  752. * This function allocates a buffer for CMDRSP
  753. */
  754. static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
  755. {
  756. struct pcie_service_card *card = adapter->card;
  757. struct sk_buff *skb;
  758. /* Allocate memory for receiving command response data */
  759. skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
  760. if (!skb) {
  761. dev_err(adapter->dev,
  762. "Unable to allocate skb for command response data.\n");
  763. return -ENOMEM;
  764. }
  765. skb_put(skb, MWIFIEX_UPLD_SIZE);
  766. if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
  767. PCI_DMA_FROMDEVICE))
  768. return -1;
  769. card->cmdrsp_buf = skb;
  770. return 0;
  771. }
  772. /*
  773. * This function deletes a buffer for CMDRSP
  774. */
  775. static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
  776. {
  777. struct pcie_service_card *card;
  778. if (!adapter)
  779. return 0;
  780. card = adapter->card;
  781. if (card && card->cmdrsp_buf) {
  782. mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
  783. PCI_DMA_FROMDEVICE);
  784. dev_kfree_skb_any(card->cmdrsp_buf);
  785. }
  786. if (card && card->cmd_buf) {
  787. mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
  788. PCI_DMA_TODEVICE);
  789. }
  790. return 0;
  791. }
  792. /*
  793. * This function allocates a buffer for sleep cookie
  794. */
  795. static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
  796. {
  797. struct pcie_service_card *card = adapter->card;
  798. card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32),
  799. &card->sleep_cookie_pbase);
  800. if (!card->sleep_cookie_vbase) {
  801. dev_err(adapter->dev, "pci_alloc_consistent failed!\n");
  802. return -ENOMEM;
  803. }
  804. /* Init val of Sleep Cookie */
  805. *(u32 *)card->sleep_cookie_vbase = FW_AWAKE_COOKIE;
  806. dev_dbg(adapter->dev, "alloc_scook: sleep cookie=0x%x\n",
  807. *((u32 *)card->sleep_cookie_vbase));
  808. return 0;
  809. }
  810. /*
  811. * This function deletes buffer for sleep cookie
  812. */
  813. static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
  814. {
  815. struct pcie_service_card *card;
  816. if (!adapter)
  817. return 0;
  818. card = adapter->card;
  819. if (card && card->sleep_cookie_vbase) {
  820. pci_free_consistent(card->dev, sizeof(u32),
  821. card->sleep_cookie_vbase,
  822. card->sleep_cookie_pbase);
  823. card->sleep_cookie_vbase = NULL;
  824. }
  825. return 0;
  826. }
  827. /* This function flushes the TX buffer descriptor ring
  828. * This function defined as handler is also called while cleaning TXRX
  829. * during disconnect/ bss stop.
  830. */
  831. static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
  832. {
  833. struct pcie_service_card *card = adapter->card;
  834. if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
  835. card->txbd_flush = 1;
  836. /* write pointer already set at last send
  837. * send dnld-rdy intr again, wait for completion.
  838. */
  839. if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
  840. CPU_INTR_DNLD_RDY)) {
  841. dev_err(adapter->dev,
  842. "failed to assert dnld-rdy interrupt.\n");
  843. return -1;
  844. }
  845. }
  846. return 0;
  847. }
  848. /*
  849. * This function unmaps and frees downloaded data buffer
  850. */
  851. static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
  852. {
  853. struct sk_buff *skb;
  854. u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
  855. struct mwifiex_pcie_buf_desc *desc;
  856. struct mwifiex_pfu_buf_desc *desc2;
  857. struct pcie_service_card *card = adapter->card;
  858. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  859. if (!mwifiex_pcie_ok_to_access_hw(adapter))
  860. mwifiex_pm_wakeup_card(adapter);
  861. /* Read the TX ring read pointer set by firmware */
  862. if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
  863. dev_err(adapter->dev,
  864. "SEND COMP: failed to read reg->tx_rdptr\n");
  865. return -1;
  866. }
  867. dev_dbg(adapter->dev, "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
  868. card->txbd_rdptr, rdptr);
  869. num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
  870. /* free from previous txbd_rdptr to current txbd_rdptr */
  871. while (((card->txbd_rdptr & reg->tx_mask) !=
  872. (rdptr & reg->tx_mask)) ||
  873. ((card->txbd_rdptr & reg->tx_rollover_ind) !=
  874. (rdptr & reg->tx_rollover_ind))) {
  875. wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
  876. reg->tx_start_ptr;
  877. skb = card->tx_buf_list[wrdoneidx];
  878. if (skb) {
  879. dev_dbg(adapter->dev,
  880. "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
  881. skb, wrdoneidx);
  882. mwifiex_unmap_pci_memory(adapter, skb,
  883. PCI_DMA_TODEVICE);
  884. unmap_count++;
  885. if (card->txbd_flush)
  886. mwifiex_write_data_complete(adapter, skb, 0,
  887. -1);
  888. else
  889. mwifiex_write_data_complete(adapter, skb, 0, 0);
  890. }
  891. card->tx_buf_list[wrdoneidx] = NULL;
  892. if (reg->pfu_enabled) {
  893. desc2 = card->txbd_ring[wrdoneidx];
  894. memset(desc2, 0, sizeof(*desc2));
  895. } else {
  896. desc = card->txbd_ring[wrdoneidx];
  897. memset(desc, 0, sizeof(*desc));
  898. }
  899. switch (card->dev->device) {
  900. case PCIE_DEVICE_ID_MARVELL_88W8766P:
  901. card->txbd_rdptr++;
  902. break;
  903. case PCIE_DEVICE_ID_MARVELL_88W8897:
  904. card->txbd_rdptr += reg->ring_tx_start_ptr;
  905. break;
  906. }
  907. if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
  908. card->txbd_rdptr = ((card->txbd_rdptr &
  909. reg->tx_rollover_ind) ^
  910. reg->tx_rollover_ind);
  911. }
  912. if (unmap_count)
  913. adapter->data_sent = false;
  914. if (card->txbd_flush) {
  915. if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
  916. card->txbd_flush = 0;
  917. else
  918. mwifiex_clean_pcie_ring_buf(adapter);
  919. }
  920. return 0;
  921. }
  922. /* This function sends data buffer to device. First 4 bytes of payload
  923. * are filled with payload length and payload type. Then this payload
  924. * is mapped to PCI device memory. Tx ring pointers are advanced accordingly.
  925. * Download ready interrupt to FW is deffered if Tx ring is not full and
  926. * additional payload can be accomodated.
  927. * Caller must ensure tx_param parameter to this function is not NULL.
  928. */
  929. static int
  930. mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
  931. struct mwifiex_tx_param *tx_param)
  932. {
  933. struct pcie_service_card *card = adapter->card;
  934. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  935. u32 wrindx, num_tx_buffs, rx_val;
  936. int ret;
  937. dma_addr_t buf_pa;
  938. struct mwifiex_pcie_buf_desc *desc = NULL;
  939. struct mwifiex_pfu_buf_desc *desc2 = NULL;
  940. __le16 *tmp;
  941. if (!(skb->data && skb->len)) {
  942. dev_err(adapter->dev, "%s(): invalid parameter <%p, %#x>\n",
  943. __func__, skb->data, skb->len);
  944. return -1;
  945. }
  946. if (!mwifiex_pcie_ok_to_access_hw(adapter))
  947. mwifiex_pm_wakeup_card(adapter);
  948. num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
  949. dev_dbg(adapter->dev, "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
  950. card->txbd_rdptr, card->txbd_wrptr);
  951. if (mwifiex_pcie_txbd_not_full(card)) {
  952. u8 *payload;
  953. adapter->data_sent = true;
  954. payload = skb->data;
  955. tmp = (__le16 *)&payload[0];
  956. *tmp = cpu_to_le16((u16)skb->len);
  957. tmp = (__le16 *)&payload[2];
  958. *tmp = cpu_to_le16(MWIFIEX_TYPE_DATA);
  959. if (mwifiex_map_pci_memory(adapter, skb, skb->len,
  960. PCI_DMA_TODEVICE))
  961. return -1;
  962. wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
  963. buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
  964. card->tx_buf_list[wrindx] = skb;
  965. if (reg->pfu_enabled) {
  966. desc2 = card->txbd_ring[wrindx];
  967. desc2->paddr = buf_pa;
  968. desc2->len = (u16)skb->len;
  969. desc2->frag_len = (u16)skb->len;
  970. desc2->offset = 0;
  971. desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
  972. MWIFIEX_BD_FLAG_LAST_DESC;
  973. } else {
  974. desc = card->txbd_ring[wrindx];
  975. desc->paddr = buf_pa;
  976. desc->len = (u16)skb->len;
  977. desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
  978. MWIFIEX_BD_FLAG_LAST_DESC;
  979. }
  980. switch (card->dev->device) {
  981. case PCIE_DEVICE_ID_MARVELL_88W8766P:
  982. card->txbd_wrptr++;
  983. break;
  984. case PCIE_DEVICE_ID_MARVELL_88W8897:
  985. card->txbd_wrptr += reg->ring_tx_start_ptr;
  986. break;
  987. }
  988. if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
  989. card->txbd_wrptr = ((card->txbd_wrptr &
  990. reg->tx_rollover_ind) ^
  991. reg->tx_rollover_ind);
  992. rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
  993. /* Write the TX ring write pointer in to reg->tx_wrptr */
  994. if (mwifiex_write_reg(adapter, reg->tx_wrptr,
  995. card->txbd_wrptr | rx_val)) {
  996. dev_err(adapter->dev,
  997. "SEND DATA: failed to write reg->tx_wrptr\n");
  998. ret = -1;
  999. goto done_unmap;
  1000. }
  1001. if ((mwifiex_pcie_txbd_not_full(card)) &&
  1002. tx_param->next_pkt_len) {
  1003. /* have more packets and TxBD still can hold more */
  1004. dev_dbg(adapter->dev,
  1005. "SEND DATA: delay dnld-rdy interrupt.\n");
  1006. adapter->data_sent = false;
  1007. } else {
  1008. /* Send the TX ready interrupt */
  1009. if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
  1010. CPU_INTR_DNLD_RDY)) {
  1011. dev_err(adapter->dev,
  1012. "SEND DATA: failed to assert dnld-rdy interrupt.\n");
  1013. ret = -1;
  1014. goto done_unmap;
  1015. }
  1016. }
  1017. dev_dbg(adapter->dev, "info: SEND DATA: Updated <Rd: %#x, Wr: "
  1018. "%#x> and sent packet to firmware successfully\n",
  1019. card->txbd_rdptr, card->txbd_wrptr);
  1020. } else {
  1021. dev_dbg(adapter->dev,
  1022. "info: TX Ring full, can't send packets to fw\n");
  1023. adapter->data_sent = true;
  1024. /* Send the TX ready interrupt */
  1025. if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
  1026. CPU_INTR_DNLD_RDY))
  1027. dev_err(adapter->dev,
  1028. "SEND DATA: failed to assert door-bell intr\n");
  1029. return -EBUSY;
  1030. }
  1031. return -EINPROGRESS;
  1032. done_unmap:
  1033. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
  1034. card->tx_buf_list[wrindx] = NULL;
  1035. if (reg->pfu_enabled)
  1036. memset(desc2, 0, sizeof(*desc2));
  1037. else
  1038. memset(desc, 0, sizeof(*desc));
  1039. return ret;
  1040. }
  1041. /*
  1042. * This function handles received buffer ring and
  1043. * dispatches packets to upper
  1044. */
  1045. static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
  1046. {
  1047. struct pcie_service_card *card = adapter->card;
  1048. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1049. u32 wrptr, rd_index, tx_val;
  1050. dma_addr_t buf_pa;
  1051. int ret = 0;
  1052. struct sk_buff *skb_tmp = NULL;
  1053. struct mwifiex_pcie_buf_desc *desc;
  1054. struct mwifiex_pfu_buf_desc *desc2;
  1055. if (!mwifiex_pcie_ok_to_access_hw(adapter))
  1056. mwifiex_pm_wakeup_card(adapter);
  1057. /* Read the RX ring Write pointer set by firmware */
  1058. if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
  1059. dev_err(adapter->dev,
  1060. "RECV DATA: failed to read reg->rx_wrptr\n");
  1061. ret = -1;
  1062. goto done;
  1063. }
  1064. card->rxbd_wrptr = wrptr;
  1065. while (((wrptr & reg->rx_mask) !=
  1066. (card->rxbd_rdptr & reg->rx_mask)) ||
  1067. ((wrptr & reg->rx_rollover_ind) ==
  1068. (card->rxbd_rdptr & reg->rx_rollover_ind))) {
  1069. struct sk_buff *skb_data;
  1070. u16 rx_len;
  1071. __le16 pkt_len;
  1072. rd_index = card->rxbd_rdptr & reg->rx_mask;
  1073. skb_data = card->rx_buf_list[rd_index];
  1074. /* If skb allocation was failed earlier for Rx packet,
  1075. * rx_buf_list[rd_index] would have been left with a NULL.
  1076. */
  1077. if (!skb_data)
  1078. return -ENOMEM;
  1079. mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE);
  1080. card->rx_buf_list[rd_index] = NULL;
  1081. /* Get data length from interface header -
  1082. * first 2 bytes for len, next 2 bytes is for type
  1083. */
  1084. pkt_len = *((__le16 *)skb_data->data);
  1085. rx_len = le16_to_cpu(pkt_len);
  1086. if (WARN_ON(rx_len <= INTF_HEADER_LEN ||
  1087. rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
  1088. dev_err(adapter->dev,
  1089. "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
  1090. rx_len, card->rxbd_rdptr, wrptr);
  1091. dev_kfree_skb_any(skb_data);
  1092. } else {
  1093. skb_put(skb_data, rx_len);
  1094. dev_dbg(adapter->dev,
  1095. "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
  1096. card->rxbd_rdptr, wrptr, rx_len);
  1097. skb_pull(skb_data, INTF_HEADER_LEN);
  1098. if (adapter->rx_work_enabled) {
  1099. skb_queue_tail(&adapter->rx_data_q, skb_data);
  1100. adapter->data_received = true;
  1101. atomic_inc(&adapter->rx_pending);
  1102. } else {
  1103. mwifiex_handle_rx_packet(adapter, skb_data);
  1104. }
  1105. }
  1106. skb_tmp = dev_alloc_skb(MWIFIEX_RX_DATA_BUF_SIZE);
  1107. if (!skb_tmp) {
  1108. dev_err(adapter->dev,
  1109. "Unable to allocate skb.\n");
  1110. return -ENOMEM;
  1111. }
  1112. if (mwifiex_map_pci_memory(adapter, skb_tmp,
  1113. MWIFIEX_RX_DATA_BUF_SIZE,
  1114. PCI_DMA_FROMDEVICE))
  1115. return -1;
  1116. buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
  1117. dev_dbg(adapter->dev,
  1118. "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
  1119. skb_tmp, rd_index);
  1120. card->rx_buf_list[rd_index] = skb_tmp;
  1121. if (reg->pfu_enabled) {
  1122. desc2 = card->rxbd_ring[rd_index];
  1123. desc2->paddr = buf_pa;
  1124. desc2->len = skb_tmp->len;
  1125. desc2->frag_len = skb_tmp->len;
  1126. desc2->offset = 0;
  1127. desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
  1128. } else {
  1129. desc = card->rxbd_ring[rd_index];
  1130. desc->paddr = buf_pa;
  1131. desc->len = skb_tmp->len;
  1132. desc->flags = 0;
  1133. }
  1134. if ((++card->rxbd_rdptr & reg->rx_mask) ==
  1135. MWIFIEX_MAX_TXRX_BD) {
  1136. card->rxbd_rdptr = ((card->rxbd_rdptr &
  1137. reg->rx_rollover_ind) ^
  1138. reg->rx_rollover_ind);
  1139. }
  1140. dev_dbg(adapter->dev, "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
  1141. card->rxbd_rdptr, wrptr);
  1142. tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
  1143. /* Write the RX ring read pointer in to reg->rx_rdptr */
  1144. if (mwifiex_write_reg(adapter, reg->rx_rdptr,
  1145. card->rxbd_rdptr | tx_val)) {
  1146. dev_err(adapter->dev,
  1147. "RECV DATA: failed to write reg->rx_rdptr\n");
  1148. ret = -1;
  1149. goto done;
  1150. }
  1151. /* Read the RX ring Write pointer set by firmware */
  1152. if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
  1153. dev_err(adapter->dev,
  1154. "RECV DATA: failed to read reg->rx_wrptr\n");
  1155. ret = -1;
  1156. goto done;
  1157. }
  1158. dev_dbg(adapter->dev,
  1159. "info: RECV DATA: Rcvd packet from fw successfully\n");
  1160. card->rxbd_wrptr = wrptr;
  1161. }
  1162. done:
  1163. return ret;
  1164. }
  1165. /*
  1166. * This function downloads the boot command to device
  1167. */
  1168. static int
  1169. mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
  1170. {
  1171. dma_addr_t buf_pa;
  1172. struct pcie_service_card *card = adapter->card;
  1173. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1174. if (!(skb->data && skb->len)) {
  1175. dev_err(adapter->dev,
  1176. "Invalid parameter in %s <%p. len %d>\n",
  1177. __func__, skb->data, skb->len);
  1178. return -1;
  1179. }
  1180. if (mwifiex_map_pci_memory(adapter, skb, skb->len , PCI_DMA_TODEVICE))
  1181. return -1;
  1182. buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
  1183. /* Write the lower 32bits of the physical address to low command
  1184. * address scratch register
  1185. */
  1186. if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
  1187. dev_err(adapter->dev,
  1188. "%s: failed to write download command to boot code.\n",
  1189. __func__);
  1190. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
  1191. return -1;
  1192. }
  1193. /* Write the upper 32bits of the physical address to high command
  1194. * address scratch register
  1195. */
  1196. if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
  1197. (u32)((u64)buf_pa >> 32))) {
  1198. dev_err(adapter->dev,
  1199. "%s: failed to write download command to boot code.\n",
  1200. __func__);
  1201. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
  1202. return -1;
  1203. }
  1204. /* Write the command length to cmd_size scratch register */
  1205. if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
  1206. dev_err(adapter->dev,
  1207. "%s: failed to write command len to cmd_size scratch reg\n",
  1208. __func__);
  1209. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
  1210. return -1;
  1211. }
  1212. /* Ring the door bell */
  1213. if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
  1214. CPU_INTR_DOOR_BELL)) {
  1215. dev_err(adapter->dev,
  1216. "%s: failed to assert door-bell intr\n", __func__);
  1217. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
  1218. return -1;
  1219. }
  1220. return 0;
  1221. }
  1222. /* This function init rx port in firmware which in turn enables to receive data
  1223. * from device before transmitting any packet.
  1224. */
  1225. static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
  1226. {
  1227. struct pcie_service_card *card = adapter->card;
  1228. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1229. int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
  1230. /* Write the RX ring read pointer in to reg->rx_rdptr */
  1231. if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
  1232. tx_wrap)) {
  1233. dev_err(adapter->dev,
  1234. "RECV DATA: failed to write reg->rx_rdptr\n");
  1235. return -1;
  1236. }
  1237. return 0;
  1238. }
  1239. /* This function downloads commands to the device
  1240. */
  1241. static int
  1242. mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
  1243. {
  1244. struct pcie_service_card *card = adapter->card;
  1245. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1246. int ret = 0;
  1247. dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
  1248. u8 *payload = (u8 *)skb->data;
  1249. if (!(skb->data && skb->len)) {
  1250. dev_err(adapter->dev, "Invalid parameter in %s <%p, %#x>\n",
  1251. __func__, skb->data, skb->len);
  1252. return -1;
  1253. }
  1254. /* Make sure a command response buffer is available */
  1255. if (!card->cmdrsp_buf) {
  1256. dev_err(adapter->dev,
  1257. "No response buffer available, send command failed\n");
  1258. return -EBUSY;
  1259. }
  1260. if (!mwifiex_pcie_ok_to_access_hw(adapter))
  1261. mwifiex_pm_wakeup_card(adapter);
  1262. adapter->cmd_sent = true;
  1263. *(__le16 *)&payload[0] = cpu_to_le16((u16)skb->len);
  1264. *(__le16 *)&payload[2] = cpu_to_le16(MWIFIEX_TYPE_CMD);
  1265. if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
  1266. return -1;
  1267. card->cmd_buf = skb;
  1268. /* To send a command, the driver will:
  1269. 1. Write the 64bit physical address of the data buffer to
  1270. cmd response address low + cmd response address high
  1271. 2. Ring the door bell (i.e. set the door bell interrupt)
  1272. In response to door bell interrupt, the firmware will perform
  1273. the DMA of the command packet (first header to obtain the total
  1274. length and then rest of the command).
  1275. */
  1276. if (card->cmdrsp_buf) {
  1277. cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
  1278. /* Write the lower 32bits of the cmdrsp buffer physical
  1279. address */
  1280. if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
  1281. (u32)cmdrsp_buf_pa)) {
  1282. dev_err(adapter->dev,
  1283. "Failed to write download cmd to boot code.\n");
  1284. ret = -1;
  1285. goto done;
  1286. }
  1287. /* Write the upper 32bits of the cmdrsp buffer physical
  1288. address */
  1289. if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
  1290. (u32)((u64)cmdrsp_buf_pa >> 32))) {
  1291. dev_err(adapter->dev,
  1292. "Failed to write download cmd to boot code.\n");
  1293. ret = -1;
  1294. goto done;
  1295. }
  1296. }
  1297. cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
  1298. /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */
  1299. if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
  1300. (u32)cmd_buf_pa)) {
  1301. dev_err(adapter->dev,
  1302. "Failed to write download cmd to boot code.\n");
  1303. ret = -1;
  1304. goto done;
  1305. }
  1306. /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */
  1307. if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
  1308. (u32)((u64)cmd_buf_pa >> 32))) {
  1309. dev_err(adapter->dev,
  1310. "Failed to write download cmd to boot code.\n");
  1311. ret = -1;
  1312. goto done;
  1313. }
  1314. /* Write the command length to reg->cmd_size */
  1315. if (mwifiex_write_reg(adapter, reg->cmd_size,
  1316. card->cmd_buf->len)) {
  1317. dev_err(adapter->dev,
  1318. "Failed to write cmd len to reg->cmd_size\n");
  1319. ret = -1;
  1320. goto done;
  1321. }
  1322. /* Ring the door bell */
  1323. if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
  1324. CPU_INTR_DOOR_BELL)) {
  1325. dev_err(adapter->dev,
  1326. "Failed to assert door-bell intr\n");
  1327. ret = -1;
  1328. goto done;
  1329. }
  1330. done:
  1331. if (ret)
  1332. adapter->cmd_sent = false;
  1333. return 0;
  1334. }
  1335. /*
  1336. * This function handles command complete interrupt
  1337. */
  1338. static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
  1339. {
  1340. struct pcie_service_card *card = adapter->card;
  1341. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1342. struct sk_buff *skb = card->cmdrsp_buf;
  1343. int count = 0;
  1344. u16 rx_len;
  1345. __le16 pkt_len;
  1346. dev_dbg(adapter->dev, "info: Rx CMD Response\n");
  1347. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE);
  1348. /* Unmap the command as a response has been received. */
  1349. if (card->cmd_buf) {
  1350. mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
  1351. PCI_DMA_TODEVICE);
  1352. card->cmd_buf = NULL;
  1353. }
  1354. pkt_len = *((__le16 *)skb->data);
  1355. rx_len = le16_to_cpu(pkt_len);
  1356. skb_trim(skb, rx_len);
  1357. skb_pull(skb, INTF_HEADER_LEN);
  1358. if (!adapter->curr_cmd) {
  1359. if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
  1360. mwifiex_process_sleep_confirm_resp(adapter, skb->data,
  1361. skb->len);
  1362. mwifiex_pcie_enable_host_int(adapter);
  1363. if (mwifiex_write_reg(adapter,
  1364. PCIE_CPU_INT_EVENT,
  1365. CPU_INTR_SLEEP_CFM_DONE)) {
  1366. dev_warn(adapter->dev,
  1367. "Write register failed\n");
  1368. return -1;
  1369. }
  1370. mwifiex_delay_for_sleep_cookie(adapter,
  1371. MWIFIEX_MAX_DELAY_COUNT);
  1372. while (reg->sleep_cookie && (count++ < 10) &&
  1373. mwifiex_pcie_ok_to_access_hw(adapter))
  1374. usleep_range(50, 60);
  1375. } else {
  1376. dev_err(adapter->dev,
  1377. "There is no command but got cmdrsp\n");
  1378. }
  1379. memcpy(adapter->upld_buf, skb->data,
  1380. min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
  1381. skb_push(skb, INTF_HEADER_LEN);
  1382. if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
  1383. PCI_DMA_FROMDEVICE))
  1384. return -1;
  1385. } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
  1386. adapter->curr_cmd->resp_skb = skb;
  1387. adapter->cmd_resp_received = true;
  1388. /* Take the pointer and set it to CMD node and will
  1389. return in the response complete callback */
  1390. card->cmdrsp_buf = NULL;
  1391. /* Clear the cmd-rsp buffer address in scratch registers. This
  1392. will prevent firmware from writing to the same response
  1393. buffer again. */
  1394. if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
  1395. dev_err(adapter->dev,
  1396. "cmd_done: failed to clear cmd_rsp_addr_lo\n");
  1397. return -1;
  1398. }
  1399. /* Write the upper 32bits of the cmdrsp buffer physical
  1400. address */
  1401. if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
  1402. dev_err(adapter->dev,
  1403. "cmd_done: failed to clear cmd_rsp_addr_hi\n");
  1404. return -1;
  1405. }
  1406. }
  1407. return 0;
  1408. }
  1409. /*
  1410. * Command Response processing complete handler
  1411. */
  1412. static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
  1413. struct sk_buff *skb)
  1414. {
  1415. struct pcie_service_card *card = adapter->card;
  1416. if (skb) {
  1417. card->cmdrsp_buf = skb;
  1418. skb_push(card->cmdrsp_buf, INTF_HEADER_LEN);
  1419. if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
  1420. PCI_DMA_FROMDEVICE))
  1421. return -1;
  1422. }
  1423. return 0;
  1424. }
  1425. /*
  1426. * This function handles firmware event ready interrupt
  1427. */
  1428. static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
  1429. {
  1430. struct pcie_service_card *card = adapter->card;
  1431. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1432. u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
  1433. u32 wrptr, event;
  1434. struct mwifiex_evt_buf_desc *desc;
  1435. if (!mwifiex_pcie_ok_to_access_hw(adapter))
  1436. mwifiex_pm_wakeup_card(adapter);
  1437. if (adapter->event_received) {
  1438. dev_dbg(adapter->dev, "info: Event being processed, "
  1439. "do not process this interrupt just yet\n");
  1440. return 0;
  1441. }
  1442. if (rdptr >= MWIFIEX_MAX_EVT_BD) {
  1443. dev_dbg(adapter->dev, "info: Invalid read pointer...\n");
  1444. return -1;
  1445. }
  1446. /* Read the event ring write pointer set by firmware */
  1447. if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
  1448. dev_err(adapter->dev,
  1449. "EventReady: failed to read reg->evt_wrptr\n");
  1450. return -1;
  1451. }
  1452. dev_dbg(adapter->dev, "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
  1453. card->evtbd_rdptr, wrptr);
  1454. if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
  1455. & MWIFIEX_EVTBD_MASK)) ||
  1456. ((wrptr & reg->evt_rollover_ind) ==
  1457. (card->evtbd_rdptr & reg->evt_rollover_ind))) {
  1458. struct sk_buff *skb_cmd;
  1459. __le16 data_len = 0;
  1460. u16 evt_len;
  1461. dev_dbg(adapter->dev, "info: Read Index: %d\n", rdptr);
  1462. skb_cmd = card->evt_buf_list[rdptr];
  1463. mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE);
  1464. /* Take the pointer and set it to event pointer in adapter
  1465. and will return back after event handling callback */
  1466. card->evt_buf_list[rdptr] = NULL;
  1467. desc = card->evtbd_ring[rdptr];
  1468. memset(desc, 0, sizeof(*desc));
  1469. event = *(u32 *) &skb_cmd->data[INTF_HEADER_LEN];
  1470. adapter->event_cause = event;
  1471. /* The first 4bytes will be the event transfer header
  1472. len is 2 bytes followed by type which is 2 bytes */
  1473. memcpy(&data_len, skb_cmd->data, sizeof(__le16));
  1474. evt_len = le16_to_cpu(data_len);
  1475. skb_pull(skb_cmd, INTF_HEADER_LEN);
  1476. dev_dbg(adapter->dev, "info: Event length: %d\n", evt_len);
  1477. if ((evt_len > 0) && (evt_len < MAX_EVENT_SIZE))
  1478. memcpy(adapter->event_body, skb_cmd->data +
  1479. MWIFIEX_EVENT_HEADER_LEN, evt_len -
  1480. MWIFIEX_EVENT_HEADER_LEN);
  1481. adapter->event_received = true;
  1482. adapter->event_skb = skb_cmd;
  1483. /* Do not update the event read pointer here, wait till the
  1484. buffer is released. This is just to make things simpler,
  1485. we need to find a better method of managing these buffers.
  1486. */
  1487. } else {
  1488. if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
  1489. CPU_INTR_EVENT_DONE)) {
  1490. dev_warn(adapter->dev,
  1491. "Write register failed\n");
  1492. return -1;
  1493. }
  1494. }
  1495. return 0;
  1496. }
  1497. /*
  1498. * Event processing complete handler
  1499. */
  1500. static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
  1501. struct sk_buff *skb)
  1502. {
  1503. struct pcie_service_card *card = adapter->card;
  1504. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1505. int ret = 0;
  1506. u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
  1507. u32 wrptr;
  1508. struct mwifiex_evt_buf_desc *desc;
  1509. if (!skb)
  1510. return 0;
  1511. if (rdptr >= MWIFIEX_MAX_EVT_BD) {
  1512. dev_err(adapter->dev, "event_complete: Invalid rdptr 0x%x\n",
  1513. rdptr);
  1514. return -EINVAL;
  1515. }
  1516. /* Read the event ring write pointer set by firmware */
  1517. if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
  1518. dev_err(adapter->dev,
  1519. "event_complete: failed to read reg->evt_wrptr\n");
  1520. return -1;
  1521. }
  1522. if (!card->evt_buf_list[rdptr]) {
  1523. skb_push(skb, INTF_HEADER_LEN);
  1524. if (mwifiex_map_pci_memory(adapter, skb,
  1525. MAX_EVENT_SIZE,
  1526. PCI_DMA_FROMDEVICE))
  1527. return -1;
  1528. card->evt_buf_list[rdptr] = skb;
  1529. desc = card->evtbd_ring[rdptr];
  1530. desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
  1531. desc->len = (u16)skb->len;
  1532. desc->flags = 0;
  1533. skb = NULL;
  1534. } else {
  1535. dev_dbg(adapter->dev,
  1536. "info: ERROR: buf still valid at index %d, <%p, %p>\n",
  1537. rdptr, card->evt_buf_list[rdptr], skb);
  1538. }
  1539. if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
  1540. card->evtbd_rdptr = ((card->evtbd_rdptr &
  1541. reg->evt_rollover_ind) ^
  1542. reg->evt_rollover_ind);
  1543. }
  1544. dev_dbg(adapter->dev, "info: Updated <Rd: 0x%x, Wr: 0x%x>",
  1545. card->evtbd_rdptr, wrptr);
  1546. /* Write the event ring read pointer in to reg->evt_rdptr */
  1547. if (mwifiex_write_reg(adapter, reg->evt_rdptr,
  1548. card->evtbd_rdptr)) {
  1549. dev_err(adapter->dev,
  1550. "event_complete: failed to read reg->evt_rdptr\n");
  1551. return -1;
  1552. }
  1553. dev_dbg(adapter->dev, "info: Check Events Again\n");
  1554. ret = mwifiex_pcie_process_event_ready(adapter);
  1555. return ret;
  1556. }
  1557. /*
  1558. * This function downloads the firmware to the card.
  1559. *
  1560. * Firmware is downloaded to the card in blocks. Every block download
  1561. * is tested for CRC errors, and retried a number of times before
  1562. * returning failure.
  1563. */
  1564. static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
  1565. struct mwifiex_fw_image *fw)
  1566. {
  1567. int ret;
  1568. u8 *firmware = fw->fw_buf;
  1569. u32 firmware_len = fw->fw_len;
  1570. u32 offset = 0;
  1571. struct sk_buff *skb;
  1572. u32 txlen, tx_blocks = 0, tries, len;
  1573. u32 block_retry_cnt = 0;
  1574. struct pcie_service_card *card = adapter->card;
  1575. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1576. if (!firmware || !firmware_len) {
  1577. dev_err(adapter->dev,
  1578. "No firmware image found! Terminating download\n");
  1579. return -1;
  1580. }
  1581. dev_dbg(adapter->dev, "info: Downloading FW image (%d bytes)\n",
  1582. firmware_len);
  1583. if (mwifiex_pcie_disable_host_int(adapter)) {
  1584. dev_err(adapter->dev,
  1585. "%s: Disabling interrupts failed.\n", __func__);
  1586. return -1;
  1587. }
  1588. skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
  1589. if (!skb) {
  1590. ret = -ENOMEM;
  1591. goto done;
  1592. }
  1593. /* Perform firmware data transfer */
  1594. do {
  1595. u32 ireg_intr = 0;
  1596. /* More data? */
  1597. if (offset >= firmware_len)
  1598. break;
  1599. for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
  1600. ret = mwifiex_read_reg(adapter, reg->cmd_size,
  1601. &len);
  1602. if (ret) {
  1603. dev_warn(adapter->dev,
  1604. "Failed reading len from boot code\n");
  1605. goto done;
  1606. }
  1607. if (len)
  1608. break;
  1609. usleep_range(10, 20);
  1610. }
  1611. if (!len) {
  1612. break;
  1613. } else if (len > MWIFIEX_UPLD_SIZE) {
  1614. pr_err("FW download failure @ %d, invalid length %d\n",
  1615. offset, len);
  1616. ret = -1;
  1617. goto done;
  1618. }
  1619. txlen = len;
  1620. if (len & BIT(0)) {
  1621. block_retry_cnt++;
  1622. if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
  1623. pr_err("FW download failure @ %d, over max "
  1624. "retry count\n", offset);
  1625. ret = -1;
  1626. goto done;
  1627. }
  1628. dev_err(adapter->dev, "FW CRC error indicated by the "
  1629. "helper: len = 0x%04X, txlen = %d\n",
  1630. len, txlen);
  1631. len &= ~BIT(0);
  1632. /* Setting this to 0 to resend from same offset */
  1633. txlen = 0;
  1634. } else {
  1635. block_retry_cnt = 0;
  1636. /* Set blocksize to transfer - checking for
  1637. last block */
  1638. if (firmware_len - offset < txlen)
  1639. txlen = firmware_len - offset;
  1640. dev_dbg(adapter->dev, ".");
  1641. tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
  1642. card->pcie.blksz_fw_dl;
  1643. /* Copy payload to buffer */
  1644. memmove(skb->data, &firmware[offset], txlen);
  1645. }
  1646. skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
  1647. skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
  1648. /* Send the boot command to device */
  1649. if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
  1650. dev_err(adapter->dev,
  1651. "Failed to send firmware download command\n");
  1652. ret = -1;
  1653. goto done;
  1654. }
  1655. /* Wait for the command done interrupt */
  1656. do {
  1657. if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
  1658. &ireg_intr)) {
  1659. dev_err(adapter->dev, "%s: Failed to read "
  1660. "interrupt status during fw dnld.\n",
  1661. __func__);
  1662. mwifiex_unmap_pci_memory(adapter, skb,
  1663. PCI_DMA_TODEVICE);
  1664. ret = -1;
  1665. goto done;
  1666. }
  1667. } while ((ireg_intr & CPU_INTR_DOOR_BELL) ==
  1668. CPU_INTR_DOOR_BELL);
  1669. mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
  1670. offset += txlen;
  1671. } while (true);
  1672. dev_dbg(adapter->dev, "info:\nFW download over, size %d bytes\n",
  1673. offset);
  1674. ret = 0;
  1675. done:
  1676. dev_kfree_skb_any(skb);
  1677. return ret;
  1678. }
  1679. /*
  1680. * This function checks the firmware status in card.
  1681. *
  1682. * The winner interface is also determined by this function.
  1683. */
  1684. static int
  1685. mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
  1686. {
  1687. int ret = 0;
  1688. u32 firmware_stat, winner_status;
  1689. struct pcie_service_card *card = adapter->card;
  1690. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1691. u32 tries;
  1692. /* Mask spurios interrupts */
  1693. if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
  1694. HOST_INTR_MASK)) {
  1695. dev_warn(adapter->dev, "Write register failed\n");
  1696. return -1;
  1697. }
  1698. dev_dbg(adapter->dev, "Setting driver ready signature\n");
  1699. if (mwifiex_write_reg(adapter, reg->drv_rdy,
  1700. FIRMWARE_READY_PCIE)) {
  1701. dev_err(adapter->dev,
  1702. "Failed to write driver ready signature\n");
  1703. return -1;
  1704. }
  1705. /* Wait for firmware initialization event */
  1706. for (tries = 0; tries < poll_num; tries++) {
  1707. if (mwifiex_read_reg(adapter, reg->fw_status,
  1708. &firmware_stat))
  1709. ret = -1;
  1710. else
  1711. ret = 0;
  1712. if (ret)
  1713. continue;
  1714. if (firmware_stat == FIRMWARE_READY_PCIE) {
  1715. ret = 0;
  1716. break;
  1717. } else {
  1718. msleep(100);
  1719. ret = -1;
  1720. }
  1721. }
  1722. if (ret) {
  1723. if (mwifiex_read_reg(adapter, reg->fw_status,
  1724. &winner_status))
  1725. ret = -1;
  1726. else if (!winner_status) {
  1727. dev_err(adapter->dev, "PCI-E is the winner\n");
  1728. adapter->winner = 1;
  1729. } else {
  1730. dev_err(adapter->dev,
  1731. "PCI-E is not the winner <%#x,%d>, exit dnld\n",
  1732. ret, adapter->winner);
  1733. }
  1734. }
  1735. return ret;
  1736. }
  1737. /*
  1738. * This function reads the interrupt status from card.
  1739. */
  1740. static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter)
  1741. {
  1742. u32 pcie_ireg;
  1743. unsigned long flags;
  1744. if (!mwifiex_pcie_ok_to_access_hw(adapter))
  1745. return;
  1746. if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, &pcie_ireg)) {
  1747. dev_warn(adapter->dev, "Read register failed\n");
  1748. return;
  1749. }
  1750. if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
  1751. mwifiex_pcie_disable_host_int(adapter);
  1752. /* Clear the pending interrupts */
  1753. if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
  1754. ~pcie_ireg)) {
  1755. dev_warn(adapter->dev, "Write register failed\n");
  1756. return;
  1757. }
  1758. spin_lock_irqsave(&adapter->int_lock, flags);
  1759. adapter->int_status |= pcie_ireg;
  1760. spin_unlock_irqrestore(&adapter->int_lock, flags);
  1761. if (!adapter->pps_uapsd_mode &&
  1762. adapter->ps_state == PS_STATE_SLEEP &&
  1763. mwifiex_pcie_ok_to_access_hw(adapter)) {
  1764. /* Potentially for PCIe we could get other
  1765. * interrupts like shared. Don't change power
  1766. * state until cookie is set */
  1767. adapter->ps_state = PS_STATE_AWAKE;
  1768. adapter->pm_wakeup_fw_try = false;
  1769. }
  1770. }
  1771. }
  1772. /*
  1773. * Interrupt handler for PCIe root port
  1774. *
  1775. * This function reads the interrupt status from firmware and assigns
  1776. * the main process in workqueue which will handle the interrupt.
  1777. */
  1778. static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
  1779. {
  1780. struct pci_dev *pdev = (struct pci_dev *)context;
  1781. struct pcie_service_card *card;
  1782. struct mwifiex_adapter *adapter;
  1783. if (!pdev) {
  1784. pr_debug("info: %s: pdev is NULL\n", (u8 *)pdev);
  1785. goto exit;
  1786. }
  1787. card = pci_get_drvdata(pdev);
  1788. if (!card || !card->adapter) {
  1789. pr_debug("info: %s: card=%p adapter=%p\n", __func__, card,
  1790. card ? card->adapter : NULL);
  1791. goto exit;
  1792. }
  1793. adapter = card->adapter;
  1794. if (adapter->surprise_removed)
  1795. goto exit;
  1796. mwifiex_interrupt_status(adapter);
  1797. queue_work(adapter->workqueue, &adapter->main_work);
  1798. exit:
  1799. return IRQ_HANDLED;
  1800. }
  1801. /*
  1802. * This function checks the current interrupt status.
  1803. *
  1804. * The following interrupts are checked and handled by this function -
  1805. * - Data sent
  1806. * - Command sent
  1807. * - Command received
  1808. * - Packets received
  1809. * - Events received
  1810. *
  1811. * In case of Rx packets received, the packets are uploaded from card to
  1812. * host and processed accordingly.
  1813. */
  1814. static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
  1815. {
  1816. int ret;
  1817. u32 pcie_ireg;
  1818. unsigned long flags;
  1819. spin_lock_irqsave(&adapter->int_lock, flags);
  1820. /* Clear out unused interrupts */
  1821. pcie_ireg = adapter->int_status;
  1822. adapter->int_status = 0;
  1823. spin_unlock_irqrestore(&adapter->int_lock, flags);
  1824. while (pcie_ireg & HOST_INTR_MASK) {
  1825. if (pcie_ireg & HOST_INTR_DNLD_DONE) {
  1826. pcie_ireg &= ~HOST_INTR_DNLD_DONE;
  1827. dev_dbg(adapter->dev, "info: TX DNLD Done\n");
  1828. ret = mwifiex_pcie_send_data_complete(adapter);
  1829. if (ret)
  1830. return ret;
  1831. }
  1832. if (pcie_ireg & HOST_INTR_UPLD_RDY) {
  1833. pcie_ireg &= ~HOST_INTR_UPLD_RDY;
  1834. dev_dbg(adapter->dev, "info: Rx DATA\n");
  1835. ret = mwifiex_pcie_process_recv_data(adapter);
  1836. if (ret)
  1837. return ret;
  1838. }
  1839. if (pcie_ireg & HOST_INTR_EVENT_RDY) {
  1840. pcie_ireg &= ~HOST_INTR_EVENT_RDY;
  1841. dev_dbg(adapter->dev, "info: Rx EVENT\n");
  1842. ret = mwifiex_pcie_process_event_ready(adapter);
  1843. if (ret)
  1844. return ret;
  1845. }
  1846. if (pcie_ireg & HOST_INTR_CMD_DONE) {
  1847. pcie_ireg &= ~HOST_INTR_CMD_DONE;
  1848. if (adapter->cmd_sent) {
  1849. dev_dbg(adapter->dev,
  1850. "info: CMD sent Interrupt\n");
  1851. adapter->cmd_sent = false;
  1852. }
  1853. /* Handle command response */
  1854. ret = mwifiex_pcie_process_cmd_complete(adapter);
  1855. if (ret)
  1856. return ret;
  1857. }
  1858. if (mwifiex_pcie_ok_to_access_hw(adapter)) {
  1859. if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
  1860. &pcie_ireg)) {
  1861. dev_warn(adapter->dev,
  1862. "Read register failed\n");
  1863. return -1;
  1864. }
  1865. if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
  1866. if (mwifiex_write_reg(adapter,
  1867. PCIE_HOST_INT_STATUS,
  1868. ~pcie_ireg)) {
  1869. dev_warn(adapter->dev,
  1870. "Write register failed\n");
  1871. return -1;
  1872. }
  1873. }
  1874. }
  1875. }
  1876. dev_dbg(adapter->dev, "info: cmd_sent=%d data_sent=%d\n",
  1877. adapter->cmd_sent, adapter->data_sent);
  1878. if (adapter->ps_state != PS_STATE_SLEEP)
  1879. mwifiex_pcie_enable_host_int(adapter);
  1880. return 0;
  1881. }
  1882. /*
  1883. * This function downloads data from driver to card.
  1884. *
  1885. * Both commands and data packets are transferred to the card by this
  1886. * function.
  1887. *
  1888. * This function adds the PCIE specific header to the front of the buffer
  1889. * before transferring. The header contains the length of the packet and
  1890. * the type. The firmware handles the packets based upon this set type.
  1891. */
  1892. static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
  1893. struct sk_buff *skb,
  1894. struct mwifiex_tx_param *tx_param)
  1895. {
  1896. if (!skb) {
  1897. dev_err(adapter->dev, "Passed NULL skb to %s\n", __func__);
  1898. return -1;
  1899. }
  1900. if (type == MWIFIEX_TYPE_DATA)
  1901. return mwifiex_pcie_send_data(adapter, skb, tx_param);
  1902. else if (type == MWIFIEX_TYPE_CMD)
  1903. return mwifiex_pcie_send_cmd(adapter, skb);
  1904. return 0;
  1905. }
  1906. /* This function read/write firmware */
  1907. static enum rdwr_status
  1908. mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
  1909. {
  1910. int ret, tries;
  1911. u8 ctrl_data;
  1912. struct pcie_service_card *card = adapter->card;
  1913. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  1914. ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, FW_DUMP_HOST_READY);
  1915. if (ret) {
  1916. dev_err(adapter->dev, "PCIE write err\n");
  1917. return RDWR_STATUS_FAILURE;
  1918. }
  1919. for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
  1920. mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
  1921. if (ctrl_data == FW_DUMP_DONE)
  1922. return RDWR_STATUS_SUCCESS;
  1923. if (doneflag && ctrl_data == doneflag)
  1924. return RDWR_STATUS_DONE;
  1925. if (ctrl_data != FW_DUMP_HOST_READY) {
  1926. dev_info(adapter->dev,
  1927. "The ctrl reg was changed, re-try again!\n");
  1928. ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
  1929. FW_DUMP_HOST_READY);
  1930. if (ret) {
  1931. dev_err(adapter->dev, "PCIE write err\n");
  1932. return RDWR_STATUS_FAILURE;
  1933. }
  1934. }
  1935. usleep_range(100, 200);
  1936. }
  1937. dev_err(adapter->dev, "Fail to pull ctrl_data\n");
  1938. return RDWR_STATUS_FAILURE;
  1939. }
  1940. /* This function dump firmware memory to file */
  1941. static void mwifiex_pcie_fw_dump_work(struct mwifiex_adapter *adapter)
  1942. {
  1943. struct pcie_service_card *card = adapter->card;
  1944. const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
  1945. unsigned int reg, reg_start, reg_end;
  1946. u8 *dbg_ptr, *end_ptr, dump_num, idx, i, read_reg, doneflag = 0;
  1947. enum rdwr_status stat;
  1948. u32 memory_size;
  1949. int ret;
  1950. static char *env[] = { "DRIVER=mwifiex_pcie", "EVENT=fw_dump", NULL };
  1951. if (!card->pcie.supports_fw_dump)
  1952. return;
  1953. for (idx = 0; idx < ARRAY_SIZE(mem_type_mapping_tbl); idx++) {
  1954. struct memory_type_mapping *entry = &mem_type_mapping_tbl[idx];
  1955. if (entry->mem_ptr) {
  1956. vfree(entry->mem_ptr);
  1957. entry->mem_ptr = NULL;
  1958. }
  1959. entry->mem_size = 0;
  1960. }
  1961. dev_info(adapter->dev, "== mwifiex firmware dump start ==\n");
  1962. /* Read the number of the memories which will dump */
  1963. stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
  1964. if (stat == RDWR_STATUS_FAILURE)
  1965. goto done;
  1966. reg = creg->fw_dump_start;
  1967. mwifiex_read_reg_byte(adapter, reg, &dump_num);
  1968. /* Read the length of every memory which will dump */
  1969. for (idx = 0; idx < dump_num; idx++) {
  1970. struct memory_type_mapping *entry = &mem_type_mapping_tbl[idx];
  1971. stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
  1972. if (stat == RDWR_STATUS_FAILURE)
  1973. goto done;
  1974. memory_size = 0;
  1975. reg = creg->fw_dump_start;
  1976. for (i = 0; i < 4; i++) {
  1977. mwifiex_read_reg_byte(adapter, reg, &read_reg);
  1978. memory_size |= (read_reg << (i * 8));
  1979. reg++;
  1980. }
  1981. if (memory_size == 0) {
  1982. dev_info(adapter->dev, "Firmware dump Finished!\n");
  1983. ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
  1984. FW_DUMP_READ_DONE);
  1985. if (ret) {
  1986. dev_err(adapter->dev, "PCIE write err\n");
  1987. goto done;
  1988. }
  1989. break;
  1990. }
  1991. dev_info(adapter->dev,
  1992. "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
  1993. entry->mem_ptr = vmalloc(memory_size + 1);
  1994. entry->mem_size = memory_size;
  1995. if (!entry->mem_ptr) {
  1996. dev_err(adapter->dev,
  1997. "Vmalloc %s failed\n", entry->mem_name);
  1998. goto done;
  1999. }
  2000. dbg_ptr = entry->mem_ptr;
  2001. end_ptr = dbg_ptr + memory_size;
  2002. doneflag = entry->done_flag;
  2003. dev_info(adapter->dev, "Start %s output, please wait...\n",
  2004. entry->mem_name);
  2005. do {
  2006. stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
  2007. if (RDWR_STATUS_FAILURE == stat)
  2008. goto done;
  2009. reg_start = creg->fw_dump_start;
  2010. reg_end = creg->fw_dump_end;
  2011. for (reg = reg_start; reg <= reg_end; reg++) {
  2012. mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
  2013. if (dbg_ptr < end_ptr) {
  2014. dbg_ptr++;
  2015. } else {
  2016. dev_err(adapter->dev,
  2017. "Allocated buf not enough\n");
  2018. goto done;
  2019. }
  2020. }
  2021. if (stat != RDWR_STATUS_DONE)
  2022. continue;
  2023. dev_info(adapter->dev, "%s done: size=0x%tx\n",
  2024. entry->mem_name, dbg_ptr - entry->mem_ptr);
  2025. break;
  2026. } while (true);
  2027. }
  2028. dev_info(adapter->dev, "== mwifiex firmware dump end ==\n");
  2029. kobject_uevent_env(&adapter->wiphy->dev.kobj, KOBJ_CHANGE, env);
  2030. done:
  2031. adapter->curr_mem_idx = 0;
  2032. }
  2033. static void mwifiex_pcie_work(struct work_struct *work)
  2034. {
  2035. struct mwifiex_adapter *adapter =
  2036. container_of(work, struct mwifiex_adapter, iface_work);
  2037. if (test_and_clear_bit(MWIFIEX_IFACE_WORK_FW_DUMP,
  2038. &adapter->iface_work_flags))
  2039. mwifiex_pcie_fw_dump_work(adapter);
  2040. }
  2041. /* This function dumps FW information */
  2042. static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
  2043. {
  2044. if (test_bit(MWIFIEX_IFACE_WORK_FW_DUMP, &adapter->iface_work_flags))
  2045. return;
  2046. set_bit(MWIFIEX_IFACE_WORK_FW_DUMP, &adapter->iface_work_flags);
  2047. schedule_work(&adapter->iface_work);
  2048. }
  2049. /*
  2050. * This function initializes the PCI-E host memory space, WCB rings, etc.
  2051. *
  2052. * The following initializations steps are followed -
  2053. * - Allocate TXBD ring buffers
  2054. * - Allocate RXBD ring buffers
  2055. * - Allocate event BD ring buffers
  2056. * - Allocate command response ring buffer
  2057. * - Allocate sleep cookie buffer
  2058. */
  2059. static int mwifiex_pcie_init(struct mwifiex_adapter *adapter)
  2060. {
  2061. struct pcie_service_card *card = adapter->card;
  2062. int ret;
  2063. struct pci_dev *pdev = card->dev;
  2064. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  2065. pci_set_drvdata(pdev, card);
  2066. ret = pci_enable_device(pdev);
  2067. if (ret)
  2068. goto err_enable_dev;
  2069. pci_set_master(pdev);
  2070. dev_dbg(adapter->dev, "try set_consistent_dma_mask(32)\n");
  2071. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2072. if (ret) {
  2073. dev_err(adapter->dev, "set_dma_mask(32) failed\n");
  2074. goto err_set_dma_mask;
  2075. }
  2076. ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2077. if (ret) {
  2078. dev_err(adapter->dev, "set_consistent_dma_mask(64) failed\n");
  2079. goto err_set_dma_mask;
  2080. }
  2081. ret = pci_request_region(pdev, 0, DRV_NAME);
  2082. if (ret) {
  2083. dev_err(adapter->dev, "req_reg(0) error\n");
  2084. goto err_req_region0;
  2085. }
  2086. card->pci_mmap = pci_iomap(pdev, 0, 0);
  2087. if (!card->pci_mmap) {
  2088. dev_err(adapter->dev, "iomap(0) error\n");
  2089. ret = -EIO;
  2090. goto err_iomap0;
  2091. }
  2092. ret = pci_request_region(pdev, 2, DRV_NAME);
  2093. if (ret) {
  2094. dev_err(adapter->dev, "req_reg(2) error\n");
  2095. goto err_req_region2;
  2096. }
  2097. card->pci_mmap1 = pci_iomap(pdev, 2, 0);
  2098. if (!card->pci_mmap1) {
  2099. dev_err(adapter->dev, "iomap(2) error\n");
  2100. ret = -EIO;
  2101. goto err_iomap2;
  2102. }
  2103. dev_dbg(adapter->dev,
  2104. "PCI memory map Virt0: %p PCI memory map Virt2: %p\n",
  2105. card->pci_mmap, card->pci_mmap1);
  2106. card->cmdrsp_buf = NULL;
  2107. ret = mwifiex_pcie_create_txbd_ring(adapter);
  2108. if (ret)
  2109. goto err_cre_txbd;
  2110. ret = mwifiex_pcie_create_rxbd_ring(adapter);
  2111. if (ret)
  2112. goto err_cre_rxbd;
  2113. ret = mwifiex_pcie_create_evtbd_ring(adapter);
  2114. if (ret)
  2115. goto err_cre_evtbd;
  2116. ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
  2117. if (ret)
  2118. goto err_alloc_cmdbuf;
  2119. if (reg->sleep_cookie) {
  2120. ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
  2121. if (ret)
  2122. goto err_alloc_cookie;
  2123. } else {
  2124. card->sleep_cookie_vbase = NULL;
  2125. }
  2126. return ret;
  2127. err_alloc_cookie:
  2128. mwifiex_pcie_delete_cmdrsp_buf(adapter);
  2129. err_alloc_cmdbuf:
  2130. mwifiex_pcie_delete_evtbd_ring(adapter);
  2131. err_cre_evtbd:
  2132. mwifiex_pcie_delete_rxbd_ring(adapter);
  2133. err_cre_rxbd:
  2134. mwifiex_pcie_delete_txbd_ring(adapter);
  2135. err_cre_txbd:
  2136. pci_iounmap(pdev, card->pci_mmap1);
  2137. err_iomap2:
  2138. pci_release_region(pdev, 2);
  2139. err_req_region2:
  2140. pci_iounmap(pdev, card->pci_mmap);
  2141. err_iomap0:
  2142. pci_release_region(pdev, 0);
  2143. err_req_region0:
  2144. err_set_dma_mask:
  2145. pci_disable_device(pdev);
  2146. err_enable_dev:
  2147. pci_set_drvdata(pdev, NULL);
  2148. return ret;
  2149. }
  2150. /*
  2151. * This function cleans up the allocated card buffers.
  2152. *
  2153. * The following are freed by this function -
  2154. * - TXBD ring buffers
  2155. * - RXBD ring buffers
  2156. * - Event BD ring buffers
  2157. * - Command response ring buffer
  2158. * - Sleep cookie buffer
  2159. */
  2160. static void mwifiex_pcie_cleanup(struct mwifiex_adapter *adapter)
  2161. {
  2162. struct pcie_service_card *card = adapter->card;
  2163. struct pci_dev *pdev = card->dev;
  2164. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  2165. if (user_rmmod) {
  2166. dev_dbg(adapter->dev, "Clearing driver ready signature\n");
  2167. if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
  2168. dev_err(adapter->dev,
  2169. "Failed to write driver not-ready signature\n");
  2170. }
  2171. if (pdev) {
  2172. pci_iounmap(pdev, card->pci_mmap);
  2173. pci_iounmap(pdev, card->pci_mmap1);
  2174. pci_disable_device(pdev);
  2175. pci_release_region(pdev, 2);
  2176. pci_release_region(pdev, 0);
  2177. pci_set_drvdata(pdev, NULL);
  2178. }
  2179. kfree(card);
  2180. }
  2181. /*
  2182. * This function registers the PCIE device.
  2183. *
  2184. * PCIE IRQ is claimed, block size is set and driver data is initialized.
  2185. */
  2186. static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
  2187. {
  2188. int ret;
  2189. struct pcie_service_card *card = adapter->card;
  2190. struct pci_dev *pdev = card->dev;
  2191. /* save adapter pointer in card */
  2192. card->adapter = adapter;
  2193. ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
  2194. "MRVL_PCIE", pdev);
  2195. if (ret) {
  2196. pr_err("request_irq failed: ret=%d\n", ret);
  2197. adapter->card = NULL;
  2198. return -1;
  2199. }
  2200. adapter->dev = &pdev->dev;
  2201. adapter->tx_buf_size = card->pcie.tx_buf_size;
  2202. adapter->mem_type_mapping_tbl = mem_type_mapping_tbl;
  2203. adapter->num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl);
  2204. strcpy(adapter->fw_name, card->pcie.firmware);
  2205. return 0;
  2206. }
  2207. /*
  2208. * This function unregisters the PCIE device.
  2209. *
  2210. * The PCIE IRQ is released, the function is disabled and driver
  2211. * data is set to null.
  2212. */
  2213. static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
  2214. {
  2215. struct pcie_service_card *card = adapter->card;
  2216. const struct mwifiex_pcie_card_reg *reg;
  2217. if (card) {
  2218. dev_dbg(adapter->dev, "%s(): calling free_irq()\n", __func__);
  2219. free_irq(card->dev->irq, card->dev);
  2220. reg = card->pcie.reg;
  2221. if (reg->sleep_cookie)
  2222. mwifiex_pcie_delete_sleep_cookie_buf(adapter);
  2223. mwifiex_pcie_delete_cmdrsp_buf(adapter);
  2224. mwifiex_pcie_delete_evtbd_ring(adapter);
  2225. mwifiex_pcie_delete_rxbd_ring(adapter);
  2226. mwifiex_pcie_delete_txbd_ring(adapter);
  2227. card->cmdrsp_buf = NULL;
  2228. }
  2229. }
  2230. static struct mwifiex_if_ops pcie_ops = {
  2231. .init_if = mwifiex_pcie_init,
  2232. .cleanup_if = mwifiex_pcie_cleanup,
  2233. .check_fw_status = mwifiex_check_fw_status,
  2234. .prog_fw = mwifiex_prog_fw_w_helper,
  2235. .register_dev = mwifiex_register_dev,
  2236. .unregister_dev = mwifiex_unregister_dev,
  2237. .enable_int = mwifiex_pcie_enable_host_int,
  2238. .process_int_status = mwifiex_process_int_status,
  2239. .host_to_card = mwifiex_pcie_host_to_card,
  2240. .wakeup = mwifiex_pm_wakeup_card,
  2241. .wakeup_complete = mwifiex_pm_wakeup_card_complete,
  2242. /* PCIE specific */
  2243. .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
  2244. .event_complete = mwifiex_pcie_event_complete,
  2245. .update_mp_end_port = NULL,
  2246. .cleanup_mpa_buf = NULL,
  2247. .init_fw_port = mwifiex_pcie_init_fw_port,
  2248. .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
  2249. .fw_dump = mwifiex_pcie_fw_dump,
  2250. .iface_work = mwifiex_pcie_work,
  2251. };
  2252. /*
  2253. * This function initializes the PCIE driver module.
  2254. *
  2255. * This initiates the semaphore and registers the device with
  2256. * PCIE bus.
  2257. */
  2258. static int mwifiex_pcie_init_module(void)
  2259. {
  2260. int ret;
  2261. pr_debug("Marvell PCIe Driver\n");
  2262. sema_init(&add_remove_card_sem, 1);
  2263. /* Clear the flag in case user removes the card. */
  2264. user_rmmod = 0;
  2265. ret = pci_register_driver(&mwifiex_pcie);
  2266. if (ret)
  2267. pr_err("Driver register failed!\n");
  2268. else
  2269. pr_debug("info: Driver registered successfully!\n");
  2270. return ret;
  2271. }
  2272. /*
  2273. * This function cleans up the PCIE driver.
  2274. *
  2275. * The following major steps are followed for cleanup -
  2276. * - Resume the device if its suspended
  2277. * - Disconnect the device if connected
  2278. * - Shutdown the firmware
  2279. * - Unregister the device from PCIE bus.
  2280. */
  2281. static void mwifiex_pcie_cleanup_module(void)
  2282. {
  2283. if (!down_interruptible(&add_remove_card_sem))
  2284. up(&add_remove_card_sem);
  2285. /* Set the flag as user is removing this module. */
  2286. user_rmmod = 1;
  2287. pci_unregister_driver(&mwifiex_pcie);
  2288. }
  2289. module_init(mwifiex_pcie_init_module);
  2290. module_exit(mwifiex_pcie_cleanup_module);
  2291. MODULE_AUTHOR("Marvell International Ltd.");
  2292. MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
  2293. MODULE_VERSION(PCIE_VERSION);
  2294. MODULE_LICENSE("GPL v2");
  2295. MODULE_FIRMWARE(PCIE8766_DEFAULT_FW_NAME);
  2296. MODULE_FIRMWARE(PCIE8897_DEFAULT_FW_NAME);