bna_tx_rx.c 96 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfi.h"
  20. /* IB */
  21. static void
  22. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  23. {
  24. ib->coalescing_timeo = coalescing_timeo;
  25. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  26. (u32)ib->coalescing_timeo, 0);
  27. }
  28. /* RXF */
  29. #define bna_rxf_vlan_cfg_soft_reset(rxf) \
  30. do { \
  31. (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
  32. (rxf)->vlan_strip_pending = true; \
  33. } while (0)
  34. #define bna_rxf_rss_cfg_soft_reset(rxf) \
  35. do { \
  36. if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
  37. (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
  38. BNA_RSS_F_CFG_PENDING | \
  39. BNA_RSS_F_STATUS_PENDING); \
  40. } while (0)
  41. static int bna_rxf_cfg_apply(struct bna_rxf *rxf);
  42. static void bna_rxf_cfg_reset(struct bna_rxf *rxf);
  43. static int bna_rxf_fltr_clear(struct bna_rxf *rxf);
  44. static int bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf);
  45. static int bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf);
  46. static int bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf);
  47. static int bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf);
  48. static int bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf,
  49. enum bna_cleanup_type cleanup);
  50. static int bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf,
  51. enum bna_cleanup_type cleanup);
  52. static int bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf,
  53. enum bna_cleanup_type cleanup);
  54. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  55. enum bna_rxf_event);
  56. bfa_fsm_state_decl(bna_rxf, paused, struct bna_rxf,
  57. enum bna_rxf_event);
  58. bfa_fsm_state_decl(bna_rxf, cfg_wait, struct bna_rxf,
  59. enum bna_rxf_event);
  60. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  61. enum bna_rxf_event);
  62. bfa_fsm_state_decl(bna_rxf, fltr_clr_wait, struct bna_rxf,
  63. enum bna_rxf_event);
  64. bfa_fsm_state_decl(bna_rxf, last_resp_wait, struct bna_rxf,
  65. enum bna_rxf_event);
  66. static void
  67. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  68. {
  69. call_rxf_stop_cbfn(rxf);
  70. }
  71. static void
  72. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  73. {
  74. switch (event) {
  75. case RXF_E_START:
  76. if (rxf->flags & BNA_RXF_F_PAUSED) {
  77. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  78. call_rxf_start_cbfn(rxf);
  79. } else
  80. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  81. break;
  82. case RXF_E_STOP:
  83. call_rxf_stop_cbfn(rxf);
  84. break;
  85. case RXF_E_FAIL:
  86. /* No-op */
  87. break;
  88. case RXF_E_CONFIG:
  89. call_rxf_cam_fltr_cbfn(rxf);
  90. break;
  91. case RXF_E_PAUSE:
  92. rxf->flags |= BNA_RXF_F_PAUSED;
  93. call_rxf_pause_cbfn(rxf);
  94. break;
  95. case RXF_E_RESUME:
  96. rxf->flags &= ~BNA_RXF_F_PAUSED;
  97. call_rxf_resume_cbfn(rxf);
  98. break;
  99. default:
  100. bfa_sm_fault(event);
  101. }
  102. }
  103. static void
  104. bna_rxf_sm_paused_entry(struct bna_rxf *rxf)
  105. {
  106. call_rxf_pause_cbfn(rxf);
  107. }
  108. static void
  109. bna_rxf_sm_paused(struct bna_rxf *rxf, enum bna_rxf_event event)
  110. {
  111. switch (event) {
  112. case RXF_E_STOP:
  113. case RXF_E_FAIL:
  114. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  115. break;
  116. case RXF_E_CONFIG:
  117. call_rxf_cam_fltr_cbfn(rxf);
  118. break;
  119. case RXF_E_RESUME:
  120. rxf->flags &= ~BNA_RXF_F_PAUSED;
  121. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  122. break;
  123. default:
  124. bfa_sm_fault(event);
  125. }
  126. }
  127. static void
  128. bna_rxf_sm_cfg_wait_entry(struct bna_rxf *rxf)
  129. {
  130. if (!bna_rxf_cfg_apply(rxf)) {
  131. /* No more pending config updates */
  132. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  133. }
  134. }
  135. static void
  136. bna_rxf_sm_cfg_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  137. {
  138. switch (event) {
  139. case RXF_E_STOP:
  140. bfa_fsm_set_state(rxf, bna_rxf_sm_last_resp_wait);
  141. break;
  142. case RXF_E_FAIL:
  143. bna_rxf_cfg_reset(rxf);
  144. call_rxf_start_cbfn(rxf);
  145. call_rxf_cam_fltr_cbfn(rxf);
  146. call_rxf_resume_cbfn(rxf);
  147. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  148. break;
  149. case RXF_E_CONFIG:
  150. /* No-op */
  151. break;
  152. case RXF_E_PAUSE:
  153. rxf->flags |= BNA_RXF_F_PAUSED;
  154. call_rxf_start_cbfn(rxf);
  155. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  156. break;
  157. case RXF_E_FW_RESP:
  158. if (!bna_rxf_cfg_apply(rxf)) {
  159. /* No more pending config updates */
  160. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  161. }
  162. break;
  163. default:
  164. bfa_sm_fault(event);
  165. }
  166. }
  167. static void
  168. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  169. {
  170. call_rxf_start_cbfn(rxf);
  171. call_rxf_cam_fltr_cbfn(rxf);
  172. call_rxf_resume_cbfn(rxf);
  173. }
  174. static void
  175. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  176. {
  177. switch (event) {
  178. case RXF_E_STOP:
  179. case RXF_E_FAIL:
  180. bna_rxf_cfg_reset(rxf);
  181. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  182. break;
  183. case RXF_E_CONFIG:
  184. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  185. break;
  186. case RXF_E_PAUSE:
  187. rxf->flags |= BNA_RXF_F_PAUSED;
  188. if (!bna_rxf_fltr_clear(rxf))
  189. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  190. else
  191. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  192. break;
  193. default:
  194. bfa_sm_fault(event);
  195. }
  196. }
  197. static void
  198. bna_rxf_sm_fltr_clr_wait_entry(struct bna_rxf *rxf)
  199. {
  200. }
  201. static void
  202. bna_rxf_sm_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  203. {
  204. switch (event) {
  205. case RXF_E_FAIL:
  206. bna_rxf_cfg_reset(rxf);
  207. call_rxf_pause_cbfn(rxf);
  208. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  209. break;
  210. case RXF_E_FW_RESP:
  211. if (!bna_rxf_fltr_clear(rxf)) {
  212. /* No more pending CAM entries to clear */
  213. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  214. }
  215. break;
  216. default:
  217. bfa_sm_fault(event);
  218. }
  219. }
  220. static void
  221. bna_rxf_sm_last_resp_wait_entry(struct bna_rxf *rxf)
  222. {
  223. }
  224. static void
  225. bna_rxf_sm_last_resp_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  226. {
  227. switch (event) {
  228. case RXF_E_FAIL:
  229. case RXF_E_FW_RESP:
  230. bna_rxf_cfg_reset(rxf);
  231. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  232. break;
  233. default:
  234. bfa_sm_fault(event);
  235. }
  236. }
  237. static void
  238. bna_bfi_ucast_req(struct bna_rxf *rxf, struct bna_mac *mac,
  239. enum bfi_enet_h2i_msgs req_type)
  240. {
  241. struct bfi_enet_ucast_req *req = &rxf->bfi_enet_cmd.ucast_req;
  242. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, req_type, 0, rxf->rx->rid);
  243. req->mh.num_entries = htons(
  244. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_ucast_req)));
  245. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  246. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  247. sizeof(struct bfi_enet_ucast_req), &req->mh);
  248. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  249. }
  250. static void
  251. bna_bfi_mcast_add_req(struct bna_rxf *rxf, struct bna_mac *mac)
  252. {
  253. struct bfi_enet_mcast_add_req *req =
  254. &rxf->bfi_enet_cmd.mcast_add_req;
  255. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_ADD_REQ,
  256. 0, rxf->rx->rid);
  257. req->mh.num_entries = htons(
  258. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_add_req)));
  259. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  260. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  261. sizeof(struct bfi_enet_mcast_add_req), &req->mh);
  262. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  263. }
  264. static void
  265. bna_bfi_mcast_del_req(struct bna_rxf *rxf, u16 handle)
  266. {
  267. struct bfi_enet_mcast_del_req *req =
  268. &rxf->bfi_enet_cmd.mcast_del_req;
  269. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_DEL_REQ,
  270. 0, rxf->rx->rid);
  271. req->mh.num_entries = htons(
  272. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_del_req)));
  273. req->handle = htons(handle);
  274. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  275. sizeof(struct bfi_enet_mcast_del_req), &req->mh);
  276. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  277. }
  278. static void
  279. bna_bfi_mcast_filter_req(struct bna_rxf *rxf, enum bna_status status)
  280. {
  281. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  282. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  283. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ, 0, rxf->rx->rid);
  284. req->mh.num_entries = htons(
  285. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  286. req->enable = status;
  287. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  288. sizeof(struct bfi_enet_enable_req), &req->mh);
  289. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  290. }
  291. static void
  292. bna_bfi_rx_promisc_req(struct bna_rxf *rxf, enum bna_status status)
  293. {
  294. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  295. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  296. BFI_ENET_H2I_RX_PROMISCUOUS_REQ, 0, rxf->rx->rid);
  297. req->mh.num_entries = htons(
  298. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  299. req->enable = status;
  300. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  301. sizeof(struct bfi_enet_enable_req), &req->mh);
  302. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  303. }
  304. static void
  305. bna_bfi_rx_vlan_filter_set(struct bna_rxf *rxf, u8 block_idx)
  306. {
  307. struct bfi_enet_rx_vlan_req *req = &rxf->bfi_enet_cmd.vlan_req;
  308. int i;
  309. int j;
  310. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  311. BFI_ENET_H2I_RX_VLAN_SET_REQ, 0, rxf->rx->rid);
  312. req->mh.num_entries = htons(
  313. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_vlan_req)));
  314. req->block_idx = block_idx;
  315. for (i = 0; i < (BFI_ENET_VLAN_BLOCK_SIZE / 32); i++) {
  316. j = (block_idx * (BFI_ENET_VLAN_BLOCK_SIZE / 32)) + i;
  317. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED)
  318. req->bit_mask[i] =
  319. htonl(rxf->vlan_filter_table[j]);
  320. else
  321. req->bit_mask[i] = 0xFFFFFFFF;
  322. }
  323. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  324. sizeof(struct bfi_enet_rx_vlan_req), &req->mh);
  325. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  326. }
  327. static void
  328. bna_bfi_vlan_strip_enable(struct bna_rxf *rxf)
  329. {
  330. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  331. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  332. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ, 0, rxf->rx->rid);
  333. req->mh.num_entries = htons(
  334. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  335. req->enable = rxf->vlan_strip_status;
  336. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  337. sizeof(struct bfi_enet_enable_req), &req->mh);
  338. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  339. }
  340. static void
  341. bna_bfi_rit_cfg(struct bna_rxf *rxf)
  342. {
  343. struct bfi_enet_rit_req *req = &rxf->bfi_enet_cmd.rit_req;
  344. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  345. BFI_ENET_H2I_RIT_CFG_REQ, 0, rxf->rx->rid);
  346. req->mh.num_entries = htons(
  347. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rit_req)));
  348. req->size = htons(rxf->rit_size);
  349. memcpy(&req->table[0], rxf->rit, rxf->rit_size);
  350. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  351. sizeof(struct bfi_enet_rit_req), &req->mh);
  352. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  353. }
  354. static void
  355. bna_bfi_rss_cfg(struct bna_rxf *rxf)
  356. {
  357. struct bfi_enet_rss_cfg_req *req = &rxf->bfi_enet_cmd.rss_req;
  358. int i;
  359. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  360. BFI_ENET_H2I_RSS_CFG_REQ, 0, rxf->rx->rid);
  361. req->mh.num_entries = htons(
  362. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rss_cfg_req)));
  363. req->cfg.type = rxf->rss_cfg.hash_type;
  364. req->cfg.mask = rxf->rss_cfg.hash_mask;
  365. for (i = 0; i < BFI_ENET_RSS_KEY_LEN; i++)
  366. req->cfg.key[i] =
  367. htonl(rxf->rss_cfg.toeplitz_hash_key[i]);
  368. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  369. sizeof(struct bfi_enet_rss_cfg_req), &req->mh);
  370. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  371. }
  372. static void
  373. bna_bfi_rss_enable(struct bna_rxf *rxf)
  374. {
  375. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  376. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  377. BFI_ENET_H2I_RSS_ENABLE_REQ, 0, rxf->rx->rid);
  378. req->mh.num_entries = htons(
  379. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  380. req->enable = rxf->rss_status;
  381. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  382. sizeof(struct bfi_enet_enable_req), &req->mh);
  383. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  384. }
  385. /* This function gets the multicast MAC that has already been added to CAM */
  386. static struct bna_mac *
  387. bna_rxf_mcmac_get(struct bna_rxf *rxf, u8 *mac_addr)
  388. {
  389. struct bna_mac *mac;
  390. struct list_head *qe;
  391. list_for_each(qe, &rxf->mcast_active_q) {
  392. mac = (struct bna_mac *)qe;
  393. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  394. return mac;
  395. }
  396. list_for_each(qe, &rxf->mcast_pending_del_q) {
  397. mac = (struct bna_mac *)qe;
  398. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  399. return mac;
  400. }
  401. return NULL;
  402. }
  403. static struct bna_mcam_handle *
  404. bna_rxf_mchandle_get(struct bna_rxf *rxf, int handle)
  405. {
  406. struct bna_mcam_handle *mchandle;
  407. struct list_head *qe;
  408. list_for_each(qe, &rxf->mcast_handle_q) {
  409. mchandle = (struct bna_mcam_handle *)qe;
  410. if (mchandle->handle == handle)
  411. return mchandle;
  412. }
  413. return NULL;
  414. }
  415. static void
  416. bna_rxf_mchandle_attach(struct bna_rxf *rxf, u8 *mac_addr, int handle)
  417. {
  418. struct bna_mac *mcmac;
  419. struct bna_mcam_handle *mchandle;
  420. mcmac = bna_rxf_mcmac_get(rxf, mac_addr);
  421. mchandle = bna_rxf_mchandle_get(rxf, handle);
  422. if (mchandle == NULL) {
  423. mchandle = bna_mcam_mod_handle_get(&rxf->rx->bna->mcam_mod);
  424. mchandle->handle = handle;
  425. mchandle->refcnt = 0;
  426. list_add_tail(&mchandle->qe, &rxf->mcast_handle_q);
  427. }
  428. mchandle->refcnt++;
  429. mcmac->handle = mchandle;
  430. }
  431. static int
  432. bna_rxf_mcast_del(struct bna_rxf *rxf, struct bna_mac *mac,
  433. enum bna_cleanup_type cleanup)
  434. {
  435. struct bna_mcam_handle *mchandle;
  436. int ret = 0;
  437. mchandle = mac->handle;
  438. if (mchandle == NULL)
  439. return ret;
  440. mchandle->refcnt--;
  441. if (mchandle->refcnt == 0) {
  442. if (cleanup == BNA_HARD_CLEANUP) {
  443. bna_bfi_mcast_del_req(rxf, mchandle->handle);
  444. ret = 1;
  445. }
  446. list_del(&mchandle->qe);
  447. bfa_q_qe_init(&mchandle->qe);
  448. bna_mcam_mod_handle_put(&rxf->rx->bna->mcam_mod, mchandle);
  449. }
  450. mac->handle = NULL;
  451. return ret;
  452. }
  453. static int
  454. bna_rxf_mcast_cfg_apply(struct bna_rxf *rxf)
  455. {
  456. struct bna_mac *mac = NULL;
  457. struct list_head *qe;
  458. int ret;
  459. /* First delete multicast entries to maintain the count */
  460. while (!list_empty(&rxf->mcast_pending_del_q)) {
  461. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  462. bfa_q_qe_init(qe);
  463. mac = (struct bna_mac *)qe;
  464. ret = bna_rxf_mcast_del(rxf, mac, BNA_HARD_CLEANUP);
  465. bna_cam_mod_mac_put(bna_mcam_mod_del_q(rxf->rx->bna), mac);
  466. if (ret)
  467. return ret;
  468. }
  469. /* Add multicast entries */
  470. if (!list_empty(&rxf->mcast_pending_add_q)) {
  471. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  472. bfa_q_qe_init(qe);
  473. mac = (struct bna_mac *)qe;
  474. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  475. bna_bfi_mcast_add_req(rxf, mac);
  476. return 1;
  477. }
  478. return 0;
  479. }
  480. static int
  481. bna_rxf_vlan_cfg_apply(struct bna_rxf *rxf)
  482. {
  483. u8 vlan_pending_bitmask;
  484. int block_idx = 0;
  485. if (rxf->vlan_pending_bitmask) {
  486. vlan_pending_bitmask = rxf->vlan_pending_bitmask;
  487. while (!(vlan_pending_bitmask & 0x1)) {
  488. block_idx++;
  489. vlan_pending_bitmask >>= 1;
  490. }
  491. rxf->vlan_pending_bitmask &= ~(1 << block_idx);
  492. bna_bfi_rx_vlan_filter_set(rxf, block_idx);
  493. return 1;
  494. }
  495. return 0;
  496. }
  497. static int
  498. bna_rxf_mcast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  499. {
  500. struct list_head *qe;
  501. struct bna_mac *mac;
  502. int ret;
  503. /* Throw away delete pending mcast entries */
  504. while (!list_empty(&rxf->mcast_pending_del_q)) {
  505. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  506. bfa_q_qe_init(qe);
  507. mac = (struct bna_mac *)qe;
  508. ret = bna_rxf_mcast_del(rxf, mac, cleanup);
  509. bna_cam_mod_mac_put(bna_mcam_mod_del_q(rxf->rx->bna), mac);
  510. if (ret)
  511. return ret;
  512. }
  513. /* Move active mcast entries to pending_add_q */
  514. while (!list_empty(&rxf->mcast_active_q)) {
  515. bfa_q_deq(&rxf->mcast_active_q, &qe);
  516. bfa_q_qe_init(qe);
  517. list_add_tail(qe, &rxf->mcast_pending_add_q);
  518. mac = (struct bna_mac *)qe;
  519. if (bna_rxf_mcast_del(rxf, mac, cleanup))
  520. return 1;
  521. }
  522. return 0;
  523. }
  524. static int
  525. bna_rxf_rss_cfg_apply(struct bna_rxf *rxf)
  526. {
  527. if (rxf->rss_pending) {
  528. if (rxf->rss_pending & BNA_RSS_F_RIT_PENDING) {
  529. rxf->rss_pending &= ~BNA_RSS_F_RIT_PENDING;
  530. bna_bfi_rit_cfg(rxf);
  531. return 1;
  532. }
  533. if (rxf->rss_pending & BNA_RSS_F_CFG_PENDING) {
  534. rxf->rss_pending &= ~BNA_RSS_F_CFG_PENDING;
  535. bna_bfi_rss_cfg(rxf);
  536. return 1;
  537. }
  538. if (rxf->rss_pending & BNA_RSS_F_STATUS_PENDING) {
  539. rxf->rss_pending &= ~BNA_RSS_F_STATUS_PENDING;
  540. bna_bfi_rss_enable(rxf);
  541. return 1;
  542. }
  543. }
  544. return 0;
  545. }
  546. static int
  547. bna_rxf_cfg_apply(struct bna_rxf *rxf)
  548. {
  549. if (bna_rxf_ucast_cfg_apply(rxf))
  550. return 1;
  551. if (bna_rxf_mcast_cfg_apply(rxf))
  552. return 1;
  553. if (bna_rxf_promisc_cfg_apply(rxf))
  554. return 1;
  555. if (bna_rxf_allmulti_cfg_apply(rxf))
  556. return 1;
  557. if (bna_rxf_vlan_cfg_apply(rxf))
  558. return 1;
  559. if (bna_rxf_vlan_strip_cfg_apply(rxf))
  560. return 1;
  561. if (bna_rxf_rss_cfg_apply(rxf))
  562. return 1;
  563. return 0;
  564. }
  565. /* Only software reset */
  566. static int
  567. bna_rxf_fltr_clear(struct bna_rxf *rxf)
  568. {
  569. if (bna_rxf_ucast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  570. return 1;
  571. if (bna_rxf_mcast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  572. return 1;
  573. if (bna_rxf_promisc_cfg_reset(rxf, BNA_HARD_CLEANUP))
  574. return 1;
  575. if (bna_rxf_allmulti_cfg_reset(rxf, BNA_HARD_CLEANUP))
  576. return 1;
  577. return 0;
  578. }
  579. static void
  580. bna_rxf_cfg_reset(struct bna_rxf *rxf)
  581. {
  582. bna_rxf_ucast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  583. bna_rxf_mcast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  584. bna_rxf_promisc_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  585. bna_rxf_allmulti_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  586. bna_rxf_vlan_cfg_soft_reset(rxf);
  587. bna_rxf_rss_cfg_soft_reset(rxf);
  588. }
  589. static void
  590. bna_rit_init(struct bna_rxf *rxf, int rit_size)
  591. {
  592. struct bna_rx *rx = rxf->rx;
  593. struct bna_rxp *rxp;
  594. struct list_head *qe;
  595. int offset = 0;
  596. rxf->rit_size = rit_size;
  597. list_for_each(qe, &rx->rxp_q) {
  598. rxp = (struct bna_rxp *)qe;
  599. rxf->rit[offset] = rxp->cq.ccb->id;
  600. offset++;
  601. }
  602. }
  603. void
  604. bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr)
  605. {
  606. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  607. }
  608. void
  609. bna_bfi_rxf_ucast_set_rsp(struct bna_rxf *rxf,
  610. struct bfi_msgq_mhdr *msghdr)
  611. {
  612. struct bfi_enet_rsp *rsp =
  613. container_of(msghdr, struct bfi_enet_rsp, mh);
  614. if (rsp->error) {
  615. /* Clear ucast from cache */
  616. rxf->ucast_active_set = 0;
  617. }
  618. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  619. }
  620. void
  621. bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
  622. struct bfi_msgq_mhdr *msghdr)
  623. {
  624. struct bfi_enet_mcast_add_req *req =
  625. &rxf->bfi_enet_cmd.mcast_add_req;
  626. struct bfi_enet_mcast_add_rsp *rsp =
  627. container_of(msghdr, struct bfi_enet_mcast_add_rsp, mh);
  628. bna_rxf_mchandle_attach(rxf, (u8 *)&req->mac_addr,
  629. ntohs(rsp->handle));
  630. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  631. }
  632. static void
  633. bna_rxf_init(struct bna_rxf *rxf,
  634. struct bna_rx *rx,
  635. struct bna_rx_config *q_config,
  636. struct bna_res_info *res_info)
  637. {
  638. rxf->rx = rx;
  639. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  640. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  641. rxf->ucast_pending_set = 0;
  642. rxf->ucast_active_set = 0;
  643. INIT_LIST_HEAD(&rxf->ucast_active_q);
  644. rxf->ucast_pending_mac = NULL;
  645. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  646. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  647. INIT_LIST_HEAD(&rxf->mcast_active_q);
  648. INIT_LIST_HEAD(&rxf->mcast_handle_q);
  649. if (q_config->paused)
  650. rxf->flags |= BNA_RXF_F_PAUSED;
  651. rxf->rit = (u8 *)
  652. res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info.mdl[0].kva;
  653. bna_rit_init(rxf, q_config->num_paths);
  654. rxf->rss_status = q_config->rss_status;
  655. if (rxf->rss_status == BNA_STATUS_T_ENABLED) {
  656. rxf->rss_cfg = q_config->rss_config;
  657. rxf->rss_pending |= BNA_RSS_F_CFG_PENDING;
  658. rxf->rss_pending |= BNA_RSS_F_RIT_PENDING;
  659. rxf->rss_pending |= BNA_RSS_F_STATUS_PENDING;
  660. }
  661. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  662. memset(rxf->vlan_filter_table, 0,
  663. (sizeof(u32) * (BFI_ENET_VLAN_ID_MAX / 32)));
  664. rxf->vlan_filter_table[0] |= 1; /* for pure priority tagged frames */
  665. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  666. rxf->vlan_strip_status = q_config->vlan_strip_status;
  667. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  668. }
  669. static void
  670. bna_rxf_uninit(struct bna_rxf *rxf)
  671. {
  672. struct bna_mac *mac;
  673. rxf->ucast_pending_set = 0;
  674. rxf->ucast_active_set = 0;
  675. while (!list_empty(&rxf->ucast_pending_add_q)) {
  676. bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
  677. bfa_q_qe_init(&mac->qe);
  678. bna_cam_mod_mac_put(bna_ucam_mod_free_q(rxf->rx->bna), mac);
  679. }
  680. if (rxf->ucast_pending_mac) {
  681. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  682. bna_cam_mod_mac_put(bna_ucam_mod_free_q(rxf->rx->bna),
  683. rxf->ucast_pending_mac);
  684. rxf->ucast_pending_mac = NULL;
  685. }
  686. while (!list_empty(&rxf->mcast_pending_add_q)) {
  687. bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
  688. bfa_q_qe_init(&mac->qe);
  689. bna_cam_mod_mac_put(bna_mcam_mod_free_q(rxf->rx->bna), mac);
  690. }
  691. rxf->rxmode_pending = 0;
  692. rxf->rxmode_pending_bitmask = 0;
  693. if (rxf->rx->bna->promisc_rid == rxf->rx->rid)
  694. rxf->rx->bna->promisc_rid = BFI_INVALID_RID;
  695. if (rxf->rx->bna->default_mode_rid == rxf->rx->rid)
  696. rxf->rx->bna->default_mode_rid = BFI_INVALID_RID;
  697. rxf->rss_pending = 0;
  698. rxf->vlan_strip_pending = false;
  699. rxf->flags = 0;
  700. rxf->rx = NULL;
  701. }
  702. static void
  703. bna_rx_cb_rxf_started(struct bna_rx *rx)
  704. {
  705. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  706. }
  707. static void
  708. bna_rxf_start(struct bna_rxf *rxf)
  709. {
  710. rxf->start_cbfn = bna_rx_cb_rxf_started;
  711. rxf->start_cbarg = rxf->rx;
  712. bfa_fsm_send_event(rxf, RXF_E_START);
  713. }
  714. static void
  715. bna_rx_cb_rxf_stopped(struct bna_rx *rx)
  716. {
  717. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  718. }
  719. static void
  720. bna_rxf_stop(struct bna_rxf *rxf)
  721. {
  722. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  723. rxf->stop_cbarg = rxf->rx;
  724. bfa_fsm_send_event(rxf, RXF_E_STOP);
  725. }
  726. static void
  727. bna_rxf_fail(struct bna_rxf *rxf)
  728. {
  729. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  730. }
  731. enum bna_cb_status
  732. bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
  733. void (*cbfn)(struct bnad *, struct bna_rx *))
  734. {
  735. struct bna_rxf *rxf = &rx->rxf;
  736. if (rxf->ucast_pending_mac == NULL) {
  737. rxf->ucast_pending_mac =
  738. bna_cam_mod_mac_get(bna_ucam_mod_free_q(rxf->rx->bna));
  739. if (rxf->ucast_pending_mac == NULL)
  740. return BNA_CB_UCAST_CAM_FULL;
  741. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  742. }
  743. memcpy(rxf->ucast_pending_mac->addr, ucmac, ETH_ALEN);
  744. rxf->ucast_pending_set = 1;
  745. rxf->cam_fltr_cbfn = cbfn;
  746. rxf->cam_fltr_cbarg = rx->bna->bnad;
  747. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  748. return BNA_CB_SUCCESS;
  749. }
  750. enum bna_cb_status
  751. bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
  752. void (*cbfn)(struct bnad *, struct bna_rx *))
  753. {
  754. struct bna_rxf *rxf = &rx->rxf;
  755. struct bna_mac *mac;
  756. /* Check if already added or pending addition */
  757. if (bna_mac_find(&rxf->mcast_active_q, addr) ||
  758. bna_mac_find(&rxf->mcast_pending_add_q, addr)) {
  759. if (cbfn)
  760. cbfn(rx->bna->bnad, rx);
  761. return BNA_CB_SUCCESS;
  762. }
  763. mac = bna_cam_mod_mac_get(bna_mcam_mod_free_q(rxf->rx->bna));
  764. if (mac == NULL)
  765. return BNA_CB_MCAST_LIST_FULL;
  766. bfa_q_qe_init(&mac->qe);
  767. memcpy(mac->addr, addr, ETH_ALEN);
  768. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  769. rxf->cam_fltr_cbfn = cbfn;
  770. rxf->cam_fltr_cbarg = rx->bna->bnad;
  771. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  772. return BNA_CB_SUCCESS;
  773. }
  774. enum bna_cb_status
  775. bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist,
  776. void (*cbfn)(struct bnad *, struct bna_rx *))
  777. {
  778. struct bna_ucam_mod *ucam_mod = &rx->bna->ucam_mod;
  779. struct bna_rxf *rxf = &rx->rxf;
  780. struct list_head list_head;
  781. struct list_head *qe;
  782. u8 *mcaddr;
  783. struct bna_mac *mac, *del_mac;
  784. int i;
  785. /* Purge the pending_add_q */
  786. while (!list_empty(&rxf->ucast_pending_add_q)) {
  787. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  788. bfa_q_qe_init(qe);
  789. mac = (struct bna_mac *)qe;
  790. bna_cam_mod_mac_put(&ucam_mod->free_q, mac);
  791. }
  792. /* Schedule active_q entries for deletion */
  793. while (!list_empty(&rxf->ucast_active_q)) {
  794. bfa_q_deq(&rxf->ucast_active_q, &qe);
  795. mac = (struct bna_mac *)qe;
  796. bfa_q_qe_init(&mac->qe);
  797. del_mac = bna_cam_mod_mac_get(&ucam_mod->del_q);
  798. memcpy(del_mac, mac, sizeof(*del_mac));
  799. list_add_tail(&del_mac->qe, &rxf->ucast_pending_del_q);
  800. bna_cam_mod_mac_put(&ucam_mod->free_q, mac);
  801. }
  802. /* Allocate nodes */
  803. INIT_LIST_HEAD(&list_head);
  804. for (i = 0, mcaddr = uclist; i < count; i++) {
  805. mac = bna_cam_mod_mac_get(&ucam_mod->free_q);
  806. if (mac == NULL)
  807. goto err_return;
  808. bfa_q_qe_init(&mac->qe);
  809. memcpy(mac->addr, mcaddr, ETH_ALEN);
  810. list_add_tail(&mac->qe, &list_head);
  811. mcaddr += ETH_ALEN;
  812. }
  813. /* Add the new entries */
  814. while (!list_empty(&list_head)) {
  815. bfa_q_deq(&list_head, &qe);
  816. mac = (struct bna_mac *)qe;
  817. bfa_q_qe_init(&mac->qe);
  818. list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
  819. }
  820. rxf->cam_fltr_cbfn = cbfn;
  821. rxf->cam_fltr_cbarg = rx->bna->bnad;
  822. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  823. return BNA_CB_SUCCESS;
  824. err_return:
  825. while (!list_empty(&list_head)) {
  826. bfa_q_deq(&list_head, &qe);
  827. mac = (struct bna_mac *)qe;
  828. bfa_q_qe_init(&mac->qe);
  829. bna_cam_mod_mac_put(&ucam_mod->free_q, mac);
  830. }
  831. return BNA_CB_UCAST_CAM_FULL;
  832. }
  833. enum bna_cb_status
  834. bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
  835. void (*cbfn)(struct bnad *, struct bna_rx *))
  836. {
  837. struct bna_mcam_mod *mcam_mod = &rx->bna->mcam_mod;
  838. struct bna_rxf *rxf = &rx->rxf;
  839. struct list_head list_head;
  840. struct list_head *qe;
  841. u8 *mcaddr;
  842. struct bna_mac *mac, *del_mac;
  843. int i;
  844. /* Purge the pending_add_q */
  845. while (!list_empty(&rxf->mcast_pending_add_q)) {
  846. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  847. bfa_q_qe_init(qe);
  848. mac = (struct bna_mac *)qe;
  849. bna_cam_mod_mac_put(&mcam_mod->free_q, mac);
  850. }
  851. /* Schedule active_q entries for deletion */
  852. while (!list_empty(&rxf->mcast_active_q)) {
  853. bfa_q_deq(&rxf->mcast_active_q, &qe);
  854. mac = (struct bna_mac *)qe;
  855. bfa_q_qe_init(&mac->qe);
  856. del_mac = bna_cam_mod_mac_get(&mcam_mod->del_q);
  857. memcpy(del_mac, mac, sizeof(*del_mac));
  858. list_add_tail(&del_mac->qe, &rxf->mcast_pending_del_q);
  859. mac->handle = NULL;
  860. bna_cam_mod_mac_put(&mcam_mod->free_q, mac);
  861. }
  862. /* Allocate nodes */
  863. INIT_LIST_HEAD(&list_head);
  864. for (i = 0, mcaddr = mclist; i < count; i++) {
  865. mac = bna_cam_mod_mac_get(&mcam_mod->free_q);
  866. if (mac == NULL)
  867. goto err_return;
  868. bfa_q_qe_init(&mac->qe);
  869. memcpy(mac->addr, mcaddr, ETH_ALEN);
  870. list_add_tail(&mac->qe, &list_head);
  871. mcaddr += ETH_ALEN;
  872. }
  873. /* Add the new entries */
  874. while (!list_empty(&list_head)) {
  875. bfa_q_deq(&list_head, &qe);
  876. mac = (struct bna_mac *)qe;
  877. bfa_q_qe_init(&mac->qe);
  878. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  879. }
  880. rxf->cam_fltr_cbfn = cbfn;
  881. rxf->cam_fltr_cbarg = rx->bna->bnad;
  882. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  883. return BNA_CB_SUCCESS;
  884. err_return:
  885. while (!list_empty(&list_head)) {
  886. bfa_q_deq(&list_head, &qe);
  887. mac = (struct bna_mac *)qe;
  888. bfa_q_qe_init(&mac->qe);
  889. bna_cam_mod_mac_put(&mcam_mod->free_q, mac);
  890. }
  891. return BNA_CB_MCAST_LIST_FULL;
  892. }
  893. void
  894. bna_rx_mcast_delall(struct bna_rx *rx,
  895. void (*cbfn)(struct bnad *, struct bna_rx *))
  896. {
  897. struct bna_rxf *rxf = &rx->rxf;
  898. struct list_head *qe;
  899. struct bna_mac *mac, *del_mac;
  900. int need_hw_config = 0;
  901. /* Purge all entries from pending_add_q */
  902. while (!list_empty(&rxf->mcast_pending_add_q)) {
  903. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  904. mac = (struct bna_mac *)qe;
  905. bfa_q_qe_init(&mac->qe);
  906. bna_cam_mod_mac_put(bna_mcam_mod_free_q(rxf->rx->bna), mac);
  907. }
  908. /* Schedule all entries in active_q for deletion */
  909. while (!list_empty(&rxf->mcast_active_q)) {
  910. bfa_q_deq(&rxf->mcast_active_q, &qe);
  911. mac = (struct bna_mac *)qe;
  912. bfa_q_qe_init(&mac->qe);
  913. del_mac = bna_cam_mod_mac_get(bna_mcam_mod_del_q(rxf->rx->bna));
  914. memcpy(del_mac, mac, sizeof(*del_mac));
  915. list_add_tail(&del_mac->qe, &rxf->mcast_pending_del_q);
  916. mac->handle = NULL;
  917. bna_cam_mod_mac_put(bna_mcam_mod_free_q(rxf->rx->bna), mac);
  918. need_hw_config = 1;
  919. }
  920. if (need_hw_config) {
  921. rxf->cam_fltr_cbfn = cbfn;
  922. rxf->cam_fltr_cbarg = rx->bna->bnad;
  923. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  924. return;
  925. }
  926. if (cbfn)
  927. (*cbfn)(rx->bna->bnad, rx);
  928. }
  929. void
  930. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  931. {
  932. struct bna_rxf *rxf = &rx->rxf;
  933. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  934. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  935. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  936. rxf->vlan_filter_table[index] |= bit;
  937. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  938. rxf->vlan_pending_bitmask |= (1 << group_id);
  939. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  940. }
  941. }
  942. void
  943. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  944. {
  945. struct bna_rxf *rxf = &rx->rxf;
  946. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  947. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  948. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  949. rxf->vlan_filter_table[index] &= ~bit;
  950. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  951. rxf->vlan_pending_bitmask |= (1 << group_id);
  952. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  953. }
  954. }
  955. static int
  956. bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf)
  957. {
  958. struct bna_mac *mac = NULL;
  959. struct list_head *qe;
  960. /* Delete MAC addresses previousely added */
  961. if (!list_empty(&rxf->ucast_pending_del_q)) {
  962. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  963. bfa_q_qe_init(qe);
  964. mac = (struct bna_mac *)qe;
  965. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  966. bna_cam_mod_mac_put(bna_ucam_mod_del_q(rxf->rx->bna), mac);
  967. return 1;
  968. }
  969. /* Set default unicast MAC */
  970. if (rxf->ucast_pending_set) {
  971. rxf->ucast_pending_set = 0;
  972. memcpy(rxf->ucast_active_mac.addr,
  973. rxf->ucast_pending_mac->addr, ETH_ALEN);
  974. rxf->ucast_active_set = 1;
  975. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  976. BFI_ENET_H2I_MAC_UCAST_SET_REQ);
  977. return 1;
  978. }
  979. /* Add additional MAC entries */
  980. if (!list_empty(&rxf->ucast_pending_add_q)) {
  981. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  982. bfa_q_qe_init(qe);
  983. mac = (struct bna_mac *)qe;
  984. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  985. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_ADD_REQ);
  986. return 1;
  987. }
  988. return 0;
  989. }
  990. static int
  991. bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  992. {
  993. struct list_head *qe;
  994. struct bna_mac *mac;
  995. /* Throw away delete pending ucast entries */
  996. while (!list_empty(&rxf->ucast_pending_del_q)) {
  997. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  998. bfa_q_qe_init(qe);
  999. mac = (struct bna_mac *)qe;
  1000. if (cleanup == BNA_SOFT_CLEANUP)
  1001. bna_cam_mod_mac_put(bna_ucam_mod_del_q(rxf->rx->bna),
  1002. mac);
  1003. else {
  1004. bna_bfi_ucast_req(rxf, mac,
  1005. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  1006. bna_cam_mod_mac_put(bna_ucam_mod_del_q(rxf->rx->bna),
  1007. mac);
  1008. return 1;
  1009. }
  1010. }
  1011. /* Move active ucast entries to pending_add_q */
  1012. while (!list_empty(&rxf->ucast_active_q)) {
  1013. bfa_q_deq(&rxf->ucast_active_q, &qe);
  1014. bfa_q_qe_init(qe);
  1015. list_add_tail(qe, &rxf->ucast_pending_add_q);
  1016. if (cleanup == BNA_HARD_CLEANUP) {
  1017. mac = (struct bna_mac *)qe;
  1018. bna_bfi_ucast_req(rxf, mac,
  1019. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  1020. return 1;
  1021. }
  1022. }
  1023. if (rxf->ucast_active_set) {
  1024. rxf->ucast_pending_set = 1;
  1025. rxf->ucast_active_set = 0;
  1026. if (cleanup == BNA_HARD_CLEANUP) {
  1027. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  1028. BFI_ENET_H2I_MAC_UCAST_CLR_REQ);
  1029. return 1;
  1030. }
  1031. }
  1032. return 0;
  1033. }
  1034. static int
  1035. bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf)
  1036. {
  1037. struct bna *bna = rxf->rx->bna;
  1038. /* Enable/disable promiscuous mode */
  1039. if (is_promisc_enable(rxf->rxmode_pending,
  1040. rxf->rxmode_pending_bitmask)) {
  1041. /* move promisc configuration from pending -> active */
  1042. promisc_inactive(rxf->rxmode_pending,
  1043. rxf->rxmode_pending_bitmask);
  1044. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  1045. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_ENABLED);
  1046. return 1;
  1047. } else if (is_promisc_disable(rxf->rxmode_pending,
  1048. rxf->rxmode_pending_bitmask)) {
  1049. /* move promisc configuration from pending -> active */
  1050. promisc_inactive(rxf->rxmode_pending,
  1051. rxf->rxmode_pending_bitmask);
  1052. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1053. bna->promisc_rid = BFI_INVALID_RID;
  1054. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  1055. return 1;
  1056. }
  1057. return 0;
  1058. }
  1059. static int
  1060. bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  1061. {
  1062. struct bna *bna = rxf->rx->bna;
  1063. /* Clear pending promisc mode disable */
  1064. if (is_promisc_disable(rxf->rxmode_pending,
  1065. rxf->rxmode_pending_bitmask)) {
  1066. promisc_inactive(rxf->rxmode_pending,
  1067. rxf->rxmode_pending_bitmask);
  1068. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1069. bna->promisc_rid = BFI_INVALID_RID;
  1070. if (cleanup == BNA_HARD_CLEANUP) {
  1071. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  1072. return 1;
  1073. }
  1074. }
  1075. /* Move promisc mode config from active -> pending */
  1076. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1077. promisc_enable(rxf->rxmode_pending,
  1078. rxf->rxmode_pending_bitmask);
  1079. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1080. if (cleanup == BNA_HARD_CLEANUP) {
  1081. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  1082. return 1;
  1083. }
  1084. }
  1085. return 0;
  1086. }
  1087. static int
  1088. bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf)
  1089. {
  1090. /* Enable/disable allmulti mode */
  1091. if (is_allmulti_enable(rxf->rxmode_pending,
  1092. rxf->rxmode_pending_bitmask)) {
  1093. /* move allmulti configuration from pending -> active */
  1094. allmulti_inactive(rxf->rxmode_pending,
  1095. rxf->rxmode_pending_bitmask);
  1096. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  1097. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_DISABLED);
  1098. return 1;
  1099. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1100. rxf->rxmode_pending_bitmask)) {
  1101. /* move allmulti configuration from pending -> active */
  1102. allmulti_inactive(rxf->rxmode_pending,
  1103. rxf->rxmode_pending_bitmask);
  1104. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1105. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1106. return 1;
  1107. }
  1108. return 0;
  1109. }
  1110. static int
  1111. bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  1112. {
  1113. /* Clear pending allmulti mode disable */
  1114. if (is_allmulti_disable(rxf->rxmode_pending,
  1115. rxf->rxmode_pending_bitmask)) {
  1116. allmulti_inactive(rxf->rxmode_pending,
  1117. rxf->rxmode_pending_bitmask);
  1118. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1119. if (cleanup == BNA_HARD_CLEANUP) {
  1120. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1121. return 1;
  1122. }
  1123. }
  1124. /* Move allmulti mode config from active -> pending */
  1125. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1126. allmulti_enable(rxf->rxmode_pending,
  1127. rxf->rxmode_pending_bitmask);
  1128. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1129. if (cleanup == BNA_HARD_CLEANUP) {
  1130. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1131. return 1;
  1132. }
  1133. }
  1134. return 0;
  1135. }
  1136. static int
  1137. bna_rxf_promisc_enable(struct bna_rxf *rxf)
  1138. {
  1139. struct bna *bna = rxf->rx->bna;
  1140. int ret = 0;
  1141. if (is_promisc_enable(rxf->rxmode_pending,
  1142. rxf->rxmode_pending_bitmask) ||
  1143. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  1144. /* Do nothing if pending enable or already enabled */
  1145. } else if (is_promisc_disable(rxf->rxmode_pending,
  1146. rxf->rxmode_pending_bitmask)) {
  1147. /* Turn off pending disable command */
  1148. promisc_inactive(rxf->rxmode_pending,
  1149. rxf->rxmode_pending_bitmask);
  1150. } else {
  1151. /* Schedule enable */
  1152. promisc_enable(rxf->rxmode_pending,
  1153. rxf->rxmode_pending_bitmask);
  1154. bna->promisc_rid = rxf->rx->rid;
  1155. ret = 1;
  1156. }
  1157. return ret;
  1158. }
  1159. static int
  1160. bna_rxf_promisc_disable(struct bna_rxf *rxf)
  1161. {
  1162. struct bna *bna = rxf->rx->bna;
  1163. int ret = 0;
  1164. if (is_promisc_disable(rxf->rxmode_pending,
  1165. rxf->rxmode_pending_bitmask) ||
  1166. (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))) {
  1167. /* Do nothing if pending disable or already disabled */
  1168. } else if (is_promisc_enable(rxf->rxmode_pending,
  1169. rxf->rxmode_pending_bitmask)) {
  1170. /* Turn off pending enable command */
  1171. promisc_inactive(rxf->rxmode_pending,
  1172. rxf->rxmode_pending_bitmask);
  1173. bna->promisc_rid = BFI_INVALID_RID;
  1174. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1175. /* Schedule disable */
  1176. promisc_disable(rxf->rxmode_pending,
  1177. rxf->rxmode_pending_bitmask);
  1178. ret = 1;
  1179. }
  1180. return ret;
  1181. }
  1182. static int
  1183. bna_rxf_allmulti_enable(struct bna_rxf *rxf)
  1184. {
  1185. int ret = 0;
  1186. if (is_allmulti_enable(rxf->rxmode_pending,
  1187. rxf->rxmode_pending_bitmask) ||
  1188. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  1189. /* Do nothing if pending enable or already enabled */
  1190. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1191. rxf->rxmode_pending_bitmask)) {
  1192. /* Turn off pending disable command */
  1193. allmulti_inactive(rxf->rxmode_pending,
  1194. rxf->rxmode_pending_bitmask);
  1195. } else {
  1196. /* Schedule enable */
  1197. allmulti_enable(rxf->rxmode_pending,
  1198. rxf->rxmode_pending_bitmask);
  1199. ret = 1;
  1200. }
  1201. return ret;
  1202. }
  1203. static int
  1204. bna_rxf_allmulti_disable(struct bna_rxf *rxf)
  1205. {
  1206. int ret = 0;
  1207. if (is_allmulti_disable(rxf->rxmode_pending,
  1208. rxf->rxmode_pending_bitmask) ||
  1209. (!(rxf->rxmode_active & BNA_RXMODE_ALLMULTI))) {
  1210. /* Do nothing if pending disable or already disabled */
  1211. } else if (is_allmulti_enable(rxf->rxmode_pending,
  1212. rxf->rxmode_pending_bitmask)) {
  1213. /* Turn off pending enable command */
  1214. allmulti_inactive(rxf->rxmode_pending,
  1215. rxf->rxmode_pending_bitmask);
  1216. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1217. /* Schedule disable */
  1218. allmulti_disable(rxf->rxmode_pending,
  1219. rxf->rxmode_pending_bitmask);
  1220. ret = 1;
  1221. }
  1222. return ret;
  1223. }
  1224. static int
  1225. bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf)
  1226. {
  1227. if (rxf->vlan_strip_pending) {
  1228. rxf->vlan_strip_pending = false;
  1229. bna_bfi_vlan_strip_enable(rxf);
  1230. return 1;
  1231. }
  1232. return 0;
  1233. }
  1234. /* RX */
  1235. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1236. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1237. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1238. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1239. #define call_rx_stop_cbfn(rx) \
  1240. do { \
  1241. if ((rx)->stop_cbfn) { \
  1242. void (*cbfn)(void *, struct bna_rx *); \
  1243. void *cbarg; \
  1244. cbfn = (rx)->stop_cbfn; \
  1245. cbarg = (rx)->stop_cbarg; \
  1246. (rx)->stop_cbfn = NULL; \
  1247. (rx)->stop_cbarg = NULL; \
  1248. cbfn(cbarg, rx); \
  1249. } \
  1250. } while (0)
  1251. #define call_rx_stall_cbfn(rx) \
  1252. do { \
  1253. if ((rx)->rx_stall_cbfn) \
  1254. (rx)->rx_stall_cbfn((rx)->bna->bnad, (rx)); \
  1255. } while (0)
  1256. #define bfi_enet_datapath_q_init(bfi_q, bna_qpt) \
  1257. do { \
  1258. struct bna_dma_addr cur_q_addr = \
  1259. *((struct bna_dma_addr *)((bna_qpt)->kv_qpt_ptr)); \
  1260. (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
  1261. (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
  1262. (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
  1263. (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
  1264. (bfi_q)->pages = htons((u16)(bna_qpt)->page_count); \
  1265. (bfi_q)->page_sz = htons((u16)(bna_qpt)->page_size);\
  1266. } while (0)
  1267. static void bna_bfi_rx_enet_start(struct bna_rx *rx);
  1268. static void bna_rx_enet_stop(struct bna_rx *rx);
  1269. static void bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx);
  1270. bfa_fsm_state_decl(bna_rx, stopped,
  1271. struct bna_rx, enum bna_rx_event);
  1272. bfa_fsm_state_decl(bna_rx, start_wait,
  1273. struct bna_rx, enum bna_rx_event);
  1274. bfa_fsm_state_decl(bna_rx, start_stop_wait,
  1275. struct bna_rx, enum bna_rx_event);
  1276. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1277. struct bna_rx, enum bna_rx_event);
  1278. bfa_fsm_state_decl(bna_rx, started,
  1279. struct bna_rx, enum bna_rx_event);
  1280. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1281. struct bna_rx, enum bna_rx_event);
  1282. bfa_fsm_state_decl(bna_rx, stop_wait,
  1283. struct bna_rx, enum bna_rx_event);
  1284. bfa_fsm_state_decl(bna_rx, cleanup_wait,
  1285. struct bna_rx, enum bna_rx_event);
  1286. bfa_fsm_state_decl(bna_rx, failed,
  1287. struct bna_rx, enum bna_rx_event);
  1288. bfa_fsm_state_decl(bna_rx, quiesce_wait,
  1289. struct bna_rx, enum bna_rx_event);
  1290. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1291. {
  1292. call_rx_stop_cbfn(rx);
  1293. }
  1294. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1295. enum bna_rx_event event)
  1296. {
  1297. switch (event) {
  1298. case RX_E_START:
  1299. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1300. break;
  1301. case RX_E_STOP:
  1302. call_rx_stop_cbfn(rx);
  1303. break;
  1304. case RX_E_FAIL:
  1305. /* no-op */
  1306. break;
  1307. default:
  1308. bfa_sm_fault(event);
  1309. break;
  1310. }
  1311. }
  1312. static void bna_rx_sm_start_wait_entry(struct bna_rx *rx)
  1313. {
  1314. bna_bfi_rx_enet_start(rx);
  1315. }
  1316. static void
  1317. bna_rx_sm_stop_wait_entry(struct bna_rx *rx)
  1318. {
  1319. }
  1320. static void
  1321. bna_rx_sm_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1322. {
  1323. switch (event) {
  1324. case RX_E_FAIL:
  1325. case RX_E_STOPPED:
  1326. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1327. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1328. break;
  1329. case RX_E_STARTED:
  1330. bna_rx_enet_stop(rx);
  1331. break;
  1332. default:
  1333. bfa_sm_fault(event);
  1334. break;
  1335. }
  1336. }
  1337. static void bna_rx_sm_start_wait(struct bna_rx *rx,
  1338. enum bna_rx_event event)
  1339. {
  1340. switch (event) {
  1341. case RX_E_STOP:
  1342. bfa_fsm_set_state(rx, bna_rx_sm_start_stop_wait);
  1343. break;
  1344. case RX_E_FAIL:
  1345. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1346. break;
  1347. case RX_E_STARTED:
  1348. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1349. break;
  1350. default:
  1351. bfa_sm_fault(event);
  1352. break;
  1353. }
  1354. }
  1355. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1356. {
  1357. rx->rx_post_cbfn(rx->bna->bnad, rx);
  1358. bna_rxf_start(&rx->rxf);
  1359. }
  1360. static void
  1361. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1362. {
  1363. }
  1364. static void
  1365. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1366. {
  1367. switch (event) {
  1368. case RX_E_FAIL:
  1369. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1370. bna_rxf_fail(&rx->rxf);
  1371. call_rx_stall_cbfn(rx);
  1372. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1373. break;
  1374. case RX_E_RXF_STARTED:
  1375. bna_rxf_stop(&rx->rxf);
  1376. break;
  1377. case RX_E_RXF_STOPPED:
  1378. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1379. call_rx_stall_cbfn(rx);
  1380. bna_rx_enet_stop(rx);
  1381. break;
  1382. default:
  1383. bfa_sm_fault(event);
  1384. break;
  1385. }
  1386. }
  1387. static void
  1388. bna_rx_sm_start_stop_wait_entry(struct bna_rx *rx)
  1389. {
  1390. }
  1391. static void
  1392. bna_rx_sm_start_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1393. {
  1394. switch (event) {
  1395. case RX_E_FAIL:
  1396. case RX_E_STOPPED:
  1397. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1398. break;
  1399. case RX_E_STARTED:
  1400. bna_rx_enet_stop(rx);
  1401. break;
  1402. default:
  1403. bfa_sm_fault(event);
  1404. }
  1405. }
  1406. static void
  1407. bna_rx_sm_started_entry(struct bna_rx *rx)
  1408. {
  1409. struct bna_rxp *rxp;
  1410. struct list_head *qe_rxp;
  1411. int is_regular = (rx->type == BNA_RX_T_REGULAR);
  1412. /* Start IB */
  1413. list_for_each(qe_rxp, &rx->rxp_q) {
  1414. rxp = (struct bna_rxp *)qe_rxp;
  1415. bna_ib_start(rx->bna, &rxp->cq.ib, is_regular);
  1416. }
  1417. bna_ethport_cb_rx_started(&rx->bna->ethport);
  1418. }
  1419. static void
  1420. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1421. {
  1422. switch (event) {
  1423. case RX_E_STOP:
  1424. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1425. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1426. bna_rxf_stop(&rx->rxf);
  1427. break;
  1428. case RX_E_FAIL:
  1429. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1430. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1431. bna_rxf_fail(&rx->rxf);
  1432. call_rx_stall_cbfn(rx);
  1433. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1434. break;
  1435. default:
  1436. bfa_sm_fault(event);
  1437. break;
  1438. }
  1439. }
  1440. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1441. enum bna_rx_event event)
  1442. {
  1443. switch (event) {
  1444. case RX_E_STOP:
  1445. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1446. break;
  1447. case RX_E_FAIL:
  1448. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1449. bna_rxf_fail(&rx->rxf);
  1450. call_rx_stall_cbfn(rx);
  1451. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1452. break;
  1453. case RX_E_RXF_STARTED:
  1454. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1455. break;
  1456. default:
  1457. bfa_sm_fault(event);
  1458. break;
  1459. }
  1460. }
  1461. static void
  1462. bna_rx_sm_cleanup_wait_entry(struct bna_rx *rx)
  1463. {
  1464. }
  1465. static void
  1466. bna_rx_sm_cleanup_wait(struct bna_rx *rx, enum bna_rx_event event)
  1467. {
  1468. switch (event) {
  1469. case RX_E_FAIL:
  1470. case RX_E_RXF_STOPPED:
  1471. /* No-op */
  1472. break;
  1473. case RX_E_CLEANUP_DONE:
  1474. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1475. break;
  1476. default:
  1477. bfa_sm_fault(event);
  1478. break;
  1479. }
  1480. }
  1481. static void
  1482. bna_rx_sm_failed_entry(struct bna_rx *rx)
  1483. {
  1484. }
  1485. static void
  1486. bna_rx_sm_failed(struct bna_rx *rx, enum bna_rx_event event)
  1487. {
  1488. switch (event) {
  1489. case RX_E_START:
  1490. bfa_fsm_set_state(rx, bna_rx_sm_quiesce_wait);
  1491. break;
  1492. case RX_E_STOP:
  1493. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1494. break;
  1495. case RX_E_FAIL:
  1496. case RX_E_RXF_STARTED:
  1497. case RX_E_RXF_STOPPED:
  1498. /* No-op */
  1499. break;
  1500. case RX_E_CLEANUP_DONE:
  1501. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1502. break;
  1503. default:
  1504. bfa_sm_fault(event);
  1505. break;
  1506. } }
  1507. static void
  1508. bna_rx_sm_quiesce_wait_entry(struct bna_rx *rx)
  1509. {
  1510. }
  1511. static void
  1512. bna_rx_sm_quiesce_wait(struct bna_rx *rx, enum bna_rx_event event)
  1513. {
  1514. switch (event) {
  1515. case RX_E_STOP:
  1516. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1517. break;
  1518. case RX_E_FAIL:
  1519. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1520. break;
  1521. case RX_E_CLEANUP_DONE:
  1522. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1523. break;
  1524. default:
  1525. bfa_sm_fault(event);
  1526. break;
  1527. }
  1528. }
  1529. static void
  1530. bna_bfi_rx_enet_start(struct bna_rx *rx)
  1531. {
  1532. struct bfi_enet_rx_cfg_req *cfg_req = &rx->bfi_enet_cmd.cfg_req;
  1533. struct bna_rxp *rxp = NULL;
  1534. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1535. struct list_head *rxp_qe;
  1536. int i;
  1537. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  1538. BFI_ENET_H2I_RX_CFG_SET_REQ, 0, rx->rid);
  1539. cfg_req->mh.num_entries = htons(
  1540. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_cfg_req)));
  1541. cfg_req->rx_cfg.frame_size = bna_enet_mtu_get(&rx->bna->enet);
  1542. cfg_req->num_queue_sets = rx->num_paths;
  1543. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1544. i < rx->num_paths;
  1545. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1546. rxp = (struct bna_rxp *)rxp_qe;
  1547. GET_RXQS(rxp, q0, q1);
  1548. switch (rxp->type) {
  1549. case BNA_RXP_SLR:
  1550. case BNA_RXP_HDS:
  1551. /* Small RxQ */
  1552. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].qs.q,
  1553. &q1->qpt);
  1554. cfg_req->q_cfg[i].qs.rx_buffer_size =
  1555. htons((u16)q1->buffer_size);
  1556. /* Fall through */
  1557. case BNA_RXP_SINGLE:
  1558. /* Large/Single RxQ */
  1559. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].ql.q,
  1560. &q0->qpt);
  1561. if (q0->multi_buffer)
  1562. /* multi-buffer is enabled by allocating
  1563. * a new rx with new set of resources.
  1564. * q0->buffer_size should be initialized to
  1565. * fragment size.
  1566. */
  1567. cfg_req->rx_cfg.multi_buffer =
  1568. BNA_STATUS_T_ENABLED;
  1569. else
  1570. q0->buffer_size =
  1571. bna_enet_mtu_get(&rx->bna->enet);
  1572. cfg_req->q_cfg[i].ql.rx_buffer_size =
  1573. htons((u16)q0->buffer_size);
  1574. break;
  1575. default:
  1576. BUG_ON(1);
  1577. }
  1578. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].cq.q,
  1579. &rxp->cq.qpt);
  1580. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  1581. rxp->cq.ib.ib_seg_host_addr.lsb;
  1582. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  1583. rxp->cq.ib.ib_seg_host_addr.msb;
  1584. cfg_req->q_cfg[i].ib.intr.msix_index =
  1585. htons((u16)rxp->cq.ib.intr_vector);
  1586. }
  1587. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_DISABLED;
  1588. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  1589. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  1590. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_DISABLED;
  1591. cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
  1592. ? BNA_STATUS_T_ENABLED :
  1593. BNA_STATUS_T_DISABLED;
  1594. cfg_req->ib_cfg.coalescing_timeout =
  1595. htonl((u32)rxp->cq.ib.coalescing_timeo);
  1596. cfg_req->ib_cfg.inter_pkt_timeout =
  1597. htonl((u32)rxp->cq.ib.interpkt_timeo);
  1598. cfg_req->ib_cfg.inter_pkt_count = (u8)rxp->cq.ib.interpkt_count;
  1599. switch (rxp->type) {
  1600. case BNA_RXP_SLR:
  1601. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_LARGE_SMALL;
  1602. break;
  1603. case BNA_RXP_HDS:
  1604. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_HDS;
  1605. cfg_req->rx_cfg.hds.type = rx->hds_cfg.hdr_type;
  1606. cfg_req->rx_cfg.hds.force_offset = rx->hds_cfg.forced_offset;
  1607. cfg_req->rx_cfg.hds.max_header_size = rx->hds_cfg.forced_offset;
  1608. break;
  1609. case BNA_RXP_SINGLE:
  1610. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_SINGLE;
  1611. break;
  1612. default:
  1613. BUG_ON(1);
  1614. }
  1615. cfg_req->rx_cfg.strip_vlan = rx->rxf.vlan_strip_status;
  1616. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL,
  1617. sizeof(struct bfi_enet_rx_cfg_req), &cfg_req->mh);
  1618. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1619. }
  1620. static void
  1621. bna_bfi_rx_enet_stop(struct bna_rx *rx)
  1622. {
  1623. struct bfi_enet_req *req = &rx->bfi_enet_cmd.req;
  1624. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  1625. BFI_ENET_H2I_RX_CFG_CLR_REQ, 0, rx->rid);
  1626. req->mh.num_entries = htons(
  1627. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  1628. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  1629. &req->mh);
  1630. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1631. }
  1632. static void
  1633. bna_rx_enet_stop(struct bna_rx *rx)
  1634. {
  1635. struct bna_rxp *rxp;
  1636. struct list_head *qe_rxp;
  1637. /* Stop IB */
  1638. list_for_each(qe_rxp, &rx->rxp_q) {
  1639. rxp = (struct bna_rxp *)qe_rxp;
  1640. bna_ib_stop(rx->bna, &rxp->cq.ib);
  1641. }
  1642. bna_bfi_rx_enet_stop(rx);
  1643. }
  1644. static int
  1645. bna_rx_res_check(struct bna_rx_mod *rx_mod, struct bna_rx_config *rx_cfg)
  1646. {
  1647. if ((rx_mod->rx_free_count == 0) ||
  1648. (rx_mod->rxp_free_count == 0) ||
  1649. (rx_mod->rxq_free_count == 0))
  1650. return 0;
  1651. if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
  1652. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1653. (rx_mod->rxq_free_count < rx_cfg->num_paths))
  1654. return 0;
  1655. } else {
  1656. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1657. (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
  1658. return 0;
  1659. }
  1660. return 1;
  1661. }
  1662. static struct bna_rxq *
  1663. bna_rxq_get(struct bna_rx_mod *rx_mod)
  1664. {
  1665. struct bna_rxq *rxq = NULL;
  1666. struct list_head *qe = NULL;
  1667. bfa_q_deq(&rx_mod->rxq_free_q, &qe);
  1668. rx_mod->rxq_free_count--;
  1669. rxq = (struct bna_rxq *)qe;
  1670. bfa_q_qe_init(&rxq->qe);
  1671. return rxq;
  1672. }
  1673. static void
  1674. bna_rxq_put(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
  1675. {
  1676. bfa_q_qe_init(&rxq->qe);
  1677. list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
  1678. rx_mod->rxq_free_count++;
  1679. }
  1680. static struct bna_rxp *
  1681. bna_rxp_get(struct bna_rx_mod *rx_mod)
  1682. {
  1683. struct list_head *qe = NULL;
  1684. struct bna_rxp *rxp = NULL;
  1685. bfa_q_deq(&rx_mod->rxp_free_q, &qe);
  1686. rx_mod->rxp_free_count--;
  1687. rxp = (struct bna_rxp *)qe;
  1688. bfa_q_qe_init(&rxp->qe);
  1689. return rxp;
  1690. }
  1691. static void
  1692. bna_rxp_put(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
  1693. {
  1694. bfa_q_qe_init(&rxp->qe);
  1695. list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
  1696. rx_mod->rxp_free_count++;
  1697. }
  1698. static struct bna_rx *
  1699. bna_rx_get(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1700. {
  1701. struct list_head *qe = NULL;
  1702. struct bna_rx *rx = NULL;
  1703. if (type == BNA_RX_T_REGULAR) {
  1704. bfa_q_deq(&rx_mod->rx_free_q, &qe);
  1705. } else
  1706. bfa_q_deq_tail(&rx_mod->rx_free_q, &qe);
  1707. rx_mod->rx_free_count--;
  1708. rx = (struct bna_rx *)qe;
  1709. bfa_q_qe_init(&rx->qe);
  1710. list_add_tail(&rx->qe, &rx_mod->rx_active_q);
  1711. rx->type = type;
  1712. return rx;
  1713. }
  1714. static void
  1715. bna_rx_put(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
  1716. {
  1717. struct list_head *prev_qe = NULL;
  1718. struct list_head *qe;
  1719. bfa_q_qe_init(&rx->qe);
  1720. list_for_each(qe, &rx_mod->rx_free_q) {
  1721. if (((struct bna_rx *)qe)->rid < rx->rid)
  1722. prev_qe = qe;
  1723. else
  1724. break;
  1725. }
  1726. if (prev_qe == NULL) {
  1727. /* This is the first entry */
  1728. bfa_q_enq_head(&rx_mod->rx_free_q, &rx->qe);
  1729. } else if (bfa_q_next(prev_qe) == &rx_mod->rx_free_q) {
  1730. /* This is the last entry */
  1731. list_add_tail(&rx->qe, &rx_mod->rx_free_q);
  1732. } else {
  1733. /* Somewhere in the middle */
  1734. bfa_q_next(&rx->qe) = bfa_q_next(prev_qe);
  1735. bfa_q_prev(&rx->qe) = prev_qe;
  1736. bfa_q_next(prev_qe) = &rx->qe;
  1737. bfa_q_prev(bfa_q_next(&rx->qe)) = &rx->qe;
  1738. }
  1739. rx_mod->rx_free_count++;
  1740. }
  1741. static void
  1742. bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0,
  1743. struct bna_rxq *q1)
  1744. {
  1745. switch (rxp->type) {
  1746. case BNA_RXP_SINGLE:
  1747. rxp->rxq.single.only = q0;
  1748. rxp->rxq.single.reserved = NULL;
  1749. break;
  1750. case BNA_RXP_SLR:
  1751. rxp->rxq.slr.large = q0;
  1752. rxp->rxq.slr.small = q1;
  1753. break;
  1754. case BNA_RXP_HDS:
  1755. rxp->rxq.hds.data = q0;
  1756. rxp->rxq.hds.hdr = q1;
  1757. break;
  1758. default:
  1759. break;
  1760. }
  1761. }
  1762. static void
  1763. bna_rxq_qpt_setup(struct bna_rxq *rxq,
  1764. struct bna_rxp *rxp,
  1765. u32 page_count,
  1766. u32 page_size,
  1767. struct bna_mem_descr *qpt_mem,
  1768. struct bna_mem_descr *swqpt_mem,
  1769. struct bna_mem_descr *page_mem)
  1770. {
  1771. u8 *kva;
  1772. u64 dma;
  1773. struct bna_dma_addr bna_dma;
  1774. int i;
  1775. rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1776. rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1777. rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
  1778. rxq->qpt.page_count = page_count;
  1779. rxq->qpt.page_size = page_size;
  1780. rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
  1781. rxq->rcb->sw_q = page_mem->kva;
  1782. kva = page_mem->kva;
  1783. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1784. for (i = 0; i < rxq->qpt.page_count; i++) {
  1785. rxq->rcb->sw_qpt[i] = kva;
  1786. kva += PAGE_SIZE;
  1787. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1788. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
  1789. bna_dma.lsb;
  1790. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
  1791. bna_dma.msb;
  1792. dma += PAGE_SIZE;
  1793. }
  1794. }
  1795. static void
  1796. bna_rxp_cqpt_setup(struct bna_rxp *rxp,
  1797. u32 page_count,
  1798. u32 page_size,
  1799. struct bna_mem_descr *qpt_mem,
  1800. struct bna_mem_descr *swqpt_mem,
  1801. struct bna_mem_descr *page_mem)
  1802. {
  1803. u8 *kva;
  1804. u64 dma;
  1805. struct bna_dma_addr bna_dma;
  1806. int i;
  1807. rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1808. rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1809. rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
  1810. rxp->cq.qpt.page_count = page_count;
  1811. rxp->cq.qpt.page_size = page_size;
  1812. rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
  1813. rxp->cq.ccb->sw_q = page_mem->kva;
  1814. kva = page_mem->kva;
  1815. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1816. for (i = 0; i < rxp->cq.qpt.page_count; i++) {
  1817. rxp->cq.ccb->sw_qpt[i] = kva;
  1818. kva += PAGE_SIZE;
  1819. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1820. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
  1821. bna_dma.lsb;
  1822. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
  1823. bna_dma.msb;
  1824. dma += PAGE_SIZE;
  1825. }
  1826. }
  1827. static void
  1828. bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx)
  1829. {
  1830. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1831. bfa_wc_down(&rx_mod->rx_stop_wc);
  1832. }
  1833. static void
  1834. bna_rx_mod_cb_rx_stopped_all(void *arg)
  1835. {
  1836. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1837. if (rx_mod->stop_cbfn)
  1838. rx_mod->stop_cbfn(&rx_mod->bna->enet);
  1839. rx_mod->stop_cbfn = NULL;
  1840. }
  1841. static void
  1842. bna_rx_start(struct bna_rx *rx)
  1843. {
  1844. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1845. if (rx->rx_flags & BNA_RX_F_ENABLED)
  1846. bfa_fsm_send_event(rx, RX_E_START);
  1847. }
  1848. static void
  1849. bna_rx_stop(struct bna_rx *rx)
  1850. {
  1851. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1852. if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
  1853. bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx);
  1854. else {
  1855. rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
  1856. rx->stop_cbarg = &rx->bna->rx_mod;
  1857. bfa_fsm_send_event(rx, RX_E_STOP);
  1858. }
  1859. }
  1860. static void
  1861. bna_rx_fail(struct bna_rx *rx)
  1862. {
  1863. /* Indicate Enet is not enabled, and failed */
  1864. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1865. bfa_fsm_send_event(rx, RX_E_FAIL);
  1866. }
  1867. void
  1868. bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1869. {
  1870. struct bna_rx *rx;
  1871. struct list_head *qe;
  1872. rx_mod->flags |= BNA_RX_MOD_F_ENET_STARTED;
  1873. if (type == BNA_RX_T_LOOPBACK)
  1874. rx_mod->flags |= BNA_RX_MOD_F_ENET_LOOPBACK;
  1875. list_for_each(qe, &rx_mod->rx_active_q) {
  1876. rx = (struct bna_rx *)qe;
  1877. if (rx->type == type)
  1878. bna_rx_start(rx);
  1879. }
  1880. }
  1881. void
  1882. bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1883. {
  1884. struct bna_rx *rx;
  1885. struct list_head *qe;
  1886. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1887. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1888. rx_mod->stop_cbfn = bna_enet_cb_rx_stopped;
  1889. bfa_wc_init(&rx_mod->rx_stop_wc, bna_rx_mod_cb_rx_stopped_all, rx_mod);
  1890. list_for_each(qe, &rx_mod->rx_active_q) {
  1891. rx = (struct bna_rx *)qe;
  1892. if (rx->type == type) {
  1893. bfa_wc_up(&rx_mod->rx_stop_wc);
  1894. bna_rx_stop(rx);
  1895. }
  1896. }
  1897. bfa_wc_wait(&rx_mod->rx_stop_wc);
  1898. }
  1899. void
  1900. bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
  1901. {
  1902. struct bna_rx *rx;
  1903. struct list_head *qe;
  1904. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1905. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1906. list_for_each(qe, &rx_mod->rx_active_q) {
  1907. rx = (struct bna_rx *)qe;
  1908. bna_rx_fail(rx);
  1909. }
  1910. }
  1911. void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
  1912. struct bna_res_info *res_info)
  1913. {
  1914. int index;
  1915. struct bna_rx *rx_ptr;
  1916. struct bna_rxp *rxp_ptr;
  1917. struct bna_rxq *rxq_ptr;
  1918. rx_mod->bna = bna;
  1919. rx_mod->flags = 0;
  1920. rx_mod->rx = (struct bna_rx *)
  1921. res_info[BNA_MOD_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
  1922. rx_mod->rxp = (struct bna_rxp *)
  1923. res_info[BNA_MOD_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
  1924. rx_mod->rxq = (struct bna_rxq *)
  1925. res_info[BNA_MOD_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  1926. /* Initialize the queues */
  1927. INIT_LIST_HEAD(&rx_mod->rx_free_q);
  1928. rx_mod->rx_free_count = 0;
  1929. INIT_LIST_HEAD(&rx_mod->rxq_free_q);
  1930. rx_mod->rxq_free_count = 0;
  1931. INIT_LIST_HEAD(&rx_mod->rxp_free_q);
  1932. rx_mod->rxp_free_count = 0;
  1933. INIT_LIST_HEAD(&rx_mod->rx_active_q);
  1934. /* Build RX queues */
  1935. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1936. rx_ptr = &rx_mod->rx[index];
  1937. bfa_q_qe_init(&rx_ptr->qe);
  1938. INIT_LIST_HEAD(&rx_ptr->rxp_q);
  1939. rx_ptr->bna = NULL;
  1940. rx_ptr->rid = index;
  1941. rx_ptr->stop_cbfn = NULL;
  1942. rx_ptr->stop_cbarg = NULL;
  1943. list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
  1944. rx_mod->rx_free_count++;
  1945. }
  1946. /* build RX-path queue */
  1947. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1948. rxp_ptr = &rx_mod->rxp[index];
  1949. bfa_q_qe_init(&rxp_ptr->qe);
  1950. list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
  1951. rx_mod->rxp_free_count++;
  1952. }
  1953. /* build RXQ queue */
  1954. for (index = 0; index < (bna->ioceth.attr.num_rxp * 2); index++) {
  1955. rxq_ptr = &rx_mod->rxq[index];
  1956. bfa_q_qe_init(&rxq_ptr->qe);
  1957. list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
  1958. rx_mod->rxq_free_count++;
  1959. }
  1960. }
  1961. void
  1962. bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
  1963. {
  1964. struct list_head *qe;
  1965. int i;
  1966. i = 0;
  1967. list_for_each(qe, &rx_mod->rx_free_q)
  1968. i++;
  1969. i = 0;
  1970. list_for_each(qe, &rx_mod->rxp_free_q)
  1971. i++;
  1972. i = 0;
  1973. list_for_each(qe, &rx_mod->rxq_free_q)
  1974. i++;
  1975. rx_mod->bna = NULL;
  1976. }
  1977. void
  1978. bna_bfi_rx_enet_start_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1979. {
  1980. struct bfi_enet_rx_cfg_rsp *cfg_rsp = &rx->bfi_enet_cmd.cfg_rsp;
  1981. struct bna_rxp *rxp = NULL;
  1982. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1983. struct list_head *rxp_qe;
  1984. int i;
  1985. bfa_msgq_rsp_copy(&rx->bna->msgq, (u8 *)cfg_rsp,
  1986. sizeof(struct bfi_enet_rx_cfg_rsp));
  1987. rx->hw_id = cfg_rsp->hw_id;
  1988. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1989. i < rx->num_paths;
  1990. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1991. rxp = (struct bna_rxp *)rxp_qe;
  1992. GET_RXQS(rxp, q0, q1);
  1993. /* Setup doorbells */
  1994. rxp->cq.ccb->i_dbell->doorbell_addr =
  1995. rx->bna->pcidev.pci_bar_kva
  1996. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  1997. rxp->hw_id = cfg_rsp->q_handles[i].hw_cqid;
  1998. q0->rcb->q_dbell =
  1999. rx->bna->pcidev.pci_bar_kva
  2000. + ntohl(cfg_rsp->q_handles[i].ql_dbell);
  2001. q0->hw_id = cfg_rsp->q_handles[i].hw_lqid;
  2002. if (q1) {
  2003. q1->rcb->q_dbell =
  2004. rx->bna->pcidev.pci_bar_kva
  2005. + ntohl(cfg_rsp->q_handles[i].qs_dbell);
  2006. q1->hw_id = cfg_rsp->q_handles[i].hw_sqid;
  2007. }
  2008. /* Initialize producer/consumer indexes */
  2009. (*rxp->cq.ccb->hw_producer_index) = 0;
  2010. rxp->cq.ccb->producer_index = 0;
  2011. q0->rcb->producer_index = q0->rcb->consumer_index = 0;
  2012. if (q1)
  2013. q1->rcb->producer_index = q1->rcb->consumer_index = 0;
  2014. }
  2015. bfa_fsm_send_event(rx, RX_E_STARTED);
  2016. }
  2017. void
  2018. bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  2019. {
  2020. bfa_fsm_send_event(rx, RX_E_STOPPED);
  2021. }
  2022. void
  2023. bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
  2024. {
  2025. u32 cq_size, hq_size, dq_size;
  2026. u32 cpage_count, hpage_count, dpage_count;
  2027. struct bna_mem_info *mem_info;
  2028. u32 cq_depth;
  2029. u32 hq_depth;
  2030. u32 dq_depth;
  2031. dq_depth = q_cfg->q0_depth;
  2032. hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q1_depth);
  2033. cq_depth = dq_depth + hq_depth;
  2034. BNA_TO_POWER_OF_2_HIGH(cq_depth);
  2035. cq_size = cq_depth * BFI_CQ_WI_SIZE;
  2036. cq_size = ALIGN(cq_size, PAGE_SIZE);
  2037. cpage_count = SIZE_TO_PAGES(cq_size);
  2038. BNA_TO_POWER_OF_2_HIGH(dq_depth);
  2039. dq_size = dq_depth * BFI_RXQ_WI_SIZE;
  2040. dq_size = ALIGN(dq_size, PAGE_SIZE);
  2041. dpage_count = SIZE_TO_PAGES(dq_size);
  2042. if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
  2043. BNA_TO_POWER_OF_2_HIGH(hq_depth);
  2044. hq_size = hq_depth * BFI_RXQ_WI_SIZE;
  2045. hq_size = ALIGN(hq_size, PAGE_SIZE);
  2046. hpage_count = SIZE_TO_PAGES(hq_size);
  2047. } else
  2048. hpage_count = 0;
  2049. res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
  2050. mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
  2051. mem_info->mem_type = BNA_MEM_T_KVA;
  2052. mem_info->len = sizeof(struct bna_ccb);
  2053. mem_info->num = q_cfg->num_paths;
  2054. res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
  2055. mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
  2056. mem_info->mem_type = BNA_MEM_T_KVA;
  2057. mem_info->len = sizeof(struct bna_rcb);
  2058. mem_info->num = BNA_GET_RXQS(q_cfg);
  2059. res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
  2060. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
  2061. mem_info->mem_type = BNA_MEM_T_DMA;
  2062. mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
  2063. mem_info->num = q_cfg->num_paths;
  2064. res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
  2065. mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
  2066. mem_info->mem_type = BNA_MEM_T_KVA;
  2067. mem_info->len = cpage_count * sizeof(void *);
  2068. mem_info->num = q_cfg->num_paths;
  2069. res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
  2070. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
  2071. mem_info->mem_type = BNA_MEM_T_DMA;
  2072. mem_info->len = PAGE_SIZE * cpage_count;
  2073. mem_info->num = q_cfg->num_paths;
  2074. res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
  2075. mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
  2076. mem_info->mem_type = BNA_MEM_T_DMA;
  2077. mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
  2078. mem_info->num = q_cfg->num_paths;
  2079. res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
  2080. mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
  2081. mem_info->mem_type = BNA_MEM_T_KVA;
  2082. mem_info->len = dpage_count * sizeof(void *);
  2083. mem_info->num = q_cfg->num_paths;
  2084. res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
  2085. mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
  2086. mem_info->mem_type = BNA_MEM_T_DMA;
  2087. mem_info->len = PAGE_SIZE * dpage_count;
  2088. mem_info->num = q_cfg->num_paths;
  2089. res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
  2090. mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
  2091. mem_info->mem_type = BNA_MEM_T_DMA;
  2092. mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
  2093. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  2094. res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
  2095. mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
  2096. mem_info->mem_type = BNA_MEM_T_KVA;
  2097. mem_info->len = hpage_count * sizeof(void *);
  2098. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  2099. res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
  2100. mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
  2101. mem_info->mem_type = BNA_MEM_T_DMA;
  2102. mem_info->len = PAGE_SIZE * hpage_count;
  2103. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  2104. res_info[BNA_RX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2105. mem_info = &res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info;
  2106. mem_info->mem_type = BNA_MEM_T_DMA;
  2107. mem_info->len = BFI_IBIDX_SIZE;
  2108. mem_info->num = q_cfg->num_paths;
  2109. res_info[BNA_RX_RES_MEM_T_RIT].res_type = BNA_RES_T_MEM;
  2110. mem_info = &res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info;
  2111. mem_info->mem_type = BNA_MEM_T_KVA;
  2112. mem_info->len = BFI_ENET_RSS_RIT_MAX;
  2113. mem_info->num = 1;
  2114. res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
  2115. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
  2116. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
  2117. }
  2118. struct bna_rx *
  2119. bna_rx_create(struct bna *bna, struct bnad *bnad,
  2120. struct bna_rx_config *rx_cfg,
  2121. const struct bna_rx_event_cbfn *rx_cbfn,
  2122. struct bna_res_info *res_info,
  2123. void *priv)
  2124. {
  2125. struct bna_rx_mod *rx_mod = &bna->rx_mod;
  2126. struct bna_rx *rx;
  2127. struct bna_rxp *rxp;
  2128. struct bna_rxq *q0;
  2129. struct bna_rxq *q1;
  2130. struct bna_intr_info *intr_info;
  2131. struct bna_mem_descr *hqunmap_mem;
  2132. struct bna_mem_descr *dqunmap_mem;
  2133. struct bna_mem_descr *ccb_mem;
  2134. struct bna_mem_descr *rcb_mem;
  2135. struct bna_mem_descr *cqpt_mem;
  2136. struct bna_mem_descr *cswqpt_mem;
  2137. struct bna_mem_descr *cpage_mem;
  2138. struct bna_mem_descr *hqpt_mem;
  2139. struct bna_mem_descr *dqpt_mem;
  2140. struct bna_mem_descr *hsqpt_mem;
  2141. struct bna_mem_descr *dsqpt_mem;
  2142. struct bna_mem_descr *hpage_mem;
  2143. struct bna_mem_descr *dpage_mem;
  2144. u32 dpage_count, hpage_count;
  2145. u32 hq_idx, dq_idx, rcb_idx;
  2146. u32 cq_depth, i;
  2147. u32 page_count;
  2148. if (!bna_rx_res_check(rx_mod, rx_cfg))
  2149. return NULL;
  2150. intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  2151. ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
  2152. rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
  2153. dqunmap_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPDQ].res_u.mem_info.mdl[0];
  2154. hqunmap_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPHQ].res_u.mem_info.mdl[0];
  2155. cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
  2156. cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
  2157. cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
  2158. hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
  2159. dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
  2160. hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
  2161. dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
  2162. hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
  2163. dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
  2164. page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.len /
  2165. PAGE_SIZE;
  2166. dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.len /
  2167. PAGE_SIZE;
  2168. hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.len /
  2169. PAGE_SIZE;
  2170. rx = bna_rx_get(rx_mod, rx_cfg->rx_type);
  2171. rx->bna = bna;
  2172. rx->rx_flags = 0;
  2173. INIT_LIST_HEAD(&rx->rxp_q);
  2174. rx->stop_cbfn = NULL;
  2175. rx->stop_cbarg = NULL;
  2176. rx->priv = priv;
  2177. rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
  2178. rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
  2179. rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
  2180. rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
  2181. rx->rx_stall_cbfn = rx_cbfn->rx_stall_cbfn;
  2182. /* Following callbacks are mandatory */
  2183. rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
  2184. rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
  2185. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_STARTED) {
  2186. switch (rx->type) {
  2187. case BNA_RX_T_REGULAR:
  2188. if (!(rx->bna->rx_mod.flags &
  2189. BNA_RX_MOD_F_ENET_LOOPBACK))
  2190. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2191. break;
  2192. case BNA_RX_T_LOOPBACK:
  2193. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_LOOPBACK)
  2194. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2195. break;
  2196. }
  2197. }
  2198. rx->num_paths = rx_cfg->num_paths;
  2199. for (i = 0, hq_idx = 0, dq_idx = 0, rcb_idx = 0;
  2200. i < rx->num_paths; i++) {
  2201. rxp = bna_rxp_get(rx_mod);
  2202. list_add_tail(&rxp->qe, &rx->rxp_q);
  2203. rxp->type = rx_cfg->rxp_type;
  2204. rxp->rx = rx;
  2205. rxp->cq.rx = rx;
  2206. q0 = bna_rxq_get(rx_mod);
  2207. if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
  2208. q1 = NULL;
  2209. else
  2210. q1 = bna_rxq_get(rx_mod);
  2211. if (1 == intr_info->num)
  2212. rxp->vector = intr_info->idl[0].vector;
  2213. else
  2214. rxp->vector = intr_info->idl[i].vector;
  2215. /* Setup IB */
  2216. rxp->cq.ib.ib_seg_host_addr.lsb =
  2217. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2218. rxp->cq.ib.ib_seg_host_addr.msb =
  2219. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2220. rxp->cq.ib.ib_seg_host_addr_kva =
  2221. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2222. rxp->cq.ib.intr_type = intr_info->intr_type;
  2223. if (intr_info->intr_type == BNA_INTR_T_MSIX)
  2224. rxp->cq.ib.intr_vector = rxp->vector;
  2225. else
  2226. rxp->cq.ib.intr_vector = (1 << rxp->vector);
  2227. rxp->cq.ib.coalescing_timeo = rx_cfg->coalescing_timeo;
  2228. rxp->cq.ib.interpkt_count = BFI_RX_INTERPKT_COUNT;
  2229. rxp->cq.ib.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
  2230. bna_rxp_add_rxqs(rxp, q0, q1);
  2231. /* Setup large Q */
  2232. q0->rx = rx;
  2233. q0->rxp = rxp;
  2234. q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2235. q0->rcb->unmap_q = (void *)dqunmap_mem[dq_idx].kva;
  2236. rcb_idx++; dq_idx++;
  2237. q0->rcb->q_depth = rx_cfg->q0_depth;
  2238. q0->q_depth = rx_cfg->q0_depth;
  2239. q0->multi_buffer = rx_cfg->q0_multi_buf;
  2240. q0->buffer_size = rx_cfg->q0_buf_size;
  2241. q0->num_vecs = rx_cfg->q0_num_vecs;
  2242. q0->rcb->rxq = q0;
  2243. q0->rcb->bnad = bna->bnad;
  2244. q0->rcb->id = 0;
  2245. q0->rx_packets = q0->rx_bytes = 0;
  2246. q0->rx_packets_with_error = q0->rxbuf_alloc_failed = 0;
  2247. bna_rxq_qpt_setup(q0, rxp, dpage_count, PAGE_SIZE,
  2248. &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[i]);
  2249. if (rx->rcb_setup_cbfn)
  2250. rx->rcb_setup_cbfn(bnad, q0->rcb);
  2251. /* Setup small Q */
  2252. if (q1) {
  2253. q1->rx = rx;
  2254. q1->rxp = rxp;
  2255. q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2256. q1->rcb->unmap_q = (void *)hqunmap_mem[hq_idx].kva;
  2257. rcb_idx++; hq_idx++;
  2258. q1->rcb->q_depth = rx_cfg->q1_depth;
  2259. q1->q_depth = rx_cfg->q1_depth;
  2260. q1->multi_buffer = BNA_STATUS_T_DISABLED;
  2261. q1->num_vecs = 1;
  2262. q1->rcb->rxq = q1;
  2263. q1->rcb->bnad = bna->bnad;
  2264. q1->rcb->id = 1;
  2265. q1->buffer_size = (rx_cfg->rxp_type == BNA_RXP_HDS) ?
  2266. rx_cfg->hds_config.forced_offset
  2267. : rx_cfg->q1_buf_size;
  2268. q1->rx_packets = q1->rx_bytes = 0;
  2269. q1->rx_packets_with_error = q1->rxbuf_alloc_failed = 0;
  2270. bna_rxq_qpt_setup(q1, rxp, hpage_count, PAGE_SIZE,
  2271. &hqpt_mem[i], &hsqpt_mem[i],
  2272. &hpage_mem[i]);
  2273. if (rx->rcb_setup_cbfn)
  2274. rx->rcb_setup_cbfn(bnad, q1->rcb);
  2275. }
  2276. /* Setup CQ */
  2277. rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
  2278. cq_depth = rx_cfg->q0_depth +
  2279. ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
  2280. 0 : rx_cfg->q1_depth);
  2281. /* if multi-buffer is enabled sum of q0_depth
  2282. * and q1_depth need not be a power of 2
  2283. */
  2284. BNA_TO_POWER_OF_2_HIGH(cq_depth);
  2285. rxp->cq.ccb->q_depth = cq_depth;
  2286. rxp->cq.ccb->cq = &rxp->cq;
  2287. rxp->cq.ccb->rcb[0] = q0->rcb;
  2288. q0->rcb->ccb = rxp->cq.ccb;
  2289. if (q1) {
  2290. rxp->cq.ccb->rcb[1] = q1->rcb;
  2291. q1->rcb->ccb = rxp->cq.ccb;
  2292. }
  2293. rxp->cq.ccb->hw_producer_index =
  2294. (u32 *)rxp->cq.ib.ib_seg_host_addr_kva;
  2295. rxp->cq.ccb->i_dbell = &rxp->cq.ib.door_bell;
  2296. rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
  2297. rxp->cq.ccb->intr_vector = rxp->cq.ib.intr_vector;
  2298. rxp->cq.ccb->rx_coalescing_timeo =
  2299. rxp->cq.ib.coalescing_timeo;
  2300. rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
  2301. rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
  2302. rxp->cq.ccb->bnad = bna->bnad;
  2303. rxp->cq.ccb->id = i;
  2304. bna_rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
  2305. &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[i]);
  2306. if (rx->ccb_setup_cbfn)
  2307. rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
  2308. }
  2309. rx->hds_cfg = rx_cfg->hds_config;
  2310. bna_rxf_init(&rx->rxf, rx, rx_cfg, res_info);
  2311. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  2312. rx_mod->rid_mask |= (1 << rx->rid);
  2313. return rx;
  2314. }
  2315. void
  2316. bna_rx_destroy(struct bna_rx *rx)
  2317. {
  2318. struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
  2319. struct bna_rxq *q0 = NULL;
  2320. struct bna_rxq *q1 = NULL;
  2321. struct bna_rxp *rxp;
  2322. struct list_head *qe;
  2323. bna_rxf_uninit(&rx->rxf);
  2324. while (!list_empty(&rx->rxp_q)) {
  2325. bfa_q_deq(&rx->rxp_q, &rxp);
  2326. GET_RXQS(rxp, q0, q1);
  2327. if (rx->rcb_destroy_cbfn)
  2328. rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
  2329. q0->rcb = NULL;
  2330. q0->rxp = NULL;
  2331. q0->rx = NULL;
  2332. bna_rxq_put(rx_mod, q0);
  2333. if (q1) {
  2334. if (rx->rcb_destroy_cbfn)
  2335. rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
  2336. q1->rcb = NULL;
  2337. q1->rxp = NULL;
  2338. q1->rx = NULL;
  2339. bna_rxq_put(rx_mod, q1);
  2340. }
  2341. rxp->rxq.slr.large = NULL;
  2342. rxp->rxq.slr.small = NULL;
  2343. if (rx->ccb_destroy_cbfn)
  2344. rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
  2345. rxp->cq.ccb = NULL;
  2346. rxp->rx = NULL;
  2347. bna_rxp_put(rx_mod, rxp);
  2348. }
  2349. list_for_each(qe, &rx_mod->rx_active_q) {
  2350. if (qe == &rx->qe) {
  2351. list_del(&rx->qe);
  2352. bfa_q_qe_init(&rx->qe);
  2353. break;
  2354. }
  2355. }
  2356. rx_mod->rid_mask &= ~(1 << rx->rid);
  2357. rx->bna = NULL;
  2358. rx->priv = NULL;
  2359. bna_rx_put(rx_mod, rx);
  2360. }
  2361. void
  2362. bna_rx_enable(struct bna_rx *rx)
  2363. {
  2364. if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
  2365. return;
  2366. rx->rx_flags |= BNA_RX_F_ENABLED;
  2367. if (rx->rx_flags & BNA_RX_F_ENET_STARTED)
  2368. bfa_fsm_send_event(rx, RX_E_START);
  2369. }
  2370. void
  2371. bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
  2372. void (*cbfn)(void *, struct bna_rx *))
  2373. {
  2374. if (type == BNA_SOFT_CLEANUP) {
  2375. /* h/w should not be accessed. Treat we're stopped */
  2376. (*cbfn)(rx->bna->bnad, rx);
  2377. } else {
  2378. rx->stop_cbfn = cbfn;
  2379. rx->stop_cbarg = rx->bna->bnad;
  2380. rx->rx_flags &= ~BNA_RX_F_ENABLED;
  2381. bfa_fsm_send_event(rx, RX_E_STOP);
  2382. }
  2383. }
  2384. void
  2385. bna_rx_cleanup_complete(struct bna_rx *rx)
  2386. {
  2387. bfa_fsm_send_event(rx, RX_E_CLEANUP_DONE);
  2388. }
  2389. void
  2390. bna_rx_vlan_strip_enable(struct bna_rx *rx)
  2391. {
  2392. struct bna_rxf *rxf = &rx->rxf;
  2393. if (rxf->vlan_strip_status == BNA_STATUS_T_DISABLED) {
  2394. rxf->vlan_strip_status = BNA_STATUS_T_ENABLED;
  2395. rxf->vlan_strip_pending = true;
  2396. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2397. }
  2398. }
  2399. void
  2400. bna_rx_vlan_strip_disable(struct bna_rx *rx)
  2401. {
  2402. struct bna_rxf *rxf = &rx->rxf;
  2403. if (rxf->vlan_strip_status != BNA_STATUS_T_DISABLED) {
  2404. rxf->vlan_strip_status = BNA_STATUS_T_DISABLED;
  2405. rxf->vlan_strip_pending = true;
  2406. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2407. }
  2408. }
  2409. enum bna_cb_status
  2410. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2411. enum bna_rxmode bitmask,
  2412. void (*cbfn)(struct bnad *, struct bna_rx *))
  2413. {
  2414. struct bna_rxf *rxf = &rx->rxf;
  2415. int need_hw_config = 0;
  2416. /* Error checks */
  2417. if (is_promisc_enable(new_mode, bitmask)) {
  2418. /* If promisc mode is already enabled elsewhere in the system */
  2419. if ((rx->bna->promisc_rid != BFI_INVALID_RID) &&
  2420. (rx->bna->promisc_rid != rxf->rx->rid))
  2421. goto err_return;
  2422. /* If default mode is already enabled in the system */
  2423. if (rx->bna->default_mode_rid != BFI_INVALID_RID)
  2424. goto err_return;
  2425. /* Trying to enable promiscuous and default mode together */
  2426. if (is_default_enable(new_mode, bitmask))
  2427. goto err_return;
  2428. }
  2429. if (is_default_enable(new_mode, bitmask)) {
  2430. /* If default mode is already enabled elsewhere in the system */
  2431. if ((rx->bna->default_mode_rid != BFI_INVALID_RID) &&
  2432. (rx->bna->default_mode_rid != rxf->rx->rid)) {
  2433. goto err_return;
  2434. }
  2435. /* If promiscuous mode is already enabled in the system */
  2436. if (rx->bna->promisc_rid != BFI_INVALID_RID)
  2437. goto err_return;
  2438. }
  2439. /* Process the commands */
  2440. if (is_promisc_enable(new_mode, bitmask)) {
  2441. if (bna_rxf_promisc_enable(rxf))
  2442. need_hw_config = 1;
  2443. } else if (is_promisc_disable(new_mode, bitmask)) {
  2444. if (bna_rxf_promisc_disable(rxf))
  2445. need_hw_config = 1;
  2446. }
  2447. if (is_allmulti_enable(new_mode, bitmask)) {
  2448. if (bna_rxf_allmulti_enable(rxf))
  2449. need_hw_config = 1;
  2450. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2451. if (bna_rxf_allmulti_disable(rxf))
  2452. need_hw_config = 1;
  2453. }
  2454. /* Trigger h/w if needed */
  2455. if (need_hw_config) {
  2456. rxf->cam_fltr_cbfn = cbfn;
  2457. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2458. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2459. } else if (cbfn)
  2460. (*cbfn)(rx->bna->bnad, rx);
  2461. return BNA_CB_SUCCESS;
  2462. err_return:
  2463. return BNA_CB_FAIL;
  2464. }
  2465. void
  2466. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2467. {
  2468. struct bna_rxf *rxf = &rx->rxf;
  2469. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2470. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2471. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  2472. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2473. }
  2474. }
  2475. void
  2476. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2477. {
  2478. struct bna_rxp *rxp;
  2479. struct list_head *qe;
  2480. list_for_each(qe, &rx->rxp_q) {
  2481. rxp = (struct bna_rxp *)qe;
  2482. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2483. bna_ib_coalescing_timeo_set(&rxp->cq.ib, coalescing_timeo);
  2484. }
  2485. }
  2486. void
  2487. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2488. {
  2489. int i, j;
  2490. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2491. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2492. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2493. }
  2494. void
  2495. bna_rx_dim_update(struct bna_ccb *ccb)
  2496. {
  2497. struct bna *bna = ccb->cq->rx->bna;
  2498. u32 load, bias;
  2499. u32 pkt_rt, small_rt, large_rt;
  2500. u8 coalescing_timeo;
  2501. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2502. (ccb->pkt_rate.large_pkt_cnt == 0))
  2503. return;
  2504. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2505. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2506. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2507. pkt_rt = small_rt + large_rt;
  2508. if (pkt_rt < BNA_PKT_RATE_10K)
  2509. load = BNA_LOAD_T_LOW_4;
  2510. else if (pkt_rt < BNA_PKT_RATE_20K)
  2511. load = BNA_LOAD_T_LOW_3;
  2512. else if (pkt_rt < BNA_PKT_RATE_30K)
  2513. load = BNA_LOAD_T_LOW_2;
  2514. else if (pkt_rt < BNA_PKT_RATE_40K)
  2515. load = BNA_LOAD_T_LOW_1;
  2516. else if (pkt_rt < BNA_PKT_RATE_50K)
  2517. load = BNA_LOAD_T_HIGH_1;
  2518. else if (pkt_rt < BNA_PKT_RATE_60K)
  2519. load = BNA_LOAD_T_HIGH_2;
  2520. else if (pkt_rt < BNA_PKT_RATE_80K)
  2521. load = BNA_LOAD_T_HIGH_3;
  2522. else
  2523. load = BNA_LOAD_T_HIGH_4;
  2524. if (small_rt > (large_rt << 1))
  2525. bias = 0;
  2526. else
  2527. bias = 1;
  2528. ccb->pkt_rate.small_pkt_cnt = 0;
  2529. ccb->pkt_rate.large_pkt_cnt = 0;
  2530. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2531. ccb->rx_coalescing_timeo = coalescing_timeo;
  2532. /* Set it to IB */
  2533. bna_ib_coalescing_timeo_set(&ccb->cq->ib, coalescing_timeo);
  2534. }
  2535. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  2536. {12, 12},
  2537. {6, 10},
  2538. {5, 10},
  2539. {4, 8},
  2540. {3, 6},
  2541. {3, 6},
  2542. {2, 4},
  2543. {1, 2},
  2544. };
  2545. /* TX */
  2546. #define call_tx_stop_cbfn(tx) \
  2547. do { \
  2548. if ((tx)->stop_cbfn) { \
  2549. void (*cbfn)(void *, struct bna_tx *); \
  2550. void *cbarg; \
  2551. cbfn = (tx)->stop_cbfn; \
  2552. cbarg = (tx)->stop_cbarg; \
  2553. (tx)->stop_cbfn = NULL; \
  2554. (tx)->stop_cbarg = NULL; \
  2555. cbfn(cbarg, (tx)); \
  2556. } \
  2557. } while (0)
  2558. #define call_tx_prio_change_cbfn(tx) \
  2559. do { \
  2560. if ((tx)->prio_change_cbfn) { \
  2561. void (*cbfn)(struct bnad *, struct bna_tx *); \
  2562. cbfn = (tx)->prio_change_cbfn; \
  2563. (tx)->prio_change_cbfn = NULL; \
  2564. cbfn((tx)->bna->bnad, (tx)); \
  2565. } \
  2566. } while (0)
  2567. static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx);
  2568. static void bna_bfi_tx_enet_start(struct bna_tx *tx);
  2569. static void bna_tx_enet_stop(struct bna_tx *tx);
  2570. enum bna_tx_event {
  2571. TX_E_START = 1,
  2572. TX_E_STOP = 2,
  2573. TX_E_FAIL = 3,
  2574. TX_E_STARTED = 4,
  2575. TX_E_STOPPED = 5,
  2576. TX_E_PRIO_CHANGE = 6,
  2577. TX_E_CLEANUP_DONE = 7,
  2578. TX_E_BW_UPDATE = 8,
  2579. };
  2580. bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, enum bna_tx_event);
  2581. bfa_fsm_state_decl(bna_tx, start_wait, struct bna_tx, enum bna_tx_event);
  2582. bfa_fsm_state_decl(bna_tx, started, struct bna_tx, enum bna_tx_event);
  2583. bfa_fsm_state_decl(bna_tx, stop_wait, struct bna_tx, enum bna_tx_event);
  2584. bfa_fsm_state_decl(bna_tx, cleanup_wait, struct bna_tx,
  2585. enum bna_tx_event);
  2586. bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
  2587. enum bna_tx_event);
  2588. bfa_fsm_state_decl(bna_tx, prio_cleanup_wait, struct bna_tx,
  2589. enum bna_tx_event);
  2590. bfa_fsm_state_decl(bna_tx, failed, struct bna_tx, enum bna_tx_event);
  2591. bfa_fsm_state_decl(bna_tx, quiesce_wait, struct bna_tx,
  2592. enum bna_tx_event);
  2593. static void
  2594. bna_tx_sm_stopped_entry(struct bna_tx *tx)
  2595. {
  2596. call_tx_stop_cbfn(tx);
  2597. }
  2598. static void
  2599. bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
  2600. {
  2601. switch (event) {
  2602. case TX_E_START:
  2603. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2604. break;
  2605. case TX_E_STOP:
  2606. call_tx_stop_cbfn(tx);
  2607. break;
  2608. case TX_E_FAIL:
  2609. /* No-op */
  2610. break;
  2611. case TX_E_PRIO_CHANGE:
  2612. call_tx_prio_change_cbfn(tx);
  2613. break;
  2614. case TX_E_BW_UPDATE:
  2615. /* No-op */
  2616. break;
  2617. default:
  2618. bfa_sm_fault(event);
  2619. }
  2620. }
  2621. static void
  2622. bna_tx_sm_start_wait_entry(struct bna_tx *tx)
  2623. {
  2624. bna_bfi_tx_enet_start(tx);
  2625. }
  2626. static void
  2627. bna_tx_sm_start_wait(struct bna_tx *tx, enum bna_tx_event event)
  2628. {
  2629. switch (event) {
  2630. case TX_E_STOP:
  2631. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2632. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2633. break;
  2634. case TX_E_FAIL:
  2635. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2636. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2637. break;
  2638. case TX_E_STARTED:
  2639. if (tx->flags & (BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED)) {
  2640. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED |
  2641. BNA_TX_F_BW_UPDATED);
  2642. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2643. } else
  2644. bfa_fsm_set_state(tx, bna_tx_sm_started);
  2645. break;
  2646. case TX_E_PRIO_CHANGE:
  2647. tx->flags |= BNA_TX_F_PRIO_CHANGED;
  2648. break;
  2649. case TX_E_BW_UPDATE:
  2650. tx->flags |= BNA_TX_F_BW_UPDATED;
  2651. break;
  2652. default:
  2653. bfa_sm_fault(event);
  2654. }
  2655. }
  2656. static void
  2657. bna_tx_sm_started_entry(struct bna_tx *tx)
  2658. {
  2659. struct bna_txq *txq;
  2660. struct list_head *qe;
  2661. int is_regular = (tx->type == BNA_TX_T_REGULAR);
  2662. list_for_each(qe, &tx->txq_q) {
  2663. txq = (struct bna_txq *)qe;
  2664. txq->tcb->priority = txq->priority;
  2665. /* Start IB */
  2666. bna_ib_start(tx->bna, &txq->ib, is_regular);
  2667. }
  2668. tx->tx_resume_cbfn(tx->bna->bnad, tx);
  2669. }
  2670. static void
  2671. bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
  2672. {
  2673. switch (event) {
  2674. case TX_E_STOP:
  2675. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2676. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2677. bna_tx_enet_stop(tx);
  2678. break;
  2679. case TX_E_FAIL:
  2680. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2681. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2682. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2683. break;
  2684. case TX_E_PRIO_CHANGE:
  2685. case TX_E_BW_UPDATE:
  2686. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2687. break;
  2688. default:
  2689. bfa_sm_fault(event);
  2690. }
  2691. }
  2692. static void
  2693. bna_tx_sm_stop_wait_entry(struct bna_tx *tx)
  2694. {
  2695. }
  2696. static void
  2697. bna_tx_sm_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2698. {
  2699. switch (event) {
  2700. case TX_E_FAIL:
  2701. case TX_E_STOPPED:
  2702. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2703. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2704. break;
  2705. case TX_E_STARTED:
  2706. /**
  2707. * We are here due to start_wait -> stop_wait transition on
  2708. * TX_E_STOP event
  2709. */
  2710. bna_tx_enet_stop(tx);
  2711. break;
  2712. case TX_E_PRIO_CHANGE:
  2713. case TX_E_BW_UPDATE:
  2714. /* No-op */
  2715. break;
  2716. default:
  2717. bfa_sm_fault(event);
  2718. }
  2719. }
  2720. static void
  2721. bna_tx_sm_cleanup_wait_entry(struct bna_tx *tx)
  2722. {
  2723. }
  2724. static void
  2725. bna_tx_sm_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2726. {
  2727. switch (event) {
  2728. case TX_E_FAIL:
  2729. case TX_E_PRIO_CHANGE:
  2730. case TX_E_BW_UPDATE:
  2731. /* No-op */
  2732. break;
  2733. case TX_E_CLEANUP_DONE:
  2734. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2735. break;
  2736. default:
  2737. bfa_sm_fault(event);
  2738. }
  2739. }
  2740. static void
  2741. bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
  2742. {
  2743. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2744. bna_tx_enet_stop(tx);
  2745. }
  2746. static void
  2747. bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2748. {
  2749. switch (event) {
  2750. case TX_E_STOP:
  2751. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2752. break;
  2753. case TX_E_FAIL:
  2754. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2755. call_tx_prio_change_cbfn(tx);
  2756. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2757. break;
  2758. case TX_E_STOPPED:
  2759. bfa_fsm_set_state(tx, bna_tx_sm_prio_cleanup_wait);
  2760. break;
  2761. case TX_E_PRIO_CHANGE:
  2762. case TX_E_BW_UPDATE:
  2763. /* No-op */
  2764. break;
  2765. default:
  2766. bfa_sm_fault(event);
  2767. }
  2768. }
  2769. static void
  2770. bna_tx_sm_prio_cleanup_wait_entry(struct bna_tx *tx)
  2771. {
  2772. call_tx_prio_change_cbfn(tx);
  2773. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2774. }
  2775. static void
  2776. bna_tx_sm_prio_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2777. {
  2778. switch (event) {
  2779. case TX_E_STOP:
  2780. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2781. break;
  2782. case TX_E_FAIL:
  2783. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2784. break;
  2785. case TX_E_PRIO_CHANGE:
  2786. case TX_E_BW_UPDATE:
  2787. /* No-op */
  2788. break;
  2789. case TX_E_CLEANUP_DONE:
  2790. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2791. break;
  2792. default:
  2793. bfa_sm_fault(event);
  2794. }
  2795. }
  2796. static void
  2797. bna_tx_sm_failed_entry(struct bna_tx *tx)
  2798. {
  2799. }
  2800. static void
  2801. bna_tx_sm_failed(struct bna_tx *tx, enum bna_tx_event event)
  2802. {
  2803. switch (event) {
  2804. case TX_E_START:
  2805. bfa_fsm_set_state(tx, bna_tx_sm_quiesce_wait);
  2806. break;
  2807. case TX_E_STOP:
  2808. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2809. break;
  2810. case TX_E_FAIL:
  2811. /* No-op */
  2812. break;
  2813. case TX_E_CLEANUP_DONE:
  2814. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2815. break;
  2816. default:
  2817. bfa_sm_fault(event);
  2818. }
  2819. }
  2820. static void
  2821. bna_tx_sm_quiesce_wait_entry(struct bna_tx *tx)
  2822. {
  2823. }
  2824. static void
  2825. bna_tx_sm_quiesce_wait(struct bna_tx *tx, enum bna_tx_event event)
  2826. {
  2827. switch (event) {
  2828. case TX_E_STOP:
  2829. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2830. break;
  2831. case TX_E_FAIL:
  2832. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2833. break;
  2834. case TX_E_CLEANUP_DONE:
  2835. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2836. break;
  2837. case TX_E_BW_UPDATE:
  2838. /* No-op */
  2839. break;
  2840. default:
  2841. bfa_sm_fault(event);
  2842. }
  2843. }
  2844. static void
  2845. bna_bfi_tx_enet_start(struct bna_tx *tx)
  2846. {
  2847. struct bfi_enet_tx_cfg_req *cfg_req = &tx->bfi_enet_cmd.cfg_req;
  2848. struct bna_txq *txq = NULL;
  2849. struct list_head *qe;
  2850. int i;
  2851. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  2852. BFI_ENET_H2I_TX_CFG_SET_REQ, 0, tx->rid);
  2853. cfg_req->mh.num_entries = htons(
  2854. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_tx_cfg_req)));
  2855. cfg_req->num_queues = tx->num_txq;
  2856. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2857. i < tx->num_txq;
  2858. i++, qe = bfa_q_next(qe)) {
  2859. txq = (struct bna_txq *)qe;
  2860. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].q.q, &txq->qpt);
  2861. cfg_req->q_cfg[i].q.priority = txq->priority;
  2862. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  2863. txq->ib.ib_seg_host_addr.lsb;
  2864. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  2865. txq->ib.ib_seg_host_addr.msb;
  2866. cfg_req->q_cfg[i].ib.intr.msix_index =
  2867. htons((u16)txq->ib.intr_vector);
  2868. }
  2869. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_ENABLED;
  2870. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  2871. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  2872. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_ENABLED;
  2873. cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
  2874. ? BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
  2875. cfg_req->ib_cfg.coalescing_timeout =
  2876. htonl((u32)txq->ib.coalescing_timeo);
  2877. cfg_req->ib_cfg.inter_pkt_timeout =
  2878. htonl((u32)txq->ib.interpkt_timeo);
  2879. cfg_req->ib_cfg.inter_pkt_count = (u8)txq->ib.interpkt_count;
  2880. cfg_req->tx_cfg.vlan_mode = BFI_ENET_TX_VLAN_WI;
  2881. cfg_req->tx_cfg.vlan_id = htons((u16)tx->txf_vlan_id);
  2882. cfg_req->tx_cfg.admit_tagged_frame = BNA_STATUS_T_ENABLED;
  2883. cfg_req->tx_cfg.apply_vlan_filter = BNA_STATUS_T_DISABLED;
  2884. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL,
  2885. sizeof(struct bfi_enet_tx_cfg_req), &cfg_req->mh);
  2886. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2887. }
  2888. static void
  2889. bna_bfi_tx_enet_stop(struct bna_tx *tx)
  2890. {
  2891. struct bfi_enet_req *req = &tx->bfi_enet_cmd.req;
  2892. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  2893. BFI_ENET_H2I_TX_CFG_CLR_REQ, 0, tx->rid);
  2894. req->mh.num_entries = htons(
  2895. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  2896. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  2897. &req->mh);
  2898. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2899. }
  2900. static void
  2901. bna_tx_enet_stop(struct bna_tx *tx)
  2902. {
  2903. struct bna_txq *txq;
  2904. struct list_head *qe;
  2905. /* Stop IB */
  2906. list_for_each(qe, &tx->txq_q) {
  2907. txq = (struct bna_txq *)qe;
  2908. bna_ib_stop(tx->bna, &txq->ib);
  2909. }
  2910. bna_bfi_tx_enet_stop(tx);
  2911. }
  2912. static void
  2913. bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
  2914. struct bna_mem_descr *qpt_mem,
  2915. struct bna_mem_descr *swqpt_mem,
  2916. struct bna_mem_descr *page_mem)
  2917. {
  2918. u8 *kva;
  2919. u64 dma;
  2920. struct bna_dma_addr bna_dma;
  2921. int i;
  2922. txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  2923. txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  2924. txq->qpt.kv_qpt_ptr = qpt_mem->kva;
  2925. txq->qpt.page_count = page_count;
  2926. txq->qpt.page_size = page_size;
  2927. txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
  2928. txq->tcb->sw_q = page_mem->kva;
  2929. kva = page_mem->kva;
  2930. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  2931. for (i = 0; i < page_count; i++) {
  2932. txq->tcb->sw_qpt[i] = kva;
  2933. kva += PAGE_SIZE;
  2934. BNA_SET_DMA_ADDR(dma, &bna_dma);
  2935. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
  2936. bna_dma.lsb;
  2937. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
  2938. bna_dma.msb;
  2939. dma += PAGE_SIZE;
  2940. }
  2941. }
  2942. static struct bna_tx *
  2943. bna_tx_get(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  2944. {
  2945. struct list_head *qe = NULL;
  2946. struct bna_tx *tx = NULL;
  2947. if (list_empty(&tx_mod->tx_free_q))
  2948. return NULL;
  2949. if (type == BNA_TX_T_REGULAR) {
  2950. bfa_q_deq(&tx_mod->tx_free_q, &qe);
  2951. } else {
  2952. bfa_q_deq_tail(&tx_mod->tx_free_q, &qe);
  2953. }
  2954. tx = (struct bna_tx *)qe;
  2955. bfa_q_qe_init(&tx->qe);
  2956. tx->type = type;
  2957. return tx;
  2958. }
  2959. static void
  2960. bna_tx_free(struct bna_tx *tx)
  2961. {
  2962. struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
  2963. struct bna_txq *txq;
  2964. struct list_head *prev_qe;
  2965. struct list_head *qe;
  2966. while (!list_empty(&tx->txq_q)) {
  2967. bfa_q_deq(&tx->txq_q, &txq);
  2968. bfa_q_qe_init(&txq->qe);
  2969. txq->tcb = NULL;
  2970. txq->tx = NULL;
  2971. list_add_tail(&txq->qe, &tx_mod->txq_free_q);
  2972. }
  2973. list_for_each(qe, &tx_mod->tx_active_q) {
  2974. if (qe == &tx->qe) {
  2975. list_del(&tx->qe);
  2976. bfa_q_qe_init(&tx->qe);
  2977. break;
  2978. }
  2979. }
  2980. tx->bna = NULL;
  2981. tx->priv = NULL;
  2982. prev_qe = NULL;
  2983. list_for_each(qe, &tx_mod->tx_free_q) {
  2984. if (((struct bna_tx *)qe)->rid < tx->rid)
  2985. prev_qe = qe;
  2986. else {
  2987. break;
  2988. }
  2989. }
  2990. if (prev_qe == NULL) {
  2991. /* This is the first entry */
  2992. bfa_q_enq_head(&tx_mod->tx_free_q, &tx->qe);
  2993. } else if (bfa_q_next(prev_qe) == &tx_mod->tx_free_q) {
  2994. /* This is the last entry */
  2995. list_add_tail(&tx->qe, &tx_mod->tx_free_q);
  2996. } else {
  2997. /* Somewhere in the middle */
  2998. bfa_q_next(&tx->qe) = bfa_q_next(prev_qe);
  2999. bfa_q_prev(&tx->qe) = prev_qe;
  3000. bfa_q_next(prev_qe) = &tx->qe;
  3001. bfa_q_prev(bfa_q_next(&tx->qe)) = &tx->qe;
  3002. }
  3003. }
  3004. static void
  3005. bna_tx_start(struct bna_tx *tx)
  3006. {
  3007. tx->flags |= BNA_TX_F_ENET_STARTED;
  3008. if (tx->flags & BNA_TX_F_ENABLED)
  3009. bfa_fsm_send_event(tx, TX_E_START);
  3010. }
  3011. static void
  3012. bna_tx_stop(struct bna_tx *tx)
  3013. {
  3014. tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
  3015. tx->stop_cbarg = &tx->bna->tx_mod;
  3016. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  3017. bfa_fsm_send_event(tx, TX_E_STOP);
  3018. }
  3019. static void
  3020. bna_tx_fail(struct bna_tx *tx)
  3021. {
  3022. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  3023. bfa_fsm_send_event(tx, TX_E_FAIL);
  3024. }
  3025. void
  3026. bna_bfi_tx_enet_start_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  3027. {
  3028. struct bfi_enet_tx_cfg_rsp *cfg_rsp = &tx->bfi_enet_cmd.cfg_rsp;
  3029. struct bna_txq *txq = NULL;
  3030. struct list_head *qe;
  3031. int i;
  3032. bfa_msgq_rsp_copy(&tx->bna->msgq, (u8 *)cfg_rsp,
  3033. sizeof(struct bfi_enet_tx_cfg_rsp));
  3034. tx->hw_id = cfg_rsp->hw_id;
  3035. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  3036. i < tx->num_txq; i++, qe = bfa_q_next(qe)) {
  3037. txq = (struct bna_txq *)qe;
  3038. /* Setup doorbells */
  3039. txq->tcb->i_dbell->doorbell_addr =
  3040. tx->bna->pcidev.pci_bar_kva
  3041. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  3042. txq->tcb->q_dbell =
  3043. tx->bna->pcidev.pci_bar_kva
  3044. + ntohl(cfg_rsp->q_handles[i].q_dbell);
  3045. txq->hw_id = cfg_rsp->q_handles[i].hw_qid;
  3046. /* Initialize producer/consumer indexes */
  3047. (*txq->tcb->hw_consumer_index) = 0;
  3048. txq->tcb->producer_index = txq->tcb->consumer_index = 0;
  3049. }
  3050. bfa_fsm_send_event(tx, TX_E_STARTED);
  3051. }
  3052. void
  3053. bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  3054. {
  3055. bfa_fsm_send_event(tx, TX_E_STOPPED);
  3056. }
  3057. void
  3058. bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod)
  3059. {
  3060. struct bna_tx *tx;
  3061. struct list_head *qe;
  3062. list_for_each(qe, &tx_mod->tx_active_q) {
  3063. tx = (struct bna_tx *)qe;
  3064. bfa_fsm_send_event(tx, TX_E_BW_UPDATE);
  3065. }
  3066. }
  3067. void
  3068. bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
  3069. {
  3070. u32 q_size;
  3071. u32 page_count;
  3072. struct bna_mem_info *mem_info;
  3073. res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
  3074. mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
  3075. mem_info->mem_type = BNA_MEM_T_KVA;
  3076. mem_info->len = sizeof(struct bna_tcb);
  3077. mem_info->num = num_txq;
  3078. q_size = txq_depth * BFI_TXQ_WI_SIZE;
  3079. q_size = ALIGN(q_size, PAGE_SIZE);
  3080. page_count = q_size >> PAGE_SHIFT;
  3081. res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
  3082. mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
  3083. mem_info->mem_type = BNA_MEM_T_DMA;
  3084. mem_info->len = page_count * sizeof(struct bna_dma_addr);
  3085. mem_info->num = num_txq;
  3086. res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
  3087. mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
  3088. mem_info->mem_type = BNA_MEM_T_KVA;
  3089. mem_info->len = page_count * sizeof(void *);
  3090. mem_info->num = num_txq;
  3091. res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
  3092. mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
  3093. mem_info->mem_type = BNA_MEM_T_DMA;
  3094. mem_info->len = PAGE_SIZE * page_count;
  3095. mem_info->num = num_txq;
  3096. res_info[BNA_TX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  3097. mem_info = &res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info;
  3098. mem_info->mem_type = BNA_MEM_T_DMA;
  3099. mem_info->len = BFI_IBIDX_SIZE;
  3100. mem_info->num = num_txq;
  3101. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
  3102. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
  3103. BNA_INTR_T_MSIX;
  3104. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
  3105. }
  3106. struct bna_tx *
  3107. bna_tx_create(struct bna *bna, struct bnad *bnad,
  3108. struct bna_tx_config *tx_cfg,
  3109. const struct bna_tx_event_cbfn *tx_cbfn,
  3110. struct bna_res_info *res_info, void *priv)
  3111. {
  3112. struct bna_intr_info *intr_info;
  3113. struct bna_tx_mod *tx_mod = &bna->tx_mod;
  3114. struct bna_tx *tx;
  3115. struct bna_txq *txq;
  3116. struct list_head *qe;
  3117. int page_count;
  3118. int i;
  3119. intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  3120. page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len) /
  3121. PAGE_SIZE;
  3122. /**
  3123. * Get resources
  3124. */
  3125. if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
  3126. return NULL;
  3127. /* Tx */
  3128. tx = bna_tx_get(tx_mod, tx_cfg->tx_type);
  3129. if (!tx)
  3130. return NULL;
  3131. tx->bna = bna;
  3132. tx->priv = priv;
  3133. /* TxQs */
  3134. INIT_LIST_HEAD(&tx->txq_q);
  3135. for (i = 0; i < tx_cfg->num_txq; i++) {
  3136. if (list_empty(&tx_mod->txq_free_q))
  3137. goto err_return;
  3138. bfa_q_deq(&tx_mod->txq_free_q, &txq);
  3139. bfa_q_qe_init(&txq->qe);
  3140. list_add_tail(&txq->qe, &tx->txq_q);
  3141. txq->tx = tx;
  3142. }
  3143. /*
  3144. * Initialize
  3145. */
  3146. /* Tx */
  3147. tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
  3148. tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
  3149. /* Following callbacks are mandatory */
  3150. tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
  3151. tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
  3152. tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
  3153. list_add_tail(&tx->qe, &tx_mod->tx_active_q);
  3154. tx->num_txq = tx_cfg->num_txq;
  3155. tx->flags = 0;
  3156. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_STARTED) {
  3157. switch (tx->type) {
  3158. case BNA_TX_T_REGULAR:
  3159. if (!(tx->bna->tx_mod.flags &
  3160. BNA_TX_MOD_F_ENET_LOOPBACK))
  3161. tx->flags |= BNA_TX_F_ENET_STARTED;
  3162. break;
  3163. case BNA_TX_T_LOOPBACK:
  3164. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_LOOPBACK)
  3165. tx->flags |= BNA_TX_F_ENET_STARTED;
  3166. break;
  3167. }
  3168. }
  3169. /* TxQ */
  3170. i = 0;
  3171. list_for_each(qe, &tx->txq_q) {
  3172. txq = (struct bna_txq *)qe;
  3173. txq->tcb = (struct bna_tcb *)
  3174. res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
  3175. txq->tx_packets = 0;
  3176. txq->tx_bytes = 0;
  3177. /* IB */
  3178. txq->ib.ib_seg_host_addr.lsb =
  3179. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  3180. txq->ib.ib_seg_host_addr.msb =
  3181. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  3182. txq->ib.ib_seg_host_addr_kva =
  3183. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  3184. txq->ib.intr_type = intr_info->intr_type;
  3185. txq->ib.intr_vector = (intr_info->num == 1) ?
  3186. intr_info->idl[0].vector :
  3187. intr_info->idl[i].vector;
  3188. if (intr_info->intr_type == BNA_INTR_T_INTX)
  3189. txq->ib.intr_vector = (1 << txq->ib.intr_vector);
  3190. txq->ib.coalescing_timeo = tx_cfg->coalescing_timeo;
  3191. txq->ib.interpkt_timeo = BFI_TX_INTERPKT_TIMEO;
  3192. txq->ib.interpkt_count = BFI_TX_INTERPKT_COUNT;
  3193. /* TCB */
  3194. txq->tcb->q_depth = tx_cfg->txq_depth;
  3195. txq->tcb->unmap_q = (void *)
  3196. res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
  3197. txq->tcb->hw_consumer_index =
  3198. (u32 *)txq->ib.ib_seg_host_addr_kva;
  3199. txq->tcb->i_dbell = &txq->ib.door_bell;
  3200. txq->tcb->intr_type = txq->ib.intr_type;
  3201. txq->tcb->intr_vector = txq->ib.intr_vector;
  3202. txq->tcb->txq = txq;
  3203. txq->tcb->bnad = bnad;
  3204. txq->tcb->id = i;
  3205. /* QPT, SWQPT, Pages */
  3206. bna_txq_qpt_setup(txq, page_count, PAGE_SIZE,
  3207. &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
  3208. &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
  3209. &res_info[BNA_TX_RES_MEM_T_PAGE].
  3210. res_u.mem_info.mdl[i]);
  3211. /* Callback to bnad for setting up TCB */
  3212. if (tx->tcb_setup_cbfn)
  3213. (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
  3214. if (tx_cfg->num_txq == BFI_TX_MAX_PRIO)
  3215. txq->priority = txq->tcb->id;
  3216. else
  3217. txq->priority = tx_mod->default_prio;
  3218. i++;
  3219. }
  3220. tx->txf_vlan_id = 0;
  3221. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  3222. tx_mod->rid_mask |= (1 << tx->rid);
  3223. return tx;
  3224. err_return:
  3225. bna_tx_free(tx);
  3226. return NULL;
  3227. }
  3228. void
  3229. bna_tx_destroy(struct bna_tx *tx)
  3230. {
  3231. struct bna_txq *txq;
  3232. struct list_head *qe;
  3233. list_for_each(qe, &tx->txq_q) {
  3234. txq = (struct bna_txq *)qe;
  3235. if (tx->tcb_destroy_cbfn)
  3236. (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
  3237. }
  3238. tx->bna->tx_mod.rid_mask &= ~(1 << tx->rid);
  3239. bna_tx_free(tx);
  3240. }
  3241. void
  3242. bna_tx_enable(struct bna_tx *tx)
  3243. {
  3244. if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
  3245. return;
  3246. tx->flags |= BNA_TX_F_ENABLED;
  3247. if (tx->flags & BNA_TX_F_ENET_STARTED)
  3248. bfa_fsm_send_event(tx, TX_E_START);
  3249. }
  3250. void
  3251. bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
  3252. void (*cbfn)(void *, struct bna_tx *))
  3253. {
  3254. if (type == BNA_SOFT_CLEANUP) {
  3255. (*cbfn)(tx->bna->bnad, tx);
  3256. return;
  3257. }
  3258. tx->stop_cbfn = cbfn;
  3259. tx->stop_cbarg = tx->bna->bnad;
  3260. tx->flags &= ~BNA_TX_F_ENABLED;
  3261. bfa_fsm_send_event(tx, TX_E_STOP);
  3262. }
  3263. void
  3264. bna_tx_cleanup_complete(struct bna_tx *tx)
  3265. {
  3266. bfa_fsm_send_event(tx, TX_E_CLEANUP_DONE);
  3267. }
  3268. static void
  3269. bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx)
  3270. {
  3271. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3272. bfa_wc_down(&tx_mod->tx_stop_wc);
  3273. }
  3274. static void
  3275. bna_tx_mod_cb_tx_stopped_all(void *arg)
  3276. {
  3277. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3278. if (tx_mod->stop_cbfn)
  3279. tx_mod->stop_cbfn(&tx_mod->bna->enet);
  3280. tx_mod->stop_cbfn = NULL;
  3281. }
  3282. void
  3283. bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
  3284. struct bna_res_info *res_info)
  3285. {
  3286. int i;
  3287. tx_mod->bna = bna;
  3288. tx_mod->flags = 0;
  3289. tx_mod->tx = (struct bna_tx *)
  3290. res_info[BNA_MOD_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
  3291. tx_mod->txq = (struct bna_txq *)
  3292. res_info[BNA_MOD_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  3293. INIT_LIST_HEAD(&tx_mod->tx_free_q);
  3294. INIT_LIST_HEAD(&tx_mod->tx_active_q);
  3295. INIT_LIST_HEAD(&tx_mod->txq_free_q);
  3296. for (i = 0; i < bna->ioceth.attr.num_txq; i++) {
  3297. tx_mod->tx[i].rid = i;
  3298. bfa_q_qe_init(&tx_mod->tx[i].qe);
  3299. list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
  3300. bfa_q_qe_init(&tx_mod->txq[i].qe);
  3301. list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
  3302. }
  3303. tx_mod->prio_map = BFI_TX_PRIO_MAP_ALL;
  3304. tx_mod->default_prio = 0;
  3305. tx_mod->iscsi_over_cee = BNA_STATUS_T_DISABLED;
  3306. tx_mod->iscsi_prio = -1;
  3307. }
  3308. void
  3309. bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
  3310. {
  3311. struct list_head *qe;
  3312. int i;
  3313. i = 0;
  3314. list_for_each(qe, &tx_mod->tx_free_q)
  3315. i++;
  3316. i = 0;
  3317. list_for_each(qe, &tx_mod->txq_free_q)
  3318. i++;
  3319. tx_mod->bna = NULL;
  3320. }
  3321. void
  3322. bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3323. {
  3324. struct bna_tx *tx;
  3325. struct list_head *qe;
  3326. tx_mod->flags |= BNA_TX_MOD_F_ENET_STARTED;
  3327. if (type == BNA_TX_T_LOOPBACK)
  3328. tx_mod->flags |= BNA_TX_MOD_F_ENET_LOOPBACK;
  3329. list_for_each(qe, &tx_mod->tx_active_q) {
  3330. tx = (struct bna_tx *)qe;
  3331. if (tx->type == type)
  3332. bna_tx_start(tx);
  3333. }
  3334. }
  3335. void
  3336. bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3337. {
  3338. struct bna_tx *tx;
  3339. struct list_head *qe;
  3340. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3341. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3342. tx_mod->stop_cbfn = bna_enet_cb_tx_stopped;
  3343. bfa_wc_init(&tx_mod->tx_stop_wc, bna_tx_mod_cb_tx_stopped_all, tx_mod);
  3344. list_for_each(qe, &tx_mod->tx_active_q) {
  3345. tx = (struct bna_tx *)qe;
  3346. if (tx->type == type) {
  3347. bfa_wc_up(&tx_mod->tx_stop_wc);
  3348. bna_tx_stop(tx);
  3349. }
  3350. }
  3351. bfa_wc_wait(&tx_mod->tx_stop_wc);
  3352. }
  3353. void
  3354. bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
  3355. {
  3356. struct bna_tx *tx;
  3357. struct list_head *qe;
  3358. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3359. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3360. list_for_each(qe, &tx_mod->tx_active_q) {
  3361. tx = (struct bna_tx *)qe;
  3362. bna_tx_fail(tx);
  3363. }
  3364. }
  3365. void
  3366. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  3367. {
  3368. struct bna_txq *txq;
  3369. struct list_head *qe;
  3370. list_for_each(qe, &tx->txq_q) {
  3371. txq = (struct bna_txq *)qe;
  3372. bna_ib_coalescing_timeo_set(&txq->ib, coalescing_timeo);
  3373. }
  3374. }