xgbe-main.c 16 KB

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  1. /*
  2. * AMD 10Gb Ethernet driver
  3. *
  4. * This file is available to you under your choice of the following two
  5. * licenses:
  6. *
  7. * License 1: GPLv2
  8. *
  9. * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10. *
  11. * This file is free software; you may copy, redistribute and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation, either version 2 of the License, or (at
  14. * your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  23. *
  24. * This file incorporates work covered by the following copyright and
  25. * permission notice:
  26. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  29. * and you.
  30. *
  31. * The Software IS NOT an item of Licensed Software or Licensed Product
  32. * under any End User Software License Agreement or Agreement for Licensed
  33. * Product with Synopsys or any supplement thereto. Permission is hereby
  34. * granted, free of charge, to any person obtaining a copy of this software
  35. * annotated with this license and the Software, to deal in the Software
  36. * without restriction, including without limitation the rights to use,
  37. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38. * of the Software, and to permit persons to whom the Software is furnished
  39. * to do so, subject to the following conditions:
  40. *
  41. * The above copyright notice and this permission notice shall be included
  42. * in all copies or substantial portions of the Software.
  43. *
  44. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54. * THE POSSIBILITY OF SUCH DAMAGE.
  55. *
  56. *
  57. * License 2: Modified BSD
  58. *
  59. * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60. * All rights reserved.
  61. *
  62. * Redistribution and use in source and binary forms, with or without
  63. * modification, are permitted provided that the following conditions are met:
  64. * * Redistributions of source code must retain the above copyright
  65. * notice, this list of conditions and the following disclaimer.
  66. * * Redistributions in binary form must reproduce the above copyright
  67. * notice, this list of conditions and the following disclaimer in the
  68. * documentation and/or other materials provided with the distribution.
  69. * * Neither the name of Advanced Micro Devices, Inc. nor the
  70. * names of its contributors may be used to endorse or promote products
  71. * derived from this software without specific prior written permission.
  72. *
  73. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76. * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83. *
  84. * This file incorporates work covered by the following copyright and
  85. * permission notice:
  86. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  89. * and you.
  90. *
  91. * The Software IS NOT an item of Licensed Software or Licensed Product
  92. * under any End User Software License Agreement or Agreement for Licensed
  93. * Product with Synopsys or any supplement thereto. Permission is hereby
  94. * granted, free of charge, to any person obtaining a copy of this software
  95. * annotated with this license and the Software, to deal in the Software
  96. * without restriction, including without limitation the rights to use,
  97. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98. * of the Software, and to permit persons to whom the Software is furnished
  99. * to do so, subject to the following conditions:
  100. *
  101. * The above copyright notice and this permission notice shall be included
  102. * in all copies or substantial portions of the Software.
  103. *
  104. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  105. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  106. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  107. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  108. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  109. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  110. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  111. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  112. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  113. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  114. * THE POSSIBILITY OF SUCH DAMAGE.
  115. */
  116. #include <linux/module.h>
  117. #include <linux/device.h>
  118. #include <linux/platform_device.h>
  119. #include <linux/spinlock.h>
  120. #include <linux/netdevice.h>
  121. #include <linux/etherdevice.h>
  122. #include <linux/io.h>
  123. #include <linux/of.h>
  124. #include <linux/of_net.h>
  125. #include <linux/clk.h>
  126. #include "xgbe.h"
  127. #include "xgbe-common.h"
  128. MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
  129. MODULE_LICENSE("Dual BSD/GPL");
  130. MODULE_VERSION(XGBE_DRV_VERSION);
  131. MODULE_DESCRIPTION(XGBE_DRV_DESC);
  132. static void xgbe_default_config(struct xgbe_prv_data *pdata)
  133. {
  134. DBGPR("-->xgbe_default_config\n");
  135. pdata->pblx8 = DMA_PBL_X8_ENABLE;
  136. pdata->tx_sf_mode = MTL_TSF_ENABLE;
  137. pdata->tx_threshold = MTL_TX_THRESHOLD_64;
  138. pdata->tx_pbl = DMA_PBL_16;
  139. pdata->tx_osp_mode = DMA_OSP_ENABLE;
  140. pdata->rx_sf_mode = MTL_RSF_DISABLE;
  141. pdata->rx_threshold = MTL_RX_THRESHOLD_64;
  142. pdata->rx_pbl = DMA_PBL_16;
  143. pdata->pause_autoneg = 1;
  144. pdata->tx_pause = 1;
  145. pdata->rx_pause = 1;
  146. pdata->power_down = 0;
  147. pdata->default_autoneg = AUTONEG_ENABLE;
  148. pdata->default_speed = SPEED_10000;
  149. DBGPR("<--xgbe_default_config\n");
  150. }
  151. static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
  152. {
  153. xgbe_init_function_ptrs_dev(&pdata->hw_if);
  154. xgbe_init_function_ptrs_desc(&pdata->desc_if);
  155. }
  156. static int xgbe_probe(struct platform_device *pdev)
  157. {
  158. struct xgbe_prv_data *pdata;
  159. struct xgbe_hw_if *hw_if;
  160. struct xgbe_desc_if *desc_if;
  161. struct net_device *netdev;
  162. struct device *dev = &pdev->dev;
  163. struct resource *res;
  164. const u8 *mac_addr;
  165. unsigned int i;
  166. int ret;
  167. DBGPR("--> xgbe_probe\n");
  168. netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
  169. XGBE_MAX_DMA_CHANNELS);
  170. if (!netdev) {
  171. dev_err(dev, "alloc_etherdev failed\n");
  172. ret = -ENOMEM;
  173. goto err_alloc;
  174. }
  175. SET_NETDEV_DEV(netdev, dev);
  176. pdata = netdev_priv(netdev);
  177. pdata->netdev = netdev;
  178. pdata->pdev = pdev;
  179. pdata->dev = dev;
  180. platform_set_drvdata(pdev, netdev);
  181. spin_lock_init(&pdata->lock);
  182. mutex_init(&pdata->xpcs_mutex);
  183. mutex_init(&pdata->rss_mutex);
  184. spin_lock_init(&pdata->tstamp_lock);
  185. /* Set and validate the number of descriptors for a ring */
  186. BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
  187. pdata->tx_desc_count = XGBE_TX_DESC_CNT;
  188. if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
  189. dev_err(dev, "tx descriptor count (%d) is not valid\n",
  190. pdata->tx_desc_count);
  191. ret = -EINVAL;
  192. goto err_io;
  193. }
  194. BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
  195. pdata->rx_desc_count = XGBE_RX_DESC_CNT;
  196. if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
  197. dev_err(dev, "rx descriptor count (%d) is not valid\n",
  198. pdata->rx_desc_count);
  199. ret = -EINVAL;
  200. goto err_io;
  201. }
  202. /* Obtain the system clock setting */
  203. pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK);
  204. if (IS_ERR(pdata->sysclk)) {
  205. dev_err(dev, "dma devm_clk_get failed\n");
  206. ret = PTR_ERR(pdata->sysclk);
  207. goto err_io;
  208. }
  209. /* Obtain the PTP clock setting */
  210. pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK);
  211. if (IS_ERR(pdata->ptpclk)) {
  212. dev_err(dev, "ptp devm_clk_get failed\n");
  213. ret = PTR_ERR(pdata->ptpclk);
  214. goto err_io;
  215. }
  216. /* Obtain the mmio areas for the device */
  217. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  218. pdata->xgmac_regs = devm_ioremap_resource(dev, res);
  219. if (IS_ERR(pdata->xgmac_regs)) {
  220. dev_err(dev, "xgmac ioremap failed\n");
  221. ret = PTR_ERR(pdata->xgmac_regs);
  222. goto err_io;
  223. }
  224. DBGPR(" xgmac_regs = %p\n", pdata->xgmac_regs);
  225. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  226. pdata->xpcs_regs = devm_ioremap_resource(dev, res);
  227. if (IS_ERR(pdata->xpcs_regs)) {
  228. dev_err(dev, "xpcs ioremap failed\n");
  229. ret = PTR_ERR(pdata->xpcs_regs);
  230. goto err_io;
  231. }
  232. DBGPR(" xpcs_regs = %p\n", pdata->xpcs_regs);
  233. /* Set the DMA mask */
  234. if (!dev->dma_mask)
  235. dev->dma_mask = &dev->coherent_dma_mask;
  236. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
  237. if (ret) {
  238. dev_err(dev, "dma_set_mask_and_coherent failed\n");
  239. goto err_io;
  240. }
  241. if (of_property_read_bool(dev->of_node, "dma-coherent")) {
  242. pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
  243. pdata->arcache = XGBE_DMA_OS_ARCACHE;
  244. pdata->awcache = XGBE_DMA_OS_AWCACHE;
  245. } else {
  246. pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN;
  247. pdata->arcache = XGBE_DMA_SYS_ARCACHE;
  248. pdata->awcache = XGBE_DMA_SYS_AWCACHE;
  249. }
  250. /* Check for per channel interrupt support */
  251. if (of_property_read_bool(dev->of_node, XGBE_DMA_IRQS))
  252. pdata->per_channel_irq = 1;
  253. ret = platform_get_irq(pdev, 0);
  254. if (ret < 0) {
  255. dev_err(dev, "platform_get_irq 0 failed\n");
  256. goto err_io;
  257. }
  258. pdata->dev_irq = ret;
  259. netdev->irq = pdata->dev_irq;
  260. netdev->base_addr = (unsigned long)pdata->xgmac_regs;
  261. /* Set all the function pointers */
  262. xgbe_init_all_fptrs(pdata);
  263. hw_if = &pdata->hw_if;
  264. desc_if = &pdata->desc_if;
  265. /* Issue software reset to device */
  266. hw_if->exit(pdata);
  267. /* Populate the hardware features */
  268. xgbe_get_all_hw_features(pdata);
  269. /* Retrieve the MAC address */
  270. mac_addr = of_get_mac_address(dev->of_node);
  271. if (!mac_addr) {
  272. dev_err(dev, "invalid mac address for this device\n");
  273. ret = -EINVAL;
  274. goto err_io;
  275. }
  276. memcpy(netdev->dev_addr, mac_addr, netdev->addr_len);
  277. /* Retrieve the PHY mode - it must be "xgmii" */
  278. pdata->phy_mode = of_get_phy_mode(dev->of_node);
  279. if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
  280. dev_err(dev, "invalid phy-mode specified for this device\n");
  281. ret = -EINVAL;
  282. goto err_io;
  283. }
  284. /* Set default configuration data */
  285. xgbe_default_config(pdata);
  286. /* Calculate the number of Tx and Rx rings to be created
  287. * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
  288. * the number of Tx queues to the number of Tx channels
  289. * enabled
  290. * -Rx (DMA) Channels do not map 1-to-1 so use the actual
  291. * number of Rx queues
  292. */
  293. pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
  294. pdata->hw_feat.tx_ch_cnt);
  295. pdata->tx_q_count = pdata->tx_ring_count;
  296. ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
  297. if (ret) {
  298. dev_err(dev, "error setting real tx queue count\n");
  299. goto err_io;
  300. }
  301. pdata->rx_ring_count = min_t(unsigned int,
  302. netif_get_num_default_rss_queues(),
  303. pdata->hw_feat.rx_ch_cnt);
  304. pdata->rx_q_count = pdata->hw_feat.rx_q_cnt;
  305. ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
  306. if (ret) {
  307. dev_err(dev, "error setting real rx queue count\n");
  308. goto err_io;
  309. }
  310. /* Initialize RSS hash key and lookup table */
  311. netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
  312. for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
  313. XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
  314. i % pdata->rx_ring_count);
  315. XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
  316. XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
  317. XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
  318. /* Prepare to regsiter with MDIO */
  319. pdata->mii_bus_id = kasprintf(GFP_KERNEL, "%s", pdev->name);
  320. if (!pdata->mii_bus_id) {
  321. dev_err(dev, "failed to allocate mii bus id\n");
  322. ret = -ENOMEM;
  323. goto err_io;
  324. }
  325. ret = xgbe_mdio_register(pdata);
  326. if (ret)
  327. goto err_bus_id;
  328. /* Set device operations */
  329. netdev->netdev_ops = xgbe_get_netdev_ops();
  330. netdev->ethtool_ops = xgbe_get_ethtool_ops();
  331. #ifdef CONFIG_AMD_XGBE_DCB
  332. netdev->dcbnl_ops = xgbe_get_dcbnl_ops();
  333. #endif
  334. /* Set device features */
  335. netdev->hw_features = NETIF_F_SG |
  336. NETIF_F_IP_CSUM |
  337. NETIF_F_IPV6_CSUM |
  338. NETIF_F_RXCSUM |
  339. NETIF_F_TSO |
  340. NETIF_F_TSO6 |
  341. NETIF_F_GRO |
  342. NETIF_F_HW_VLAN_CTAG_RX |
  343. NETIF_F_HW_VLAN_CTAG_TX |
  344. NETIF_F_HW_VLAN_CTAG_FILTER;
  345. if (pdata->hw_feat.rss)
  346. netdev->hw_features |= NETIF_F_RXHASH;
  347. netdev->vlan_features |= NETIF_F_SG |
  348. NETIF_F_IP_CSUM |
  349. NETIF_F_IPV6_CSUM |
  350. NETIF_F_TSO |
  351. NETIF_F_TSO6;
  352. netdev->features |= netdev->hw_features;
  353. pdata->netdev_features = netdev->features;
  354. netdev->priv_flags |= IFF_UNICAST_FLT;
  355. xgbe_init_rx_coalesce(pdata);
  356. xgbe_init_tx_coalesce(pdata);
  357. netif_carrier_off(netdev);
  358. ret = register_netdev(netdev);
  359. if (ret) {
  360. dev_err(dev, "net device registration failed\n");
  361. goto err_reg_netdev;
  362. }
  363. xgbe_ptp_register(pdata);
  364. xgbe_debugfs_init(pdata);
  365. netdev_notice(netdev, "net device enabled\n");
  366. DBGPR("<-- xgbe_probe\n");
  367. return 0;
  368. err_reg_netdev:
  369. xgbe_mdio_unregister(pdata);
  370. err_bus_id:
  371. kfree(pdata->mii_bus_id);
  372. err_io:
  373. free_netdev(netdev);
  374. err_alloc:
  375. dev_notice(dev, "net device not enabled\n");
  376. return ret;
  377. }
  378. static int xgbe_remove(struct platform_device *pdev)
  379. {
  380. struct net_device *netdev = platform_get_drvdata(pdev);
  381. struct xgbe_prv_data *pdata = netdev_priv(netdev);
  382. DBGPR("-->xgbe_remove\n");
  383. xgbe_debugfs_exit(pdata);
  384. xgbe_ptp_unregister(pdata);
  385. unregister_netdev(netdev);
  386. xgbe_mdio_unregister(pdata);
  387. kfree(pdata->mii_bus_id);
  388. free_netdev(netdev);
  389. DBGPR("<--xgbe_remove\n");
  390. return 0;
  391. }
  392. #ifdef CONFIG_PM
  393. static int xgbe_suspend(struct device *dev)
  394. {
  395. struct net_device *netdev = dev_get_drvdata(dev);
  396. int ret;
  397. DBGPR("-->xgbe_suspend\n");
  398. if (!netif_running(netdev)) {
  399. DBGPR("<--xgbe_dev_suspend\n");
  400. return -EINVAL;
  401. }
  402. ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
  403. DBGPR("<--xgbe_suspend\n");
  404. return ret;
  405. }
  406. static int xgbe_resume(struct device *dev)
  407. {
  408. struct net_device *netdev = dev_get_drvdata(dev);
  409. int ret;
  410. DBGPR("-->xgbe_resume\n");
  411. if (!netif_running(netdev)) {
  412. DBGPR("<--xgbe_dev_resume\n");
  413. return -EINVAL;
  414. }
  415. ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);
  416. DBGPR("<--xgbe_resume\n");
  417. return ret;
  418. }
  419. #endif /* CONFIG_PM */
  420. static const struct of_device_id xgbe_of_match[] = {
  421. { .compatible = "amd,xgbe-seattle-v1a", },
  422. {},
  423. };
  424. MODULE_DEVICE_TABLE(of, xgbe_of_match);
  425. static SIMPLE_DEV_PM_OPS(xgbe_pm_ops, xgbe_suspend, xgbe_resume);
  426. static struct platform_driver xgbe_driver = {
  427. .driver = {
  428. .name = "amd-xgbe",
  429. .of_match_table = xgbe_of_match,
  430. .pm = &xgbe_pm_ops,
  431. },
  432. .probe = xgbe_probe,
  433. .remove = xgbe_remove,
  434. };
  435. module_platform_driver(xgbe_driver);